72785 lines
4.6 MiB
72785 lines
4.6 MiB
; --------------------------------------------------------------------------------
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; @Title: RCARH1 On-Chip Peripherals
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; @Props: Released
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; @Author: CNA, STR
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; @Changelog: 2012-08-07
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: R-CAR H1 Hardware Manual 05_02.pdf
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; @Core: Cortex-A9
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perrcarh1.per 14376 2022-02-24 11:15:06Z kwisniewski $
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; Known problems:
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; Cannot obtain OS62420 Hardware Manual which is necessary to create
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; registers's dectription for OS62420 SMSC's module in MLP (MediaLB+) module.
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; Cannot obtain OS62400 Hardware Manual which is necessary to create
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; registers's dectription for OS62400 SMSC's module in MIMLCP module.
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; Following units's registers are not desctripted in hardware manual:
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; CryptoEngine, GPS, SDHI, JPU, TSIF, 2D-DMAC, VSP1C, DISP, VDP1,
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; MERAM,
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config 16. 8.
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width 0xb
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tree "Core Registers (Cortex-A9MPCore)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup.long c15:0x0++0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long c15:0x100++0x0
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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textline " "
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup.long c15:0x200++0x0
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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rgroup.long c15:0x300++0x0
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
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textline " "
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bitfld.long 0x0 0. " nU ,Unified or Separate TLBs" "Unified,Separate"
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rgroup.long c15:0x500++0x0
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
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bitfld.long 0x00 8.--11. " ClusterID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "0,1,2,3"
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rgroup.long c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..."
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bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..."
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bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..."
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rgroup.long c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
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rgroup.long c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not supported"
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bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
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bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Not supported,Supported,?..."
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..."
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bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..."
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rgroup.long c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..."
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bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..."
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rgroup.long c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..."
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group.long c15:0x1++0x0
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disabled,Enabled"
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
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textline " "
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
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group.long c15:0x101++0x0
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " PARON ,Parity On" "Disabled,Enabled"
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bitfld.long 0x00 8. " ALIOW ,Enable allocation in one cache way only" "Disabled,Enabled"
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bitfld.long 0x00 7. " EXCL ,Exclusive cache Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 6. " SMP ,Signals if the Cortex-A9 processor is taking part in coherency or not" "0,1"
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bitfld.long 0x00 3. " FOZ ,Full Of Zero mode Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " DP1 ,L1 Dside prefetch Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 1. " PH2 ,L2 prefetch hint Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " FW ,Cache and TLB maintenance broadcast" "Disabled,Enabled"
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group.long c15:0x201++0x0
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes"
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bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes"
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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group.long c15:0x11++0x0
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line.long 0x0 "SCR,Secure Configuration Register"
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bitfld.long 0x00 6. " nET ,Not early termination" "Not early,Early"
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bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
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bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
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textline " "
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bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
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bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
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bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
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textline " "
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bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
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group.long c15:0x111++0x0
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line.long 0x0 "SDER,Secure Debug Enable Register"
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bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
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bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
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group.long c15:0x0211++0x00
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
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bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writable in Non-secure state" "Disabled,Enabled"
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bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
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bitfld.long 0x00 16. " PLE ,NS accesses to the Preload Engine resources control" "Secure,Non-secure"
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textline " "
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bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes"
|
|
bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register" "No,Yes"
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
group.long c15:0x0311++0x00
|
|
line.long 0x00 "VCR,Virtualization Control Register"
|
|
bitfld.long 0x00 8. " AMO ,Abort Mask Override" "0,1"
|
|
bitfld.long 0x00 7. " IMO ,IRQ Mask Override" "0,1"
|
|
bitfld.long 0x00 6. " IFO ,FIQ Mask Override" "0,1"
|
|
group.long c15:0xf++0x0
|
|
line.long 0x00 "PCR,Power Control Register"
|
|
bitfld.long 0x00 8.--10. " MCL ,Max Clock Latency" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EDCG ,Enable Dynamic Clock Gating" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group.long c15:0x10c++0x00
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
rgroup.long c15:0x1C++0x0
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
group.long c15:0x11c++0x0
|
|
line.long 0x00 "VIR,Virtualization Interrupt Register"
|
|
bitfld.long 0x00 8. " VA ,Virtual Abort" "0,1"
|
|
bitfld.long 0x00 7. " VI ,Virtual IRQ" "0,1"
|
|
bitfld.long 0x00 6. " VF ,Virtual FIQ" "0,1"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
group.long c15:0x1++0x0
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 14. " RR ,Replacement strategy for caches, BTAC, and micro TLBs" "Random,Round robin"
|
|
textline " "
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled"
|
|
textline " "
|
|
group.long c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable"
|
|
group.long c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 0. 6. " IRGN[1:0] ,Indicates inner cacheability" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 5. " NOS ,Not Outer Shareable" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
bitfld.long 0x00 2. " IMP ,Implementation Defined" "0,1"
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " C ,Cacheable" "Non-cacheable,Cacheable"
|
|
group.long c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group.long c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " DFA ,Data Fault Address"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " SD ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " IFA ,Instruction Fault Address"
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " DAFS ,Data Auxiliary Fault Status"
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,AuxiliaryInstruction Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. " IAFS ,Instruction Auxiliary Fault Status"
|
|
textline " "
|
|
group.long c15:0xa++0x0
|
|
line.long 0x0 "TLBLR,TLB Lockdown Register"
|
|
bitfld.long 0x0 28.--29. " VICTIM ,Victim Value Increments after Each Tabel Walk" "0,1,2,3"
|
|
bitfld.long 0x0 0. " P ,Lockdown by Victim or Set Associative Region of TLB" "Associative,Lockdown"
|
|
group.long c15:0x0047++0x00
|
|
line.long 0x00 "PAR,PA Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " PA ,Physical Adress"
|
|
bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NS ,Non-secure" "Not secured,Secured"
|
|
bitfld.long 0x00 7. " SH ,Shareable attribute" "Non-shareable,Shareable"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " Inner ,Signals region inner attributes" "Noncacheable,Strongly-ordered,Reserved,Device,Reserved,Write-back allocate,Write-through,Write-back"
|
|
bitfld.long 0x00 2.--3. " Outer ,Signals region outer attributes for normal memory type" "Noncacheable,Write-back allocate,Write-through,Write-back"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SS ,Supersection Enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " F ,Translation Successful" "Successful,No successful"
|
|
textline " "
|
|
group.long c15:0x002A++0x0
|
|
line.long 0x00 "PRRR,Primary Region Remap Register"
|
|
bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attribute 7" "Outer,Inner"
|
|
bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attribute 6" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attribute 5" "Outer,Inner"
|
|
bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attribute 4" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attribute 3" "Outer,Inner"
|
|
bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attribute 2" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attribute 1" "Outer,Inner"
|
|
bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attribute 0" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,?..."
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,?..."
|
|
group.long c15:0x012A++0x0
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncachable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group.long c15:0x400f++0x0
|
|
line.long 0x00 "CBAR,Configuration Base Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " CBA ,Configuration Base Address"
|
|
textline " "
|
|
rgroup.long c15:0x000d++0x00
|
|
line.long 0x00 "FCSEIDR,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 0x02 " PID ,Process for Fast Context Switch Identification and Specification"
|
|
group.long c15:0x10d++0x0
|
|
line.long 0x0 "CONTEXTIDR,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group.long c15:0x020d++0x00
|
|
line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRURW ,User Read/Write Thread ID"
|
|
group.long c15:0x030d++0x00
|
|
line.long 0x00 "TPIDRURO,User Read-only Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRURO ,User Read-only Thread ID"
|
|
group.long c15:0x040d++0x00
|
|
line.long 0x00 "TPIDRPRW,Privileged Only Thread ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " TPIDRPRW ,Privileged Only Thread ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100++0x0
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 18.--20. " CType7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CType6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CType5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CType4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CType3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CType2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CType1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup.long c15:0x1000++0x0
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group.long c15:0x2000++0x0
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data,Instruction"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group.long c15:0xC9++0x0
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group.long c15:0x1C9++0x0
|
|
line.long 0x0 "PMCNTENSET,Count Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x2C9++0x0
|
|
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMN5 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMN3 Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMN2 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMN1 Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMN0 Enabled" "Disabled,Enabled"
|
|
group.long c15:0x3C9++0x0
|
|
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 4. " P4 ,PMN5 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow"
|
|
group.long c15:0x4C9++0x0
|
|
line.long 0x0 "PMSWINC,Software Increment Register"
|
|
eventfld.long 0x00 5. " P5 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 4. " P4 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
textline " "
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group.long c15:0x5C9++0x0
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,CNT4,CNT5,?..."
|
|
group.long c15:0xD9++0x0
|
|
line.long 0x00 "PMCCNTR,Cycle Count Register"
|
|
hexmask.long 0x00 0.--31. 1. " CCNT ,Cycle Count"
|
|
group.long c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Type Select Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EVCNT ,Event to count"
|
|
group.long c15:0x02d9++0x00
|
|
line.long 0x00 "PMXEVCNTR,Event Count Register"
|
|
hexmask.long 0x00 0.--31. 1. " PMNX ,Event Count"
|
|
group.long c15:0xE9++0x0
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group.long c15:0x1E9++0x0
|
|
line.long 0x0 "PMINTENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
group.long c15:0x2E9++0x0
|
|
line.long 0x0 "PMINTENCLR,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Preload Engine"
|
|
rgroup.long c15:0x000b++0x00
|
|
line.long 0x00 "PLEIDR,PLE ID Register"
|
|
bitfld.long 0x00 16.--20. " FIFOS ,PLE FIFO size" "Not present,Reserved,Reserved,Reserved,4,Reserved,Reserved,Reserved,8,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16,?..."
|
|
bitfld.long 0x00 0. " PEP ,Preload Engine presence" "Not present,Present"
|
|
rgroup.long c15:0x020b++0x00
|
|
line.long 0x00 "PLEASR,PLE Activity Status Register"
|
|
bitfld.long 0x00 0. " R ,PLE Channel running" "Not running,Running"
|
|
rgroup.long c15:0x040b++0x00
|
|
line.long 0x00 "PLEFSR,PLE FIFO Status Register"
|
|
bitfld.long 0x00 0.--4. " AE ,Number of available entries in the PLE FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,Preload Engine User Accessibility Register"
|
|
bitfld.long 0x00 0. " U ,User accessibility" "Not permited,Permited"
|
|
group.long c15:0x011b++0x00
|
|
line.long 0x00 "PLEPCR,Preload Engine Parameters Control Register"
|
|
hexmask.long.word 0x00 16.--29. 1. " BSM ,Block size mask"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BNM ,Block number mask"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WS ,PLE wait states"
|
|
tree.end
|
|
tree "NEON"
|
|
rgroup.long c15:0x000f++0x00
|
|
line.long 0x00 "NEON,NEON busy Register"
|
|
bitfld.long 0x00 0. " Busy ,NEON busy" "Not busy,Busy"
|
|
tree.end
|
|
width 0xb
|
|
width 9.
|
|
tree "Debug Registers"
|
|
tree "Jazelle Register"
|
|
group.long c14:0x7000++0x0
|
|
line.long 0x00 "JIDR,Jazelle ID Register"
|
|
bitfld.long 0x00 28.--31. " ARCH ,Architecture code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 20.--27. 1. " DESIGN ,Implementor code of the designer of the subarchitecture"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--19. 1. " SAMAJ ,The subarchitecture code"
|
|
bitfld.long 0x00 8.--11. " SAMIN ,The subarchitecture minor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TRTBFR ,Format of the Jazelle Configurable Opcode Translation Table Register" "0,1"
|
|
bitfld.long 0x00 0.--5. " TRTBSZ ,Size of the Jazelle Configurable Opcode Translation Table Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long c14:0x7001++0x0
|
|
line.long 0x00 "JOSCR,Jazelle OS Control Register"
|
|
bitfld.long 0x00 1. " CV ,Configuration Valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " CD ,Configuration Disabled" "No,Yes"
|
|
group.long c14:0x7002++0x0
|
|
line.long 0x00 "JMCR,Jazelle Main Configuration Register"
|
|
bitfld.long 0x00 31. " nAR ,Not Array Operations" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FP ,Floating-point opcodes handler" "VM implementation,VFP instructions"
|
|
bitfld.long 0x00 29. " AP ,Array Pointer" "Handler,Pointer"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OP ,Object Pointer" "Handler,Pointer"
|
|
bitfld.long 0x00 27. " IS ,Index Size" "8 bits,16 bits"
|
|
bitfld.long 0x00 26. " SP ,Static Pointer" "Handler,Pointer"
|
|
textline " "
|
|
bitfld.long 0x00 0. " JE ,Jazelle Enable" "Disabled,Enabled"
|
|
group.long c14:0x7003++0x0
|
|
line.long 0x00 "JPR,Jazelle Parameters Register"
|
|
bitfld.long 0x00 17.--21. " BSH ,Bounds SHift" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 12.--16. " sADO ,Signed Array Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--11. " ARO ,Array Reference Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STO ,STatic Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " ODO ,Object Descriptor Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long c14:0x7004++0x0
|
|
line.long 0x00 "JCOTTRR,Jazelle Configurable Opcode Translation Table Register"
|
|
bitfld.long 0x00 10.--15. " OPCODE ,Bottom bits of the configurable opcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. " OPERATION ,Code for the operation" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
tree.end
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
|
|
bitfld.long 0x0 24.--27. " CWG ,Cache Writeback Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " DMinLine ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " L1_Ipolicy ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " IMinLine ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILsize ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLsize ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TLB_size ,TLB Size" "64,128"
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " State3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " State2 ,Java Extension Interface Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " State1 ,Thumb Encoding Supported by the Processor Type" "Not supported,Supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " State0 ,ARM Instruction Set Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Not supported,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,Reserved,Reserved,v6.1,v7,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,Reserved,v6,v6.1,v7,?..."
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " ISB ,Innermost shareability bits" "Non-cacheable,Hardware coherency,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ARS ,Auxiliary Registers Support" "Not supported,Control only,Fault status and Control,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,IMPLEMENTATION DEFINED,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SLS ,Shareability levels Support" "One level,Two levels,?..."
|
|
bitfld.long 0x00 8.--11. " OSS ,Outermost shareability Support" "Non-cacheable,Supported,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,IMPLEMENTATION DEFINED,PMSAv6,PMSAv7,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Not supported,IMPLEMENTATION DEFINED,VMSAv6,VMSAv7,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Disabled,Required,Required,Required,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..."
|
|
bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Not supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Not supported,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 28.--31. " SWP_frac ,SWAP_frac" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Not supported,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Not supported,Supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Not supported,Supported,Supported,?..."
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
width 0xc
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
width 0xc
|
|
rgroup c14:0x3f2--0x3f2
|
|
line.long 0x0 "DEVID,Device Identifier"
|
|
bitfld.long 0x00 0.--3. " PCSAMPLE ,Level of Program Counter sampling support (DBGPCSR and DBGCIDSR)" "Not implemented,DBGPCSR,Both,?..."
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x0 4.--7. 1. " STPC ,Sub Type: Processor Core"
|
|
hexmask.long.byte 0x0 0.--3. 1. " MCDL ,Main Class: Debug Logic"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " JEPCD ,JEP 106 ID code" "Not used,Used"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "Reserved,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " Version ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,ARMv7 no ext.,?..."
|
|
textline " "
|
|
bitfld.long 0x0 15. " DEVID_IMP ,Debug Device ID Register DBGDEVID implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 14. " NSUHD_IMP ,Secure User halting debug implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSR_IMP ,Program Counter Sampling Register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SE_IMP ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " Variant ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " Revision ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x7
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXfull ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXfull_l ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " PIPEADV ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " INSTRCOMPL_L ,Latched Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " EXTDCCMODE ,External DCC access mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " ADADISCARD ,Asynchronous Data Aborts Discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disabled" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 16. " SPIDDIS ,Secure Privileged Invasive Debug Disabled" "No,Yes"
|
|
bitfld.long 0x0 15. " MDBGEN ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " UDCCDIS ,User mode access to Comms Channel disable" "No,Yes"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DbgAck ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UND_l ,Sticky Undefined Instruction" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " ADABORT_l ,Sticky Asynchronous Data Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " SDABORT_l ,Sticky Synchronous Data Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Halt request,Breakpoint,Asynchronous Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,Reserved,Synchronous Watchpoint,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
width 0x7
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
;rgroup c14:0x1++0x1
|
|
; line.long 0x0 "DRAR,Debug ROM Address Register"
|
|
; hexmask.long 0x0 12.--31. 0x1000 " DBROMPA ,Debug bus ROM physical address"
|
|
; bitfld.long 0x0 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid"
|
|
; line.long 0x4 "DSAR,Debug Self Address Offset Register"
|
|
; hexmask.long 0x4 12.--31. 0x1000 " DBSAOV ,Debug bus self-address offset value"
|
|
; bitfld.long 0x4 0.--1. " VB ,Valid bits" "Not valid,Reserved,Reserved,Valid"
|
|
;hgroup c14:0x50++0x0
|
|
; hide.long 0x0 "DTR,Data Transfer Register"
|
|
; in
|
|
width 0x7
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 4. " CBIUR , Cancel Bus Interface Unit Requests" "Not canceled,Canceled"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
rgroup c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HNDLR ,Hold non-debug logic reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " WRR ,Warm reset request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
width 6.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked context ID,Linked context ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SSAC ,Secure state access control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " SP ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " BAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " L/S ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
width 0xb
|
|
width 9.
|
|
base ad:(d.l(c15:0x400f))
|
|
tree "Snoop Control Unit (SCU)"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCUCR,SCU Control Register"
|
|
bitfld.long 0x00 6. " ICSE ,IC standby enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SCUSE ,SCU standby enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FADTP0E ,Force all Device to port0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SCUSLE ,SCU Speculative linefills enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCURPE ,SCU RAMs Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AFE ,Address filtering enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SCUE ,SCU enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SCUCON,SCU Configuration Register"
|
|
bitfld.long 0x00 14.--15. " RAM3 ,Cortex-A9 CPU3 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 12.--13. " RAM2 ,Cortex-A9 CPU2 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 10.--11. " RAM1 ,Cortex-A9 CPU1 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " RAM0 ,Cortex-A9 CPU0 Tag RAM Size" "16KB,32KB,64KB,?..."
|
|
bitfld.long 0x00 7. " MOD3 ,CPU3 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 6. " MOD2 ,CPU2 Mode" "AMP,SMP"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MOD1 ,CPU1 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 4. " MOD0 ,CPU0 Mode" "AMP,SMP"
|
|
bitfld.long 0x00 0.--1. " NUM ,CPU Number" "CPU0,CPU0-CPU1,CPU0-CPU2,CPU0-CPU3"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCUSTAT,SCU CPU Power Status Register"
|
|
bitfld.long 0x00 24.--25. " STAT3 ,CPU3 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 16.--17. " STAT2 ,CPU2 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " STAT1 ,CPU1 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
bitfld.long 0x00 0.--1. " STAT0 ,CPU0 Status" "Normal,Reserved,Dormant,Powered-off"
|
|
wgroup.long 0x0c++0x03
|
|
line.long 0x00 "INV,SCU Invalidate All Register"
|
|
bitfld.long 0x00 12.--15. " WAY3 ,Cortex-A9 CPU3 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " WAY2 ,Cortex-A9 CPU2 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " WAY1 ,Cortex-A9 CPU1 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " WAY0 ,Cortex-A9 CPU0 Invalidated Ways" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FSAR,Filtering Start Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FSA ,Filtering start address"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FEAR,Filtering End Address Register"
|
|
hexmask.long.word 0x00 20.--31. 0x10 " FEA ,Filtering end address"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SAC,SCU Access Control Register"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SSAC,SCU Secure Access Control Register"
|
|
bitfld.long 0x00 11. " GCPU3 ,Global timer for CPU3" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 10. " GCPU2 ,Global timer for CPU2" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 9. " GCPU1 ,Global timer for CPU1" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GCPU0 ,Global timer for CPU0" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 7. " TCPU3 ,Private timer for CPU3 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 6. " TCPU2 ,Private timer for CPU2 Access" "Secure only,Secure/Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TCPU1 ,Private timer for CPU1 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 4. " TCPU0 ,Private timer for CPU0 Access" "Secure only,Secure/Non-secure"
|
|
bitfld.long 0x00 3. " CPU3 ,CPU3 Access the SAC" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CPU2 ,CPU2 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 1. " CPU1 ,CPU1 Access the SAC" "No access,Access"
|
|
bitfld.long 0x00 0. " CPU0 ,CPU0 Access the SAC" "No access,Access"
|
|
tree.end
|
|
width 0xb
|
|
width 8.
|
|
tree "Timer and Watchdog Blocks"
|
|
base ad:(d.l(c15:0x400f))+0x600
|
|
group.long 0x00++0xb "Timer"
|
|
line.long 0x00 "TLR,Timer Load Register"
|
|
line.long 0x04 "TCR,Timer Counter Register"
|
|
line.long 0x08 "TCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto reload" "Single shot,Auto-reload"
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "TISR,Timer Interrupt Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x20++0x13 "Watchdog"
|
|
line.long 0x00 "WLR,Watchdog Load Register"
|
|
line.long 0x04 "WCR,Watchdog Counter Register"
|
|
line.long 0x08 "WCONR,Watchdog Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " WDM ,WD Mode" "Timer,Watchdog"
|
|
bitfld.long 0x08 2. " ITEN ,IT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " AREL ,Auto-Reload" "Single shot,Auto-reload"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WEN ,Watchdog Enable" "Disabled,Enabled"
|
|
line.long 0x0c "WISR,Watchdog Interrupt Status Register"
|
|
eventfld.long 0x0C 0. " EFLAG ,Event Flag" "0,1"
|
|
line.long 0x10 "WRSR,Watchdog Reset Sent Register"
|
|
eventfld.long 0x10 0. " RFLAG ,Reset Flag" "No effect,Reset"
|
|
wgroup.long 0x34++0x3
|
|
line.long 0x00 "WDR,Watchdog Disable Register"
|
|
base ad:(d.l(c15:0x400f))+0x200
|
|
group.long 0x00++0xb "Global Timer"
|
|
line.long 0x00 "GTLCR,Lower 32-bit Timer Counter Register"
|
|
line.long 0x04 "GTUCR,Upper 32-bit Timer Counter Register"
|
|
line.long 0x08 "GTCONR,Timer Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PRES ,Prescaler"
|
|
bitfld.long 0x08 3. " AINC ,Auto Increment" "Single shot,Auto increment"
|
|
bitfld.long 0x08 2. " IRQEN ,IRQ Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " COMPEN ,Comp Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TEN ,Global Timer Enable" "Disabled,Enabled"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "GTSR,Timer Status Register"
|
|
eventfld.long 0x00 0. " EFLAG ,Event Flag" "0,1"
|
|
group.long 0x10++0xb
|
|
line.long 0x00 "GTLCOMR,Lower 32-bit Comparator Register"
|
|
line.long 0x04 "GTUCOMR,Upper 32-bit Comparator Register"
|
|
line.long 0x08 "GTINCR,Auto-increment Register for Comparator"
|
|
tree.end
|
|
width 11.
|
|
tree.open "Interrupt Controller (PL-390)"
|
|
width 17.
|
|
base AD:0xf0001000
|
|
tree "Distributor Interface"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x400)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
|
|
bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICD_CTLR,Distributor Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x400)
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
|
|
else
|
|
rgroup.long 0x0004++0x03
|
|
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..."
|
|
bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020"
|
|
endif
|
|
rgroup.long 0x0008++0x03
|
|
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
|
|
bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..."
|
|
hexmask.long.word 0x00 12.--23. 1. " REV_NUM ,Returns the revision number of the GIC"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure)
|
|
width 17.
|
|
tree "Group/Security Registers"
|
|
group.long 0x0080++0x03
|
|
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0084++0x03
|
|
line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0084++0x03
|
|
hide.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0088++0x03
|
|
line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0088++0x03
|
|
hide.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x008C++0x03
|
|
line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x008C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0090++0x03
|
|
line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0090++0x03
|
|
hide.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0094++0x03
|
|
line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0094++0x03
|
|
hide.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0098++0x03
|
|
line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0098++0x03
|
|
hide.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x009C++0x03
|
|
line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x009C++0x03
|
|
hide.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x00A0++0x03
|
|
line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x00A4++0x03
|
|
line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x00A8++0x03
|
|
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00A8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x00AC++0x03
|
|
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00AC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x00B0++0x03
|
|
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x00B4++0x03
|
|
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x00B8++0x03
|
|
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00B8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x00BC++0x03
|
|
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00BC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x00C0++0x03
|
|
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x00C4++0x03
|
|
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x00C8++0x03
|
|
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00C8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x00CC++0x03
|
|
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00CC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x00D0++0x03
|
|
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x00D4++0x03
|
|
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x00D8++0x03
|
|
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00D8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x00DC++0x03
|
|
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00DC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x00E0++0x03
|
|
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0E0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x00E4++0x03
|
|
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x00E8++0x03
|
|
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00E8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x00EC++0x03
|
|
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)"
|
|
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00EC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x00F0++0x03
|
|
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x0F0++0x03
|
|
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x00F4++0x03
|
|
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F4++0x03
|
|
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x00F8++0x03
|
|
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)"
|
|
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
|
|
bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1"
|
|
bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
|
|
bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00F8++0x03
|
|
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x00FC++0x03
|
|
line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)"
|
|
bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1"
|
|
bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1"
|
|
bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1"
|
|
bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1"
|
|
bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1"
|
|
bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1"
|
|
bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1"
|
|
bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1"
|
|
bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1"
|
|
bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1"
|
|
bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1"
|
|
bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1"
|
|
bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1"
|
|
bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1"
|
|
bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1"
|
|
bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1"
|
|
bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1"
|
|
bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1"
|
|
bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1"
|
|
else
|
|
hgroup.long 0x00FC++0x03
|
|
hide.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
endif
|
|
width 24.
|
|
tree "Set/Clear Enable Registers"
|
|
group.long 0x0100++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0104++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0104++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0108++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0108++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x010C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x010C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0110++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0110++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0114++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0114++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0118++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0118++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x011C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x011C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0120++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0120++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0124++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0124++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0128++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0128++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x012C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x012C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0130++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0130++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0134++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0134++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0138++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0138++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x013C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x013C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0140++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0140++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0144++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0144++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0148++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0148++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x014C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x014C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0150++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0150++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0154++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0154++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0158++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0158++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x015C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x015C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0160++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0160++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0164++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0164++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0168++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0168++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x016C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x016C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0170++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0170++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0174++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0174++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0178++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0178++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x017C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x017C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 22.
|
|
tree "Set/Clear Pending Registers"
|
|
group.long 0x0200++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Disabled,Enabled"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x0204++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0204++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x0208++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0208++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x020C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x020C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x0210++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0210++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x0214++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0214++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x0218++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0218++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x021C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x021C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x0220++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0220++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x0224++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0224++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x0228++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0228++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x022C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x022C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x0230++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0230++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x0234++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0234++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x0238++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0238++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x023C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x023C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x0240++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0240++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x0244++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0244++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x0248++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0248++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x024C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x024C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x0250++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0250++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x0254++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0254++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x0258++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0258++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x025C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x025C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x0260++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0260++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x0264++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0264++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x0268++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0268++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x026C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x026C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x0270++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0270++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x0274++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0274++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x0278++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x0278++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)==0x1F)
|
|
group.long 0x027C++0x03
|
|
line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x027C++0x03
|
|
hide.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Set/Clear Active Registers"
|
|
rgroup.long 0x0300++0x03
|
|
line.long 0x0 "GICD_ICDABR0,Active Status Register 0"
|
|
bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
rgroup.long 0x0304++0x03
|
|
line.long 0x0 "GICD_ICDABR1,Active Status Register 1"
|
|
bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0304++0x03
|
|
hide.long 0x0 "GICD_ICDABR1,Active Status Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
rgroup.long 0x0308++0x03
|
|
line.long 0x0 "GICD_ICDABR2,Active Status Register 2"
|
|
bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0308++0x03
|
|
hide.long 0x0 "GICD_ICDABR2,Active Status Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
rgroup.long 0x030C++0x03
|
|
line.long 0x0 "GICD_ICDABR3,Active Status Register 3"
|
|
bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active"
|
|
else
|
|
hgroup.long 0x030C++0x03
|
|
hide.long 0x0 "GICD_ICDABR3,Active Status Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
rgroup.long 0x0310++0x03
|
|
line.long 0x0 "GICD_ICDABR4,Active Status Register 4"
|
|
bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0310++0x03
|
|
hide.long 0x0 "GICD_ICDABR4,Active Status Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
rgroup.long 0x0314++0x03
|
|
line.long 0x0 "GICD_ICDABR5,Active Status Register 5"
|
|
bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0314++0x03
|
|
hide.long 0x0 "GICD_ICDABR5,Active Status Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
rgroup.long 0x0318++0x03
|
|
line.long 0x0 "GICD_ICDABR6,Active Status Register 6"
|
|
bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0318++0x03
|
|
hide.long 0x0 "GICD_ICDABR6,Active Status Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
rgroup.long 0x031C++0x03
|
|
line.long 0x0 "GICD_ICDABR7,Active Status Register 7"
|
|
bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active"
|
|
else
|
|
hgroup.long 0x031C++0x03
|
|
hide.long 0x0 "GICD_ICDABR7,Active Status Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
rgroup.long 0x0320++0x03
|
|
line.long 0x0 "GICD_ICDABR8,Active Status Register 8"
|
|
bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0320++0x03
|
|
hide.long 0x0 "GICD_ICDABR8,Active Status Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
rgroup.long 0x0324++0x03
|
|
line.long 0x0 "GICD_ICDABR9,Active Status Register 9"
|
|
bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0324++0x03
|
|
hide.long 0x0 "GICD_ICDABR9,Active Status Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
rgroup.long 0x0328++0x03
|
|
line.long 0x0 "GICD_ICDABR10,Active Status Register 10"
|
|
bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0328++0x03
|
|
hide.long 0x0 "GICD_ICDABR10,Active Status Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
rgroup.long 0x032C++0x03
|
|
line.long 0x0 "GICD_ICDABR11,Active Status Register 11"
|
|
bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active"
|
|
else
|
|
hgroup.long 0x032C++0x03
|
|
hide.long 0x0 "GICD_ICDABR11,Active Status Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
rgroup.long 0x0330++0x03
|
|
line.long 0x0 "GICD_ICDABR12,Active Status Register 12"
|
|
bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0330++0x03
|
|
hide.long 0x0 "GICD_ICDABR12,Active Status Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
rgroup.long 0x0334++0x03
|
|
line.long 0x0 "GICD_ICDABR13,Active Status Register 13"
|
|
bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0334++0x03
|
|
hide.long 0x0 "GICD_ICDABR13,Active Status Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
rgroup.long 0x0338++0x03
|
|
line.long 0x0 "GICD_ICDABR14,Active Status Register 14"
|
|
bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0338++0x03
|
|
hide.long 0x0 "GICD_ICDABR14,Active Status Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
rgroup.long 0x033C++0x03
|
|
line.long 0x0 "GICD_ICDABR15,Active Status Register 15"
|
|
bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active"
|
|
else
|
|
hgroup.long 0x033C++0x03
|
|
hide.long 0x0 "GICD_ICDABR15,Active Status Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
rgroup.long 0x0340++0x03
|
|
line.long 0x0 "GICD_ICDABR16,Active Status Register 16"
|
|
bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0340++0x03
|
|
hide.long 0x0 "GICD_ICDABR16,Active Status Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
rgroup.long 0x0344++0x03
|
|
line.long 0x0 "GICD_ICDABR17,Active Status Register 17"
|
|
bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0344++0x03
|
|
hide.long 0x0 "GICD_ICDABR17,Active Status Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
rgroup.long 0x0348++0x03
|
|
line.long 0x0 "GICD_ICDABR18,Active Status Register 18"
|
|
bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0348++0x03
|
|
hide.long 0x0 "GICD_ICDABR18,Active Status Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
rgroup.long 0x034C++0x03
|
|
line.long 0x0 "GICD_ICDABR19,Active Status Register 19"
|
|
bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active"
|
|
else
|
|
hgroup.long 0x034C++0x03
|
|
hide.long 0x0 "GICD_ICDABR19,Active Status Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
rgroup.long 0x0350++0x03
|
|
line.long 0x0 "GICD_ICDABR20,Active Status Register 20"
|
|
bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0350++0x03
|
|
hide.long 0x0 "GICD_ICDABR20,Active Status Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
rgroup.long 0x0354++0x03
|
|
line.long 0x0 "GICD_ICDABR21,Active Status Register 21"
|
|
bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0354++0x03
|
|
hide.long 0x0 "GICD_ICDABR21,Active Status Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
rgroup.long 0x0358++0x03
|
|
line.long 0x0 "GICD_ICDABR22,Active Status Register 22"
|
|
bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0358++0x03
|
|
hide.long 0x0 "GICD_ICDABR22,Active Status Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
rgroup.long 0x035C++0x03
|
|
line.long 0x0 "GICD_ICDABR23,Active Status Register 23"
|
|
bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active"
|
|
else
|
|
hgroup.long 0x035C++0x03
|
|
hide.long 0x0 "GICD_ICDABR23,Active Status Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
rgroup.long 0x0360++0x03
|
|
line.long 0x0 "GICD_ICDABR24,Active Status Register 24"
|
|
bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0360++0x03
|
|
hide.long 0x0 "GICD_ICDABR24,Active Status Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
rgroup.long 0x0364++0x03
|
|
line.long 0x0 "GICD_ICDABR25,Active Status Register 25"
|
|
bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0364++0x03
|
|
hide.long 0x0 "GICD_ICDABR25,Active Status Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
rgroup.long 0x0368++0x03
|
|
line.long 0x0 "GICD_ICDABR26,Active Status Register 26"
|
|
bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0368++0x03
|
|
hide.long 0x0 "GICD_ICDABR26,Active Status Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
rgroup.long 0x036C++0x03
|
|
line.long 0x0 "GICD_ICDABR27,Active Status Register 27"
|
|
bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active"
|
|
else
|
|
hgroup.long 0x036C++0x03
|
|
hide.long 0x0 "GICD_ICDABR27,Active Status Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
rgroup.long 0x0370++0x03
|
|
line.long 0x0 "GICD_ICDABR28,Active Status Register 28"
|
|
bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0370++0x03
|
|
hide.long 0x0 "GICD_ICDABR28,Active Status Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
rgroup.long 0x0374++0x03
|
|
line.long 0x0 "GICD_ICDABR29,Active Status Register 29"
|
|
bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0374++0x03
|
|
hide.long 0x0 "GICD_ICDABR29,Active Status Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
rgroup.long 0x0378++0x03
|
|
line.long 0x0 "GICD_ICDABR30,Active Status Register 30"
|
|
bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active"
|
|
bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active"
|
|
bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active"
|
|
bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active"
|
|
else
|
|
hgroup.long 0x0378++0x03
|
|
hide.long 0x0 "GICD_ICDABR30,Active Status Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)==0x1F)
|
|
rgroup.long 0x037C++0x03
|
|
line.long 0x0 "GICD_ICDABR31,Active Status Register 31"
|
|
bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active"
|
|
bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active"
|
|
bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active"
|
|
bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active"
|
|
bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active"
|
|
bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active"
|
|
bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active"
|
|
bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active"
|
|
bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active"
|
|
bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active"
|
|
bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active"
|
|
bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active"
|
|
bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active"
|
|
bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active"
|
|
bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active"
|
|
bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active"
|
|
bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active"
|
|
bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active"
|
|
bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active"
|
|
else
|
|
hgroup.long 0x037C++0x03
|
|
hide.long 0x0 "GICD_ICDABR31,Active Status Register 31"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 20.
|
|
tree "Priority Registers"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 "
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 "
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 "
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 "
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 "
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 "
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 "
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 "
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 "
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 "
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 "
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 "
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 "
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 "
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 "
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 "
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 "
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 "
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 "
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 "
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 "
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 "
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 "
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 "
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 "
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 "
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 "
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 "
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 "
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 "
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 "
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 "
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 "
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 "
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 "
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 "
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x480++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
|
|
hgroup.long 0x484++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
|
|
hgroup.long 0x488++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
|
|
hgroup.long 0x48C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
|
|
hgroup.long 0x494++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
|
|
hgroup.long 0x498++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
|
|
hgroup.long 0x49C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 "
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 "
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 "
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 "
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 "
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 "
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 "
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x4A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
|
|
hgroup.long 0x4A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
|
|
hgroup.long 0x4A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
|
|
hgroup.long 0x4AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
|
|
hgroup.long 0x4B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
|
|
hgroup.long 0x4B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
|
|
hgroup.long 0x4B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
|
|
hgroup.long 0x4BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 "
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 "
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 "
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 "
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 "
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 "
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 "
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x4C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
|
|
hgroup.long 0x4C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
|
|
hgroup.long 0x4C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
|
|
hgroup.long 0x4CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
|
|
hgroup.long 0x4D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
|
|
hgroup.long 0x4D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
|
|
hgroup.long 0x4D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
|
|
hgroup.long 0x4DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 "
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 "
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 "
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 "
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 "
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 "
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 "
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x4E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
|
|
hgroup.long 0x4E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
|
|
hgroup.long 0x4E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
|
|
hgroup.long 0x4EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
|
|
hgroup.long 0x4F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
|
|
hgroup.long 0x4F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
|
|
hgroup.long 0x4F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
|
|
hgroup.long 0x4FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 "
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 "
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 "
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 "
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 "
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 "
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 "
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
|
|
hgroup.long 0x504++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
|
|
hgroup.long 0x508++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
|
|
hgroup.long 0x50C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
|
|
hgroup.long 0x510++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
|
|
hgroup.long 0x514++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
|
|
hgroup.long 0x518++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
|
|
hgroup.long 0x51C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 "
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 "
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 "
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 "
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 "
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 "
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 "
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
|
|
hgroup.long 0x524++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
|
|
hgroup.long 0x528++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
|
|
hgroup.long 0x52C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
|
|
hgroup.long 0x530++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
|
|
hgroup.long 0x534++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
|
|
hgroup.long 0x538++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
|
|
hgroup.long 0x53C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 "
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 "
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 "
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 "
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 "
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 "
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 "
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
|
|
hgroup.long 0x544++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
|
|
hgroup.long 0x548++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
|
|
hgroup.long 0x54C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
|
|
hgroup.long 0x550++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
|
|
hgroup.long 0x554++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
|
|
hgroup.long 0x558++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
|
|
hgroup.long 0x55C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 "
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 "
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 "
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 "
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 "
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 "
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 "
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
|
|
hgroup.long 0x564++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
|
|
hgroup.long 0x568++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
|
|
hgroup.long 0x56C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
|
|
hgroup.long 0x570++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
|
|
hgroup.long 0x574++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
|
|
hgroup.long 0x578++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
|
|
hgroup.long 0x57C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 "
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 "
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 "
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 "
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 "
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 "
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 "
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
|
|
hgroup.long 0x584++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
|
|
hgroup.long 0x588++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
|
|
hgroup.long 0x58C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
|
|
hgroup.long 0x590++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
|
|
hgroup.long 0x594++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
|
|
hgroup.long 0x598++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
|
|
hgroup.long 0x59C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 "
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 "
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 "
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 "
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 "
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 "
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 "
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
|
|
hgroup.long 0x5A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
|
|
hgroup.long 0x5A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
|
|
hgroup.long 0x5AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
|
|
hgroup.long 0x5B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
|
|
hgroup.long 0x5B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
|
|
hgroup.long 0x5B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
|
|
hgroup.long 0x5BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 "
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 "
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 "
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 "
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 "
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 "
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 "
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
|
|
hgroup.long 0x5C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
|
|
hgroup.long 0x5C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
|
|
hgroup.long 0x5CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
|
|
hgroup.long 0x5D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
|
|
hgroup.long 0x5D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
|
|
hgroup.long 0x5D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
|
|
hgroup.long 0x5DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 "
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 "
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 "
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 "
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 "
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 "
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 "
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
|
|
hgroup.long 0x5E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
|
|
hgroup.long 0x5E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
|
|
hgroup.long 0x5EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
|
|
hgroup.long 0x5F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
|
|
hgroup.long 0x5F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
|
|
hgroup.long 0x5F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
|
|
hgroup.long 0x5FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 "
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 "
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 "
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 "
|
|
group.long 0x610++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 "
|
|
group.long 0x614++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 "
|
|
group.long 0x618++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 "
|
|
group.long 0x61C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 "
|
|
else
|
|
hgroup.long 0x600++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
|
|
hgroup.long 0x604++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
|
|
hgroup.long 0x608++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
|
|
hgroup.long 0x60C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
|
|
hgroup.long 0x610++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
|
|
hgroup.long 0x614++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
|
|
hgroup.long 0x618++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
|
|
hgroup.long 0x61C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 "
|
|
group.long 0x624++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 "
|
|
group.long 0x628++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 "
|
|
group.long 0x62C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 "
|
|
group.long 0x630++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 "
|
|
group.long 0x634++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 "
|
|
group.long 0x638++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 "
|
|
group.long 0x63C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 "
|
|
else
|
|
hgroup.long 0x620++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
|
|
hgroup.long 0x624++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
|
|
hgroup.long 0x628++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
|
|
hgroup.long 0x62C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
|
|
hgroup.long 0x630++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
|
|
hgroup.long 0x634++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
|
|
hgroup.long 0x638++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
|
|
hgroup.long 0x63C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0x640++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 "
|
|
group.long 0x644++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 "
|
|
group.long 0x648++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 "
|
|
group.long 0x64C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 "
|
|
group.long 0x650++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 "
|
|
group.long 0x654++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 "
|
|
group.long 0x658++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 "
|
|
group.long 0x65C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 "
|
|
else
|
|
hgroup.long 0x640++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
|
|
hgroup.long 0x644++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
|
|
hgroup.long 0x648++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
|
|
hgroup.long 0x64C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
|
|
hgroup.long 0x650++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
|
|
hgroup.long 0x654++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
|
|
hgroup.long 0x658++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
|
|
hgroup.long 0x65C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0x660++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 "
|
|
group.long 0x664++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 "
|
|
group.long 0x668++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 "
|
|
group.long 0x66C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 "
|
|
group.long 0x670++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 "
|
|
group.long 0x674++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 "
|
|
group.long 0x678++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 "
|
|
group.long 0x67C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 "
|
|
else
|
|
hgroup.long 0x660++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
|
|
hgroup.long 0x664++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
|
|
hgroup.long 0x668++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
|
|
hgroup.long 0x66C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
|
|
hgroup.long 0x670++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
|
|
hgroup.long 0x674++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
|
|
hgroup.long 0x678++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
|
|
hgroup.long 0x67C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0x680++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 "
|
|
group.long 0x684++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 "
|
|
group.long 0x688++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 "
|
|
group.long 0x68C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 "
|
|
group.long 0x690++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 "
|
|
group.long 0x694++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 "
|
|
group.long 0x698++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 "
|
|
group.long 0x69C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 "
|
|
else
|
|
hgroup.long 0x680++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
|
|
hgroup.long 0x684++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
|
|
hgroup.long 0x688++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
|
|
hgroup.long 0x68C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
|
|
hgroup.long 0x690++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
|
|
hgroup.long 0x694++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
|
|
hgroup.long 0x698++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
|
|
hgroup.long 0x69C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0x6A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 "
|
|
group.long 0x6A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 "
|
|
group.long 0x6A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 "
|
|
group.long 0x6AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 "
|
|
group.long 0x6B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 "
|
|
group.long 0x6B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 "
|
|
group.long 0x6B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 "
|
|
group.long 0x6BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 "
|
|
else
|
|
hgroup.long 0x6A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
|
|
hgroup.long 0x6A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
|
|
hgroup.long 0x6A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
|
|
hgroup.long 0x6AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
|
|
hgroup.long 0x6B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
|
|
hgroup.long 0x6B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
|
|
hgroup.long 0x6B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
|
|
hgroup.long 0x6BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0x6C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 "
|
|
group.long 0x6C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 "
|
|
group.long 0x6C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 "
|
|
group.long 0x6CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 "
|
|
group.long 0x6D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 "
|
|
group.long 0x6D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 "
|
|
group.long 0x6D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 "
|
|
group.long 0x6DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 "
|
|
else
|
|
hgroup.long 0x6C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
|
|
hgroup.long 0x6C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
|
|
hgroup.long 0x6C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
|
|
hgroup.long 0x6CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
|
|
hgroup.long 0x6D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
|
|
hgroup.long 0x6D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
|
|
hgroup.long 0x6D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
|
|
hgroup.long 0x6DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0x6E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 "
|
|
group.long 0x6E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 "
|
|
group.long 0x6E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 "
|
|
group.long 0x6EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 "
|
|
group.long 0x6F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 "
|
|
group.long 0x6F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 "
|
|
group.long 0x6F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 "
|
|
group.long 0x6FC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 "
|
|
else
|
|
hgroup.long 0x6E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
|
|
hgroup.long 0x6E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
|
|
hgroup.long 0x6E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
|
|
hgroup.long 0x6EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
|
|
hgroup.long 0x6F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
|
|
hgroup.long 0x6F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
|
|
hgroup.long 0x6F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
|
|
hgroup.long 0x6FC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 "
|
|
group.long 0x704++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 "
|
|
group.long 0x708++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 "
|
|
group.long 0x70C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 "
|
|
group.long 0x710++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 "
|
|
group.long 0x714++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 "
|
|
group.long 0x718++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 "
|
|
group.long 0x71C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 "
|
|
else
|
|
hgroup.long 0x700++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
|
|
hgroup.long 0x704++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
|
|
hgroup.long 0x708++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
|
|
hgroup.long 0x70C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
|
|
hgroup.long 0x710++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
|
|
hgroup.long 0x714++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
|
|
hgroup.long 0x718++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
|
|
hgroup.long 0x71C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0x720++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 "
|
|
group.long 0x724++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 "
|
|
group.long 0x728++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 "
|
|
group.long 0x72C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 "
|
|
group.long 0x730++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 "
|
|
group.long 0x734++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 "
|
|
group.long 0x738++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 "
|
|
group.long 0x73C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 "
|
|
else
|
|
hgroup.long 0x720++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
|
|
hgroup.long 0x724++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
|
|
hgroup.long 0x728++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
|
|
hgroup.long 0x72C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
|
|
hgroup.long 0x730++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
|
|
hgroup.long 0x734++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
|
|
hgroup.long 0x738++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
|
|
hgroup.long 0x73C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0x740++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 "
|
|
group.long 0x744++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 "
|
|
group.long 0x748++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 "
|
|
group.long 0x74C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 "
|
|
group.long 0x750++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 "
|
|
group.long 0x754++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 "
|
|
group.long 0x758++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 "
|
|
group.long 0x75C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 "
|
|
else
|
|
hgroup.long 0x740++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
|
|
hgroup.long 0x744++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
|
|
hgroup.long 0x748++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
|
|
hgroup.long 0x74C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
|
|
hgroup.long 0x750++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
|
|
hgroup.long 0x754++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
|
|
hgroup.long 0x758++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
|
|
hgroup.long 0x75C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0x760++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 "
|
|
group.long 0x764++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 "
|
|
group.long 0x768++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 "
|
|
group.long 0x76C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 "
|
|
group.long 0x770++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 "
|
|
group.long 0x774++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 "
|
|
group.long 0x778++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 "
|
|
group.long 0x77C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 "
|
|
else
|
|
hgroup.long 0x760++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
|
|
hgroup.long 0x764++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
|
|
hgroup.long 0x768++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
|
|
hgroup.long 0x76C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
|
|
hgroup.long 0x770++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
|
|
hgroup.long 0x774++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
|
|
hgroup.long 0x778++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
|
|
hgroup.long 0x77C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0x780++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 "
|
|
group.long 0x784++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 "
|
|
group.long 0x788++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 "
|
|
group.long 0x78C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 "
|
|
group.long 0x790++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 "
|
|
group.long 0x794++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 "
|
|
group.long 0x798++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 "
|
|
group.long 0x79C++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 "
|
|
else
|
|
hgroup.long 0x780++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
|
|
hgroup.long 0x784++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
|
|
hgroup.long 0x788++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
|
|
hgroup.long 0x78C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
|
|
hgroup.long 0x790++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
|
|
hgroup.long 0x794++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
|
|
hgroup.long 0x798++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
|
|
hgroup.long 0x79C++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0x7A0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 "
|
|
group.long 0x7A4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 "
|
|
group.long 0x7A8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 "
|
|
group.long 0x7AC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 "
|
|
group.long 0x7B0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 "
|
|
group.long 0x7B4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 "
|
|
group.long 0x7B8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 "
|
|
group.long 0x7BC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 "
|
|
else
|
|
hgroup.long 0x7A0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
|
|
hgroup.long 0x7A4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
|
|
hgroup.long 0x7A8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
|
|
hgroup.long 0x7AC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
|
|
hgroup.long 0x7B0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
|
|
hgroup.long 0x7B4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
|
|
hgroup.long 0x7B8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
|
|
hgroup.long 0x7BC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0x7C0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 "
|
|
group.long 0x7C4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 "
|
|
group.long 0x7C8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 "
|
|
group.long 0x7CC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 "
|
|
group.long 0x7D0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 "
|
|
group.long 0x7D4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 "
|
|
group.long 0x7D8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 "
|
|
group.long 0x7DC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 "
|
|
else
|
|
hgroup.long 0x7C0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
|
|
hgroup.long 0x7C4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
|
|
hgroup.long 0x7C8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
|
|
hgroup.long 0x7CC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
|
|
hgroup.long 0x7D0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
|
|
hgroup.long 0x7D4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
|
|
hgroup.long 0x7D8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
|
|
hgroup.long 0x7DC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0x7E0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 "
|
|
group.long 0x7E4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 "
|
|
group.long 0x7E8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000"
|
|
group.long 0x7EC++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004"
|
|
group.long 0x7F0++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008"
|
|
group.long 0x7F4++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012"
|
|
group.long 0x7F8++0x03
|
|
line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016"
|
|
else
|
|
hgroup.long 0x7E0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248"
|
|
hgroup.long 0x7E4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249"
|
|
hgroup.long 0x7E8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250"
|
|
hgroup.long 0x7EC++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251"
|
|
hgroup.long 0x7F0++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252"
|
|
hgroup.long 0x7F4++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253"
|
|
hgroup.long 0x7F8++0x03
|
|
hide.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254"
|
|
endif
|
|
tree.end
|
|
width 19.
|
|
tree "Processor Targets Registers"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x000000E0)>0x1)
|
|
rgroup.long 0x800++0x03
|
|
line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 "
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 "
|
|
rgroup.long 0x808++0x03
|
|
line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 "
|
|
rgroup.long 0x80C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 "
|
|
rgroup.long 0x810++0x03
|
|
line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 "
|
|
rgroup.long 0x814++0x03
|
|
line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 "
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 "
|
|
rgroup.long 0x81C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 "
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 "
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 "
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 "
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 "
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 "
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 "
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 "
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 "
|
|
else
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 "
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 "
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 "
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 "
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 "
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 "
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 "
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 "
|
|
else
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
group.long 0x860++0x03
|
|
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 "
|
|
group.long 0x864++0x03
|
|
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 "
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 "
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 "
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 "
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 "
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 "
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 "
|
|
else
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 "
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 "
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 "
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 "
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 "
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 "
|
|
group.long 0x898++0x03
|
|
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 "
|
|
group.long 0x89C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 "
|
|
else
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
group.long 0x8A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 "
|
|
group.long 0x8A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 "
|
|
group.long 0x8A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 "
|
|
group.long 0x8AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 "
|
|
group.long 0x8B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 "
|
|
group.long 0x8B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 "
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 "
|
|
group.long 0x8BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 "
|
|
else
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
group.long 0x8C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 "
|
|
group.long 0x8C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 "
|
|
group.long 0x8C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 "
|
|
group.long 0x8CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 "
|
|
group.long 0x8D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 "
|
|
group.long 0x8D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 "
|
|
group.long 0x8D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 "
|
|
group.long 0x8DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 "
|
|
else
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
group.long 0x8E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 "
|
|
group.long 0x8E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 "
|
|
group.long 0x8E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 "
|
|
group.long 0x8EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 "
|
|
group.long 0x8F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 "
|
|
group.long 0x8F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 "
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 "
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 "
|
|
else
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
group.long 0x900++0x03
|
|
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 "
|
|
group.long 0x904++0x03
|
|
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 "
|
|
group.long 0x908++0x03
|
|
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 "
|
|
group.long 0x90C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 "
|
|
group.long 0x910++0x03
|
|
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 "
|
|
group.long 0x914++0x03
|
|
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 "
|
|
group.long 0x918++0x03
|
|
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 "
|
|
group.long 0x91C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 "
|
|
else
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
group.long 0x920++0x03
|
|
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 "
|
|
group.long 0x924++0x03
|
|
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 "
|
|
group.long 0x928++0x03
|
|
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 "
|
|
group.long 0x92C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 "
|
|
group.long 0x930++0x03
|
|
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 "
|
|
group.long 0x934++0x03
|
|
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 "
|
|
group.long 0x938++0x03
|
|
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 "
|
|
group.long 0x93C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 "
|
|
else
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 "
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 "
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 "
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 "
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 "
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 "
|
|
group.long 0x958++0x03
|
|
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 "
|
|
group.long 0x95C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 "
|
|
else
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
group.long 0x960++0x03
|
|
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 "
|
|
group.long 0x964++0x03
|
|
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 "
|
|
group.long 0x968++0x03
|
|
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 "
|
|
group.long 0x96C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 "
|
|
group.long 0x970++0x03
|
|
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 "
|
|
group.long 0x974++0x03
|
|
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 "
|
|
group.long 0x978++0x03
|
|
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 "
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 "
|
|
else
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
group.long 0x980++0x03
|
|
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 "
|
|
group.long 0x984++0x03
|
|
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 "
|
|
group.long 0x988++0x03
|
|
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 "
|
|
group.long 0x98C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 "
|
|
group.long 0x990++0x03
|
|
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 "
|
|
group.long 0x994++0x03
|
|
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 "
|
|
group.long 0x998++0x03
|
|
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 "
|
|
group.long 0x99C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 "
|
|
else
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
group.long 0x9A0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 "
|
|
group.long 0x9A4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 "
|
|
group.long 0x9A8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 "
|
|
group.long 0x9AC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 "
|
|
group.long 0x9B0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 "
|
|
group.long 0x9B4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 "
|
|
group.long 0x9B8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 "
|
|
group.long 0x9BC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 "
|
|
else
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
group.long 0x9C0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 "
|
|
group.long 0x9C4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 "
|
|
group.long 0x9C8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 "
|
|
group.long 0x9CC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 "
|
|
group.long 0x9D0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 "
|
|
group.long 0x9D4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 "
|
|
group.long 0x9D8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 "
|
|
group.long 0x9DC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 "
|
|
else
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
group.long 0x9E0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 "
|
|
group.long 0x9E4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 "
|
|
group.long 0x9E8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 "
|
|
group.long 0x9EC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 "
|
|
group.long 0x9F0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 "
|
|
group.long 0x9F4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 "
|
|
group.long 0x9F8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 "
|
|
group.long 0x9FC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 "
|
|
else
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xA00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 "
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 "
|
|
group.long 0xA08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 "
|
|
group.long 0xA0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 "
|
|
group.long 0xA10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 "
|
|
group.long 0xA14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 "
|
|
group.long 0xA18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 "
|
|
group.long 0xA1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 "
|
|
else
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xA20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 "
|
|
group.long 0xA24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 "
|
|
group.long 0xA28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 "
|
|
group.long 0xA2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 "
|
|
group.long 0xA30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 "
|
|
group.long 0xA34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 "
|
|
group.long 0xA38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 "
|
|
group.long 0xA3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 "
|
|
else
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xA40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 "
|
|
group.long 0xA44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 "
|
|
group.long 0xA48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 "
|
|
group.long 0xA4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 "
|
|
group.long 0xA50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 "
|
|
group.long 0xA54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 "
|
|
group.long 0xA58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 "
|
|
group.long 0xA5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 "
|
|
else
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xA60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 "
|
|
group.long 0xA64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 "
|
|
group.long 0xA68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 "
|
|
group.long 0xA6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 "
|
|
group.long 0xA70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 "
|
|
group.long 0xA74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 "
|
|
group.long 0xA78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 "
|
|
group.long 0xA7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 "
|
|
else
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xA80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 "
|
|
group.long 0xA84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 "
|
|
group.long 0xA88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 "
|
|
group.long 0xA8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 "
|
|
group.long 0xA90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 "
|
|
group.long 0xA94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 "
|
|
group.long 0xA98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 "
|
|
group.long 0xA9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 "
|
|
else
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xAA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 "
|
|
group.long 0xAA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 "
|
|
group.long 0xAA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 "
|
|
group.long 0xAAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 "
|
|
group.long 0xAB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 "
|
|
group.long 0xAB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 "
|
|
group.long 0xAB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 "
|
|
group.long 0xABC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 "
|
|
else
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xAC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 "
|
|
group.long 0xAC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 "
|
|
group.long 0xAC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 "
|
|
group.long 0xACC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 "
|
|
group.long 0xAD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 "
|
|
group.long 0xAD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 "
|
|
group.long 0xAD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 "
|
|
group.long 0xADC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 "
|
|
else
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xAE0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 "
|
|
group.long 0xAE4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 "
|
|
group.long 0xAE8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 "
|
|
group.long 0xAEC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 "
|
|
group.long 0xAF0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 "
|
|
group.long 0xAF4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 "
|
|
group.long 0xAF8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 "
|
|
group.long 0xAFC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 "
|
|
else
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 "
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 "
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 "
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 "
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 "
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 "
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 "
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 "
|
|
else
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 "
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 "
|
|
group.long 0xB28++0x03
|
|
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 "
|
|
group.long 0xB2C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 "
|
|
group.long 0xB30++0x03
|
|
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 "
|
|
group.long 0xB34++0x03
|
|
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 "
|
|
group.long 0xB38++0x03
|
|
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 "
|
|
group.long 0xB3C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 "
|
|
else
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xB40++0x03
|
|
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 "
|
|
group.long 0xB44++0x03
|
|
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 "
|
|
group.long 0xB48++0x03
|
|
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 "
|
|
group.long 0xB4C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 "
|
|
group.long 0xB50++0x03
|
|
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 "
|
|
group.long 0xB54++0x03
|
|
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 "
|
|
group.long 0xB58++0x03
|
|
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 "
|
|
group.long 0xB5C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 "
|
|
else
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xB60++0x03
|
|
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 "
|
|
group.long 0xB64++0x03
|
|
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 "
|
|
group.long 0xB68++0x03
|
|
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 "
|
|
group.long 0xB6C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 "
|
|
group.long 0xB70++0x03
|
|
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 "
|
|
group.long 0xB74++0x03
|
|
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 "
|
|
group.long 0xB78++0x03
|
|
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 "
|
|
group.long 0xB7C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 "
|
|
else
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xB80++0x03
|
|
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 "
|
|
group.long 0xB84++0x03
|
|
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 "
|
|
group.long 0xB88++0x03
|
|
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 "
|
|
group.long 0xB8C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 "
|
|
group.long 0xB90++0x03
|
|
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 "
|
|
group.long 0xB94++0x03
|
|
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 "
|
|
group.long 0xB98++0x03
|
|
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 "
|
|
group.long 0xB9C++0x03
|
|
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 "
|
|
else
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xBA0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 "
|
|
group.long 0xBA4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 "
|
|
group.long 0xBA8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 "
|
|
group.long 0xBAC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 "
|
|
group.long 0xBB0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 "
|
|
group.long 0xBB4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 "
|
|
group.long 0xBB8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 "
|
|
group.long 0xBBC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 "
|
|
else
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xBC0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 "
|
|
group.long 0xBC4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 "
|
|
group.long 0xBC8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 "
|
|
group.long 0xBCC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 "
|
|
group.long 0xBD0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 "
|
|
group.long 0xBD4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 "
|
|
group.long 0xBD8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 "
|
|
group.long 0xBDC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 "
|
|
else
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0xBE0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 "
|
|
group.long 0xBE4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 "
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 "
|
|
group.long 0xBE8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000"
|
|
group.long 0xBEC++0x03
|
|
line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004"
|
|
group.long 0xBF0++0x03
|
|
line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008"
|
|
group.long 0xBF4++0x03
|
|
line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012"
|
|
group.long 0xBF8++0x03
|
|
line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016"
|
|
else
|
|
hgroup.long 0xBE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hgroup.long 0xBE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hgroup.long 0xBE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hgroup.long 0xBEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hgroup.long 0xBF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hgroup.long 0xBF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hgroup.long 0xBF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
endif
|
|
else
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 "
|
|
hgroup.long 0x804++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 "
|
|
hgroup.long 0x808++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 "
|
|
hgroup.long 0x80C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 "
|
|
hgroup.long 0x810++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 "
|
|
hgroup.long 0x814++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 "
|
|
hgroup.long 0x818++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 "
|
|
hgroup.long 0x81C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 "
|
|
hgroup.long 0x820++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 "
|
|
hgroup.long 0x824++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 "
|
|
hgroup.long 0x828++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
|
|
hgroup.long 0x82C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
|
|
hgroup.long 0x830++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
|
|
hgroup.long 0x834++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
|
|
hgroup.long 0x838++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
|
|
hgroup.long 0x83C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
|
|
hgroup.long 0x840++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
|
|
hgroup.long 0x844++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
|
|
hgroup.long 0x848++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
|
|
hgroup.long 0x84C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
|
|
hgroup.long 0x850++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
|
|
hgroup.long 0x854++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
|
|
hgroup.long 0x858++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
|
|
hgroup.long 0x85C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
|
|
hgroup.long 0x860++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
|
|
hgroup.long 0x864++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
|
|
hgroup.long 0x868++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
|
|
hgroup.long 0x86C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
|
|
hgroup.long 0x870++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
|
|
hgroup.long 0x874++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
|
|
hgroup.long 0x878++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
|
|
hgroup.long 0x87C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
|
|
hgroup.long 0x880++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
|
|
hgroup.long 0x884++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
|
|
hgroup.long 0x888++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
|
|
hgroup.long 0x88C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
|
|
hgroup.long 0x890++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
|
|
hgroup.long 0x894++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
|
|
hgroup.long 0x898++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
|
|
hgroup.long 0x89C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
|
|
hgroup.long 0x8A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
|
|
hgroup.long 0x8A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
|
|
hgroup.long 0x8A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
|
|
hgroup.long 0x8AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
|
|
hgroup.long 0x8B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
|
|
hgroup.long 0x8B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
|
|
hgroup.long 0x8B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
|
|
hgroup.long 0x8BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
|
|
hgroup.long 0x8C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
|
|
hgroup.long 0x8C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
|
|
hgroup.long 0x8C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
|
|
hgroup.long 0x8CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
|
|
hgroup.long 0x8D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
|
|
hgroup.long 0x8D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
|
|
hgroup.long 0x8D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
|
|
hgroup.long 0x8DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
|
|
hgroup.long 0x8E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
|
|
hgroup.long 0x8E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
|
|
hgroup.long 0x8E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
|
|
hgroup.long 0x8EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
|
|
hgroup.long 0x8F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
|
|
hgroup.long 0x8F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
|
|
hgroup.long 0x8F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
|
|
hgroup.long 0x8FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
|
|
hgroup.long 0x900++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
|
|
hgroup.long 0x904++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
|
|
hgroup.long 0x908++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
|
|
hgroup.long 0x90C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
|
|
hgroup.long 0x910++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
|
|
hgroup.long 0x914++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
|
|
hgroup.long 0x918++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
|
|
hgroup.long 0x91C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
|
|
hgroup.long 0x920++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
|
|
hgroup.long 0x924++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
|
|
hgroup.long 0x928++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
|
|
hgroup.long 0x92C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
|
|
hgroup.long 0x930++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
|
|
hgroup.long 0x934++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
|
|
hgroup.long 0x938++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
|
|
hgroup.long 0x93C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
|
|
hgroup.long 0x940++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
|
|
hgroup.long 0x944++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
|
|
hgroup.long 0x948++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
|
|
hgroup.long 0x94C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
|
|
hgroup.long 0x950++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
|
|
hgroup.long 0x954++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
|
|
hgroup.long 0x958++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
|
|
hgroup.long 0x95C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
|
|
hgroup.long 0x960++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
|
|
hgroup.long 0x964++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
|
|
hgroup.long 0x968++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
|
|
hgroup.long 0x96C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
|
|
hgroup.long 0x970++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
|
|
hgroup.long 0x974++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
|
|
hgroup.long 0x978++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
|
|
hgroup.long 0x97C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
|
|
hgroup.long 0x980++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
|
|
hgroup.long 0x984++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
|
|
hgroup.long 0x988++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
|
|
hgroup.long 0x98C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
|
|
hgroup.long 0x990++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
|
|
hgroup.long 0x994++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
|
|
hgroup.long 0x998++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
|
|
hgroup.long 0x99C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
|
|
hgroup.long 0x9A0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
|
|
hgroup.long 0x9A4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
|
|
hgroup.long 0x9A8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
|
|
hgroup.long 0x9AC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
|
|
hgroup.long 0x9B0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
|
|
hgroup.long 0x9B4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
|
|
hgroup.long 0x9B8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
|
|
hgroup.long 0x9BC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
|
|
hgroup.long 0x9C0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
|
|
hgroup.long 0x9C4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
|
|
hgroup.long 0x9C8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
|
|
hgroup.long 0x9CC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
|
|
hgroup.long 0x9D0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
|
|
hgroup.long 0x9D4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
|
|
hgroup.long 0x9D8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
|
|
hgroup.long 0x9DC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
|
|
hgroup.long 0x9E0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
|
|
hgroup.long 0x9E4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
|
|
hgroup.long 0x9E8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
|
|
hgroup.long 0x9EC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
|
|
hgroup.long 0x9F0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
|
|
hgroup.long 0x9F4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
|
|
hgroup.long 0x9F8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
|
|
hgroup.long 0x9FC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
|
|
hgroup.long 0xA00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
|
|
hgroup.long 0xA04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
|
|
hgroup.long 0xA08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
|
|
hgroup.long 0xA0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
|
|
hgroup.long 0xA10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
|
|
hgroup.long 0xA14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
|
|
hgroup.long 0xA18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
|
|
hgroup.long 0xA1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
|
|
hgroup.long 0xA20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
|
|
hgroup.long 0xA24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
|
|
hgroup.long 0xA28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
|
|
hgroup.long 0xA2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
|
|
hgroup.long 0xA30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
|
|
hgroup.long 0xA34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
|
|
hgroup.long 0xA38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
|
|
hgroup.long 0xA3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
|
|
hgroup.long 0xA40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
|
|
hgroup.long 0xA44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
|
|
hgroup.long 0xA48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
|
|
hgroup.long 0xA4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
|
|
hgroup.long 0xA50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
|
|
hgroup.long 0xA54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
|
|
hgroup.long 0xA58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
|
|
hgroup.long 0xA5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
|
|
hgroup.long 0xA60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
|
|
hgroup.long 0xA64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
|
|
hgroup.long 0xA68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
|
|
hgroup.long 0xA6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
|
|
hgroup.long 0xA70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
|
|
hgroup.long 0xA74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
|
|
hgroup.long 0xA78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
|
|
hgroup.long 0xA7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
|
|
hgroup.long 0xA80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
|
|
hgroup.long 0xA84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
|
|
hgroup.long 0xA88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
|
|
hgroup.long 0xA8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
|
|
hgroup.long 0xA90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
|
|
hgroup.long 0xA94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
|
|
hgroup.long 0xA98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
|
|
hgroup.long 0xA9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
|
|
hgroup.long 0xAA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
|
|
hgroup.long 0xAA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
|
|
hgroup.long 0xAA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
|
|
hgroup.long 0xAAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
|
|
hgroup.long 0xAB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
|
|
hgroup.long 0xAB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
|
|
hgroup.long 0xAB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
|
|
hgroup.long 0xABC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
|
|
hgroup.long 0xAC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
|
|
hgroup.long 0xAC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
|
|
hgroup.long 0xAC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
|
|
hgroup.long 0xACC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
|
|
hgroup.long 0xAD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
|
|
hgroup.long 0xAD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
|
|
hgroup.long 0xAD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
|
|
hgroup.long 0xADC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
|
|
hgroup.long 0xAE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
|
|
hgroup.long 0xAE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
|
|
hgroup.long 0xAE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
|
|
hgroup.long 0xAEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
|
|
hgroup.long 0xAF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
|
|
hgroup.long 0xAF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
|
|
hgroup.long 0xAF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
|
|
hgroup.long 0xAFC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
|
|
hgroup.long 0xB00++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
|
|
hgroup.long 0xB04++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
|
|
hgroup.long 0xB08++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
|
|
hgroup.long 0xB0C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
|
|
hgroup.long 0xB10++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
|
|
hgroup.long 0xB14++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
|
|
hgroup.long 0xB18++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
|
|
hgroup.long 0xB1C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
|
|
hgroup.long 0xB20++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
|
|
hgroup.long 0xB24++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
|
|
hgroup.long 0xB28++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
|
|
hgroup.long 0xB2C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
|
|
hgroup.long 0xB30++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
|
|
hgroup.long 0xB34++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
|
|
hgroup.long 0xB38++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
|
|
hgroup.long 0xB3C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
|
|
hgroup.long 0xB40++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
|
|
hgroup.long 0xB44++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
|
|
hgroup.long 0xB48++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
|
|
hgroup.long 0xB4C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
|
|
hgroup.long 0xB50++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
|
|
hgroup.long 0xB54++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
|
|
hgroup.long 0xB58++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
|
|
hgroup.long 0xB5C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
|
|
hgroup.long 0xB60++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
|
|
hgroup.long 0xB64++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
|
|
hgroup.long 0xB68++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
|
|
hgroup.long 0xB6C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
|
|
hgroup.long 0xB70++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
|
|
hgroup.long 0xB74++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
|
|
hgroup.long 0xB78++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
|
|
hgroup.long 0xB7C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
|
|
hgroup.long 0xB80++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
|
|
hgroup.long 0xB84++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
|
|
hgroup.long 0xB88++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
|
|
hgroup.long 0xB8C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
|
|
hgroup.long 0xB90++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
|
|
hgroup.long 0xB94++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
|
|
hgroup.long 0xB98++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
|
|
hgroup.long 0xB9C++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
|
|
hgroup.long 0xBA0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
|
|
hgroup.long 0xBA4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
|
|
hgroup.long 0xBA8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
|
|
hgroup.long 0xBAC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
|
|
hgroup.long 0xBB0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
|
|
hgroup.long 0xBB4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
|
|
hgroup.long 0xBB8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
|
|
hgroup.long 0xBBC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
|
|
hgroup.long 0xBC0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
|
|
hgroup.long 0xBC4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
|
|
hgroup.long 0xBC8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
|
|
hgroup.long 0xBCC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
|
|
hgroup.long 0xBD0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
|
|
hgroup.long 0xBD4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
|
|
hgroup.long 0xBD8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
|
|
hgroup.long 0xBDC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
|
|
hgroup.long 0xBE0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248"
|
|
hgroup.long 0xBE4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249"
|
|
hgroup.long 0xBE8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250"
|
|
hgroup.long 0xBEC++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251"
|
|
hgroup.long 0xBF0++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252"
|
|
hgroup.long 0xBF4++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253"
|
|
hgroup.long 0xBF8++0x03
|
|
hide.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254"
|
|
endif
|
|
tree.end
|
|
width 14.
|
|
tree "Configuration Registers"
|
|
hgroup.long 0xC00++0x03
|
|
hide.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
|
|
textline " "
|
|
rgroup.long 0xC04++0x03
|
|
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1)
|
|
group.long 0xC08++0x03
|
|
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC0C++0x03
|
|
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC08++0x03
|
|
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
|
|
hgroup.long 0xC0C++0x03
|
|
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x2)
|
|
group.long 0xC10++0x03
|
|
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC14++0x03
|
|
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC10++0x03
|
|
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
|
|
hgroup.long 0xC14++0x03
|
|
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x3)
|
|
group.long 0xC18++0x03
|
|
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC1C++0x03
|
|
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC18++0x03
|
|
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
|
|
hgroup.long 0xC1C++0x03
|
|
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x4)
|
|
group.long 0xC20++0x03
|
|
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC24++0x03
|
|
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC20++0x03
|
|
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
|
|
hgroup.long 0xC24++0x03
|
|
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x5)
|
|
group.long 0xC28++0x03
|
|
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC2C++0x03
|
|
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC28++0x03
|
|
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
|
|
hgroup.long 0xC2C++0x03
|
|
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x6)
|
|
group.long 0xC30++0x03
|
|
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC34++0x03
|
|
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC30++0x03
|
|
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
|
|
hgroup.long 0xC34++0x03
|
|
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x7)
|
|
group.long 0xC38++0x03
|
|
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC3C++0x03
|
|
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC38++0x03
|
|
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
|
|
hgroup.long 0xC3C++0x03
|
|
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x8)
|
|
group.long 0xC40++0x03
|
|
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC44++0x03
|
|
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC40++0x03
|
|
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
|
|
hgroup.long 0xC44++0x03
|
|
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x9)
|
|
group.long 0xC48++0x03
|
|
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC4C++0x03
|
|
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC48++0x03
|
|
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
|
|
hgroup.long 0xC4C++0x03
|
|
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xA)
|
|
group.long 0xC50++0x03
|
|
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC54++0x03
|
|
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC50++0x03
|
|
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
|
|
hgroup.long 0xC54++0x03
|
|
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xB)
|
|
group.long 0xC58++0x03
|
|
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC5C++0x03
|
|
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC58++0x03
|
|
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
|
|
hgroup.long 0xC5C++0x03
|
|
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xC)
|
|
group.long 0xC60++0x03
|
|
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC64++0x03
|
|
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC60++0x03
|
|
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
|
|
hgroup.long 0xC64++0x03
|
|
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xD)
|
|
group.long 0xC68++0x03
|
|
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC6C++0x03
|
|
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC68++0x03
|
|
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
|
|
hgroup.long 0xC6C++0x03
|
|
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xE)
|
|
group.long 0xC70++0x03
|
|
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC74++0x03
|
|
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC70++0x03
|
|
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
|
|
hgroup.long 0xC74++0x03
|
|
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0xF)
|
|
group.long 0xC78++0x03
|
|
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC7C++0x03
|
|
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC78++0x03
|
|
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
|
|
hgroup.long 0xC7C++0x03
|
|
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
group.long 0xC80++0x03
|
|
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC84++0x03
|
|
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC80++0x03
|
|
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
|
|
hgroup.long 0xC84++0x03
|
|
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
group.long 0xC88++0x03
|
|
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC8C++0x03
|
|
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC88++0x03
|
|
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
|
|
hgroup.long 0xC8C++0x03
|
|
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
group.long 0xC90++0x03
|
|
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC94++0x03
|
|
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC90++0x03
|
|
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
|
|
hgroup.long 0xC94++0x03
|
|
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
group.long 0xC98++0x03
|
|
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xC9C++0x03
|
|
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xC98++0x03
|
|
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
|
|
hgroup.long 0xC9C++0x03
|
|
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
group.long 0xCA0++0x03
|
|
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCA4++0x03
|
|
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA0++0x03
|
|
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
|
|
hgroup.long 0xCA4++0x03
|
|
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
group.long 0xCA8++0x03
|
|
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCAC++0x03
|
|
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCA8++0x03
|
|
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
|
|
hgroup.long 0xCAC++0x03
|
|
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
group.long 0xCB0++0x03
|
|
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCB4++0x03
|
|
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB0++0x03
|
|
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
|
|
hgroup.long 0xCB4++0x03
|
|
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
group.long 0xCB8++0x03
|
|
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCBC++0x03
|
|
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCB8++0x03
|
|
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
|
|
hgroup.long 0xCBC++0x03
|
|
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
group.long 0xCC0++0x03
|
|
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCC4++0x03
|
|
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC0++0x03
|
|
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
|
|
hgroup.long 0xCC4++0x03
|
|
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
group.long 0xCC8++0x03
|
|
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCCC++0x03
|
|
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCC8++0x03
|
|
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
|
|
hgroup.long 0xCCC++0x03
|
|
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
group.long 0xCD0++0x03
|
|
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCD4++0x03
|
|
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD0++0x03
|
|
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
|
|
hgroup.long 0xCD4++0x03
|
|
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
group.long 0xCD8++0x03
|
|
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCDC++0x03
|
|
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCD8++0x03
|
|
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
|
|
hgroup.long 0xCDC++0x03
|
|
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
group.long 0xCE0++0x03
|
|
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCE4++0x03
|
|
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE0++0x03
|
|
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
|
|
hgroup.long 0xCE4++0x03
|
|
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
group.long 0xCE8++0x03
|
|
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCEC++0x03
|
|
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCE8++0x03
|
|
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
|
|
hgroup.long 0xCEC++0x03
|
|
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
group.long 0xCF0++0x03
|
|
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCF4++0x03
|
|
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCF0++0x03
|
|
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
|
|
hgroup.long 0xCF4++0x03
|
|
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1F)
|
|
group.long 0xCF8++0x03
|
|
line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
group.long 0xCFC++0x03
|
|
line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
|
|
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge"
|
|
bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge"
|
|
bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge"
|
|
bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge"
|
|
bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge"
|
|
bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge"
|
|
bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge"
|
|
bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge"
|
|
bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge"
|
|
bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge"
|
|
bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge"
|
|
else
|
|
hgroup.long 0xCF8++0x03
|
|
hide.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62"
|
|
hgroup.long 0xCFC++0x03
|
|
hide.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral Interrupt Status Registers"
|
|
rgroup.long 0x0D00++0x03
|
|
line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register"
|
|
bitfld.long 0x00 15. " PPI_C[15] ,Returns the status of the ppi_c[15] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 14. " PPI_C[14] ,Returns the status of the ppi_c[14] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 13. " PPI_C[13] ,Returns the status of the ppi_c[13] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 12. " PPI_C[12] ,Returns the status of the ppi_c[12] inputs on the Distributor" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PPI_C[11] ,Returns the status of the ppi_c[11] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 10. " PPI_C[10] ,Returns the status of the ppi_c[10] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 9. " PPI_C[9] ,Returns the status of the ppi_c[9] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 8. " PPI_C[8] ,Returns the status of the ppi_c[8] inputs on the Distributor" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PPI_C[7] ,Returns the status of the ppi_c[7] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 6. " PPI_C[6] ,Returns the status of the ppi_c[6] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 5. " PPI_C[5] ,Returns the status of the ppi_c[5] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 4. " PPI_C[4] ,Returns the status of the ppi_c[4] inputs on the Distributor" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PPI_C[3] ,Returns the status of the ppi_c[3] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 2. " PPI_C[2] ,Returns the status of the ppi_c[2] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 1. " PPI_C[1] ,Returns the status of the ppi_c[1] inputs on the Distributor" "Low,High"
|
|
bitfld.long 0x00 0. " PPI_C[0] ,Returns the status of the ppi_c[0] inputs on the Distributor" "Low,High"
|
|
textline " "
|
|
width 22.
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x01)
|
|
rgroup.long 0x0D04++0x03
|
|
line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0"
|
|
bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x0D04++0x03
|
|
hide.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x02)
|
|
rgroup.long 0x0D08++0x03
|
|
line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High"
|
|
else
|
|
hgroup.long 0x0D08++0x03
|
|
hide.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x03)
|
|
rgroup.long 0x0D0C++0x03
|
|
line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High"
|
|
else
|
|
hgroup.long 0x0D0C++0x03
|
|
hide.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x04)
|
|
rgroup.long 0x0D10++0x03
|
|
line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High"
|
|
else
|
|
hgroup.long 0x0D10++0x03
|
|
hide.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x05)
|
|
rgroup.long 0x0D14++0x03
|
|
line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High"
|
|
else
|
|
hgroup.long 0x0D14++0x03
|
|
hide.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x06)
|
|
rgroup.long 0x0D18++0x03
|
|
line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High"
|
|
else
|
|
hgroup.long 0x0D18++0x03
|
|
hide.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x07)
|
|
rgroup.long 0x0D1C++0x03
|
|
line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High"
|
|
else
|
|
hgroup.long 0x0D1C++0x03
|
|
hide.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x08)
|
|
rgroup.long 0x0D20++0x03
|
|
line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High"
|
|
else
|
|
hgroup.long 0x0D20++0x03
|
|
hide.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x09)
|
|
rgroup.long 0x0D24++0x03
|
|
line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High"
|
|
else
|
|
hgroup.long 0x0D24++0x03
|
|
hide.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0A)
|
|
rgroup.long 0x0D28++0x03
|
|
line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High"
|
|
else
|
|
hgroup.long 0x0D28++0x03
|
|
hide.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0B)
|
|
rgroup.long 0x0D2C++0x03
|
|
line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High"
|
|
else
|
|
hgroup.long 0x0D2C++0x03
|
|
hide.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0C)
|
|
rgroup.long 0x0D30++0x03
|
|
line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High"
|
|
else
|
|
hgroup.long 0x0D30++0x03
|
|
hide.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0D)
|
|
rgroup.long 0x0D34++0x03
|
|
line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High"
|
|
else
|
|
hgroup.long 0x0D34++0x03
|
|
hide.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0E)
|
|
rgroup.long 0x0D38++0x03
|
|
line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High"
|
|
else
|
|
hgroup.long 0x0D38++0x03
|
|
hide.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x0F)
|
|
rgroup.long 0x0D3C++0x03
|
|
line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High"
|
|
else
|
|
hgroup.long 0x0D3C++0x03
|
|
hide.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x10)
|
|
rgroup.long 0x0D40++0x03
|
|
line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High"
|
|
else
|
|
hgroup.long 0x0D40++0x03
|
|
hide.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x11)
|
|
rgroup.long 0x0D44++0x03
|
|
line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High"
|
|
else
|
|
hgroup.long 0x0D44++0x03
|
|
hide.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x12)
|
|
rgroup.long 0x0D48++0x03
|
|
line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High"
|
|
else
|
|
hgroup.long 0x0D48++0x03
|
|
hide.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x13)
|
|
rgroup.long 0x0D4C++0x03
|
|
line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High"
|
|
else
|
|
hgroup.long 0x0D4C++0x03
|
|
hide.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x14)
|
|
rgroup.long 0x0D50++0x03
|
|
line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High"
|
|
else
|
|
hgroup.long 0x0D50++0x03
|
|
hide.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x15)
|
|
rgroup.long 0x0D54++0x03
|
|
line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High"
|
|
else
|
|
hgroup.long 0x0D54++0x03
|
|
hide.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x16)
|
|
rgroup.long 0x0D58++0x03
|
|
line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High"
|
|
else
|
|
hgroup.long 0x0D58++0x03
|
|
hide.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x17)
|
|
rgroup.long 0x0D5C++0x03
|
|
line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High"
|
|
else
|
|
hgroup.long 0x0D5C++0x03
|
|
hide.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x18)
|
|
rgroup.long 0x060++0x03
|
|
line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High"
|
|
else
|
|
hgroup.long 0x0D60++0x03
|
|
hide.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x19)
|
|
rgroup.long 0x0D64++0x03
|
|
line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High"
|
|
else
|
|
hgroup.long 0x0D64++0x03
|
|
hide.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1A)
|
|
rgroup.long 0x0D68++0x03
|
|
line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High"
|
|
else
|
|
hgroup.long 0x0D68++0x03
|
|
hide.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1B)
|
|
rgroup.long 0x0D6C++0x03
|
|
line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High"
|
|
else
|
|
hgroup.long 0x0D6C++0x03
|
|
hide.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1C)
|
|
rgroup.long 0x0D70++0x03
|
|
line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High"
|
|
else
|
|
hgroup.long 0x0D70++0x03
|
|
hide.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1D)
|
|
rgroup.long 0x0D74++0x03
|
|
line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High"
|
|
else
|
|
hgroup.long 0x0D74++0x03
|
|
hide.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1E)
|
|
rgroup.long 0x0D78++0x03
|
|
line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High"
|
|
bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High"
|
|
bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High"
|
|
bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High"
|
|
else
|
|
hgroup.long 0x0D78++0x03
|
|
hide.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if (((d.l(AD:0xf0001000+0x04))&0x0000001F)>=0x1F)
|
|
rgroup.long 0x0D7C++0x03
|
|
line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
|
|
bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High"
|
|
bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High"
|
|
bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High"
|
|
bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High"
|
|
bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High"
|
|
bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High"
|
|
bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High"
|
|
bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High"
|
|
bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High"
|
|
bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High"
|
|
bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High"
|
|
bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High"
|
|
bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High"
|
|
bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High"
|
|
bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High"
|
|
bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High"
|
|
bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High"
|
|
bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High"
|
|
bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High"
|
|
else
|
|
hgroup.long 0x0D7C++0x03
|
|
hide.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 25.
|
|
tree "Software Generated Interrupt"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x400)
|
|
wgroup.long 0x0F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure"
|
|
bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
wgroup.long 0x0F00++0x03
|
|
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
|
|
bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Peripheral/Component ID Registers"
|
|
rgroup.byte 0x0FE0++0x00
|
|
line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register"
|
|
hexmask.byte 0x00 0.--7. 1. " PART_NUMBER_0 ,Returns 0x90"
|
|
rgroup.byte 0x0FE4++0x00
|
|
line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register"
|
|
bitfld.byte 0x00 4.--7. " JEP106_ID_3_0 ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PART_NUMBER_1 ,Returns 0x3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FE8++0x00
|
|
line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register"
|
|
bitfld.byte 0x00 4.--7. " ARCHITECTURE ,Identifies the architecture version of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 3. " JEDEC_USED ,This indicates that the GIC uses a manufacturers identity code that was allocated by JEDEC according to JEP106" "Low,High"
|
|
bitfld.byte 0x00 0.--2. " JEP106_ID_CODE ,JEP106 identity code field" "0,1,2,3,4,5,6,7"
|
|
rgroup.byte 0x0FEC++0x00
|
|
line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register"
|
|
bitfld.byte 0x00 4.--7. " REVAND ,The top-level RTL provides four AND gates that are tied-off to provide an output value of 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " MOD_NUMBER ,The customer can update this field if they modify the RTL of the GIC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FD0++0x00
|
|
line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register"
|
|
bitfld.byte 0x00 4.--7. " 4KB_COUNT ,The number of 4KB address blocks you require to access the registers expressed in powers of 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " JEP106_C_CODE ,The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturers identity code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FD4++0x00
|
|
line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register"
|
|
bitfld.byte 0x00 5.--7. " PPI_NUMBER_0 ,The LSBs of the number of PPIs that the GIC provides" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. " SGI_NUMBER ,The number of SGIs that the GIC provides" "None,INTID0,INTID[1:0],INTID[2:0],INTID[3:0],INTID[4:0],INTID[5:0],INTID[6:0],INTID[7:0],INTID[8:0],INTID[9:0],INTID[10:0],INTID[11:0],INTID[12:0],INTID[13:0],INTID[14:0],INTID[15:0],?..."
|
|
rgroup.byte 0x0FD8++0x00
|
|
line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register"
|
|
bitfld.byte 0x00 2.--7. " SPI_NUMBER_0 ,The LSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.byte 0x00 0.--1. " PPI_NUMBER_1 ,The MSBs of the number of PPIs that the GIC provides" "0,1,2,3"
|
|
rgroup.byte 0x0FDC++0x00
|
|
line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register"
|
|
bitfld.byte 0x00 7. " TZ ,Identifies the number of security states that the GIC supports" "S,NS&S"
|
|
bitfld.byte 0x00 4.--6. " PRIORITY ,The number of priority levels that the GIC provides" "16,32,64,128,256,?..."
|
|
bitfld.byte 0x00 0.--3. " SPI_NUMBER_1 ,The MSBs of the number of SPIs that the GIC provides" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0x0FC0++0x00
|
|
line.byte 0x00 "GICD_PIDR8,Peripheral ID8 Register"
|
|
bitfld.byte 0x00 7. " IDENTIFIER ,Identifies the AMBA interface that this register belongs to" "Distributor,CPU Interface"
|
|
bitfld.byte 0x00 5.--6. " IF_TYPE ,Identifies the AMBA protocol that the GIC supports" "AXI,AHB-Lite,?..."
|
|
bitfld.byte 0x00 2.--4. " CPU_IF ,Identifies the number of CPU Interfaces that the GIC contains" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FIQ_LEGACY ,Identifies if the GIC provides a legacy FIQ input signal for each CPU Interface" "Not supported,Supported"
|
|
bitfld.byte 0x00 0. " IRQ_LEGACY ,Identifies if the GIC provides a legacy IRQ input signal for each CPU Interface" "Not supported,Supported"
|
|
tree.end
|
|
tree.end
|
|
base AD:0xf0000100
|
|
width 17.
|
|
tree "CPU Interface"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x0)
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
else
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "GICC_CTLR,CPU Interface Control Register (Non-secure access)"
|
|
bitfld.long 0x00 0. " ENABLE ,Enable for the signaling of Group 1 interrupts by the CPU interface to the connected processor" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
group.long 0x0004++0x03
|
|
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x400)
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register (Non-secure access)"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
else
|
|
group.long 0x0008++0x03
|
|
line.long 0x00 "GICC_BPR,Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "Reserved,Reserved,Reserved,[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
endif
|
|
hgroup.long 0x000C++0x03
|
|
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
|
|
in
|
|
wgroup.long 0x0010++0x03
|
|
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the write refers to an SGI this field contains the CPUID value from the corresponding GICC_IAR access" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,The Interrupt ID value from the corresponding GICC_IAR access"
|
|
rgroup.long 0x0014++0x03
|
|
line.long 0x00 "GICC_RPR,Running Priority Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,The current running priority on the CPU interface"
|
|
rgroup.long 0x0018++0x03
|
|
line.long 0x00 "GICC_HPIR,Highest Priority Pending Interrupt Register"
|
|
bitfld.long 0x00 10.--12. " CPUID ,On a multiprocessor implementation if the PENDINTID field returns the ID of an SGI this field contains the CPUID value for that interrupt" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,The interrupt ID of the highest priority pending interrupt"
|
|
if (((d.l(AD:0xf0001000+0x04))&0x400)==0x400)
|
|
group.long 0x001C++0x03
|
|
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
bitfld.long 0x00 0.--2. " BINARY_POINT ,The value of this field controls how the 8-bit interrupt priority field is split into a group priority field and subpriority field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
else
|
|
hgroup.long 0x001C++0x03
|
|
hide.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
|
|
endif
|
|
rgroup.long 0x00FC++0x03
|
|
line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID"
|
|
bitfld.long 0x00 16.--19. " ARCH_VER ,Identifies the architecture version of the GIC" "GICv1,GICv1,GICv2,GICv2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "GPIO"
|
|
base ad:0xFFC40000
|
|
width 11.
|
|
tree "GPIO A"
|
|
group.long (0x00+0x0)++0xB
|
|
line.long 0x00 "IOINTSEL0,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL0_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL0_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL0_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL0_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL0_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL0_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL0_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL0_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL0_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL0_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL0_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL0_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL0_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL0_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL0_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL0_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL0_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL0_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL0_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL0_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL0_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL0_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL0_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL0_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL0_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL0_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL0_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL0_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL0_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL0_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL0_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL0_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL0,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL0_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL0_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL0_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL0_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL0_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL0_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL0_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL0_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL0_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL0_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL0_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL0_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL0_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL0_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL0_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL0_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL0_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL0_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL0_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL0_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL0_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL0_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL0_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL0_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL0_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL0_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL0_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL0_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL0_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL0_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL0_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL0_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT0,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT0_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT0_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT0_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT0_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT0_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT0_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT0_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT0_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT0_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT0_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT0_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT0_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT0_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT0_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT0_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT0_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT0_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT0_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT0_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT0_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT0_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT0_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT0_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT0_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT0_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT0_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT0_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT0_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT0_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT0_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT0_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT0_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x0)++0x07
|
|
line.long 0x00 "INDT0,General input register 0"
|
|
bitfld.long 0x00 31. " INDT0_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT0_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT0_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT0_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT0_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT0_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT0_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT0_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT0_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT0_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT0_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT0_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT0_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT0_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT0_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT0_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT0_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT0_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT0_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT0_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT0_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT0_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT0_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT0_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT0_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT0_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT0_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT0_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT0_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT0_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT0_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT0_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT0,Interrupt display register 0"
|
|
bitfld.long 0x04 31. " INTDT0_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT0_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT0_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT0_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT0_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT0_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT0_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT0_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT0_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT0_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT0_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT0_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT0_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT0_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT0_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT0_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT0_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT0_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT0_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT0_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT0_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT0_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT0_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT0_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT0_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT0_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT0_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT0_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT0_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT0_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT0_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT0_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x0)++0x17
|
|
line.long 0x00 "INTCLR0,Interrupt clear register 0"
|
|
bitfld.long 0x00 31. " INTCLR0_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR0_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR0_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR0_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR0_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR0_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR0_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR0_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR0_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR0_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR0_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR0_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR0_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR0_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR0_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR0_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR0_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR0_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR0_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR0_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR0_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR0_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR0_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR0_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR0_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR0_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR0_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR0_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR0_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR0_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR0_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR0_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK0,Interrupt mask register 0"
|
|
bitfld.long 0x04 31. " INTMSK0_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK0_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK0_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK0_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK0_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK0_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK0_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK0_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK0_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK0_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK0_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK0_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK0_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK0_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK0_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK0_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK0_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK0_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK0_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK0_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK0_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK0_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK0_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK0_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK0_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK0_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK0_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK0_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK0_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK0_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK0_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK0_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR0,Interrupt mask clear register 0"
|
|
bitfld.long 0x08 31. " MSKCLR0_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR0_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR0_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR0_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR0_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR0_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR0_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR0_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR0_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR0_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR0_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR0_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR0_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR0_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR0_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR0_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR0_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR0_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR0_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR0_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR0_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR0_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR0_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR0_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR0_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR0_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR0_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR0_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR0_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR0_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR0_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR0_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG0,Positive/negative logic select register 0"
|
|
bitfld.long 0x0C 31. " POSNEG0_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG0_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG0_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG0_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG0_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG0_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG0_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG0_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG0_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG0_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG0_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG0_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG0_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG0_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG0_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG0_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG0_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG0_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG0_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG0_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG0_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG0_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG0_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG0_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG0_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG0_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG0_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG0_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG0_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG0_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG0_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG0_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL0,Edge/level select register 0"
|
|
bitfld.long 0x10 31. " EDGLEVEL0_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL0_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL0_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL0_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL0_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL0_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL0_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL0_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL0_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL0_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL0_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL0_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL0_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL0_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL0_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL0_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL0_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL0_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL0_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL0_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL0_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL0_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL0_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL0_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL0_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL0_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL0_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL0_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL0_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL0_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL0_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL0_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF0,Chattering prevention on/off register 0"
|
|
bitfld.long 0x14 3. " FILONOFF0_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF0_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF0_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF0_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO B"
|
|
group.long (0x00+0x1000)++0xB
|
|
line.long 0x00 "IOINTSEL1,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL1_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL1_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL1_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL1_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL1_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL1_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL1_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL1_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL1_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL1_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL1_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL1_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL1_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL1_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL1_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL1_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL1_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL1_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL1_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL1_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL1_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL1_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL1_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL1_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL1_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL1_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL1_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL1_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL1_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL1_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL1_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL1_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL1,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL1_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL1_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL1_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL1_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL1_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL1_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL1_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL1_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL1_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL1_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL1_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL1_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL1_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL1_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL1_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL1_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL1_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL1_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL1_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL1_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL1_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL1_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL1_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL1_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL1_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL1_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL1_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL1_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL1_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL1_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL1_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL1_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT1,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT1_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT1_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT1_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT1_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT1_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT1_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT1_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT1_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT1_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT1_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT1_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT1_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT1_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT1_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT1_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT1_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT1_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT1_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT1_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT1_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT1_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT1_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT1_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT1_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT1_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT1_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT1_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT1_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT1_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT1_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT1_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT1_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x1000)++0x07
|
|
line.long 0x00 "INDT1,General input register 1"
|
|
bitfld.long 0x00 31. " INDT1_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT1_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT1_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT1_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT1_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT1_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT1_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT1_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT1_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT1_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT1_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT1_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT1_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT1_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT1_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT1_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT1_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT1_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT1_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT1_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT1_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT1_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT1_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT1_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT1_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT1_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT1_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT1_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT1_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT1_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT1_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT1_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT1,Interrupt display register 1"
|
|
bitfld.long 0x04 31. " INTDT1_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT1_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT1_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT1_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT1_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT1_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT1_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT1_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT1_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT1_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT1_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT1_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT1_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT1_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT1_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT1_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT1_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT1_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT1_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT1_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT1_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT1_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT1_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT1_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT1_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT1_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT1_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT1_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT1_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT1_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT1_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT1_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x1000)++0x17
|
|
line.long 0x00 "INTCLR1,Interrupt clear register 1"
|
|
bitfld.long 0x00 31. " INTCLR1_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR1_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR1_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR1_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR1_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR1_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR1_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR1_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR1_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR1_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR1_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR1_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR1_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR1_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR1_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR1_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR1_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR1_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR1_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR1_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR1_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR1_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR1_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR1_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR1_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR1_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR1_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR1_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR1_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR1_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR1_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR1_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK1,Interrupt mask register 1"
|
|
bitfld.long 0x04 31. " INTMSK1_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK1_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK1_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK1_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK1_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK1_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK1_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK1_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK1_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK1_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK1_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK1_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK1_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK1_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK1_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK1_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK1_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK1_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK1_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK1_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK1_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK1_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK1_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK1_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK1_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK1_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK1_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK1_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK1_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK1_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK1_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK1_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR1,Interrupt mask clear register 1"
|
|
bitfld.long 0x08 31. " MSKCLR1_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR1_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR1_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR1_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR1_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR1_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR1_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR1_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR1_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR1_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR1_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR1_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR1_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR1_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR1_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR1_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR1_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR1_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR1_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR1_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR1_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR1_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR1_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR1_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR1_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR1_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR1_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR1_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR1_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR1_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR1_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR1_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG1,Positive/negative logic select register 1"
|
|
bitfld.long 0x0C 31. " POSNEG1_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG1_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG1_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG1_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG1_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG1_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG1_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG1_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG1_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG1_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG1_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG1_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG1_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG1_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG1_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG1_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG1_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG1_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG1_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG1_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG1_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG1_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG1_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG1_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG1_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG1_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG1_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG1_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG1_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG1_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG1_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG1_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL1,Edge/level select register 1"
|
|
bitfld.long 0x10 31. " EDGLEVEL1_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL1_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL1_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL1_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL1_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL1_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL1_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL1_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL1_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL1_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL1_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL1_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL1_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL1_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL1_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL1_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL1_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL1_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL1_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL1_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL1_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL1_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL1_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL1_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL1_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL1_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL1_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL1_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL1_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL1_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL1_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL1_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF1,Chattering prevention on/off register 1"
|
|
bitfld.long 0x14 3. " FILONOFF1_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF1_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF1_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF1_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO C"
|
|
group.long (0x00+0x2000)++0xB
|
|
line.long 0x00 "IOINTSEL2,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL2_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL2_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL2_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL2_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL2_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL2_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL2_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL2_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL2_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL2_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL2_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL2_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL2_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL2_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL2_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL2_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL2_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL2_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL2_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL2_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL2_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL2_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL2_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL2_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL2_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL2_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL2_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL2_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL2_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL2_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL2_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL2_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL2,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL2_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL2_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL2_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL2_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL2_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL2_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL2_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL2_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL2_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL2_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL2_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL2_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL2_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL2_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL2_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL2_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL2_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL2_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL2_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL2_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL2_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL2_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL2_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL2_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL2_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL2_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL2_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL2_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL2_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL2_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL2_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL2_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT2,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT2_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT2_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT2_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT2_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT2_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT2_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT2_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT2_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT2_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT2_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT2_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT2_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT2_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT2_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT2_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT2_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT2_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT2_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT2_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT2_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT2_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT2_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT2_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT2_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT2_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT2_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT2_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT2_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT2_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT2_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT2_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT2_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x2000)++0x07
|
|
line.long 0x00 "INDT2,General input register 2"
|
|
bitfld.long 0x00 31. " INDT2_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT2_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT2_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT2_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT2_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT2_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT2_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT2_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT2_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT2_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT2_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT2_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT2_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT2_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT2_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT2_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT2_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT2_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT2_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT2_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT2_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT2_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT2_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT2_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT2_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT2_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT2_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT2_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT2_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT2_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT2_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT2_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT2,Interrupt display register 2"
|
|
bitfld.long 0x04 31. " INTDT2_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT2_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT2_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT2_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT2_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT2_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT2_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT2_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT2_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT2_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT2_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT2_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT2_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT2_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT2_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT2_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT2_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT2_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT2_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT2_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT2_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT2_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT2_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT2_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT2_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT2_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT2_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT2_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT2_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT2_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT2_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT2_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x2000)++0x17
|
|
line.long 0x00 "INTCLR2,Interrupt clear register 2"
|
|
bitfld.long 0x00 31. " INTCLR2_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR2_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR2_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR2_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR2_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR2_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR2_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR2_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR2_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR2_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR2_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR2_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR2_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR2_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR2_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR2_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR2_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR2_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR2_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR2_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR2_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR2_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR2_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR2_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR2_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR2_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR2_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR2_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR2_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR2_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR2_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR2_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK2,Interrupt mask register 2"
|
|
bitfld.long 0x04 31. " INTMSK2_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK2_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK2_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK2_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK2_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK2_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK2_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK2_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK2_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK2_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK2_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK2_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK2_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK2_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK2_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK2_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK2_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK2_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK2_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK2_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK2_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK2_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK2_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK2_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK2_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK2_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK2_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK2_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK2_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK2_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK2_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK2_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR2,Interrupt mask clear register 2"
|
|
bitfld.long 0x08 31. " MSKCLR2_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR2_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR2_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR2_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR2_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR2_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR2_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR2_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR2_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR2_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR2_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR2_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR2_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR2_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR2_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR2_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR2_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR2_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR2_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR2_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR2_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR2_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR2_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR2_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR2_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR2_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR2_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR2_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR2_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR2_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR2_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR2_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG2,Positive/negative logic select register 2"
|
|
bitfld.long 0x0C 31. " POSNEG2_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG2_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG2_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG2_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG2_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG2_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG2_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG2_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG2_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG2_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG2_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG2_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG2_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG2_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG2_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG2_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG2_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG2_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG2_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG2_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG2_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG2_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG2_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG2_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG2_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG2_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG2_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG2_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG2_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG2_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG2_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG2_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL2,Edge/level select register 2"
|
|
bitfld.long 0x10 31. " EDGLEVEL2_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL2_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL2_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL2_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL2_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL2_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL2_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL2_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL2_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL2_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL2_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL2_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL2_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL2_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL2_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL2_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL2_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL2_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL2_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL2_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL2_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL2_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL2_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL2_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL2_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL2_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL2_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL2_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL2_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL2_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL2_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL2_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF2,Chattering prevention on/off register 2"
|
|
bitfld.long 0x14 3. " FILONOFF2_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF2_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF2_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF2_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO D"
|
|
group.long (0x00+0x3000)++0xB
|
|
line.long 0x00 "IOINTSEL3,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL3_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL3_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL3_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL3_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL3_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL3_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL3_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL3_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL3_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL3_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL3_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL3_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL3_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL3_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL3_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL3_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL3_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL3_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL3_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL3_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL3_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL3_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL3_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL3_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL3_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL3_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL3_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL3_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL3_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL3_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL3_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL3_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL3,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL3_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL3_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL3_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL3_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL3_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL3_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL3_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL3_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL3_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL3_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL3_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL3_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL3_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL3_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL3_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL3_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL3_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL3_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL3_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL3_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL3_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL3_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL3_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL3_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL3_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL3_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL3_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL3_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL3_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL3_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL3_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL3_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT3,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT3_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT3_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT3_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT3_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT3_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT3_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT3_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT3_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT3_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT3_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT3_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT3_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT3_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT3_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT3_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT3_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT3_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT3_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT3_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT3_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT3_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT3_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT3_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT3_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT3_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT3_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT3_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT3_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT3_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT3_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT3_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT3_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x3000)++0x07
|
|
line.long 0x00 "INDT3,General input register 3"
|
|
bitfld.long 0x00 31. " INDT3_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT3_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT3_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT3_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT3_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT3_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT3_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT3_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT3_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT3_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT3_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT3_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT3_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT3_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT3_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT3_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT3_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT3_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT3_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT3_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT3_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT3_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT3_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT3_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT3_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT3_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT3_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT3_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT3_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT3_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT3_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT3_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT3,Interrupt display register 3"
|
|
bitfld.long 0x04 31. " INTDT3_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT3_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT3_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT3_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT3_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT3_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT3_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT3_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT3_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT3_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT3_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT3_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT3_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT3_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT3_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT3_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT3_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT3_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT3_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT3_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT3_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT3_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT3_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT3_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT3_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT3_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT3_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT3_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT3_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT3_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT3_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT3_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x3000)++0x17
|
|
line.long 0x00 "INTCLR3,Interrupt clear register 3"
|
|
bitfld.long 0x00 31. " INTCLR3_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR3_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR3_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR3_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR3_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR3_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR3_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR3_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR3_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR3_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR3_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR3_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR3_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR3_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR3_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR3_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR3_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR3_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR3_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR3_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR3_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR3_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR3_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR3_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR3_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR3_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR3_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR3_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR3_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR3_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR3_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR3_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK3,Interrupt mask register 3"
|
|
bitfld.long 0x04 31. " INTMSK3_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK3_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK3_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK3_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK3_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK3_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK3_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK3_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK3_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK3_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK3_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK3_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK3_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK3_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK3_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK3_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK3_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK3_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK3_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK3_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK3_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK3_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK3_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK3_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK3_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK3_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK3_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK3_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK3_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK3_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK3_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK3_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR3,Interrupt mask clear register 3"
|
|
bitfld.long 0x08 31. " MSKCLR3_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR3_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR3_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR3_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR3_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR3_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR3_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR3_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR3_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR3_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR3_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR3_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR3_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR3_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR3_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR3_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR3_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR3_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR3_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR3_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR3_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR3_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR3_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR3_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR3_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR3_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR3_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR3_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR3_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR3_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR3_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR3_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG3,Positive/negative logic select register 3"
|
|
bitfld.long 0x0C 31. " POSNEG3_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG3_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG3_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG3_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG3_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG3_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG3_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG3_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG3_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG3_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG3_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG3_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG3_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG3_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG3_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG3_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG3_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG3_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG3_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG3_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG3_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG3_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG3_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG3_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG3_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG3_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG3_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG3_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG3_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG3_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG3_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG3_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL3,Edge/level select register 3"
|
|
bitfld.long 0x10 31. " EDGLEVEL3_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL3_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL3_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL3_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL3_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL3_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL3_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL3_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL3_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL3_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL3_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL3_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL3_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL3_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL3_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL3_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL3_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL3_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL3_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL3_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL3_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL3_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL3_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL3_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL3_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL3_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL3_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL3_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL3_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL3_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL3_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL3_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF3,Chattering prevention on/off register 3"
|
|
bitfld.long 0x14 3. " FILONOFF3_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF3_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF3_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF3_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO E"
|
|
group.long (0x00+0x4000)++0xB
|
|
line.long 0x00 "IOINTSEL4,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL4_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL4_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL4_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL4_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL4_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL4_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL4_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL4_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL4_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL4_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL4_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL4_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL4_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL4_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL4_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL4_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL4_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL4_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL4_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL4_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL4_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL4_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL4_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL4_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL4_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL4_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL4_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL4_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL4_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL4_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL4_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL4_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL4,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL4_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL4_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL4_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL4_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL4_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL4_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL4_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL4_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL4_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL4_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL4_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL4_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL4_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL4_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL4_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL4_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL4_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL4_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL4_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL4_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL4_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL4_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL4_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL4_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL4_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL4_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL4_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL4_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL4_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL4_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL4_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL4_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT4,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT4_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT4_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT4_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT4_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT4_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT4_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT4_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT4_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT4_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT4_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT4_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT4_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT4_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT4_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT4_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT4_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT4_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT4_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT4_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT4_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT4_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT4_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT4_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT4_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT4_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT4_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT4_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT4_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT4_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT4_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT4_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT4_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x4000)++0x07
|
|
line.long 0x00 "INDT4,General input register 4"
|
|
bitfld.long 0x00 31. " INDT4_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT4_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT4_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT4_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT4_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT4_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT4_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT4_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT4_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT4_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT4_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT4_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT4_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT4_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT4_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT4_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT4_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT4_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT4_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT4_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT4_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT4_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT4_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT4_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT4_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT4_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT4_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT4_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT4_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT4_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT4_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT4_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT4,Interrupt display register 4"
|
|
bitfld.long 0x04 31. " INTDT4_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT4_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT4_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT4_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT4_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT4_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT4_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT4_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT4_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT4_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT4_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT4_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT4_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT4_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT4_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT4_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT4_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT4_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT4_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT4_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT4_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT4_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT4_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT4_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT4_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT4_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT4_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT4_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT4_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT4_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT4_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT4_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x4000)++0x17
|
|
line.long 0x00 "INTCLR4,Interrupt clear register 4"
|
|
bitfld.long 0x00 31. " INTCLR4_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR4_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR4_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR4_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR4_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR4_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR4_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR4_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR4_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR4_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR4_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR4_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR4_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR4_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR4_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR4_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR4_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR4_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR4_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR4_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR4_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR4_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR4_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR4_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR4_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR4_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR4_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR4_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR4_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR4_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR4_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR4_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK4,Interrupt mask register 4"
|
|
bitfld.long 0x04 31. " INTMSK4_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK4_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK4_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK4_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK4_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK4_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK4_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK4_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK4_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK4_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK4_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK4_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK4_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK4_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK4_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK4_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK4_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK4_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK4_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK4_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK4_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK4_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK4_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK4_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK4_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK4_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK4_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK4_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK4_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK4_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK4_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK4_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR4,Interrupt mask clear register 4"
|
|
bitfld.long 0x08 31. " MSKCLR4_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR4_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR4_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR4_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR4_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR4_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR4_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR4_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR4_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR4_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR4_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR4_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR4_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR4_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR4_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR4_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR4_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR4_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR4_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR4_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR4_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR4_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR4_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR4_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR4_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR4_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR4_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR4_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR4_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR4_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR4_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR4_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG4,Positive/negative logic select register 4"
|
|
bitfld.long 0x0C 31. " POSNEG4_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG4_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG4_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG4_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG4_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG4_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG4_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG4_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG4_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG4_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG4_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG4_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG4_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG4_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG4_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG4_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG4_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG4_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG4_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG4_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG4_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG4_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG4_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG4_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG4_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG4_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG4_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG4_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG4_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG4_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG4_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG4_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL4,Edge/level select register 4"
|
|
bitfld.long 0x10 31. " EDGLEVEL4_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL4_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL4_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL4_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL4_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL4_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL4_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL4_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL4_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL4_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL4_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL4_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL4_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL4_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL4_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL4_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL4_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL4_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL4_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL4_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL4_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL4_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL4_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL4_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL4_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL4_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL4_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL4_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL4_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL4_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL4_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL4_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF4,Chattering prevention on/off register 4"
|
|
bitfld.long 0x14 3. " FILONOFF4_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF4_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF4_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF4_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO F"
|
|
group.long (0x00+0x5000)++0xB
|
|
line.long 0x00 "IOINTSEL5,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 31. " IOINTSEL5_31 ,General input/output or interrupt mode select for channel 31" "General I/O,Interrupt"
|
|
bitfld.long 0x00 30. " IOINTSEL5_30 ,General input/output or interrupt mode select for channel 30" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IOINTSEL5_29 ,General input/output or interrupt mode select for channel 29" "General I/O,Interrupt"
|
|
bitfld.long 0x00 28. " IOINTSEL5_28 ,General input/output or interrupt mode select for channel 28" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IOINTSEL5_27 ,General input/output or interrupt mode select for channel 27" "General I/O,Interrupt"
|
|
bitfld.long 0x00 26. " IOINTSEL5_26 ,General input/output or interrupt mode select for channel 26" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IOINTSEL5_25 ,General input/output or interrupt mode select for channel 25" "General I/O,Interrupt"
|
|
bitfld.long 0x00 24. " IOINTSEL5_24 ,General input/output or interrupt mode select for channel 24" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IOINTSEL5_23 ,General input/output or interrupt mode select for channel 23" "General I/O,Interrupt"
|
|
bitfld.long 0x00 22. " IOINTSEL5_22 ,General input/output or interrupt mode select for channel 22" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IOINTSEL5_21 ,General input/output or interrupt mode select for channel 21" "General I/O,Interrupt"
|
|
bitfld.long 0x00 20. " IOINTSEL5_20 ,General input/output or interrupt mode select for channel 20" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IOINTSEL5_19 ,General input/output or interrupt mode select for channel 19" "General I/O,Interrupt"
|
|
bitfld.long 0x00 18. " IOINTSEL5_18 ,General input/output or interrupt mode select for channel 18" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IOINTSEL5_17 ,General input/output or interrupt mode select for channel 17" "General I/O,Interrupt"
|
|
bitfld.long 0x00 16. " IOINTSEL5_16 ,General input/output or interrupt mode select for channel 16" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IOINTSEL5_15 ,General input/output or interrupt mode select for channel 15" "General I/O,Interrupt"
|
|
bitfld.long 0x00 14. " IOINTSEL5_14 ,General input/output or interrupt mode select for channel 14" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IOINTSEL5_13 ,General input/output or interrupt mode select for channel 13" "General I/O,Interrupt"
|
|
bitfld.long 0x00 12. " IOINTSEL5_12 ,General input/output or interrupt mode select for channel 12" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IOINTSEL5_11 ,General input/output or interrupt mode select for channel 11" "General I/O,Interrupt"
|
|
bitfld.long 0x00 10. " IOINTSEL5_10 ,General input/output or interrupt mode select for channel 10" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IOINTSEL5_9 ,General input/output or interrupt mode select for channel 9" "General I/O,Interrupt"
|
|
bitfld.long 0x00 8. " IOINTSEL5_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IOINTSEL5_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
bitfld.long 0x00 6. " IOINTSEL5_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IOINTSEL5_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
bitfld.long 0x00 4. " IOINTSEL5_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IOINTSEL5_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
bitfld.long 0x00 2. " IOINTSEL5_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IOINTSEL5_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
bitfld.long 0x00 0. " IOINTSEL5_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL5,General input/output switching register 0"
|
|
bitfld.long 0x04 31. " INOUTSEL5_31 ,General input or output mode select for channel 31" "Input,Output"
|
|
bitfld.long 0x04 30. " INOUTSEL5_30 ,General input or output mode select for channel 30" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INOUTSEL5_29 ,General input or output mode select for channel 29" "Input,Output"
|
|
bitfld.long 0x04 28. " INOUTSEL5_28 ,General input or output mode select for channel 28" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INOUTSEL5_27 ,General input or output mode select for channel 27" "Input,Output"
|
|
bitfld.long 0x04 26. " INOUTSEL5_26 ,General input or output mode select for channel 26" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INOUTSEL5_25 ,General input or output mode select for channel 25" "Input,Output"
|
|
bitfld.long 0x04 24. " INOUTSEL5_24 ,General input or output mode select for channel 24" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INOUTSEL5_23 ,General input or output mode select for channel 23" "Input,Output"
|
|
bitfld.long 0x04 22. " INOUTSEL5_22 ,General input or output mode select for channel 22" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INOUTSEL5_21 ,General input or output mode select for channel 21" "Input,Output"
|
|
bitfld.long 0x04 20. " INOUTSEL5_20 ,General input or output mode select for channel 20" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INOUTSEL5_19 ,General input or output mode select for channel 19" "Input,Output"
|
|
bitfld.long 0x04 18. " INOUTSEL5_18 ,General input or output mode select for channel 18" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INOUTSEL5_17 ,General input or output mode select for channel 17" "Input,Output"
|
|
bitfld.long 0x04 16. " INOUTSEL5_16 ,General input or output mode select for channel 16" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INOUTSEL5_15 ,General input or output mode select for channel 15" "Input,Output"
|
|
bitfld.long 0x04 14. " INOUTSEL5_14 ,General input or output mode select for channel 14" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INOUTSEL5_13 ,General input or output mode select for channel 13" "Input,Output"
|
|
bitfld.long 0x04 12. " INOUTSEL5_12 ,General input or output mode select for channel 12" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INOUTSEL5_11 ,General input or output mode select for channel 11" "Input,Output"
|
|
bitfld.long 0x04 10. " INOUTSEL5_10 ,General input or output mode select for channel 10" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INOUTSEL5_9 ,General input or output mode select for channel 9" "Input,Output"
|
|
bitfld.long 0x04 8. " INOUTSEL5_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INOUTSEL5_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
bitfld.long 0x04 6. " INOUTSEL5_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INOUTSEL5_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
bitfld.long 0x04 4. " INOUTSEL5_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INOUTSEL5_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
bitfld.long 0x04 2. " INOUTSEL5_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INOUTSEL5_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
bitfld.long 0x04 0. " INOUTSEL5_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT5,General output register 0"
|
|
bitfld.long 0x08 31. " OUTDT5_31 ,Output value for channel 31" "0,1"
|
|
bitfld.long 0x08 30. " OUTDT5_30 ,Output value for channel 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OUTDT5_29 ,Output value for channel 29" "0,1"
|
|
bitfld.long 0x08 28. " OUTDT5_28 ,Output value for channel 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OUTDT5_27 ,Output value for channel 27" "0,1"
|
|
bitfld.long 0x08 26. " OUTDT5_26 ,Output value for channel 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OUTDT5_25 ,Output value for channel 25" "0,1"
|
|
bitfld.long 0x08 24. " OUTDT5_24 ,Output value for channel 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OUTDT5_23 ,Output value for channel 23" "0,1"
|
|
bitfld.long 0x08 22. " OUTDT5_22 ,Output value for channel 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " OUTDT5_21 ,Output value for channel 21" "0,1"
|
|
bitfld.long 0x08 20. " OUTDT5_20 ,Output value for channel 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OUTDT5_19 ,Output value for channel 19" "0,1"
|
|
bitfld.long 0x08 18. " OUTDT5_18 ,Output value for channel 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 17. " OUTDT5_17 ,Output value for channel 17" "0,1"
|
|
bitfld.long 0x08 16. " OUTDT5_16 ,Output value for channel 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OUTDT5_15 ,Output value for channel 15" "0,1"
|
|
bitfld.long 0x08 14. " OUTDT5_14 ,Output value for channel 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OUTDT5_13 ,Output value for channel 13" "0,1"
|
|
bitfld.long 0x08 12. " OUTDT5_12 ,Output value for channel 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OUTDT5_11 ,Output value for channel 11" "0,1"
|
|
bitfld.long 0x08 10. " OUTDT5_10 ,Output value for channel 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OUTDT5_9 ,Output value for channel 9" "0,1"
|
|
bitfld.long 0x08 8. " OUTDT5_8 ,Output value for channel 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OUTDT5_7 ,Output value for channel 7" "0,1"
|
|
bitfld.long 0x08 6. " OUTDT5_6 ,Output value for channel 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OUTDT5_5 ,Output value for channel 5" "0,1"
|
|
bitfld.long 0x08 4. " OUTDT5_4 ,Output value for channel 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 3. " OUTDT5_3 ,Output value for channel 3" "0,1"
|
|
bitfld.long 0x08 2. " OUTDT5_2 ,Output value for channel 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OUTDT5_1 ,Output value for channel 1" "0,1"
|
|
bitfld.long 0x08 0. " OUTDT5_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x5000)++0x07
|
|
line.long 0x00 "INDT5,General input register 5"
|
|
bitfld.long 0x00 31. " INDT5_31 ,Value received through pin 31" "0,1"
|
|
bitfld.long 0x00 30. " INDT5_30 ,Value received through pin 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INDT5_29 ,Value received through pin 29" "0,1"
|
|
bitfld.long 0x00 28. " INDT5_28 ,Value received through pin 28" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INDT5_27 ,Value received through pin 27" "0,1"
|
|
bitfld.long 0x00 26. " INDT5_26 ,Value received through pin 26" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INDT5_25 ,Value received through pin 25" "0,1"
|
|
bitfld.long 0x00 24. " INDT5_24 ,Value received through pin 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INDT5_23 ,Value received through pin 23" "0,1"
|
|
bitfld.long 0x00 22. " INDT5_22 ,Value received through pin 22" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INDT5_21 ,Value received through pin 21" "0,1"
|
|
bitfld.long 0x00 20. " INDT5_20 ,Value received through pin 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INDT5_19 ,Value received through pin 19" "0,1"
|
|
bitfld.long 0x00 18. " INDT5_18 ,Value received through pin 18" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INDT5_17 ,Value received through pin 17" "0,1"
|
|
bitfld.long 0x00 16. " INDT5_16 ,Value received through pin 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INDT5_15 ,Value received through pin 15" "0,1"
|
|
bitfld.long 0x00 14. " INDT5_14 ,Value received through pin 14" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INDT5_13 ,Value received through pin 13" "0,1"
|
|
bitfld.long 0x00 12. " INDT5_12 ,Value received through pin 12" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INDT5_11 ,Value received through pin 11" "0,1"
|
|
bitfld.long 0x00 10. " INDT5_10 ,Value received through pin 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INDT5_9 ,Value received through pin 9" "0,1"
|
|
bitfld.long 0x00 8. " INDT5_8 ,Value received through pin 8" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INDT5_7 ,Value received through pin 7" "0,1"
|
|
bitfld.long 0x00 6. " INDT5_6 ,Value received through pin 6" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INDT5_5 ,Value received through pin 5" "0,1"
|
|
bitfld.long 0x00 4. " INDT5_4 ,Value received through pin 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INDT5_3 ,Value received through pin 3" "0,1"
|
|
bitfld.long 0x00 2. " INDT5_2 ,Value received through pin 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INDT5_1 ,Value received through pin 1" "0,1"
|
|
bitfld.long 0x00 0. " INDT5_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT5,Interrupt display register 5"
|
|
bitfld.long 0x04 31. " INTDT5_31 ,Input of an interrupt signal on the pin 31" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " INTDT5_30 ,Input of an interrupt signal on the pin 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTDT5_29 ,Input of an interrupt signal on the pin 29" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " INTDT5_28 ,Input of an interrupt signal on the pin 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTDT5_27 ,Input of an interrupt signal on the pin 27" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " INTDT5_26 ,Input of an interrupt signal on the pin 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTDT5_25 ,Input of an interrupt signal on the pin 25" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 24. " INTDT5_24 ,Input of an interrupt signal on the pin 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTDT5_23 ,Input of an interrupt signal on the pin 23" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " INTDT5_22 ,Input of an interrupt signal on the pin 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTDT5_21 ,Input of an interrupt signal on the pin 21" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " INTDT5_20 ,Input of an interrupt signal on the pin 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTDT5_19 ,Input of an interrupt signal on the pin 19" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " INTDT5_18 ,Input of an interrupt signal on the pin 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTDT5_17 ,Input of an interrupt signal on the pin 17" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " INTDT5_16 ,Input of an interrupt signal on the pin 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTDT5_15 ,Input of an interrupt signal on the pin 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " INTDT5_14 ,Input of an interrupt signal on the pin 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTDT5_13 ,Input of an interrupt signal on the pin 13" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " INTDT5_12 ,Input of an interrupt signal on the pin 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTDT5_11 ,Input of an interrupt signal on the pin 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " INTDT5_10 ,Input of an interrupt signal on the pin 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTDT5_9 ,Input of an interrupt signal on the pin 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " INTDT5_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTDT5_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " INTDT5_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTDT5_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " INTDT5_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTDT5_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " INTDT5_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTDT5_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " INTDT5_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x5000)++0x17
|
|
line.long 0x00 "INTCLR5,Interrupt clear register 5"
|
|
bitfld.long 0x00 31. " INTCLR5_31 ,Clears pin 31 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " INTCLR5_30 ,Clears pin 30 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " INTCLR5_29 ,Clears pin 29 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 28. " INTCLR5_28 ,Clears pin 28 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " INTCLR5_27 ,Clears pin 27 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " INTCLR5_26 ,Clears pin 26 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INTCLR5_25 ,Clears pin 25 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " INTCLR5_24 ,Clears pin 24 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " INTCLR5_23 ,Clears pin 23 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 22. " INTCLR5_22 ,Clears pin 22 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " INTCLR5_21 ,Clears pin 21 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " INTCLR5_20 ,Clears pin 20 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " INTCLR5_19 ,Clears pin 19 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " INTCLR5_18 ,Clears pin 18 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " INTCLR5_17 ,Clears pin 17 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16. " INTCLR5_16 ,Clears pin 16 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " INTCLR5_15 ,Clears pin 15 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " INTCLR5_14 ,Clears pin 14 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " INTCLR5_13 ,Clears pin 13 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " INTCLR5_12 ,Clears pin 12 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " INTCLR5_11 ,Clears pin 11 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " INTCLR5_10 ,Clears pin 10 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " INTCLR5_9 ,Clears pin 9 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " INTCLR5_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " INTCLR5_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " INTCLR5_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " INTCLR5_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 4. " INTCLR5_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INTCLR5_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR5_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INTCLR5_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR5_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK5,Interrupt mask register 5"
|
|
bitfld.long 0x04 31. " INTMSK5_31 ,Masks interrupt request for pin 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " INTMSK5_30 ,Masks interrupt request for pin 30" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " INTMSK5_29 ,Masks interrupt request for pin 29" "Masked,Not masked"
|
|
bitfld.long 0x04 28. " INTMSK5_28 ,Masks interrupt request for pin 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INTMSK5_27 ,Masks interrupt request for pin 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " INTMSK5_26 ,Masks interrupt request for pin 26" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " INTMSK5_25 ,Masks interrupt request for pin 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " INTMSK5_24 ,Masks interrupt request for pin 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " INTMSK5_23 ,Masks interrupt request for pin 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " INTMSK5_22 ,Masks interrupt request for pin 22" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " INTMSK5_21 ,Masks interrupt request for pin 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " INTMSK5_20 ,Masks interrupt request for pin 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " INTMSK5_19 ,Masks interrupt request for pin 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " INTMSK5_18 ,Masks interrupt request for pin 18" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 17. " INTMSK5_17 ,Masks interrupt request for pin 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " INTMSK5_16 ,Masks interrupt request for pin 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " INTMSK5_15 ,Masks interrupt request for pin 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " INTMSK5_14 ,Masks interrupt request for pin 14" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 13. " INTMSK5_13 ,Masks interrupt request for pin 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " INTMSK5_12 ,Masks interrupt request for pin 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " INTMSK5_11 ,Masks interrupt request for pin 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " INTMSK5_10 ,Masks interrupt request for pin 10" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 9. " INTMSK5_9 ,Masks interrupt request for pin 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " INTMSK5_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " INTMSK5_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " INTMSK5_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 5. " INTMSK5_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " INTMSK5_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " INTMSK5_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK5_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " INTMSK5_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK5_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR5,Interrupt mask clear register 5"
|
|
bitfld.long 0x08 31. " MSKCLR5_31 ,Clears mask for pin 31" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " MSKCLR5_30 ,Clears mask for pin 30" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " MSKCLR5_29 ,Clears mask for pin 29" "Not cleared,Cleared"
|
|
bitfld.long 0x08 28. " MSKCLR5_28 ,Clears mask for pin 28" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MSKCLR5_27 ,Clears mask for pin 27" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " MSKCLR5_26 ,Clears mask for pin 26" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " MSKCLR5_25 ,Clears mask for pin 25" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " MSKCLR5_24 ,Clears mask for pin 24" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MSKCLR5_23 ,Clears mask for pin 23" "Not cleared,Cleared"
|
|
bitfld.long 0x08 22. " MSKCLR5_22 ,Clears mask for pin 22" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " MSKCLR5_21 ,Clears mask for pin 21" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " MSKCLR5_20 ,Clears mask for pin 20" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MSKCLR5_19 ,Clears mask for pin 19" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " MSKCLR5_18 ,Clears mask for pin 18" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " MSKCLR5_17 ,Clears mask for pin 17" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " MSKCLR5_16 ,Clears mask for pin 16" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MSKCLR5_15 ,Clears mask for pin 15" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " MSKCLR5_14 ,Clears mask for pin 14" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " MSKCLR5_13 ,Clears mask for pin 13" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " MSKCLR5_12 ,Clears mask for pin 12" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MSKCLR5_11 ,Clears mask for pin 11" "Not cleared,Cleared"
|
|
bitfld.long 0x08 10. " MSKCLR5_10 ,Clears mask for pin 10" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " MSKCLR5_9 ,Clears mask for pin 9" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " MSKCLR5_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSKCLR5_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " MSKCLR5_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSKCLR5_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
bitfld.long 0x08 4. " MSKCLR5_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSKCLR5_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " MSKCLR5_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " MSKCLR5_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " MSKCLR5_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG5,Positive/negative logic select register 5"
|
|
bitfld.long 0x0C 31. " POSNEG5_31 ,Selects polarity for pin 31" "Positive,Negative"
|
|
bitfld.long 0x0C 30. " POSNEG5_30 ,Selects polarity for pin 30" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " POSNEG5_29 ,Selects polarity for pin 29" "Positive,Negative"
|
|
bitfld.long 0x0C 28. " POSNEG5_28 ,Selects polarity for pin 28" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " POSNEG5_27 ,Selects polarity for pin 27" "Positive,Negative"
|
|
bitfld.long 0x0C 26. " POSNEG5_26 ,Selects polarity for pin 26" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " POSNEG5_25 ,Selects polarity for pin 25" "Positive,Negative"
|
|
bitfld.long 0x0C 24. " POSNEG5_24 ,Selects polarity for pin 24" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " POSNEG5_23 ,Selects polarity for pin 23" "Positive,Negative"
|
|
bitfld.long 0x0C 22. " POSNEG5_22 ,Selects polarity for pin 22" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " POSNEG5_21 ,Selects polarity for pin 21" "Positive,Negative"
|
|
bitfld.long 0x0C 20. " POSNEG5_20 ,Selects polarity for pin 20" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " POSNEG5_19 ,Selects polarity for pin 19" "Positive,Negative"
|
|
bitfld.long 0x0C 18. " POSNEG5_18 ,Selects polarity for pin 18" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " POSNEG5_17 ,Selects polarity for pin 17" "Positive,Negative"
|
|
bitfld.long 0x0C 16. " POSNEG5_16 ,Selects polarity for pin 16" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " POSNEG5_15 ,Selects polarity for pin 15" "Positive,Negative"
|
|
bitfld.long 0x0C 14. " POSNEG5_14 ,Selects polarity for pin 14" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " POSNEG5_13 ,Selects polarity for pin 13" "Positive,Negative"
|
|
bitfld.long 0x0C 12. " POSNEG5_12 ,Selects polarity for pin 12" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " POSNEG5_11 ,Selects polarity for pin 11" "Positive,Negative"
|
|
bitfld.long 0x0C 10. " POSNEG5_10 ,Selects polarity for pin 10" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " POSNEG5_9 ,Selects polarity for pin 9" "Positive,Negative"
|
|
bitfld.long 0x0C 8. " POSNEG5_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " POSNEG5_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
bitfld.long 0x0C 6. " POSNEG5_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " POSNEG5_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
bitfld.long 0x0C 4. " POSNEG5_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " POSNEG5_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
bitfld.long 0x0C 2. " POSNEG5_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " POSNEG5_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
bitfld.long 0x0C 0. " POSNEG5_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL5,Edge/level select register 5"
|
|
bitfld.long 0x10 31. " EDGLEVEL5_31 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 31" "Level,Edge"
|
|
bitfld.long 0x10 30. " EDGLEVEL5_30 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 30" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 29. " EDGLEVEL5_29 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 29" "Level,Edge"
|
|
bitfld.long 0x10 28. " EDGLEVEL5_28 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 28" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 27. " EDGLEVEL5_27 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 27" "Level,Edge"
|
|
bitfld.long 0x10 26. " EDGLEVEL5_26 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 26" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EDGLEVEL5_25 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 25" "Level,Edge"
|
|
bitfld.long 0x10 24. " EDGLEVEL5_24 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 24" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 23. " EDGLEVEL5_23 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 23" "Level,Edge"
|
|
bitfld.long 0x10 22. " EDGLEVEL5_22 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 22" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 21. " EDGLEVEL5_21 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 21" "Level,Edge"
|
|
bitfld.long 0x10 20. " EDGLEVEL5_20 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 20" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 19. " EDGLEVEL5_19 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 19" "Level,Edge"
|
|
bitfld.long 0x10 18. " EDGLEVEL5_18 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 18" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EDGLEVEL5_17 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 17" "Level,Edge"
|
|
bitfld.long 0x10 16. " EDGLEVEL5_16 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 16" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 15. " EDGLEVEL5_15 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 15" "Level,Edge"
|
|
bitfld.long 0x10 14. " EDGLEVEL5_14 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 14" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 13. " EDGLEVEL5_13 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 13" "Level,Edge"
|
|
bitfld.long 0x10 12. " EDGLEVEL5_12 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 12" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 11. " EDGLEVEL5_11 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 11" "Level,Edge"
|
|
bitfld.long 0x10 10. " EDGLEVEL5_10 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 10" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 9. " EDGLEVEL5_9 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 9" "Level,Edge"
|
|
bitfld.long 0x10 8. " EDGLEVEL5_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 7. " EDGLEVEL5_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
bitfld.long 0x10 6. " EDGLEVEL5_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 5. " EDGLEVEL5_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
bitfld.long 0x10 4. " EDGLEVEL5_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 3. " EDGLEVEL5_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
bitfld.long 0x10 2. " EDGLEVEL5_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 1. " EDGLEVEL5_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
bitfld.long 0x10 0. " EDGLEVEL5_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF5,Chattering prevention on/off register 5"
|
|
bitfld.long 0x14 3. " FILONOFF5_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF5_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF5_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF5_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
tree "GPIO G"
|
|
group.long (0x00+0x6000)++0xB
|
|
line.long 0x00 "IOINTSEL6,General IO/interrupt switching register 0"
|
|
bitfld.long 0x00 8. " IOINTSEL6_8 ,General input/output or interrupt mode select for channel 8" "General I/O,Interrupt"
|
|
bitfld.long 0x00 7. " IOINTSEL6_7 ,General input/output or interrupt mode select for channel 7" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IOINTSEL6_6 ,General input/output or interrupt mode select for channel 6" "General I/O,Interrupt"
|
|
bitfld.long 0x00 5. " IOINTSEL6_5 ,General input/output or interrupt mode select for channel 5" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IOINTSEL6_4 ,General input/output or interrupt mode select for channel 4" "General I/O,Interrupt"
|
|
bitfld.long 0x00 3. " IOINTSEL6_3 ,General input/output or interrupt mode select for channel 3" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IOINTSEL6_2 ,General input/output or interrupt mode select for channel 2" "General I/O,Interrupt"
|
|
bitfld.long 0x00 1. " IOINTSEL6_1 ,General input/output or interrupt mode select for channel 1" "General I/O,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IOINTSEL6_0 ,General input/output or interrupt mode select for channel 0" "General I/O,Interrupt"
|
|
textline " "
|
|
line.long 0x04 "INOUTSEL6,General input/output switching register 0"
|
|
bitfld.long 0x04 8. " INOUTSEL6_8 ,General input or output mode select for channel 8" "Input,Output"
|
|
bitfld.long 0x04 7. " INOUTSEL6_7 ,General input or output mode select for channel 7" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INOUTSEL6_6 ,General input or output mode select for channel 6" "Input,Output"
|
|
bitfld.long 0x04 5. " INOUTSEL6_5 ,General input or output mode select for channel 5" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INOUTSEL6_4 ,General input or output mode select for channel 4" "Input,Output"
|
|
bitfld.long 0x04 3. " INOUTSEL6_3 ,General input or output mode select for channel 3" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INOUTSEL6_2 ,General input or output mode select for channel 2" "Input,Output"
|
|
bitfld.long 0x04 1. " INOUTSEL6_1 ,General input or output mode select for channel 1" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INOUTSEL6_0 ,General input or output mode select for channel 0" "Input,Output"
|
|
textline " "
|
|
line.long 0x08 "OUTDT6,General output register 0"
|
|
bitfld.long 0x08 8. " OUTDT6_8 ,Output value for channel 8" "0,1"
|
|
bitfld.long 0x08 7. " OUTDT6_7 ,Output value for channel 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 6. " OUTDT6_6 ,Output value for channel 6" "0,1"
|
|
bitfld.long 0x08 5. " OUTDT6_5 ,Output value for channel 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OUTDT6_4 ,Output value for channel 4" "0,1"
|
|
bitfld.long 0x08 3. " OUTDT6_3 ,Output value for channel 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OUTDT6_2 ,Output value for channel 2" "0,1"
|
|
bitfld.long 0x08 1. " OUTDT6_1 ,Output value for channel 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 0. " OUTDT6_0 ,Output value for channel 0" "0,1"
|
|
textline " "
|
|
rgroup.long (0x0C+0x6000)++0x07
|
|
line.long 0x00 "INDT6,General input register 6"
|
|
bitfld.long 0x00 8. " INDT6_8 ,Value received through pin 8" "0,1"
|
|
bitfld.long 0x00 7. " INDT6_7 ,Value received through pin 7" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INDT6_6 ,Value received through pin 6" "0,1"
|
|
bitfld.long 0x00 5. " INDT6_5 ,Value received through pin 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INDT6_4 ,Value received through pin 4" "0,1"
|
|
bitfld.long 0x00 3. " INDT6_3 ,Value received through pin 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INDT6_2 ,Value received through pin 2" "0,1"
|
|
bitfld.long 0x00 1. " INDT6_1 ,Value received through pin 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INDT6_0 ,Value received through pin 0" "0,1"
|
|
textline " "
|
|
line.long 0x04 "INTDT6,Interrupt display register 6"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INTDT6_8 ,Input of an interrupt signal on the pin 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " INTDT6_7 ,Input of an interrupt signal on the pin 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INTDT6_6 ,Input of an interrupt signal on the pin 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " INTDT6_5 ,Input of an interrupt signal on the pin 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTDT6_4 ,Input of an interrupt signal on the pin 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " INTDT6_3 ,Input of an interrupt signal on the pin 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INTDT6_2 ,Input of an interrupt signal on the pin 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " INTDT6_1 ,Input of an interrupt signal on the pin 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INTDT6_0 ,Input of an interrupt signal on the pin 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
group.long (0x14+0x6000)++0x17
|
|
line.long 0x00 "INTCLR6,Interrupt clear register 6"
|
|
bitfld.long 0x00 8. " INTCLR6_8 ,Clears pin 8 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 7. " INTCLR6_7 ,Clears pin 7 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INTCLR6_6 ,Clears pin 6 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " INTCLR6_5 ,Clears pin 5 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INTCLR6_4 ,Clears pin 4 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 3. " INTCLR6_3 ,Clears pin 3 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INTCLR6_2 ,Clears pin 2 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " INTCLR6_1 ,Clears pin 1 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " INTCLR6_0 ,Clears pin 0 bit in the Interrupt Display Register" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x04 "INTMSK6,Interrupt mask register 6"
|
|
bitfld.long 0x04 8. " INTMSK6_8 ,Masks interrupt request for pin 8" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " INTMSK6_7 ,Masks interrupt request for pin 7" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " INTMSK6_6 ,Masks interrupt request for pin 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " INTMSK6_5 ,Masks interrupt request for pin 5" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INTMSK6_4 ,Masks interrupt request for pin 4" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " INTMSK6_3 ,Masks interrupt request for pin 3" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " INTMSK6_2 ,Masks interrupt request for pin 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " INTMSK6_1 ,Masks interrupt request for pin 1" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " INTMSK6_0 ,Masks interrupt request for pin 0" "Masked,Not masked"
|
|
textline " "
|
|
line.long 0x08 "MSKCLR6,Interrupt mask clear register 6"
|
|
bitfld.long 0x08 8. " MSKCLR6_8 ,Clears mask for pin 8" "Not cleared,Cleared"
|
|
bitfld.long 0x08 7. " MSKCLR6_7 ,Clears mask for pin 7" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MSKCLR6_6 ,Clears mask for pin 6" "Not cleared,Cleared"
|
|
bitfld.long 0x08 5. " MSKCLR6_5 ,Clears mask for pin 5" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 4. " MSKCLR6_4 ,Clears mask for pin 4" "Not cleared,Cleared"
|
|
bitfld.long 0x08 3. " MSKCLR6_3 ,Clears mask for pin 3" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 2. " MSKCLR6_2 ,Clears mask for pin 2" "Not cleared,Cleared"
|
|
bitfld.long 0x08 1. " MSKCLR6_1 ,Clears mask for pin 1" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MSKCLR6_0 ,Clears mask for pin 0" "Not cleared,Cleared"
|
|
textline " "
|
|
line.long 0x0C "POSNEG6,Positive/negative logic select register 6"
|
|
bitfld.long 0x0C 8. " POSNEG6_8 ,Selects polarity for pin 8" "Positive,Negative"
|
|
bitfld.long 0x0C 7. " POSNEG6_7 ,Selects polarity for pin 7" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " POSNEG6_6 ,Selects polarity for pin 6" "Positive,Negative"
|
|
bitfld.long 0x0C 5. " POSNEG6_5 ,Selects polarity for pin 5" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " POSNEG6_4 ,Selects polarity for pin 4" "Positive,Negative"
|
|
bitfld.long 0x0C 3. " POSNEG6_3 ,Selects polarity for pin 3" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " POSNEG6_2 ,Selects polarity for pin 2" "Positive,Negative"
|
|
bitfld.long 0x0C 1. " POSNEG6_1 ,Selects polarity for pin 1" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " POSNEG6_0 ,Selects polarity for pin 0" "Positive,Negative"
|
|
textline " "
|
|
line.long 0x10 "EDGLEVEL6,Edge/level select register 6"
|
|
bitfld.long 0x10 8. " EDGLEVEL6_8 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 8" "Level,Edge"
|
|
bitfld.long 0x10 7. " EDGLEVEL6_7 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 7" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 6. " EDGLEVEL6_6 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 6" "Level,Edge"
|
|
bitfld.long 0x10 5. " EDGLEVEL6_5 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 5" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 4. " EDGLEVEL6_4 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 4" "Level,Edge"
|
|
bitfld.long 0x10 3. " EDGLEVEL6_3 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 3" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 2. " EDGLEVEL6_2 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 2" "Level,Edge"
|
|
bitfld.long 0x10 1. " EDGLEVEL6_1 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 1" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x10 0. " EDGLEVEL6_0 ,Selects the level or edge as detection conditions of the interrupt input signal for pin 0" "Level,Edge"
|
|
textline " "
|
|
line.long 0x14 "FILONOFF6,Chattering prevention on/off register 6"
|
|
bitfld.long 0x14 3. " FILONOFF6_3 ,Enables or disables the chattering prevention function 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FILONOFF6_2 ,Enables or disables the chattering prevention function 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FILONOFF6_1 ,Enables or disables the chattering prevention function 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " FILONOFF6_0 ,Enables or disables the chattering prevention function 0" "Disabled,Enabled"
|
|
textline " "
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "CPG (Clock Pulse Generator)"
|
|
base ad:0xFFC80000
|
|
width 11.
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FRQMR,Frequency display register"
|
|
bitfld.long 0x00 28.--31. " IFS ,IFS[0:3]" ",1/2 of the PLLA,?..."
|
|
bitfld.long 0x00 20.--23. " SFS ,Division ratio of SuperHyway clock (clks)" ",,,1/6 of the PLLA,1/8 of the PLLA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BFS ,Division ratio of external bus clock (CLKOUT)" ",,,,,,,,1/24 of the PLLA,1/32 of the PLLA,1/36 of the PLLA,?..."
|
|
bitfld.long 0x00 12.--15. " S4FS ,Division ratio of SuperHyway clock (clks4)" ",,,,,,1/16 of the PLLA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " S3FS ,Division ratio of SuperHyway clock (clks3)" ",,,,1/8 of the PLLA,?..."
|
|
bitfld.long 0x00 4.--7. " S1FS ,Division ratio of SuperHyway clock (clks1)" ",,,,,1/12 of the PLLA,1/16 of the PLLA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PFS ,Division ratio of peripheral clock (clkp)" ",,,,,,,,1/24 of the PLLA,1/32 of the PLLA,?..."
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "MSTPCR0,Module standby control register 0"
|
|
bitfld.long 0x00 30. " MSTP030 ,Controls the I2C0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 29. " MSTP029 ,Controls the I2C1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MSTP028 ,Controls the I2C2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 27. " MSTP027 ,Controls the I2C3 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MSTP026 ,Controls the SCIF0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 25. " MSTP025 ,Controls the SCIF1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTP024 ,Controls the SCIF2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 23. " MSTP023 ,Controls the SCIF3 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MSTP022 ,Controls the SCIF4 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 21. " MSTP021 ,Controls the SCIF5 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSTP019 ,Controls the HSCIF0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 18. " MSTP018 ,Controls the HSCIF1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSTP016 ,Controls the TMU0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 15. " MSTP015 ,Controls the TMU1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MSTP014 ,Controls the TMU2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 12. " MSTP012 ,Controls the SSI0 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MSTP011 ,Controls the SSI1 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 10. " MSTP010 ,Controls the SSI2 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MSTP009 ,Controls the SSI3 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 8. " MSTP008 ,Controls the SRU clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSTP007 ,Controls the HSPI0 to HSPI2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 6. " MSTP006 ,Controls the FM multiplex demodulator clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MSTP005 ,Controls the PWM0 to PWM6 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 3. " MSTP003 ,Controls the IR receiver clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MSTP002 ,Controls the speed-pulse I/F clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 1. " MSTP001 ,Controls the GYRO-ADC I/F clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTP000 ,Controls the GPS clock" "Supplied,Not supplied"
|
|
line.long 0x04 "MSTPCR1,Module standby control register 1"
|
|
bitfld.long 0x04 24. " MSTP124 ,Controls module standby of the IMP-X3" "Operate,Standby"
|
|
bitfld.long 0x04 23. " MSTP123 ,Controls module standby of the IMR-LSX1" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 22. " MSTP122 ,Controls module standby of the IMR-X0" "Operate,Standby"
|
|
bitfld.long 0x04 21. " MSTP121 ,Controls module standby of the IMR-X1" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 20. " MSTP120 ,Controls module standby of the VIN3" "Operate,Standby"
|
|
bitfld.long 0x04 16. " MSTP116 ,Controls module standby of the PCI-Express" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MSTP115 ,Controls module standby of the Serial-ATA" "Operate,Standby"
|
|
bitfld.long 0x04 14. " MSTP114 ,Controls module standby of the EthernetMAC" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MSTP113 ,Controls module standby of the Crypto Engine" "Operate,Standby"
|
|
bitfld.long 0x04 11. " MSTP111 ,Controls module standby of the SuperHyway-DMAC" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTP110 ,Controls module standby of the VIN0" "Operate,Standby"
|
|
bitfld.long 0x04 9. " MSTP109 ,Controls module standby of the VIN1" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 8. " MSTP108 ,Controls module standby of the VIN2" "Operate,Standby"
|
|
bitfld.long 0x04 7. " MSTP107 ,Controls module standby of the R-GP2D" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 5. " MSTP105 ,Controls module standby of the SGX543MP2" "Operate,Standby"
|
|
bitfld.long 0x04 4. " MSTP104 ,Controls module standby of the IMR-LSX0" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MSTP103 ,Controls module standby of the DU" "Operate,Standby"
|
|
bitfld.long 0x04 1. " MSTP101 ,Controls module standby of the USB - port 2" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MSTP100 ,Controls module standby of the USB - port 0 and 1" "Operate,Standby"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "MSTPCR3,Module standby control register 3"
|
|
bitfld.long 0x00 31. " MSTP331 ,Controls the MMC0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 30. " MSTP330 ,Controls the MMC1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MSTP326 ,Controls the MLBPLL clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 24. " MSTP324 ,Controls the MIM clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MSTP323 ,Controls the SDHI0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 22. " MSTP322 ,Controls the SDHI1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MSTP321 ,Controls the SDHI2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 20. " MSTP320 ,Controls the SDHI3 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSTP319 ,Controls the SGX control register clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 18. " MSTP318 ,Controls the IEB clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MSTP316 ,Controls the CAN0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 15. " MSTP315 ,Controls the CAN1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MSTP312 ,Controls the SSI4 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 11. " MSTP311 ,Controls the SSI5 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MSTP310 ,Controls the SSI6 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 9. " MSTP309 ,Controls the SSI7 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MSTP308 ,Controls the SSI8 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x00 7. " MSTP307 ,Controls the SSI9 clock" "Supplied,Not supplied"
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "MSTPCR4,Module standby control register 4"
|
|
bitfld.long 0x00 10. " MSTP410 ,Controls the ICB clock" "Operate,Standby"
|
|
bitfld.long 0x00 9. " MSTP409 ,Controls the TSG clock" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MSTP408 ,Controls the VPC clock" "Operate,Standby"
|
|
bitfld.long 0x00 3. " MSTP403 ,Controls the SLM clock" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MSTP402 ,Controls the MLB+ clock" "Operate,Standby"
|
|
bitfld.long 0x00 1. " MSTP401 ,Controls the SPU2F (Audio) clock" "Operate,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MSTP400 ,Controls the SPU2F (Voice) clock" "Operate,Standby"
|
|
line.long 0x04 "MSTPCR5,Module standby control register 5"
|
|
bitfld.long 0x04 31. " MSTP531 ,Controls the SRC0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 30. " MSTP530 ,Controls the SRC1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 29. " MSTP529 ,Controls the SRC2 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 28. " MSTP528 ,Controls the SRC3 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MSTP527 ,Controls the SRC4 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 26. " MSTP526 ,Controls the SRC5 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 25. " MSTP525 ,Controls the SRC6 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 24. " MSTP524 ,Controls the SRC7 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MSTP523 ,Controls the SRC8 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 22. " MSTP522 ,Controls the SRC9 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 21. " MSTP521 ,Controls the CTU00/CTU01/CTU02/CTU03/MIX0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 20. " MSTP520 ,Controls the CTU10/CTU11/CTU12/CTU13/MIX1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MSTP519 ,Controls the DVC0 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 18. " MSTP518 ,Controls the DVC1 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MSTP515 ,Controls the 2D-DMAC clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 14. " MSTP514 ,Controls the RVSP1C clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MSTP513 ,Controls the MERAM clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 10. " MSTP510 ,Controls the DISP clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 9. " MSTP509 ,Controls the TSIF1 clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 8. " MSTP508 ,Controls the TSIF0 clock" "Supplied,Not supplied"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MSTP506 ,Controls the JPU clock" "Supplied,Not supplied"
|
|
bitfld.long 0x04 1. " MSTP501 ,Controls the VDP1 clock" "Supplied,Not supplied"
|
|
line.long 0x08 "MSTPCR6,Module standby control register 6"
|
|
bitfld.long 0x08 1. " MSTP601 ,Controls the CoreSight clock" "Operate,Standby"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "MSTPCR7,Module standby control register 7"
|
|
in
|
|
rgroup.long 0x44++0x0B
|
|
line.long 0x00 "MSTPSR1,Module standby status register 1"
|
|
bitfld.long 0x00 24. " STBY124 ,Indicates the state of operation of the IMP-X3 module" "Operation,Standby/Stopped"
|
|
bitfld.long 0x00 23. " STBY123 ,Indicates the state of operation of the IMR-LSX1 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 22. " STBY122 ,Indicates the state of operation of the IMR-X0 module" "Operation,Standby"
|
|
bitfld.long 0x00 21. " STBY121 ,Indicates the state of operation of the IMR-X1 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 20. " STBY120 ,Indicates the state of operation of the VIN3 module" "Operation,Standby"
|
|
bitfld.long 0x00 16. " STBY116 ,Indicates the state of operation of the PCI-Express module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 15. " STBY115 ,Indicates the state of operation of the Serial-ATA module" "Operation,Standby"
|
|
bitfld.long 0x00 14. " STBY114 ,Indicates the state of operation of the EthernetMAC module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 13. " STBY113 ,Indicates the state of operation of the Crypto Engine module" "Operation,Standby"
|
|
bitfld.long 0x00 11. " STBY111 ,Indicates the state of operation of the SuperHyway-DMAC module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 10. " STBY110 ,Indicates the state of operation of the VIN0 module" "Operation,Standby"
|
|
bitfld.long 0x00 9. " STBY109 ,Indicates the state of operation of the VIN1 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 8. " STBY108 ,Indicates the state of operation of the VIN2 module" "Operation,Standby"
|
|
bitfld.long 0x00 7. " STBY107 ,Indicates the state of operation of the R-GP2D module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STBY105 ,Indicates the state of operation of the SGX543MP2 module" "Operation,Standby/Stopped"
|
|
bitfld.long 0x00 4. " STBY104 ,Indicates the state of operation of the IMR-LSX0 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STBY103 ,Indicates the state of operation of the display module" "Operation,Standby"
|
|
bitfld.long 0x00 1. " STBY101 ,Indicates the state of operation of the USB - port 2 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " STBY100 ,Indicates the state of operation of the USB - port 0 and 1 module" "Operation,Standby"
|
|
line.long 0x04 "MSTPSR4,Module standby status register 4"
|
|
bitfld.long 0x04 10. " STBY410 ,Indicates the state of operation of the ICB module" "Operation,Standby"
|
|
bitfld.long 0x04 9. " STBY409 ,Indicates the state of operation of the TSG module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 8. " STBY408 ,Indicates the state of operation of the VPC module" "Operation,Standby"
|
|
bitfld.long 0x04 3. " STBY403 ,Indicates the state of operation of the SLM module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 2. " STBY402 ,Indicates the state of operation of the MLB+ module" "Operation,Standby"
|
|
bitfld.long 0x04 1. " STBY401 ,Indicates the state of operation of the SPU2F1 module" "Operation,Standby"
|
|
textline " "
|
|
bitfld.long 0x04 0. " STBY400 ,Indicates the state of operation of the SPU2F2 module" "Operation,Standby"
|
|
line.long 0x08 "MSTPSR6,Module standby status register 6"
|
|
bitfld.long 0x08 1. " STBY601 ,Indicates the state of operation of the CoreSight module" "Operation,Standby"
|
|
width 11.
|
|
tree.end
|
|
tree "RESET/WDT (Resets and Watchdog Timer)"
|
|
base ad:0xFFCC0000
|
|
width 9.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "WDTST,Watchdog timer stop time register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE_VALUE ,Code Value"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDTST ,WDTCNT Overflow Time"
|
|
line.long 0x04 "WDTCSR,Watchdog timer control/status register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " CODE_VALUE ,Code Value"
|
|
bitfld.long 0x04 7. " TME ,Timer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " WT/IT ,Timer Mode Select" "Interval,Watchdog"
|
|
textline " "
|
|
bitfld.long 0x04 4. " WOVF ,Watchdog Timer Overflow" "No overflow,Overflowed"
|
|
bitfld.long 0x04 3. " IOVF ,Interval Timer Overflow" "No overflow,Overflowed"
|
|
line.long 0x08 "WDTBST,Watchdog timer base stop time register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " CODE_VALUE ,Code Value"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " WDTBST ,WDTBCNT Overflow Time"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "WDTCNT,Watchdog timer counter"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDTCNT ,Counter Value "
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "WDTBCNT,Watchdog timer base counter"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " WDTBCNT ,Counter Value"
|
|
if (((per.l((ad:0xFFCC0000+0x20)))&0x2)==0x2)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "MODEMR,Operating mode display register"
|
|
bitfld.long 0x00 22. " MPMD ,Value Latched from the MPMD Pin" "Emulation support,Independent chip/Boundary scan"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE21 ,Sub-JTAG function select signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MODE16_17 ,Boot mode" "0,1,2,3"
|
|
bitfld.long 0x00 14. " MODE14 ,LSI operating mode 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MODE13 ,29-/32-bit address mode" "29-bit,32-bit"
|
|
bitfld.long 0x00 11.--12. " MODE11_12 ,System PLL multiplication rate setting" "35.71 MHz,31.25 MHz,26.78 MHz,23.43 MHz"
|
|
bitfld.long 0x00 10. " MODE10 ,EXTAL/XTAL pin setting" "EXTAL,EXTAL/XTAL"
|
|
textline " "
|
|
bitfld.long 0x00 7. 9. " MODE07_09 ,Division into areas" "0,1,2,3"
|
|
bitfld.long 0x00 8. " MODE08 ,Big/little endian" "Big endian,Little endian"
|
|
bitfld.long 0x00 5.--6. " MODE05_06 ," ",8 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " MODE03_04 ,LSI operating mode 1" "0,1,2,3"
|
|
bitfld.long 0x00 2. " MODE02 ,External bus clock frequency setting" "/12,/18"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE01 ,Frequency mode setting" "800 MHz without overdrive,1000 MHz with overdrive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MODE00 ,Free-running/step-up mode" "Free-running,Step-up"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "MODEMR,Operating mode display register"
|
|
bitfld.long 0x00 22. " MPMD ,Value Latched from the MPMD Pin" "Emulation support mode,Independent chip/Boundary scan mode"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MODE21 ,Sub-JTAG function select signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " MODE16_17 ,Boot mode" "0,1,2,3"
|
|
bitfld.long 0x00 14. " MODE14 ,LSI operating mode 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MODE13 ,29-/32-bit address mode" "29-bit,32-bit"
|
|
bitfld.long 0x00 11.--12. " MODE11_12 ,System PLL multiplication rate setting" "38.09 MHz,33.33 MHz,28.57 MHz,25.00 MHz"
|
|
bitfld.long 0x00 10. " MODE10 ,EXTAL/XTAL pin setting" "EXTAL,EXTAL/XTAL"
|
|
textline " "
|
|
bitfld.long 0x00 7. 9. " MODE07_09 ,Division into areas" "0,1,2,3"
|
|
bitfld.long 0x00 8. " MODE08 ,Big/little endian" "Big endian,Little endian"
|
|
bitfld.long 0x00 5.--6. " MODE05_06 ," ",8 bits,16 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " MODE03_04 ,LSI operating mode 1" "0,1,2,3"
|
|
bitfld.long 0x00 2. " MODE02 ,External bus clock frequency setting" "/12,/16"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MODE01 ,Frequency mode setting" "800 MHz without overdrive,1000 MHz with overdrive"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MODE00 ,Free-running/step-up mode" "Free-running,Step-up"
|
|
endif
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "MRST0,Module reset register 0"
|
|
bitfld.long 0x00 30. " I2C0_R ,I2C0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 29. " I2C1_R ,I2C1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 28. " I2C2_R ,I2C2 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " I2C3_R ,I2C3 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 26. " SCIF0_R ,SCIF0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " SCIF1_R ,SCIF1 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SCIF2_R ,SCIF2 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " SCIF3_R ,SCIF3 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 22. " SCIF4_R ,SCIF4 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SCIF5_R ,SCIF5 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " HSCIF0_R ,HSCIF0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " HSCIF1_R ,HSCIF1 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TMR0_R ,TMR0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " TMR1_R ,TMR1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 14. " TMR2_R ,TMR2 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSI0_R ,SSI0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 11. " SSI1_R ,SSI1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 10. " SSI2_R ,SSI2 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSI3_R ,SSI3 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " SRU_R ,SRU Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " SPI_R ,SPI Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FMM_R ,FM multiplex demodulator Reset" "No reset,Reset"
|
|
bitfld.long 0x00 5. " PWM_R ,PWM Reset" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RCN_R ,RCN Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SPEED_R ,Seed Pulse IF Reset" "No reset,Reset"
|
|
bitfld.long 0x00 1. " GYROADC_R ,GYROADC IF Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " GPS_R ,GPS Reset" "No reset,Reset"
|
|
line.long 0x04 "MRST1,Module reset register 1"
|
|
bitfld.long 0x04 24. " IMPX3_R ,IMP-X3 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 23. " IMRLSX1_R ,IMR-LSX1 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 22. " IMRX0_R ,IMR-X0 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 21. " IMRX1_R ,IMR-X1 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 20. " VIN3_R ,VIN3 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 16. " PCIE_R ,PCI-Express Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 15. " SATA_R ,Serial-ATA Reset" "No reset,Reset"
|
|
bitfld.long 0x04 14. " ETHER_R ,ETHER Reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " CRIPTO_R ,Cripto Engine Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DMAC_R ,DMAC Reset" "No reset,Reset"
|
|
bitfld.long 0x04 10. " VIN0_R ,VIN0 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " VIN1_R ,VIN1 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 8. " VIN2_R ,VIN2 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 7. " G2D_R ,R-GP2 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 5. " SGX_R ,SGX540 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IMRX_R ,IMR-X Reset" "No reset,Reset"
|
|
bitfld.long 0x04 3. " DU_R ,DU Reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " USB_R ,USB Reset" "No reset,Reset"
|
|
line.long 0x08 "MRST2,Module reset register 2"
|
|
bitfld.long 0x08 0. " RESOUT ,/PRESETOUT" "Assert,Negate"
|
|
group.long 0x34++0x13
|
|
line.long 0x00 "MRST4,Module reset register 4"
|
|
bitfld.long 0x00 31. " MMC0_R ,MMC0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 30. " MMC1_R ,MMC1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 26. " MLBPLL_R ,MLBPLL Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MIM2_R ,MIM2 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " MIM1_R ,MIM1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " SDHI0_R ,SDHI0 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SDHI1_R ,SDHI1 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " SDHI2_R ,SDHI2 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 20. " SDHI3_R ,SDHI3 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IEB_R ,IEB Reset" "No reset,Reset"
|
|
bitfld.long 0x00 16. " CAN0_R ,CAN0 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " CAN1_R ,CAN1 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSI4_R ,SSI4 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 11. " SSI5_R ,SSI5 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 10. " SSI6_R ,SSI6 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SSI7_R ,SSI7 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " SSI8_R ,SSI8 Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " SSI9_R ,SSI9 Reset" "No reset,Reset"
|
|
line.long 0x04 "MRST5,Module reset register 5"
|
|
bitfld.long 0x04 15. " SSB0_R ,SSB0 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 14. " SSB1_R ,SSB1 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 13. " SSB2_R ,SSB2 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SSB3_R ,SSB3 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 11. " SSB4_R ,SSB4 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 10. " ICB_R ,ICB Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 9. " TSG_R ,TSG Reset" "No reset,Reset"
|
|
bitfld.long 0x04 8. " VPC_R ,VPC for VPU5HD2 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 3. " SLM_R ,SLM Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MLP_R ,MLB+ Reset" "No reset,Reset"
|
|
bitfld.long 0x04 1. " SPU2F1_R ,SPU2F1 Reset" "No reset,Reset"
|
|
bitfld.long 0x04 0. " SPU2F2_R ,SPU2F2 Reset" "No reset,Reset"
|
|
line.long 0x08 "MRST6,Module reset register 6"
|
|
bitfld.long 0x08 15. " 2DDMAC_R ,2D-DMAC Reset" "No reset,Reset"
|
|
bitfld.long 0x08 14. " RVSP1C_R ,RVSP1C Reset" "No reset,Reset"
|
|
bitfld.long 0x08 13. " MERAM_R ,MERAM Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DISP_R ,DISP Reset" "No reset,Reset"
|
|
bitfld.long 0x08 9. " TSIF1_R ,TSIF1 Reset" "No reset,Reset"
|
|
bitfld.long 0x08 8. " TSIF0_R ,TSIF0 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 6. " JPU_R ,JPU Reset" "No reset,Reset"
|
|
bitfld.long 0x08 1. " VDP1_R ,VDP1 Reset" "No reset,Reset"
|
|
line.long 0x0C "MRST7,Module reset register 7"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CODE_VALUE ,Code value"
|
|
bitfld.long 0x0C 3. " ARM_R ,ARM0 to ARM3 Reset" "No reset,Reset"
|
|
bitfld.long 0x0C 2. " ARM1_R ,ARM1 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " ARM2_R ,ARM2 Reset" "No reset,Reset"
|
|
bitfld.long 0x0C 0. " ARM3_R ,ARM3 Reset" "No reset,Reset"
|
|
line.long 0x10 "MRST8,Module reset register 8"
|
|
bitfld.long 0x10 28. " GPIO0_R ,GPIO0 Reset" "No reset,Reset"
|
|
bitfld.long 0x10 27. " GPIO1_R ,GPIO1 Reset" "No reset,Reset"
|
|
bitfld.long 0x10 26. " GPIO2_R ,GPIO2 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 25. " GPIO3_R ,GPIO3 Reset" "No reset,Reset"
|
|
bitfld.long 0x10 24. " GPIO4_R ,GPIO4 Reset" "No reset,Reset"
|
|
bitfld.long 0x10 23. " GPIO5_R ,GPIO5 Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 22. " GPIO6_R ,GPIO6 Reset" "No reset,Reset"
|
|
width 11.
|
|
tree.end
|
|
tree "HPBREG"
|
|
base ad:0xFE700000
|
|
width 8.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "BMSR,Boot mode state indication register"
|
|
bitfld.long 0x00 5.--6. " MD16_17 ,Boot Mode Indication" "Boot from area 0,Boot from ROM,?..."
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "GSR0,General register 0"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "AVECR,ARM reset vector address register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ARMVEC ,Reset vector for the ARM core"
|
|
bitfld.long 0x00 0.--3. " ARMVSIZE ,Size of the area to be allocated starting from the address specified by the ARMVEC bits" "4 K,8 K,16 K,32 K,64 K,128 K,256 K,512 K,1 M,2 M,4 M,8 M,16 M,32 M,64 M,128 M"
|
|
group.long 0x54++0x07
|
|
line.long 0x00 "APIDR,ARM SuperHyway PID control register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " APIDNS ,PID Setting for Non-Secure Access"
|
|
hexmask.long.byte 0x00 0.--7. 1. " APIDS ,PID Setting for Secure Access"
|
|
line.long 0x04 "APRIR,ARM SuperHyway priority control register"
|
|
bitfld.long 0x04 4.--7. " ARMHPRI ,High Priority Level Setting " ",,,,,,,,Standard,High,?..."
|
|
bitfld.long 0x04 0.--3. " ARMLPRI ,Low Priority Level Setting " ",,,,,,,,Standard,High,?..."
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "IISCR0,INTC2 interrupt select control register 0"
|
|
bitfld.long 0x00 31. " HPB-DMAC_CH37 ,Interrupt destination select from HPB-DMAC channel 37" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 30. " HPB-DMAC_CH36 ,Interrupt destination select from HPB-DMAC channel 36" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 29. " HPB-DMAC_CH35 ,Interrupt destination select from HPB-DMAC channel 35" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 28. " HPB-DMAC_CH34 ,Interrupt destination select from HPB-DMAC channel 34" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 27. " HPB-DMAC_CH33 ,Interrupt destination select from HPB-DMAC channel 33" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 26. " HPB-DMAC_CH32 ,Interrupt destination select from HPB-DMAC channel 32" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HPB-DMAC_CH31 ,Interrupt destination select from HPB-DMAC channel 31" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 24. " HPB-DMAC_CH30 ,Interrupt destination select from HPB-DMAC channel 30" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 23. " HPB-DMAC_CH29 ,Interrupt destination select from HPB-DMAC channel 29" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 22. " HPB-DMAC_CH28 ,Interrupt destination select from HPB-DMAC channel 28" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HPB-DMAC_CH27 ,Interrupt destination select from HPB-DMAC channel 27" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 20. " HPB-DMAC_CH26 ,Interrupt destination select from HPB-DMAC channel 26" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 19. " HPB-DMAC_CH25 ,Interrupt destination select from HPB-DMAC channel 25" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 18. " HPB-DMAC_CH24 ,Interrupt destination select from HPB-DMAC channel 24" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HPB-DMAC_CH23 ,Interrupt destination select from HPB-DMAC channel 23" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 16. " HPB-DMAC_CH22 ,Interrupt destination select from HPB-DMAC channel 22" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 15. " HPB-DMAC_CH21 ,Interrupt destination select from HPB-DMAC channel 21" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 14. " HPB-DMAC_CH20 ,Interrupt destination select from HPB-DMAC channel 20" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 13. " HPB-DMAC_CH19 ,Interrupt destination select from HPB-DMAC channel 19" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 12. " HPB-DMAC_CH18 ,Interrupt destination select from HPB-DMAC channel 18" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HPB-DMAC_CH17 ,Interrupt destination select from HPB-DMAC channel 17" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 10. " HPB-DMAC_CH16 ,Interrupt destination select from HPB-DMAC channel 16" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 9. " HPB-DMAC_CH15 ,Interrupt destination select from HPB-DMAC channel 15" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 8. " HPB-DMAC_CH14 ,Interrupt destination select from HPB-DMAC channel 14" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HPB-DMAC_CH13 ,Interrupt destination select from HPB-DMAC channel 13" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 6. " HPB-DMAC_CH12 ,Interrupt destination select from HPB-DMAC channel 12" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HPB-DMAC_CH11 ,Interrupt destination select from HPB-DMAC channel 11" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 4. " HPB-DMAC_CH[8:10] ,Interrupt destination select from HPB-DMAC channel 8 to 10" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HPB-DMAC_CH[6/7] ,Interrupt destination select from HPB-DMAC channel 6 to 7" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 2. " HPB-DMAC_CH[4/5] ,Interrupt destination select from HPB-DMAC channel 4 to 5" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HPB-DMAC_CH[2/3] ,Interrupt destination select from HPB-DMAC channel 2 to 3" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x00 0. " HPB-DMAC_CH[0/1] ,Interrupt destination select from HPB-DMAC channel 0 to 1" "Conveyed to MME,Conveyed to ARM"
|
|
line.long 0x04 "IISCR1,INTC2 interrupt select control register 1"
|
|
bitfld.long 0x04 29. " GPIO6 ,Interrupt destination select from GPIO6" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 28. " GPIO5 ,Interrupt destination select from GPIO5" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 27. " GPIO4 ,Interrupt destination select from GPIO4" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 26. " GPIO3 ,Interrupt destination select from GPIO3" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GPIO2 ,Interrupt destination select from GPIO2" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 24. " GPIO1 ,Interrupt destination select from GPIO1" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 23. " GPIO0 ,Interrupt destination select from GPIO0" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 22. " SDHI3 ,Interrupt destination select from SDHI3" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 21. " SDHI2 ,Interrupt destination select from SDHI2" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 20. " SDHI1 ,Interrupt destination select from SDHI1" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 19. " SDHI0 ,Interrupt destination select from SDHI0" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 18. " LBS-DMAC_CH2 ,Interrupt destination select from LBS-DMAC channel 2" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LBS-DMAC_CH1 ,Interrupt destination select from LBS-DMAC channel 1" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 16. " LBS-DMAC_CH0 ,Interrupt destination select from LBS-DMAC channel 0" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 15. " HSCIF1 ,Interrupt destination select from HSCIF1" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 14. " HSCIF0 ,Interrupt destination select from HSCIF0" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 13. " I2C3 ,Interrupt destination select from I2C3" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 12. " I2C2 ,Interrupt destination select from I2C2" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 11. " I2C1 ,Interrupt destination select from I2C1" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 10. " I2C0 ,Interrupt destination select from I2C0" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 9. " VIN3 ,Interrupt destination select from VIN3" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 8. " VIN2 ,Interrupt destination select from VIN2" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 7. " VIN1 ,Interrupt destination select from VIN1" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 6. " VIN0 ,Interrupt destination select from VIN0" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 5. " HPB-DMAC_CH43 ,Interrupt destination select from HPB-DMAC channel 43" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 4. " HPB-DMAC_CH42 ,Interrupt destination select from HPB-DMAC channel 42" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 3. " HPB-DMAC_CH41 ,Interrupt destination select from HPB-DMAC channel 41" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 2. " HPB-DMAC_CH40 ,Interrupt destination select from HPB-DMAC channel 40" "Conveyed to MME,Conveyed to ARM"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HPB-DMAC_CH39 ,Interrupt destination select from HPB-DMAC channel 39" "Conveyed to MME,Conveyed to ARM"
|
|
bitfld.long 0x04 0. " HPB-DMAC_CH38 ,Interrupt destination select from HPB-DMAC channel 38" "Conveyed to MME,Conveyed to ARM"
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|
line.long 0x08 "LCKR0,Lock register 0"
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|
bitfld.long 0x08 0. " LCKBIT0 ,Exclusive control bit[Reading/Writing]" "Not used/Released,Used/"
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|
line.long 0x0C "LCKR1,Lock register 1"
|
|
bitfld.long 0x0C 0. " LCKBIT1 ,Exclusive control bit[Reading/Writing]" "Not used/Released,Used/"
|
|
width 11.
|
|
tree.end
|
|
tree "INTC/INTC2 (Interrupt Controllers)"
|
|
base ad:0xFE800000
|
|
width 13.
|
|
tree "INTC"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ICR0,Interrupt Control Register 0"
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|
bitfld.long 0x00 31. " NMIL ,NMI Input Level" "Low,High"
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|
bitfld.long 0x00 30. " MAI ,MAI Interrupt Mask" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x00 25. " NMIB ,NMI Block Mode" "Retained,Not retained"
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|
bitfld.long 0x00 24. " NMIE ,NMI Edge Select" "Falling,Rising"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRLM0 ,IRL Pin Mode 0" "Encoded,Independent"
|
|
bitfld.long 0x00 21. " LVLMODE ,Source Retention Mode" "Retained,Not retained"
|
|
if (((per.l((ad:0xFE800000)))&0x800000)==0x0)
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|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ICR1,Interrupt Control Register 1"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "INTPRI,Interrupt Priority Register"
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|
else
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group.long 0x1C++0x03
|
|
line.long 0x00 "ICR1,Interrupt Control Register 1"
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|
bitfld.long 0x00 30.--31. " IRQ0S ,IRQ 0 Sense Select" "Falling,Rising,Low,High"
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|
bitfld.long 0x00 28.--29. " IRQ1S ,IRQ 1 Sense Select" "Falling,Rising,Low,High"
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|
textline " "
|
|
bitfld.long 0x00 26.--27. " IRQ2S ,IRQ 2 Sense Select" "Falling,Risinge,Low,High"
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|
bitfld.long 0x00 24.--25. " IRQ3S ,IRQ 3 Sense Select" "Falling,Rising,Low,High"
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|
group.long 0x10++0x03
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|
line.long 0x00 "INTPRI,Interrupt Priority Register"
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|
bitfld.long 0x00 28.--31. " IP0 ,IRQ0 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " IP1 ,IRQ1 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
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bitfld.long 0x00 20.--23. " IP2 ,IRQ2 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " IP3 ,IRQ3 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INTREQ,Interrupt Source Register"
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|
bitfld.long 0x00 31. " IR0 ,IRQ 0 Interrupt Request" "No interrupt,Interrupt"
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|
bitfld.long 0x00 30. " IR1 ,IRQ 1 Interrupt Request" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IR2 ,IRQ 2 Interrupt Request" "No interrupt,Interrupt"
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|
bitfld.long 0x00 28. " IR3 ,IRQ 3 Interrupt Request" "No interrupt,Interrupt"
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|
group.long 0x44++0x07
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|
line.long 0x00 "INTMSK0,Interrupt Mask Register 0"
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|
bitfld.long 0x00 31. " IM00 ,Individual interrupt source on IRQ0 mask" "Not masked,Masked"
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|
bitfld.long 0x00 30. " IM01 ,Individual interrupt source on IRQ1 mask" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x00 29. " IM02 ,Individual interrupt source on IRQ2 mask" "Not masked,Masked"
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|
bitfld.long 0x00 28. " IM03 ,Individual interrupt source on IRQ3 mask" "Not masked,Masked"
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line.long 0x04 "INTMSK1,Interrupt Mask Register 1"
|
|
bitfld.long 0x04 31. " IM10 ,Interrupt Mask For IRQ3-IRQ0" "Not masked,Masked"
|
|
wgroup.long 0x64++0x07
|
|
line.long 0x00 "INTMSKCLR0,Interrupt Mask Clear Register 0"
|
|
bitfld.long 0x00 31. " IC00 ,Clears Masking IRQ0" "No effect,Cleared"
|
|
bitfld.long 0x00 30. " IC01 ,Clears Masking IRQ1" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " IC02 ,Clears Masking IRQ2" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " IC03 ,Clears Masking IRQ3" "No effect,Cleared"
|
|
line.long 0x04 "INTMSKCLR1,Interrupt Mask Clear Register 1"
|
|
bitfld.long 0x04 31. " IC10 ,Clears Masking IRQ3-IRQ0" "No effect,Cleared"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "NMIFCR,NMI Flag Control Register"
|
|
bitfld.long 0x00 31. " NMIL ,NMI Level Input" "Low,High"
|
|
bitfld.long 0x00 16. " NMIFL ,NMI Flag [read/write]" "Not detected/Cleared,Detected/No effect"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "USERIMASK,User Interrupt Mask Level Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WKEY ,Write key - should be h'A5 when writing to the UIMASK bits"
|
|
bitfld.long 0x00 4.--7. " UIMASK ,Interrupt Mask Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "INTC 2"
|
|
group.long 0x2000++0x37
|
|
line.long 0x00 "INT2PRI0,Interrupt Priority Register 0"
|
|
bitfld.long 0x00 24.--28. " DU ,DU Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 16.--20. " TMU00 ,TMU00 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " TMU10 ,TMU10 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " TMU[20/21] ,TMU20/TMU21 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x04 "INT2PRI1,Interrupt Priority Register 1"
|
|
bitfld.long 0x04 24.--28. " TMU[30/40/50/51] ,TMU30/TMU40/TMU50/TMU51 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16.--20. " TMU[60/70/80] ,TMU60/TMU70/TMU80 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " SPU2FO/SPU2F1 ,SPU2FO/SPU2F1 (SPU0) Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--4. " SDHI[0:3] ,SDHI[0:3] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "INT2PRI2,Interrupt Priority Register 2"
|
|
bitfld.long 0x08 24.--28. " H-UDI/CORESIGHT ,H-UDI/CoreSight Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 16.--20. " SH-DMAC[0:3] ,SH-DMAC[0:3] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x08 8.--12. " USB2.0 ,USB2.0 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--4. " ARM0/ARM1 ,ARM0/ARM1 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0c "INT2PRI3,Interrupt Priority Register 3"
|
|
bitfld.long 0x0c 24.--28. " VIN[0:3] ,VIN[0:3] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0c 16.--20. " HSPI[0:2] ,HSPI[0:2] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0c 8.--12. " R-GP2/OVG ,R-GP2/OVG Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x0c 0.--4. " LBSC-ATA/LBSC-WTO ,LBSC-ATA/LBSC-WTO Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
line.long 0x10 "INT2PRI4,Interrupt Priority Register 4"
|
|
bitfld.long 0x10 24.--28. " SCIF[0:2] ,SCIF0-SCIF2 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x10 16.--20. " SCIF[3:5] ,SCIF3-SCIF5 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x10 8.--12. " HSCIF[0:2] ,HSCIF[0:2] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x10 0.--4. " GPS ,GPS Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x14 "INT2PRI5,Interrupt Priority Register 5"
|
|
bitfld.long 0x14 24.--28. " RCAN[0/1] ,RCAN0/RCAN1 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 16.--20. " LBSC-DMAC[0:2] ,LBSC-DMAC[0:2] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x14 8.--12. " TSC/SYS ,TSC/SYS Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x14 0.--4. " MMC[0/1] ,MMC[0/1] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x18 "INT2PRI6,Interrupt Priority Register 6"
|
|
bitfld.long 0x18 24.--28. " HPB-DMAC[0:19] ,HPB-DMAC[0:19] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 16.--20. " HPB-DMAC[20:27]/[39:41] ,HPB-DMAC[20:27]/[39:41] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x18 8.--12. " HPB-DMAC[28:38]/[42:43] ,HPB-DMAC[28:38]/[42:43] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 0.--4. " MIM/MLB/MLB+ ,MIM/MLB/MLB+ Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x1c "INT2PRI7,Interrupt Priority Register 7"
|
|
bitfld.long 0x1c 24.--28. " SRU/SRU_SSI/SLM ,SRU/SRU_SSI/SLM Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 16.--20. " I2C[0:3] ,I2C[0:3] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x1c 8.--12. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed_pulse Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x1c 0.--4. " EMUX2/JPU/MSTIF0/MSTIF1/TSIF0/TSIF1/TSG ,EMUX2/JPU/MSTIF0/MSTIF1/TSIF0/TSIF1/TSG Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x20 "INT2PRI8,Interrupt Priority Register 8"
|
|
bitfld.long 0x20 24.--28. " 12-BIT_ADC_IF/IEB ,12-bit ADC IF/IEB Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x20 16.--20. " SGX ,SGX Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x20 8.--12. " RESET/WDT ,RESET/WDT Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x20 0.--4. " FM_MULTIPLEX ,FM multiplex Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x24 "INT2PRI9,Interrupt Priority Register 9"
|
|
bitfld.long 0x24 24.--28. " FIVE_WIRES/RDS ,Five wires/RDS Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 16.--20. " VSP ,VSP Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x24 8.--12. " GPIO[0:6] ,GPIO[0:6] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 0.--4. " SPU2F0/SPU2F1 ,SPU2F0/SPU2F1 (SPU1) Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0x28 "INT2PRI10,Interrupt Priority Register 10"
|
|
bitfld.long 0x28 24.--28. " IMR-X[0:3] ,IMR-X[0:3] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x28 16.--20. " VDP ,VDP Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 8.--12. " INTER-CPU_INT ,Inter-CPU Interrupt Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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bitfld.long 0x28 0.--4. " DISP ,DISP Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x2C "INT2PRI11,Interrupt Priority Register 11"
|
|
bitfld.long 0x2C 24.--28. " DRC/DIC[0/1] ,DRC/DIC[0/1] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x2C 16.--20. " ETHER ,Ether Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--4. " SIM ,SIM Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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line.long 0x30 "INT2PRI12,Interrupt Priority Register 12"
|
|
bitfld.long 0x30 24.--28. " CRYPTO_ENGINE ,Crypto Engine Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x30 16.--20. " SATA ,SATA Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x30 8.--12. " PCI ,PCI Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x30 0.--4. " IMP-X3 ,IMP-X3 Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x34 "INT2PRI13,Interrupt Priority Register 13"
|
|
bitfld.long 0x34 24.--28. " GCU[0/1] ,GCU[0/1] Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x34 16.--20. " 2D-DMAC ,2D-DMAC Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x34 8.--12. " ICB ,ICB Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x34 0.--4. " ICB_MMU ,ICB_MMU Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
rgroup.long 0x2038++0x07
|
|
line.long 0x0 "INT2A0,Interrupt Source Register 0"
|
|
bitfld.long 0x0 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 29. " SDHI[0:3] ,SDHI[0:3] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 28. " FIVE_WIRE/TSIF[0/1]/TSG/RDS ,Five_wire/TSIF[0/1]/TSG/RDS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 27. " FM_MULTIPLEX ,FM_multiplex interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 26. " RESET/WDT ,RESET/WDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 24. " 12-BIT_ADC_IF/IEB ,12-bit_ADC_IF/IEB interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 23. " ARM[0/1]/INTER-CPU ,ARM[0/1]/Inter-CPU interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 21. " GPIO[0:6] ,GPIO0-6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 20. " TSC/SYS ,TSC/SYS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 19. " HPB-DMAC[0:43] ,HPB-DMAC0-43 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 18. " LBSC-DMAC[0:2] ,LBSC-DMAC0-2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 16. " GPS/SATA ,GPS/SATA interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 12. " R-GP2/SGX ,R-GP2/SGX interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 10. " VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] ,VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] interrupt" "No interrupt,Interrupt"
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|
bitfld.long 0x0 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 8. " USB2.0 ,USB2.0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 7. " SHDMAC[0:3] ,SuperHyway DMAC 0 - 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 5. " MMC/SIM ,MMC/SIM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 4. " SPU2F[0/1] ,SPU2F[0/1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 3. " I2C[0:3] ,I2C0 - 03 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 2. " TMU[30:80] ,TMU30 - 80 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0 1. " TMU[00:21] ,TMU00 - 21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0 0. " DU ,DU interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4 "INT2A1,Interrupt Source Register 1"
|
|
bitfld.long 0x4 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 29. " SDHI[0:3] ,SDHI[0:3] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 28. " FIVE_WIRE/TSIF[0/1]/TSG/RDS ,Five_wire/TSIF[0/1]/TSG/RDS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 27. " FM_MULTIPLEX ,FM_multiplex interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 26. " RESET/WDT ,RESET/WDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 24. " 12-BIT_ADC_IF/IEB ,12-bit_ADC_IF/IEB interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 23. " ARM[0/1]/INTER-CPU ,ARM[0/1]/Inter-CPU interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 21. " GPIO[0:6] ,GPIO0-6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 20. " TSC/SYS ,TSC/SYS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 19. " HPB-DMAC[0:43] ,HPB-DMAC0-43 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 18. " LBSC-DMAC[0:2] ,LBSC-DMAC0-2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 16. " GPS/SATA ,GPS/SATA interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 12. " R-GP2/SGX ,R-GP2/SGX interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 10. " VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] ,VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 8. " USB2.0 ,USB2.0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 7. " SHDMAC[0:3] ,SuperHyway DMAC 0 - 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 5. " MMC/SIM ,MMC/SIM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 4. " SPU2F[0/1] ,SPU2F[0/1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 3. " I2C[0:3] ,I2C0 - 03 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 2. " TMU[30:80] ,TMU30 - 80 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4 1. " TMU[00:21] ,TMU00 - 21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4 0. " DU ,DU interrupt" "No interrupt,Interrupt"
|
|
group.long 0x2040++0x03
|
|
line.long 0x00 "INT2MSKRG,Interrupt Mask Register"
|
|
bitfld.long 0x00 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " SDHI[0:3] ,SDHI[0:3] interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FIVE_WIRE/TSIF[0/1]/TSG/RDS ,Five_wire/TSIF[0/1]/TSG/RDS interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " FM_MULTIPLEX ,FM_multiplex interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RESET/WDT ,RESET/WDT interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " 12-BIT_ADC_IF/IEB ,12-bit_ADC_IF/IEB interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " ARM[0/1]/INTER-CPU ,ARM[0/1]/Inter-CPU interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " GPIO[0:6] ,GPIO0-6 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSC/SYS ,TSC/SYS interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " HPB-DMAC[0:43] ,HPB-DMAC0-43 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LBSC-DMAC[0:2] ,LBSC-DMAC0-2 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPS/SATA ,GPS/SATA interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " R-GP2/SGX ,R-GP2/SGX interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] ,VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB2.0 ,USB2.0 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " SHDMAC[0:3] ,SuperHyway DMAC 0 - 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MMC/SIM ,MMC/SIM interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPU2F[0/1] ,SPU2F[0/1] interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C[0:3] ,I2C0 - 03 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TMU[30-80] ,TMU30 - 80 interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " TMU[00-21] ,TMU00 - 21 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DU ,DU interrupt mask" "Not masked,Masked"
|
|
wgroup.long 0x2044++0x03
|
|
line.long 0x00 "INT2MSKCR,Interrupt Mask Clear Register"
|
|
bitfld.long 0x00 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " SDHI[0:3] ,SDHI[0:3] interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FIVE_WIRE/TSIF[0/1]/TSG/RDS ,Five_wire/TSIF[0/1]/TSG/RDS interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 27. " FM_MULTIPLEX ,FM_multiplex interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RESET/WDT ,RESET/WDT interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " 12-BIT_ADC_IF/IEB ,12-bit_ADC_IF/IEB interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " ARM[0/1]/INTER-CPU ,ARM[0/1]/Inter-CPU interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " GPIO[0:6] ,GPIO0-6 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSC/SYS ,TSC/SYS interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " HPB-DMAC[0:43] ,HPB-DMAC0-43 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LBSC-DMAC[0:2] ,LBSC-DMAC0-2 interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPS/SATA ,GPS/SATA interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " R-GP2/SGX ,R-GP2/SGX interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] ,VIN[0:3]/DRC[0/1]/DIC0/IMR-X[0:3] interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB2.0 ,USB2.0 interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " SHDMAC[0:3] ,SuperHyway DMAC 0 - 3 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " MMC/SIM ,MMC/SIM interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPU2F[0/1] ,SPU2F[0/1] interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " I2C[0:3] ,I2C0 - 03 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TMU[30-80] ,TMU30 - 80 interrupt mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " TMU[00-21] ,TMU00 - 21 interrupt mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DU ,DU interrupt mask clear" "No effect,Clear"
|
|
tree "Interrupt Detailed Source Registers"
|
|
rgroup.long 0x2048++0x27
|
|
line.long 0x00 "INT2B0,Interrupt Detailed Source Registers 0 (DU)"
|
|
bitfld.long 0x00 31. " TVR2 ,TVR2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " FRM2 ,FRM2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 27. " VBK2 ,VBK2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " ,RINT2" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RINT2 ,HBK2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TVR ,TVR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FRM ,FRM interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " VBK ,VBK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RINT ,RINT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HBK ,HBK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADC8 ,ADC8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " ADC7 ,ADC7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADC6 ,ADC6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " ADC5 ,ADC5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADC4 ,ADC4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " ADC3 ,ADC3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC2 ,ADC2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " ADC1 ,ADC1 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT2B1,Interrupt Detailed Source Registers 1 (TMU00-21)"
|
|
bitfld.long 0x04 3. " TICPI21 ,TICPI 21 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " TUNI20 ,TUNI 20 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TUNI10 ,TUNI 10 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TUNI00 ,TUNI 00 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "INT2B2,Interrupt Detailed Source Registers 2 (TMU30-80)"
|
|
bitfld.long 0x08 6. " TUNI80 ,TUNI 80 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 5. " TUNI70 ,TUNI 70 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TUNI60 ,TUNI 60 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 3. " TICPI51 ,TICPI 51 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TUNI50 ,TUNI 50 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 1. " TUNI40 ,TUNI 40 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TUNI30 ,TUNI 30 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "INT2B3,Interrupt Detailed Source Registers 3 (RESET, WDT)"
|
|
bitfld.long 0x0C 0. " RESET ,Reset interrupt" "No interrupt,Interrupt"
|
|
line.long 0x10 "INT2B4,Interrupt Detailed Source Registers 4 (USB2.0 h/f)"
|
|
bitfld.long 0x10 5. " USB-H1-EHCI ,USB-h1-EHCI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " USB-H1-OHCI ,USB-h1-OHCI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 2. " USB-F0 ,USB-f0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 1. " USB-H0-EHCI ,USB-h0-EHCI interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 0. " USB-H0-OHCI ,USB-h0-OHCI interrupt" "No interrupt,Interrupt"
|
|
line.long 0x14 "INT2B5,Interrupt Detailed Source Registers 5 (SIU2)"
|
|
bitfld.long 0x14 17. " SPV_IN2_IRQ_N[1] ,Spv_in2_irq_n[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " SPV_IN2_IRQ_N[0] ,Spv_in2_irq_n[0] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 1. " SPA_IN2_IRQ_N[1] ,Spa_in2_irq_n[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " SPA_IN2_IRQ_N[0] ,Spa_in2_irq_n[0] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x18 "INT2B6,Interrupt Detailed Source Registers 6 (FM multiplex)"
|
|
bitfld.long 0x18 15. " DB00_OUT15 ,DB00 out15 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 14. " DB00_OUT14 ,DB00 out14 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 13. " DB00_OUT13 ,DB00 out13 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 12. " DB00_OUT12 ,DB00 out12 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " DB00_OUT11 ,DB00 out11 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " DB00_OUT10 ,DB00 out10 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 9. " DB00_OUT9 ,DB00 out9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " DB00_OUT8 ,DB00 out8 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x1C "INT2B7,Interrupt Detailed Source Registers 7(MMC0/MMC1)"
|
|
bitfld.long 0x1C 18. " MMC2_ACC ,MMC2 ACC interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " MMC1_ERR ,MMC1 ERR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " MMC2_ACC ,MMC1 ACC out9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " MMC1_ERR ,MMC1 ERR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x20 "INT2B8,Interrupt Detailed Source Registers 8 (DEBUG (H-UDI)/CoreSight)"
|
|
bitfld.long 0x20 16. " CSDI ,CSDI interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " INTREQ ,INTREQ interrupt" "No interrupt,Interrupt"
|
|
line.long 0x24 "INT2B9,Interrupt Detailed Source Registers 9 (SHwy-DMAC0, 1)"
|
|
bitfld.long 0x24 31. " DMASE3 ,DMASE3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 29. " DMADE3 ,DMADE3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 24. " DMATE3 ,DMATE3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 23. " DMASE2 ,DMASE2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 21. " DMADE2 ,DMADE2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16. " DMATE2 ,DMATE2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 15. " DMASE1 ,DMASE1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 13. " DMADE1 ,DMADE1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 8. " DMATE1 ,DMATE1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 7. " DMASE0 ,DMASE0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 5. " DMADE0 ,DMADE0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 0. " DMATE0 ,DMATE0 interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x2070++0x03
|
|
hide.long 0x00 "INT2B10,Interrupt Detailed Source Registers 10"
|
|
rgroup.long 0x2074++0x73
|
|
line.long 0x00 "INT2B11,Interrupt Detailed Source Registers 11 (TSIF0/TSIF1/JPU/TSG/EMUX2/MSTIF0/MSTIF1)"
|
|
bitfld.long 0x00 25. " MST10_1 ,MST10_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " MST10_0 ,MST10_0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MST00_1 ,MST00_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " MST00_0 ,MST00_0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EMUX2_1 ,EMUX2_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " EMUX2_0 ,EMUX2_0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TSG ,TSG interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " JPU ,JPU interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TSIF1 ,TSIF1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TSIF0 ,TSIF0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT2B12,Interrupt Detailed Source Registers 12(12-bit ADC IF/RDS)"
|
|
bitfld.long 0x04 16. " RDS ,RDS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " ADI ,ADI interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "INT2B13,Interrupt Detailed Source Registers 13(REMOCON)"
|
|
bitfld.long 0x08 7. " RCDEND ,RCDEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 6. " RFREND ,RFREND interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "INT2B14,Interrupt Detailed Source Registers 14(SRU)"
|
|
bitfld.long 0x0C 1. " SYSTEM0 ,SYSTEM0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " DINT ,DINT interrupt" "No interrupt,Interrupt"
|
|
line.long 0x10 "INT2B15,Interrupt Detailed Source Registers 15(SSI[0:4])"
|
|
bitfld.long 0x10 19. " UIRQ_SSI4 ,UIRQ SSI4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 18. " OIRQ_SSI4 ,OIRQ SSI4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 17. " IIRQ_SSI4 ,IIRQ SSI4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 16. " DIRQ_SSI4 ,DIRQ SSI4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 15. " UIRQ_SSI3 ,UIRQ SSI3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 14. " OIRQ_SSI3 ,OIRQ SSI3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 13. " IIRQ_SSI3 ,IIRQ SSI3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 12. " DIRQ_SSI3 ,DIRQ SSI3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " UIRQ_SSI2 ,UIRQ SSI2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " OIRQ_SSI2 ,OIRQ SSI2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 9. " IIRQ_SSI2 ,IIRQ SSI2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " DIRQ_SSI2 ,DIRQ SSI2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " UIRQ_SSI1 ,UIRQ SSI1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " OIRQ_SSI1 ,OIRQ SSI1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 5. " IIRQ_SSI1 ,IIRQ SSI1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " DIRQ_SSI1 ,DIRQ SSI1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UIRQ_SSI0 ,UIRQ SSI0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " OIRQ_SSI0 ,OIRQ SSI0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 1. " IIRQ_SSI0 ,IIRQ SSI0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " DIRQ_SSI0 ,DIRQ SSI0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x14 "INT2B16,Interrupt Detailed Source Registers 16(SRU/SSI[5:9])"
|
|
bitfld.long 0x14 19. " UIRQ_SSI9 ,UIRQ SSI9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 18. " OIRQ_SSI9 ,OIRQ SSI9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 17. " IIRQ_SSI9 ,IIRQ SSI9 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 16. " DIRQ_SSI9 ,DIRQ SSI9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 15. " UIRQ_SSI8 ,UIRQ SSI8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 14. " OIRQ_SSI8 ,OIRQ SSI8 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 13. " IIRQ_SSI8 ,IIRQ SSI8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " DIRQ_SSI8 ,DIRQ SSI8 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 11. " UIRQ_SSI7 ,UIRQ SSI7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 10. " OIRQ_SSI7 ,OIRQ SSI7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 9. " IIRQ_SSI7 ,IIRQ SSI7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 8. " DIRQ_SSI7 ,DIRQ SSI7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 7. " UIRQ_SSI6 ,UIRQ SSI6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 6. " OIRQ_SSI6 ,OIRQ SSI6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 5. " IIRQ_SSI6 ,IIRQ SSI6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " DIRQ_SSI6 ,DIRQ SSI6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 3. " UIRQ_SSI5 ,UIRQ SSI5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 2. " OIRQ_SSI5 ,OIRQ SSI5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 1. " IIRQ_SSI5 ,IIRQ SSI5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " DIRQ_SSI5 ,DIRQ SSI5 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x18 "INT2B17,Interrupt Detailed Source Registers 17(ARM0/ARM1/Inter-CPU interrupt)"
|
|
bitfld.long 0x18 27. " IIR_SHX(ARM3) ,IIR_SHX(ARM3) interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 26. " IIR_SHX(ARM2) ,IIR_SHX(ARM2) interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 25. " IIR_SHX(ARM1) ,IIR_SHX(ARM1) interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 24. " IIR_SHX(ARM0) ,IIR_SHX(ARM0) interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 19. " IIR_ARM3 ,IIR_ARM3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 18. " IIR_ARM2 ,IIR_ARM2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 17. " IIR_ARM1 ,IIR_ARM1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 16. " IIR_ARM0 ,IIR_ARM0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 11. " CTIIRQ3_N ,CTIIRQ3_n interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 10. " CTIIRQ2_N ,CTIIRQ2_n interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 9. " CTIIRQ1_N ,CTIIRQ1_n interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 8. " CTIIRQ0_N ,CTIIRQ0_n interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PL310_INTR_P ,PL310_INTR_P interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 3. " PMUIRQ3_N ,Pmuirq3_n interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 2. " PMUIRQ2_N ,Pmuirq2_n interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " PMUIRQ1_N ,Pmuirq1_n interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 0. " PMUIRQ0_N ,Pmuirq0_n interrupt" "No interrupt,Interrupt"
|
|
line.long 0x1C "INT2B18,Interrupt Detailed Source Registers 18(VIN[0/1]/DRC/DIC[0/1]/IMR-X[0:3])"
|
|
bitfld.long 0x1C 31. " IMR3 ,IMR3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 30. " IMR2 ,IMR2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " IMR1 ,IMR1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 28. " IMR0 ,IMR0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " DIC1 ,DIC1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 26. " DIC0 ,DIC0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " DRC0 ,DRC0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 22. " SLS1 ,SLS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " EFS21 ,EFS21 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 20. " SIS21 ,SIS21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " FIS21 ,FIS21 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 18. " VFS1 ,VFS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " VRS1 ,VRS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 16. " FIS1 ,FIS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " CES1 ,CES1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 14. " SIS1 ,SIS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " EFS1 ,EFS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 12. " FOS1 ,FOS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " SLS0 ,SLS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " EFS20 ,EFS20 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " SIS20 ,SIS20 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " FIS20 ,FIS20 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " VFS0 ,VFS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " VRS0 ,VRS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " FIS0 ,FIS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " CES0 ,CES0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " SIS0 ,SIS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " EFS0 ,EFS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " FOS0 ,FOS0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x20 "INT2B19,Interrupt Detailed Source Registers 19(Speed Control/Speed-pulse IF)"
|
|
bitfld.long 0x20 16. " RSP_IN2_IRQ_N ,RSP_IN2_IRQ_N interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " VSPCNT ,VSPCNT interrupt" "No interrupt,Interrupt"
|
|
line.long 0x24 "INT2B20,Interrupt Detailed Source Registers 20(R-GP2/OVG)"
|
|
bitfld.long 0x24 19. " OVG_VAD_INT ,OVG_VAD_INT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 18. " OVG_GPM_INT ,OVG_GPM_INT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 17. " OVG_VAD_TRAP ,OVG_VAD_TRAP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16. " OVG_GPM_TRAP ,OVG_GPM_TRAP interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 3. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 2. " CER ,CER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 1. " INT ,INT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 0. " TRA ,TRA interrupt" "No interrupt,Interrupt"
|
|
line.long 0x28 "INT2B21,Interrupt Detailed Source Registers 21(Ether)"
|
|
bitfld.long 0x28 29. " BCR ,BCR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 28. " PRO ,PRO interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 27. " LNK ,LNK interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 26. " MPR ,MPR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 25. " FCD ,FCD interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 24. " TWB ,TWB interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 22. " TABT ,TABT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 21. " RABT ,RABT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 20. " RFRMER ,RFRMER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 19. " BER ,BER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 18. " MINT ,MINT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 17. " FTC ,FTC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 15. " TFE ,TFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 14. " FRC ,FRC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 13. " RDE ,RDE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 12. " RFE ,RFE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 11. " TINT4 ,TINT4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 10. " TINT3 ,TINT3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 9. " TINT2 ,TINT2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 8. " TINT1 ,TINT1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 7. " RINT8 ,RINT8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 4. " RINT5 ,RINT5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 3. " RINT4 ,RINT4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 2. " RINT3 ,RINT3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 1. " RINT2 ,RINT2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 0. " RINT1 ,RINT1 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x2C "INT2B22,Interrupt Detailed Source Registers 22(Five-wire System)"
|
|
bitfld.long 0x2C 2. " TXRDY ,TXRDY interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 1. " RXRDY ,RXRDY interrupt" "No interrupt,Interrupt"
|
|
line.long 0x30 "INT2B23,Interrupt Detailed Source Registers 23(HSPI[0:2])"
|
|
bitfld.long 0x30 8. " SPI2 ,SPI2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " SPI1 ,SPI1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 0. " SPI0 ,SPI0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x34 "INT2B24,Interrupt Detailed Source Registers 24(LBSC-ATA/LBSC-WTO/LBSC-DMAC[0:2])"
|
|
bitfld.long 0x34 10. " DTE2 ,DTE2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 9. " DTE1 ,DTE1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 8. " DTE0 ,DTE0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 4. " WTOE ,WTOE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 0. " ATTE ,ATTE interrupt" "No interrupt,Interrupt"
|
|
line.long 0x38 "INT2B25,Interrupt Detailed Source Registers 25(I2C0)"
|
|
bitfld.long 0x38 14. " MNR ,MNR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 13. " MAL ,MAL interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 12. " MST ,MST interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 11. " MDE ,MDE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 10. " MDT ,MDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 9. " MDR ,MDR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 8. " MAT ,MAT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 4. " SSR ,SSR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 3. " SDE ,SDE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 2. " SDT ,SDT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 1. " SDR ,SDR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 0. " SAR ,SAR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x3C "INT2B26,Interrupt Detailed Source Registers 26(RCAN0)"
|
|
bitfld.long 0x3C 6. " ERS_0 ,ERS_0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 5. " TXF_0 ,TXF_0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " TXM_0 ,TXM_0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 3. " RXF_0 ,RXF_0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x3C 2. " RXM1_0 ,RXM1_0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 1. " RXM0_0 ,RXM0_0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x40 "INT2B27,Interrupt Detailed Source Registers 27(MIM/MLB/MLB+)"
|
|
bitfld.long 0x40 26. " MLB_INT[MLB] ,MLB_INT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 25. " AHB_INT[1][MLB] ,AHB_INT[1] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 24. " AHB_INT[0][MLB] ,AHB_INT[0] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 20. " CINT[MLB] ,CINT [MLB] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 19. " SINT[MLB] ,SINT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 18. " SYSTEM[MLB] ,SYSTEM [MLB] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 17. " PACKET[MLB] ,PACKET [MLB] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 16. " FIFO[MLB] ,FIFO [MLB] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 9. " CINT[MLM] ,CINT [MLM] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 8. " SINT[MLM] ,SINT [MLM] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 7. " DTCP2[MLM] ,DTCP2 [MLM] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 6. " DTCP1[MLM] ,DTCP1 [MLM] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 5. " SYSTEM3[MLM] ,SYSTEM3 [MLM] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 4. " SYSTEM2[MLM] ,SYSTEM2 [MLM] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 3. " SYSTEM1[MLM] ,SYSTEM1 [MLM] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 2. " SRC[MLM] ,SRC [MLM] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 1. " SYSTEM_MEM[MLM] ,SYSTEM_MEM [MLM] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 0. " FIFO[MLM] ,FIFO [MLM] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x44 "INT2B28,Interrupt Detailed Source Registers 28(SCIF0)"
|
|
bitfld.long 0x44 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x48 "INT2B29,Interrupt Detailed Source Registers 29(SCIF1)"
|
|
bitfld.long 0x48 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x48 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x48 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x48 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x48 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x4C "INT2B30,Interrupt Detailed Source Registers 30(SCIF2)"
|
|
bitfld.long 0x4C 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4C 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4C 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x4C 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x4C 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x50 "INT2B31,Interrupt Detailed Source Registers 31(SCIF3)"
|
|
bitfld.long 0x50 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x50 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x50 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x50 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x50 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x50 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x50 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x50 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x54 "INT2B32,Interrupt Detailed Source Registers 32(SCIF4)"
|
|
bitfld.long 0x54 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x54 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x54 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x54 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x54 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x54 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x54 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x54 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x58 "INT2B33,Interrupt Detailed Source Registers 33(SCIF5)"
|
|
bitfld.long 0x58 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x58 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x58 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x58 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x58 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x58 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x58 1. " RDF ,RDF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x58 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x5C "INT2B34,Interrupt Detailed Source Registers 34 (I2C2)"
|
|
bitfld.long 0x5C 14. " MNR ,MNR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 13. " MAL ,MAL interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x5C 12. " MST ,MST interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 11. " MDE ,MDE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x5C 10. " MDT ,MDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 9. " MDR ,MDR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x5C 8. " MAT ,MAT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 4. " SSR ,SSR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x5C 3. " SDE ,SDE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 2. " SDT ,SDT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x5C 1. " SDR ,SDR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x5C 0. " SAR ,SAR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x60 "INT2B35,Interrupt Detailed Source Registers 35 (I2C3)"
|
|
bitfld.long 0x60 14. " MNR ,MNR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 13. " MAL ,MAL interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x60 12. " MST ,MST interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 11. " MDE ,MDE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x60 10. " MDT ,MDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 9. " MDR ,MDR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x60 8. " MAT ,MAT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 4. " SSR ,SSR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x60 3. " SDE ,SDE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 2. " SDT ,SDT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x60 1. " SDR ,SDR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x60 0. " SAR ,SAR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x64 "INT2B36,Interrupt Detailed Source Registers 36 (I2C1)"
|
|
bitfld.long 0x64 14. " MNR ,MNR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 13. " MAL ,MAL interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x64 12. " MST ,MST interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 11. " MDE ,MDE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x64 10. " MDT ,MDT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 9. " MDR ,MDR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x64 8. " MAT ,MAT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 4. " SSR ,SSR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x64 3. " SDE ,SDE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 2. " SDT ,SDT interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x64 1. " SDR ,SDR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x64 0. " SAR ,SAR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x68 "INT2B37,Interrupt Detailed Source Registers 37 (Crypto Engine)"
|
|
bitfld.long 0x68 0. " CRP_IN2_IRQ ,CRP_IN2_IRQ interrupt" "No interrupt,Interrupt"
|
|
line.long 0x6C "INT2B38,Interrupt Detailed Source Registers 38 (SGX)"
|
|
bitfld.long 0x6C 0. " SGX_IN2_IRQ ,SGX_IN2_IRQ interrupt" "No interrupt,Interrupt"
|
|
line.long 0x70 "INT2B39,Interrupt Detailed Source Registers 39 (RCAN1)"
|
|
bitfld.long 0x70 6. " ERS_1 ,ERS_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x70 5. " TXF_1 ,TXF_1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x70 4. " TXM_1 ,TXM_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x70 3. " RXF_1 ,RXF_1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x70 2. " RXM1_1 ,RXM1_1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x70 1. " RXM0_1 ,RXM0_1 interrupt" "No interrupt,Interrupt"
|
|
hgroup.long 0x20E8++0x03
|
|
hide.long 0x00 "INT2B40,Interrupt Detailed Source Registers 40"
|
|
rgroup.long 0x20E8++0x47
|
|
line.long 0x00 "INT2B41,Interrupt Detailed Source Registers 41(SIM)"
|
|
bitfld.long 0x00 4. " SIM_IN2_IRQ_N[3] ,Sim_in2_irq_n[3] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " SIM_IN2_IRQ_N[2] ,Sim_in2_irq_n[2] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SIM_IN2_IRQ_N[1] ,Sim_in2_irq_n[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " SIM_IN2_IRQ_N[0] ,Sim_in2_irq_n[0] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INT2B42,Interrupt Detailed Source Registers 42(HPB-DMAC[28:38], HPB-DMAC[42/43])"
|
|
bitfld.long 0x04 12. " DTE_43 ,DTE43 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " DTE_42 ,DTE42 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DTE_38 ,DTE38 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " DTE_37 ,DTE37 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DTE_36 ,DTE36 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " DTE_35 ,DTE35 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DTE_34 ,DTE34 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " DTE_33 ,DTE33 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DTE_32 ,DTE32 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " DTE_31 ,DTE31 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DTE_30 ,DTE30 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " DTE_29 ,DTE29 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DTE_28 ,DTE 28 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "INT2B43,Interrupt Detailed Source Registers 43(SDHI[0/3])"
|
|
bitfld.long 0x08 19. " SD_3[SDHI3] ,SD 3 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 18. " SD_2[SDHI3] ,SD 2 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SD_1[SDHI3] ,SD 1 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 16. " SD_0[SDHI3] ,SD 0 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SD_3[SDHI0] ,SD 3 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " SD_2[SDHI0] ,SD 2 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SD_1[SDHI0] ,SD 1 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " SD_0[SDHI0] ,SD 0 [SDHI0] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "INT2B44,Interrupt Detailed Source Registers 44(SDHI[1/2])"
|
|
bitfld.long 0x0C 19. " SD_3[SDHI2] ,SD 3 [SDHI2] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 18. " SD_2[SDHI2] ,SD 2 [SDHI2] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " SD_1[SDHI2] ,SD 1 [SDHI2] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 16. " SD_0[SDHI2] ,SD 0 [SDHI2] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SD_3[SDHI1] ,SD 3 [SDHI1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 2. " SD_2[SDHI1] ,SD 2 [SDHI1] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SD_1[SDHI1] ,SD 1 [SDHI1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x0C 0. " SD_0[SDHI1] ,SD 0 [SDHI1] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x10 "INT2B45,Interrupt Detailed Source Registers 45(SDHI[1/2])"
|
|
bitfld.long 0x10 14. " IETSR_TXS ,IETSR_TXS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 13. " IETSR_TXF ,IETSR_TXF interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 11. " IETSR_TXEAL ,IETSR_TXEAL interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 10. " IETSR_TXETTME ,IETSR_TXETTME interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 9. " IETSR_TXERO ,IETSR_TXERO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 8. " IETSR_TXEACK ,IETSR_TXEACK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 7. " IERSR_RXBSY ,IERSR_RXBSY interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 6. " IERSR_RXS ,IERSR_RXS interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 5. " IERSR_RXF ,IERSR_RXF interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 4. " IERSR_RXEDE ,IERSR_RXEDE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 3. " IERSR_RXEOVE ,IERSR_RXEOVE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 2. " IERSR_RXERTME ,IERSR_RXERTME interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 1. " IERSR_RXEDLE ,IERSR_RXEDLE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 0. " IERSR_RXEPE ,IERSR_RXEPE interrupt" "No interrupt,Interrupt"
|
|
line.long 0x14 "INT2B46,Interrupt Detailed Source Registers 46(GCU[0/1]/VDP/VSP/2D-DMAC/DISP/MERAM/MERAM)"
|
|
bitfld.long 0x14 21. " ICB_MMU ,ICB_MMU interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 20. " ICB ,ICBinterrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 16. " DISP ,DISP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 12. " 2D-DMAC ,2D-DMAC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 8. " VSP ,VSP interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 4. " VDP ,VDP interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x14 1. " GCU1 ,GCU1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x14 0. " GCU0 ,GCU0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x18 "INT2B47,Interrupt Detailed Source Registers 47(HPB-DMAC[0:27]/HPB-DMAC[39:41])"
|
|
bitfld.long 0x18 30. " DTE41 ,DTE41 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 29. " DTE40 ,DTE40 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 28. " DTE39 ,DTE39 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 27. " DTE27 ,DTE27 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 26. " DTE26 ,DTE26 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 25. " DTE25 ,DTE25 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 24. " DTE24 ,DTE24 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 23. " DTE23 ,DTE23 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 22. " DTE22 ,DTE22 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 21. " DTE21 ,DTE21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 20. " DTE20 ,DTE20 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 19. " DTE19 ,DTE19 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 18. " DTE18 ,DTE18 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 17. " DTE17 ,DTE17 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 16. " DTE16 ,DTE16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 15. " DTE15 ,DTE15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 14. " DTE14 ,DTE14 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 13. " DTE13 ,DTE13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 12. " DTE12 ,DTE12 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 11. " DTE11 ,DTE11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 10. " DTE10 ,DTE10 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 9. " DTE9 ,DTE9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 8. " DTE8 ,DTE8 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 7. " DTE7 ,DTE7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 6. " DTE6 ,DTE6 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 5. " DTE5 ,DTE5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 4. " DTE4 ,DTE4 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 3. " DTE3 ,DTE3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 2. " DTE2 ,DTE2 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x18 1. " DTE1 ,DTE1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x18 0. " DTE0 ,DTE0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x1C "INT2B48,Interrupt Detailed Source Registers 48(GPIO[0:6]/TSC/SYS)"
|
|
bitfld.long 0x1C 31. " TSC3 ,TSC3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 30. " TSC2 ,TSC2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " TSC1 ,TSC1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 28. " TSC0 ,TSC0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " SYS ,SYS interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 25. " 6_INTDT_08 ,6_INTDT 08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " 6_INTDT_07-00 ,6_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 23. " 5_INTDT_26-24 ,5_INTDT 26-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 22. " 5_INTDT_23-16 ,5_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 21. " 5_INTDT_15-08 ,5_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " 5_INTDT_07-00 ,5_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 19. " 4_INTDT_26-24 ,4_INTDT 26-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " 4_INTDT_23-16 ,4_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 17. " 4_INTDT_15-08 ,4_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 16. " 4_INTDT_07-00 ,4_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 15. " 3_INTDT_31-24 ,3_INTDT 31-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " 3_INTDT_23-16 ,3_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 13. " 3_INTDT_15-08 ,3_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " 3_INTDT_07-00 ,3_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 11. " 2_INTDT_31-24 ,2_INTDT 31-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " 2_INTDT_23-16 ,2_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 9. " 2_INTDT_15-08 ,2_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " 2_INTDT_07-00 ,2_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 7. " 1_INTDT_31-24 ,1_INTDT 31-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " 1_INTDT_23-16 ,1_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 5. " 1_INTDT_15-08 ,1_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " 1_INTDT_07-00 ,1_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 3. " 0_INTDT_31-24 ,0_INTDT 31-24 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " 0_INTDT_23-16 ,0_INTDT 23-16 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x1C 1. " 0_INTDT_15-08 ,0_INTDT 15-08 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " 0_INTDT_07-00 ,0_INTDT 07-00 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x20 "INT2B49,Interrupt Detailed Source Registers 49(GPS)"
|
|
bitfld.long 0x20 0. " GPS_INT ,GPS_INT interrupt" "No interrupt,Interrupt"
|
|
line.long 0x24 "INT2B50,Interrupt Detailed Source Registers 50(HSCIF1)"
|
|
bitfld.long 0x24 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x24 1. " RDF ,RDF interrupt interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x24 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x28 "INT2B51,Interrupt Detailed Source Registers 51(HSCIF0)"
|
|
bitfld.long 0x28 18. " TO ,TO interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 16. " ORER ,ORER interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 7. " ER ,ER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 6. " TEND ,TEND interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 5. " TDFE ,TDFE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 4. " BRK ,BRK interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x28 1. " RDF ,RDF interrupt interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x28 0. " DR ,DR interrupt" "No interrupt,Interrupt"
|
|
line.long 0x2C "INT2B52,Interrupt Detailed Source Registers 52(VIN[2/3])"
|
|
bitfld.long 0x2C 22. " SLS1 ,SLS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 21. " EFS21 ,EFS21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " SIS21 ,SIS21 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 19. " FIS21 ,FIS21 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 18. " VFS1 ,VFS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 17. " VRS1 ,VRS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 16. " FIS1 ,FIS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 15. " CES1 ,CES1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 14. " SIS1 ,SIS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 13. " EFS1 ,EFS1 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " FOS1 ,FOS1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 10. " SLS0 ,SLS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " EFS20 ,EFS20 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 8. " SIS20 ,SIS20 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " FIS20 ,FIS20 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 6. " VFS0 ,VFS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " VRS0 ,VRS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 4. " FIS0 ,FIS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " CES0 ,CES0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 2. " SIS0 ,SIS0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x2C 1. " EFS0 ,EFS0 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x2C 0. " FOS0 ,FOS0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x30 "INT2B53,Interrupt Detailed Source Registers 53(PCI-0)"
|
|
bitfld.long 0x30 23. " PCI_INT_MSI[19] ,PCI_INT_MSI[19] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 22. " PCI_INT_MSI[18] ,PCI_INT_MSI[18] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 21. " PCI_INT_MSI[17] ,PCI_INT_MSI[17] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 20. " PCI_INT_MSI[16] ,PCI_INT_MSI[16] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PCI_INT_MSI[15] ,PCI_INT_MSI[15] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 18. " PCI_INT_MSI[14] ,PCI_INT_MSI[14] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 17. " PCI_INT_MSI[13] ,PCI_INT_MSI[13] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 16. " PCI_INT_MSI[12] ,PCI_INT_MSI[12] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 15. " PCI_INT_MSI[11] ,PCI_INT_MSI[11] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 14. " PCI_INT_MSI[10] ,PCI_INT_MSI[10] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 13. " PCI_INT_MSI[9] ,PCI_INT_MSI[9] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 12. " PCI_INT_MSI[8] ,PCI_INT_MSI[8] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 11. " PCI_INT_MSI[7] ,PCI_INT_MSI[7] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 10. " PCI_INT_MSI[6] ,PCI_INT_MSI[6] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 9. " PCI_INT_MSI[5] ,PCI_INT_MSI[5] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 8. " PCI_INT_MSI[4] ,PCI_INT_MSI[4] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 7. " PCI_INT_MSI[3] ,PCI_INT_MSI[3] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 6. " PCI_INT_MSI[2] ,PCI_INT_MSI[2] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 5. " PCI_INT_MSI[1] ,PCI_INT_MSI[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 4. " PCI_INT_MSI[0] ,PCI_INT_MSI[0] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PCI_INT_INTX[3] ,PCI_INT_INTX[3] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 2. " PCI_INT_INTX[2] ,PCI_INT_INTX[2] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x30 1. " PCI_INT_INTX[1] ,PCI_INT_INTX[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x30 0. " PCI_INT_INTX[0] ,PCI_INT_INTX[0] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x34 "INT2B54,Interrupt Detailed Source Registers 54(PCI-1)"
|
|
bitfld.long 0x34 22. " PCI_INT_DMACE ,PCI_INT_DMACE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 21. " PCI_INT_DMAC0 ,PCI_INT_DMAC0 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PCI_INT_DMAC1 ,PCI_INT_DMAC1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 19. " PCI_INT_DMAC2 ,PCI_INT_DMAC2 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 18. " PCI_INT_DMAC3 ,PCI_INT_DMAC3 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 17. " PCI_INT_DMAC4 ,PCI_INT_DMAC4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 16. " PCI_INT_DMAC5 ,PCI_INT_DMAC5 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 15. " PCI_INT_DMAC6 ,PCI_INT_DMAC6 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 14. " PCI_INT_DMAC7 ,PCI_INT_DMAC7 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 13. " PCI_INT_MSGTXE ,PCI_INT_MSGTXE interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 12. " PCI_INT_MSGTX ,PCI_INT_MSGTX interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 11. " PCI_INT_MSI[31] ,PCI_INT_MSI[31] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 10. " PCI_INT_MSI[30] ,PCI_INT_MSI[30] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 9. " PCI_INT_MSI[29] ,PCI_INT_MSI[29] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 8. " PCI_INT_MSI[28] ,PCI_INT_MSI[28] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 7. " PCI_INT_MSI[27] ,PCI_INT_MSI[27] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 6. " PCI_INT_MSI[26] ,PCI_INT_MSI[26] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 5. " PCI_INT_MSI[25] ,PCI_INT_MSI[25] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PCI_INT_MSI[24] ,PCI_INT_MSI[24] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 3. " PCI_INT_MSI[23] ,PCI_INT_MSI[23] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 2. " PCI_INT_MSI[22] ,PCI_INT_MSI[22] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x34 1. " PCI_INT_MSI[21] ,PCI_INT_MSI[21] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x34 0. " PCI_INT_MSI[20] ,PCI_INT_MSI[20] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x38 "INT2B55,Interrupt Detailed Source Registers 55(PCI-2)"
|
|
bitfld.long 0x38 22. " PCI_INT_SERR ,PCI_INT_SERR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 21. " PCI_INT_FERR ,PCI_INT_FERR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PCI_INT_NFERR ,PCI_INT_NFERR interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 19. " PCI_INT_CERR ,PCI_INT_CERR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 18. " PCI_INT_POWER ,PCI_INT_POWER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 17. " PCI_INT_MES ,PCI_INT_MES interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 16. " PCI_INT_BW ,PCI_INT_BW interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 15. " PCI_INT_TXALLEMP ,PCI_INT_TXALLEMP interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 14. " PCI_INT_TE ,PCI_INT_TE interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 13. " PCI_INT_SC ,PCI_INT_SC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x38 10. " PCI_INT_MAC ,PCI_INT_MAC interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x38 9. " PCI_INT_PM ,PCI_INT_PM interrupt" "No interrupt,Interrupt"
|
|
line.long 0x3C "INT2B56,Interrupt Detailed Source Registers 56(IMP-X3)"
|
|
bitfld.long 0x3C 1. " IMP_IN2_IRQ[1] ,IMP_IN2_IRQ[1] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x3C 0. " IMP_IN2_IRQ[0] ,IMP_IN2_IRQ[0] interrupt" "No interrupt,Interrupt"
|
|
line.long 0x40 "INT2B57,Interrupt Detailed Source Registers 57(SATA)"
|
|
bitfld.long 0x40 11. " SATAINT ,SATAINT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 8. " SWERR ,SWERR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 6. " DNEND ,DNEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 5. " DEVTRM ,DEVTRM interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 4. " DEVINT ,DEVINT interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 2. " ERR ,ERR interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x40 1. " NEND ,NEND interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x40 0. " ACT ,ACT interrupt" "No interrupt,Interrupt"
|
|
line.long 0x44 "INT2B58,Interrupt Detailed Source Registers 58(SLM)"
|
|
bitfld.long 0x44 26. " SLM_IN2_IRQ[26] ,SLM_IN2_IRQ[26] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 25. " SLM_IN2_IRQ[25] ,SLM_IN2_IRQ[25] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 24. " SLM_IN2_IRQ[24] ,SLM_IN2_IRQ[24] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 23. " SLM_IN2_IRQ[23] ,SLM_IN2_IRQ[23] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 22. " SLM_IN2_IRQ[22] ,SLM_IN2_IRQ[22] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 21. " SLM_IN2_IRQ[21] ,SLM_IN2_IRQ[21] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 20. " SLM_IN2_IRQ[20] ,SLM_IN2_IRQ[20] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 19. " SLM_IN2_IRQ[19] ,SLM_IN2_IRQ[19] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 18. " SLM_IN2_IRQ[18] ,SLM_IN2_IRQ[18] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 17. " SLM_IN2_IRQ[17] ,SLM_IN2_IRQ[17] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 16. " SLM_IN2_IRQ[16] ,SLM_IN2_IRQ[16] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 15. " SLM_IN2_IRQ[15] ,SLM_IN2_IRQ[15] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 14. " SLM_IN2_IRQ[14] ,SLM_IN2_IRQ[14] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 13. " SLM_IN2_IRQ[13] ,SLM_IN2_IRQ[13] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 12. " SLM_IN2_IRQ[12] ,SLM_IN2_IRQ[12] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 11. " SLM_IN2_IRQ[11] ,SLM_IN2_IRQ[11] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 10. " SLM_IN2_IRQ[10] ,SLM_IN2_IRQ[10] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 9. " SLM_IN2_IRQ[9] ,SLM_IN2_IRQ[9] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 8. " SLM_IN2_IRQ[8] ,SLM_IN2_IRQ[8] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 7. " SLM_IN2_IRQ[7] ,SLM_IN2_IRQ[7] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 6. " SLM_IN2_IRQ[6] ,SLM_IN2_IRQ[6] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 5. " SLM_IN2_IRQ[5] ,SLM_IN2_IRQ[5] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 4. " SLM_IN2_IRQ[4] ,SLM_IN2_IRQ[4] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 3. " SLM_IN2_IRQ[3] ,SLM_IN2_IRQ[3] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 2. " SLM_IN2_IRQ[2] ,SLM_IN2_IRQ[2] interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x44 1. " SLM_IN2_IRQ[1] ,SLM_IN2_IRQ[1] interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x44 0. " SLM_IN2_IRQ[0] ,SLM_IN2_IRQ[0] interrupt" "No interrupt,Interrupt"
|
|
tree.end
|
|
group.long 0x2200++0x7
|
|
line.long 0x00 "INT2HMS,Interrupt Temporary High-Speed Mask Register"
|
|
bitfld.long 0x00 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " SDHI[0:3] ,SDHI[0:3] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FIVE-WIRE_SYSTEM/TSIF[0/1]/TSG/RDS ,Five-wire_system/TSIF[0/1]/TSG/RDS high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " FM_MULTIPLEX ,FM_multiplex high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RESET/WDT ,RESET/WDT high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 24. " 12-BIT_ADCIF/IEB ,12-bit_ADCIF/IEB high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " ARM[0/1]/INTER-CPU_INT ,ARM[0/1]/Inter-CPU_interrupt high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse_IF high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " GPIO[0:6] ,GPIO[0:6] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSC/SYS ,TSC/SYS high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 19. " HPB-DMAC[0:43] ,HPB-DMAC[0:43] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LBSC-DMAC[0:2] ,LBSC-DMAC[0:2] high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPS/SATA ,GPS/SATA high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " R-GP2/SGX ,R-GP2/SGX high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] ,VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB2.0 ,USB2.0 high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " SH-DMAC[0:3] ,SH-DMAC[0:3] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " MMC/SIM ,MMC/SIM high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPU2F0/SPU2F1 ,SPU2F0/SPU2F1 high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C[0:3] ,I2C[0:3] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TMU[30:80] ,TMU[30:80] high-speed mask" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " TMU[00:21] ,TMU[00:21] high-speed mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DU ,DU high-speed mask" "Not masked,Masked"
|
|
line.long 0x04 "INT2HMCMS,Interrupt Temporary High-Speed Mask Clear Mode Setting Register"
|
|
bitfld.long 0x04 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 29. " SDHI[0:3] ,SDHI[0:3] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 28. " FIVE-WIRE_SYSTEM/TSIF[0/1]/TSG/RDS ,Five-wire_system/TSIF[0/1]/TSG/RDS high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 27. " FM_MULTIPLEX ,FM_multiplex high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 26. " RESET/WDT ,RESET/WDT high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 24. " 12-BIT_ADCIF/IEB ,12-bit_ADCIF/IEB high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 23. " ARM[0/1]/INTER-CPU_INT ,ARM[0/1]/Inter-CPU_interrupt high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse_IF high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 21. " GPIO[0:6] ,GPIO[0:6] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 20. " TSC/SYS ,TSC/SYS high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 19. " HPB-DMAC[0:43] ,HPB-DMAC[0:43] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 18. " LBSC-DMAC[0:2] ,LBSC-DMAC[0:2] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 16. " GPS/SATA ,GPS/SATA high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 12. " R-GP2/SGX ,R-GP2/SGX high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 10. " VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] ,VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 8. " USB2.0 ,USB2.0 high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 7. " SH-DMAC[0:3] ,SH-DMAC[0:3] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 5. " MMC/SIM ,MMC/SIM high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 4. " SPU2F0/SPU2F1 ,SPU2F0/SPU2F1 high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 3. " I2C[0:3] ,I2C[0:3] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TMU[30:80] ,TMU[30:80] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
bitfld.long 0x04 1. " TMU[00:21] ,TMU[00:21] high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DU ,DU high-speed mask clear mode" "By writing to INT2HMCMS,Automatically"
|
|
wgroup.long 0x2208++0x3
|
|
line.long 0x00 "INT2HMCR,Interrupt Temporary High-Speed Mask Clear Register"
|
|
bitfld.long 0x00 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 29. " SDHI[0:3] ,SDHI[0:3] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FIVE-WIRE_SYSTEM/TSIF[0/1]/TSG/RDS ,Five-wire_system/TSIF[0/1]/TSG/RDS high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 27. " FM_MULTIPLEX ,FM_multiplex high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RESET/WDT ,RESET/WDT high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 24. " 12-BIT_ADCIF/IEB ,12-bit_ADCIF/IEB high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 23. " ARM[0/1]/INTER-CPU_INT ,ARM[0/1]/Inter-CPU_interrupt high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse_IF high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " GPIO[0:6] ,GPIO[0:6] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSC/SYS ,TSC/SYS high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " HPB-DMAC[0:43] ,HPB-DMAC[0:43] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LBSC-DMAC[0:2] ,LBSC-DMAC[0:2] high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPS/SATA ,GPS/SATA high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " R-GP2/SGX ,R-GP2/SGX high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] ,VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB2.0 ,USB2.0 high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " SH-DMAC[0:3] ,SH-DMAC[0:3] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " MMC/SIM ,MMC/SIM high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPU2F0/SPU2F1 ,SPU2F0/SPU2F1 high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " I2C[0:3] ,I2C[0:3] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TMU[30:80] ,TMU[30:80] high-speed mask clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " TMU[00:21] ,TMU[00:21] high-speed mask clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DU ,DU high-speed mask clear" "No effect,Clear"
|
|
group.long 0x220C++0x3
|
|
line.long 0x00 "INT2HMCRS,Interrupt Temporary High-Speed Mask Auto Clear Status Register"
|
|
bitfld.long 0x00 30. " GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP ,GCU[0/1]/2D-DMAC/MERAM/DISP/VSP/VDP high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 29. " SDHI[0:3] ,SDHI[0:3] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FIVE-WIRE_SYSTEM/TSIF[0/1]/TSG/RDS ,Five-wire_system/TSIF[0/1]/TSG/RDS high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 27. " FM_MULTIPLEX ,FM_multiplex high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RESET/WDT ,RESET/WDT high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 25. " MSTIF[0/1]/EMUX2/JPU ,MSTIF[0/1]/EMUX2/JPU high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 24. " 12-BIT_ADCIF/IEB ,12-bit_ADCIF/IEB high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 23. " ARM[0/1]/INTER-CPU_INT ,ARM[0/1]/Inter-CPU_interrupt high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SPEED_CONTROL/REMOCON/SPEED-PULSE ,Speed_control/REMOCON/Speed-pulse_IF high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 21. " GPIO[0:6] ,GPIO[0:6] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TSC/SYS ,TSC/SYS high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 19. " HPB-DMAC[0:43] ,HPB-DMAC[0:43] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LBSC-DMAC[0:2] ,LBSC-DMAC[0:2] high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 17. " RCAN[0/1]/PCI ,RCAN[0/1]/PCI high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPS/SATA ,GPS/SATA high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 15. " LBSC-ATA/WTO ,LBSC-ATA/WTO high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SCIF[0:5]/HSCIF[0/1] ,SCIF[0:5]/HSCIF[0/1] high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 13. " MIM/MLB/SRU/MLB+/SLM ,MIM/MLB/SRU/MLB+/SLM high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 12. " R-GP2/SGX ,R-GP2/SGX high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 11. " HSPI[0:2]/IMP-X3 ,HSPI[0:2]/IMP-X3 high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] ,VIN[0:3]/DRC/DIC0/DRC1/IMR-X[0:3] high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 9. " CRYPTO_ENGINE/ETHER ,Crypto_Engine/Ether high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 8. " USB2.0 ,USB2.0 high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 7. " SH-DMAC[0:3] ,SH-DMAC[0:3] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " H-UDI/CORESIGHT ,H-UDI/CoreSight high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " MMC/SIM ,MMC/SIM high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPU2F0/SPU2F1 ,SPU2F0/SPU2F1 high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 3. " I2C[0:3] ,I2C[0:3] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TMU[30:80] ,TMU[30:80] high-speed mask auto clear status" "Not generated,Generated"
|
|
bitfld.long 0x00 1. " TMU[00:21] ,TMU[00:21] high-speed mask auto clear status" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DU ,DU high-speed mask auto clear status" "Not generated,Generated"
|
|
group.long 0x2280++0x13
|
|
line.long 0x0 "INT2SMSKRG0,Interrupt Submask Register 0"
|
|
bitfld.long 0x00 31. " PL390 ,PL390 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " SGX ,SGX submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MFI(ARM3) ,MFI(ARM3) submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 28. " MFI(ARM2) ,MFI(ARM2) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MFI(ARM1) ,MFI(ARM1) submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " MFI(ARM0) ,MFI(ARM0) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 25. " REMOCON ,Remocon submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " 12-BIT_ADC_IF ,12-bit_ADC_IF submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SH-DMAC ,SuperHyway-DMAC submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 22. " CSD ,CSD submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DEBUG(H-UDI) ,DEBUG(H-UDI) submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " FM_MULTIPLEX ,FM_multiplex submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " USB2.0-F ,USB2.0-F submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " USB2.0-H_1 ,USB2.0-h_1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB2.0-H_0 ,USB2.0-h_0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " RESET/WDT ,RESET/WDT submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMU_80 ,TMU_80 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " TMU_70 ,TMU_70 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TMU_60 ,TMU_60 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " TMU_51 ,TMU_51 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TMU_50 ,TMU_50 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " TMU_40 ,TMU_40 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TMU_30 ,TMU_30 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " TMU_21 ,TMU_21 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TMU_20 ,TMU_20 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " TMU_10 ,TMU_10 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TMU_00 ,TMU_00 submask register" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " DU ,DU submask register" "Not masked,Masked"
|
|
line.long 0x4 "INT2SMSKRG1,Interrupt Submask Register 1"
|
|
bitfld.long 0x04 31. " SCIF_2 ,SCIF_2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " SCIF_1 ,SCIF_1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SCIF_0 ,SCIF_0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 28. " MLB+ ,MLB+ submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MLB ,MLB submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " MIM ,MIM submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 25. " RCAN_1 ,RCAN_1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " RCAN_0 ,RCAN_0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I2C_1 ,I2C_1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 22. " I2C_3 ,I2C_3 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I2C_2 ,I2C_2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " I2C_0 ,I2C_0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 18. " LBSWTO ,LBSWTO submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " LBSATA ,LBSATA submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 16. " HSPI_2 ,HSPI_2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " HSPI_1 ,HSPI_1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " HSPI_0 ,HSPI_0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 13. " FIVE-WIRE_SYSTEM ,Five-wire_system submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " MMC1 ,MMC1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " MMC0 ,MMC0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OVG ,OVG submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " R-GP2 ,R-GP2 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SPEED_CONTROL ,Speed_control submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 7. " VIN3 ,VIN3 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VIN2 ,VIN2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " VIN1 ,VIN1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VIN0 ,VIN0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " ARM3 ,ARM3 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ARM2 ,ARM2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " ARM1 ,ARM1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ARM0 ,ARM0 submask register" "Not masked,Masked"
|
|
line.long 0x8 "INT2SMSKRG2,Interrupt Submask Register 2"
|
|
bitfld.long 0x08 31. " DRC ,DRC submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " HPB-DMAC43_(P14BUS) ,HPB-DMAC43 (P14BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HPB-DMAC[37/38]_(P11BUS) ,HPB-DMAC[37/38] (P11BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 28. " HPB-DMAC[39:41]_(P12BUS) ,HPB-DMAC[39:41] (P12BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HPB-DMAC[28:36/42]_(P10BUS) ,HPB-DMAC[28:36/42] (P10BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " HPB-DMAC[25:27]_(P9BUS) ,HPB-DMAC[25:27] (P9BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HPB-DMAC24_(P8BUS) ,HPB-DMAC24 (P8BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " HPB-DMAC[21:23]_(P7BUS) ,HPB-DMAC[21:23] (P7BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HPB-DMAC20_(P6BUS) ,HPB-DMAC20 (P6BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 22. " HPB-DMAC[16:19]_(P5BUS) ,HPB-DMAC[16:19] (P5BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HPB-DMAC[14/15]_(P3BUS) ,HPB-DMAC[14/15] (P3BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " HPB-DMAC[11:13]_(P4BUS) ,HPB-DMAC[11:13] (P4BUS) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HPB-DMAC[0:10]_(P2BUS) ,HPB-DMAC[0:10] (P2BUS) submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " RDS ,RDS submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IEB ,IEB submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 16. " SDHI2 ,SDHI2 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SDHI3 ,SDHI3 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " SDHI1 ,SDHI1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SDHI0 ,SDHI0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " PCI-2 ,PCI-2 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PCI-1 ,PCI-1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " PCI-0 ,PCI-0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SATA ,SATA submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " LBSC-DMAC2 ,LBSC-DMAC2 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " LBSC-DMAC1 ,LBSC-DMAC1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " LBSC-DMAC0 ,LBSC-DMAC0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SIM ,SIM submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " HSCIF_1 ,HSCIF_1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HSCIF_0 ,HSCIF_0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " SCIF_5 ,SCIF_5 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SCIF_4 ,SCIF_4 submask register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " SCIF_3 ,SCIF_3 submask register" "Not masked,Masked"
|
|
line.long 0xC "INT2SMSKRG3,Interrupt Submask Register 3"
|
|
bitfld.long 0x0C 31. " IMP-X3[0] ,IMP-X3[0] submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 29. " SPEED-PULSE_IF ,Speed-pulse_IF submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " TSG ,TSG submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 27. " GPS ,GPS submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " CRYPTO_ENGINE ,Crypto_Engine submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 25. " ETHER ,Ether submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " GPIO6 ,GPIO6 submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 23. " GPIO5 ,GPIO5 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " GPIO4 ,GPIO4 submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 21. " GPIO3 ,GPIO3 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " GPIO2 ,GPIO2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 19. " GPIO1 ,GPIO1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " GPIO0 ,GPIO0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 17. " SLM ,SLM submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SRU(SSI9) ,SRU(SSI9) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 15. " SRU(SSI8) ,SRU(SSI8) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " SRU(SSI7) ,SRU(SSI7) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 13. " SRU(SSI6) ,SRU(SSI6) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SRU(SSI5) ,SRU(SSI5) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 11. " SRU(SSI4) ,SRU(SSI4) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " SRU(SSI3) ,SRU(SSI3) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " SRU(SSI2) ,SRU(SSI2) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " SRU(SSI1) ,SRU(SSI1) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 7. " SRU(SSI0) ,SRU(SSI0) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SRU ,SRU submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " SPU2F1(SPU1) ,SPU2F1(SPU1) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " SPU2F1(SPU0) ,SPU2F1(SPU0) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 3. " SPU2F0(SPU1) ,SPU2F0(SPU1) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SPU2F0(SPU0) ,SPU2F0(SPU0) submask register" "Not masked,Masked"
|
|
bitfld.long 0x0C 1. " DIC1 ,DIC1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " DIC0 ,DIC0 submask register" "Not masked,Masked"
|
|
line.long 0x10 "INT2SMSKRG4,Interrupt Submask Register 4"
|
|
bitfld.long 0x10 21. " SYS ,SYS submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 20. " TSC ,TSC submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 19. " MERAM(ICB_MMU) ,MERAM(ICB_MMU) submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 18. " MERAM(ICB) ,MERAM(ICB) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 17. " 2D-DMAC ,2D-DMAC submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 16. " VDP ,VDP submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 15. " VSP ,VSP submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 14. " GCU1 ,GCU1 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 13. " GCU0 ,GCU0 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 11. " DISP ,DISP submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TSIF1 ,TSIF1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 9. " TSIF0 ,TSIF0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 8. " MSTIF1 ,MSTIF1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 7. " MSTIF0 ,MSTIF0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 6. " EMUX2 ,EMUX2 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 5. " JPU(JPEG) ,JPU(JPEG) submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 4. " IMR-X3 ,IMR-X3 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 3. " IMR-X2 ,IMR-X2 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 2. " IMR-X1 ,IMR-X1 submask register" "Not masked,Masked"
|
|
bitfld.long 0x10 1. " IMR-X0 ,IMR-X0 submask register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x10 0. " IMR-X3[1] ,IMR-X3[1] submask register" "Not masked,Masked"
|
|
wgroup.long 0x22A0++0x13
|
|
line.long 0x0 "INT2SMSKCR0,Interrupt Submask Clear Register 0"
|
|
bitfld.long 0x00 31. " PL390 ,PL390 submask clear register" "No effect,Clear"
|
|
bitfld.long 0x00 30. " SGX ,SGX submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 29. " MFI(ARM3) ,MFI(ARM3) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 28. " MFI(ARM2) ,MFI(ARM2) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MFI(ARM1) ,MFI(ARM1) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " MFI(ARM0) ,MFI(ARM0) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " REMOCON ,Remocon submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " 12-BIT_ADC_IF ,12-bit_ADC_IF submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SH-DMAC ,SHwy-DMAC submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 22. " CSD ,CSD submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DEBUG(H-UDI) ,DEBUG(H-UDI) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " FM_MULTIPLEX ,FM_multiplex submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " USB2.0-F ,USB2.0-F submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " USB2.0-H_1 ,USB2.0-h_1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 17. " USB2.0-H_0 ,USB2.0-h_0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 16. " RESET/WDT ,RESET/WDT submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TMU_80 ,TMU_80 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " TMU_70 ,TMU_70 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TMU_60 ,TMU_60 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " TMU_51 ,TMU_51 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TMU_50 ,TMU_50 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " TMU_40 ,TMU_40 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TMU_30 ,TMU_30 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " TMU_21 ,TMU_21 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TMU_20 ,TMU_20 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " TMU_10 ,TMU_10 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TMU_00 ,TMU_00 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x00 4. " DU ,TMU_00 submask clear register" "No effect,Cleared"
|
|
line.long 0x4 "INT2SMSKCR1,Interrupt Submask Clear Register 1"
|
|
bitfld.long 0x04 31. " SCIF_2 ,SCIF_2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 30. " SCIF_1 ,SCIF_1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 29. " SCIF_0 ,SCIF_0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 28. " MLB+ ,MLB+ submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MLB ,MLB submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 26. " MIM ,MIM submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 25. " RCAN_1 ,RCAN_1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 24. " RCAN_0 ,RCAN_0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 23. " I2C_1 ,I2C_1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 22. " I2C_3 ,I2C_3 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 21. " I2C_2 ,I2C_2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 20. " I2C_0 ,I2C_0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 18. " LBSWTO ,LBSWTO submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 17. " LBSATA ,LBSATA submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 16. " HSPI_2 ,HSPI_2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 15. " HSPI_1 ,HSPI_1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 14. " HSPI_0 ,HSPI_0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 13. " FIVE-WIRE_SYSTEM ,Five-wire_system submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 12. " MMC1 ,MMC1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 11. " MMC0 ,MMC0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OVG ,OVG submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 9. " R-GP2 ,R-GP2 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SPEED_CONTROL ,Speed_control submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 7. " VIN3 ,VIN3 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VIN2 ,VIN2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 5. " VIN1 ,VIN1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 4. " VIN0 ,VIN0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 3. " ARM3 ,ARM3 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ARM2 ,ARM2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x04 1. " ARM1 ,ARM1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ARM0 ,ARM0 submask clear register" "No effect,Cleared"
|
|
line.long 0x8 "INT2SMSKCR2,Interrupt Submask Clear Register 2"
|
|
bitfld.long 0x08 31. " DRC ,DRC submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " HPB-DMAC43_(P14BUS) ,HPB-DMAC43 (P14BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HPB-DMAC[37/38]_(P11BUS) ,HPB-DMAC[37/38] (P11BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " HPB-DMAC[39:41]_(P12BUS) ,HPB-DMAC[39:41] (P12BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HPB-DMAC[28:36/42]_(P10BUS) ,HPB-DMAC[28:36/42] (P10BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 26. " HPB-DMAC[25:27]_(P9BUS) ,HPB-DMAC[25:27] (P9BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HPB-DMAC24_(P8BUS) ,HPB-DMAC24 (P8BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " HPB-DMAC[21:23]_(P7BUS) ,HPB-DMAC[21:23] (P7BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HPB-DMAC20_(P6BUS) ,HPB-DMAC20 (P6BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " HPB-DMAC[16:19]_(P5BUS) ,HPB-DMAC[16:19] (P5BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HPB-DMAC[14/15]_(P3BUS) ,HPB-DMAC[14/15] (P3BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " HPB-DMAC[11:13]_(P4BUS) ,HPB-DMAC[11:13] (P4BUS) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HPB-DMAC[0:10]_(P2BUS) ,HPB-DMAC[0:10] (P2BUS) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " RDS ,RDS submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " IEB ,IEB submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 16. " SDHI2 ,SDHI2 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SDHI3 ,SDHI3 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 14. " SDHI1 ,SDHI1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SDHI0 ,SDHI0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 12. " PCI-2 ,PCI-2 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 11. " PCI-1 ,PCI-1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " PCI-0 ,PCI-0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SATA ,SATA submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " LBSC-DMAC2 ,LBSC-DMAC2 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 7. " LBSC-DMAC1 ,LBSC-DMAC1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " LBSC-DMAC0 ,LBSC-DMAC0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SIM ,SIM submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " HSCIF_1 ,HSCIF_1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HSCIF_0 ,HSCIF_0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 2. " SCIF_5 ,SCIF_5 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SCIF_4 ,SCIF_4 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " SCIF_3 ,SCIF_3 submask clear register" "No effect,Cleared"
|
|
line.long 0xC "INT2SMSKCR3,Interrupt Submask Clear Register 3"
|
|
bitfld.long 0x0C 31. " IMP-X3[0] ,IMP-X3[0] submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 29. " SPEED-PULSE_IF ,Speed-pulse_IF submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " TSG ,TSG submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 27. " GPS ,GPS submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " CRYPTO_ENGINE ,Crypto_Engine submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 25. " ETHER ,Ether submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " GPIO6 ,GPIO6 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 23. " GPIO5 ,GPIO5 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " GPIO4 ,GPIO4 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 21. " GPIO3 ,GPIO3 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " GPIO2 ,GPIO2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 19. " GPIO1 ,GPIO1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " GPIO0 ,GPIO0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 17. " SLM ,SLM submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " SRU(SSI9) ,SRU(SSI9) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 15. " SRU(SSI8) ,SRU(SSI8) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " SRU(SSI7) ,SRU(SSI7) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 13. " SRU(SSI6) ,SRU(SSI6) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SRU(SSI5) ,SRU(SSI5) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 11. " SRU(SSI4) ,SRU(SSI4) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " SRU(SSI3) ,SRU(SSI3) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 9. " SRU(SSI2) ,SRU(SSI2) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " SRU(SSI1) ,SRU(SSI1) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 7. " SRU(SSI0) ,SRU(SSI0) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " SRU ,SRU submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 5. " SPU2F1(SPU1) ,SPU2F1(SPU1) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " SPU2F1(SPU0) ,SPU2F1(SPU0) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 3. " SPU2F0(SPU1) ,SPU2F0(SPU1) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SPU2F0(SPU0) ,SPU2F0(SPU0) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x0C 1. " DIC1 ,DIC1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " DIC0 ,DIC0 submask clear register" "No effect,Cleared"
|
|
line.long 0x10 "INT2SMSKCR4,Interrupt Submask Clear Register 4"
|
|
bitfld.long 0x10 21. " SYS ,SYS submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 20. " TSC ,TSC submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 19. " MERAM(ICB_MMU) ,MERAM(ICB_MMU) submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 18. " MERAM(ICB) ,MERAM(ICB) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 17. " 2D-DMAC ,2D-DMAC submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 16. " VDP ,VDP submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 15. " VSP ,VSP submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 14. " GCU1 ,GCU1 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 13. " GCU0 ,GCU0 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 11. " DISP ,DISP submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 10. " TSIF1 ,TSIF1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 9. " TSIF0 ,TSIF0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 8. " MSTIF1 ,MSTIF1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 7. " MSTIF0 ,MSTIF0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 6. " EMUX2 ,EMUX2 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 5. " JPU(JPEG) ,JPU(JPEG) submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 4. " IMR-X3 ,IMR-X3 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 3. " IMR-X2 ,IMR-X2 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 2. " IMR-X1 ,IMR-X1 submask clear register" "No effect,Cleared"
|
|
bitfld.long 0x10 1. " IMR-X0 ,IMR-X0 submask clear register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x10 0. " IMR-X3[1] ,IMR-X3[1] submask clear register" "No effect,Cleared"
|
|
group.long 0x22C0++0xB
|
|
line.long 0x0 "NMICTL,NMI Control Register"
|
|
bitfld.long 0x0 0. " NMI ,NMI interrupt select" "Low level,High level"
|
|
line.long 0x4 "IRQCTL,IRQ Control Register"
|
|
bitfld.long 0x4 3. " IRQ3 ,IRQ3 interrupt select" "Low level,High level"
|
|
bitfld.long 0x4 2. " IRQ2 ,IRQ2 interrupt select" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x4 1. " IRQ1 ,IRQ1 interrupt select" "Low level,High level"
|
|
bitfld.long 0x4 0. " IRQ0 ,IRQ0 interrupt select" "Low level,High level"
|
|
line.long 0x8 "IRLCTL,IRL Control Register"
|
|
bitfld.long 0x8 0. " IRL ,Select IRQ[0:3] for encoded or independent interrupt signals" "Encoded,Independent"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "LBSC within Bus Bridge"
|
|
base ad:0xFF800000
|
|
width 12.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "CS0CTRL,Area 0 Control Register"
|
|
sif ((cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77430")||(cpu()=="R8A77450")||(cpu()=="R8A77420")||(cpu()=="R8A77470")||(cpu()=="R8A77440"))
|
|
rbitfld.long 0x00 8. " 128B ,Area 0 capacity indication (Mbytes)" "64,128"
|
|
rbitfld.long 0x00 4.--5. " CS0SZ ,Area 0 bus size indication (bits)" ",8,16,?..."
|
|
textline " "
|
|
elif (cpuis("R8J7795*")||cpuis("R8A7795*")||cpuis("R8A77970*"))||(cpuis("R8A77960*"))||(cpuis("R8A77990*"))
|
|
rbitfld.long 0x00 4.--5. " CS0SZ ,Area 0 bus size indication (bits)" ",8,16,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 15. " ENDIAN ,Endian indication" "Big,Little"
|
|
bitfld.long 0x00 8. " 128B ,Area 0 capacity indication (Mbytes)" "64,128"
|
|
bitfld.long 0x00 4.--5. " CS0SZ ,Area 0 bus size indication (bits)" ",8,16,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " CS0IF ,Area 0 interface select" "Standard,Burst ROM,?..."
|
|
line.long 0x04 "CS1CTRL,Area 1 Control Register"
|
|
bitfld.long 0x04 4.--5. " CS1SZ ,Area 1 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x04 2. " CS1BRM ,Area 1 byte-control SRAM mode selection" "/CS,/RD"
|
|
textline " "
|
|
sif ((cpu()=="R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")||cpuis("R8A77970*")||cpuis("R8A77960*")||cpuis("R8A77990*")||(cpu()=="R8A77470"))
|
|
bitfld.long 0x04 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470")
|
|
if (((per.l(ad:0xFF800000+0x200+0x8))&0x3)==0x01)
|
|
group.long (0x200+0x8)++0x03
|
|
line.long 0x00 "ECS0CTRL,Expansion Area 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS0CP ,Expansion area 0 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS0SZ ,Expansion area 0 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS0BRM ,Expansion area 0 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS0IF ,Expansion area 0 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0x8)++0x03
|
|
line.long 0x00 "ECS0CTRL,Expansion Area 0 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS0CP ,Expansion area 0 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS0SZ ,Expansion area 0 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS0IF ,Expansion area 0 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200+0xC))&0x3)==0x01)
|
|
group.long (0x200+0xC)++0x03
|
|
line.long 0x00 "ECS1CTRL,Expansion Area 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS1CP ,Expansion area 1 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS1SZ ,Expansion area 1 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS1BRM ,Expansion area 1 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS1IF ,Expansion area 1 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0xC)++0x03
|
|
line.long 0x00 "ECS1CTRL,Expansion Area 1 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS1CP ,Expansion area 1 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS1SZ ,Expansion area 1 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS1IF ,Expansion area 1 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200+0x10))&0x3)==0x01)
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "ECS2CTRL,Expansion Area 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS2CP ,Expansion area 2 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS2SZ ,Expansion area 2 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS2BRM ,Expansion area 2 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS2IF ,Expansion area 2 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0x10)++0x03
|
|
line.long 0x00 "ECS2CTRL,Expansion Area 2 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS2CP ,Expansion area 2 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS2SZ ,Expansion area 2 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS2IF ,Expansion area 2 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200+0x14))&0x3)==0x01)
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "ECS3CTRL,Expansion Area 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS3CP ,Expansion area 3 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS3SZ ,Expansion area 3 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS3BRM ,Expansion area 3 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS3IF ,Expansion area 3 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "ECS3CTRL,Expansion Area 3 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS3CP ,Expansion area 3 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS3SZ ,Expansion area 3 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS3IF ,Expansion area 3 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200+0x18))&0x3)==0x01)
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "ECS4CTRL,Expansion Area 4 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS4CP ,Expansion area 4 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS4SZ ,Expansion area 4 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS4BRM ,Expansion area 4 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS4IF ,Expansion area 4 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0x18)++0x03
|
|
line.long 0x00 "ECS4CTRL,Expansion Area 4 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS4CP ,Expansion area 4 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS4SZ ,Expansion area 4 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS4IF ,Expansion area 4 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200+0x1C))&0x3)==0x01)
|
|
group.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "ECS5CTRL,Expansion Area 5 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS5CP ,Expansion area 5 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS5SZ ,Expansion area 5 bus size selection (bits)" ",8,16,?..."
|
|
bitfld.long 0x00 2. " ECS5BRM ,Expansion area 5 byte-control SRAM mode" "/CS,/RD"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS5IF ,Expansion area 5 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
else
|
|
group.long (0x200+0x1C)++0x03
|
|
line.long 0x00 "ECS5CTRL,Expansion Area 5 Control Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " ECS5CP ,Expansion area 5 capacity setting"
|
|
bitfld.long 0x00 4.--5. " ECS5SZ ,Expansion area 5 bus size selection (bits)" ",8,16,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 0.--1. " CS1IF ,Area 1 interface selection" "Standard,Byte-control SRAM,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0.--1. " ECS5IF ,Expansion area 5 interface selection" "Standard,Byte-control SRAM,ATA,?..."
|
|
textline " "
|
|
endif
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(cpu()!="R8A77940")&&(cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77990*"))&&(!cpuis("R8A77965*"))&&(cpu()!="R8A77470")&&(cpu()!="R8A77420")&&(cpu()!="R8A77430")&&(cpu()!="R8A77450")&&(cpu()!="R8A77440"))
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CS0CTRL2,Area 0 Control 2 Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CS0CP ,Area 0 capacity setting"
|
|
endif
|
|
textline " "
|
|
group.long 0x230++0x07
|
|
line.long 0x00 "CSWCR0,Area 0 RD/WE Pulse Control Register"
|
|
sif ((cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")||cpuis("R8A77970*")||(cpuis("R8A77960*"))||(cpuis("R8A77965*"))||(cpuis("R8A77990*"))||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77440"))
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x04 "CSWCR1,Area 1 RD/WE Pulse Control Register"
|
|
sif ((cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")||cpuis("R8A77970*")||(cpuis("R8A77960*"))||(cpuis("R8A77965*"))||(cpuis("R8A77990*"))||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77440"))
|
|
bitfld.long 0x04 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470")
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "ECSWCR0,Expansion Area 0 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "ECSWCR1,Expansion Area 1 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "ECSWCR2,Expansion Area 2 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "ECSWCR3,Expansion Area 3 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 3" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 3" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 3" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 3" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "ECSWCR4,Expansion Area 4 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 4" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 4" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 4" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 4" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "ECSWCR5,Expansion Area 5 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 5" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 5" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 5" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 5" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x250+0x0)++0x03
|
|
line.long 0x00 "EXDMAWCR0,LBSC-DMAC Channel 0 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 0" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 0" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x250+0x4)++0x03
|
|
line.long 0x00 "EXDMAWCR1,LBSC-DMAC Channel 1 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 1" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x250+0x8)++0x03
|
|
line.long 0x00 "EXDMAWCR2,LBSC-DMAC Channel 2 RD/WE Pulse Control Register"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 27.--31. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 11.--15. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 24.--26. " WRITE_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " WRITE_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /WE signal during writing to area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " WRITE_PULSE_CYCLE ,/WE pulse cycles during writing to area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " READ_CS_SETUP_CYCLE ,/CS and address setup cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " READ_CS_HOLD_CYCLE ,/CS and address hold cycles with respect to the /RD signal during reading from area 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--3. " READ_PULSE_CYCLE ,/RD pulse cycles during reading from area 2" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long 0x280++0x7
|
|
line.long 0x00 "CSPWCR0,Area 0 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Area 0 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 4. " RB ,Area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Area 0 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Area 0 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Area 0 external Wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Area 0 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Area 0 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif ((cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470"))
|
|
bitfld.long 0x00 2. " EXWT2 ,Area 0 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Area 0 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Area 0 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="R8A77470")
|
|
bitfld.long 0x00 1. " EXWT1 ,Area 0 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Area 0 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Area 0 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "CSPWCR1,Area 1 External Wait Control Register"
|
|
bitfld.long 0x04 5. " V ,Area 1 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x04 4. " RB ,Area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x04 3. " WINV ,Area 1 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 4. " RB ,Area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x04 3. " WINV ,Area 1 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x04 4. " RB ,Area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x04 3. " WINV ,Area 1 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif ((cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470"))
|
|
bitfld.long 0x04 2. " EXWT2 ,Area 1 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EXWT1 ,Area 1 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EXWT0 ,Area 1 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="R8A77470")
|
|
bitfld.long 0x04 1. " EXWT1 ,Area 1 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EXWT0 ,Area 1 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 0. " EXWT0 ,Area 1 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif ((!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77990*"))&&(!cpuis("R8A77965*"))&&(cpu()!="R8A77470"))
|
|
group.long (0x288+0x0)++0x03
|
|
line.long 0x00 "ECSPWCR0,Expansion Area 0 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 0 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 0 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 0 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 0 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 0 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 0 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 0 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 0 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 0 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long (0x288+0x4)++0x03
|
|
line.long 0x00 "ECSPWCR1,Expansion Area 1 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 1 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 1 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 1 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 1 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 1 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 1 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 1 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 1 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long (0x288+0x8)++0x03
|
|
line.long 0x00 "ECSPWCR2,Expansion Area 2 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 2 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 2 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 2 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 2 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 2 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 2 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 2 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 2 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 2 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long (0x288+0xC)++0x03
|
|
line.long 0x00 "ECSPWCR3,Expansion Area 3 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 3 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 3 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 3 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 3 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 3 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 3 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 3 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 3 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 3 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long (0x288+0x10)++0x03
|
|
line.long 0x00 "ECSPWCR4,Expansion Area 4 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 4 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 4 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 4 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 4 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 4 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 4 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 4 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 4 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 4 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
group.long (0x288+0x14)++0x03
|
|
line.long 0x00 "ECSPWCR5,Expansion Area 5 External Wait Control Register"
|
|
bitfld.long 0x00 5. " V ,Expansion area 5 external wait signal Enable/Disable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 4. " RB ,Expansion area 5 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 5 External wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4. " RB ,Expansion area 5 READY/BUSY logic selection" "Busy,Ready"
|
|
bitfld.long 0x00 3. " WINV ,Expansion area 5 external wait signal polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 2. " EXWT2 ,Expansion area 5 EX_WAIT2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EXWT1 ,Expansion area 5 EX_WAIT1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 5 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0 ,Expansion area 5 EX_WAIT0 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
endif
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "EXWTSYNC,External Wait Input Control Register"
|
|
sif ((cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*")&&(!cpuis("R8A77970*")))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470"))
|
|
bitfld.long 0x00 2. " EXWTSYNC2 ,EX_WAIT[2] synchronize" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 1. " EXWTSYNC1 ,EX_WAIT[1] synchronize" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXWTSYNC0 ,EX_WAIT[0] synchronize" "Not synchronized,Synchronized"
|
|
textline " "
|
|
elif (cpu()=="R8A77470")
|
|
bitfld.long 0x00 1. " EXWTSYNC1 ,EX_WAIT[1] synchronize" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 0. " EXWTSYNC0 ,EX_WAIT[0] synchronize" "Not synchronized,Synchronized"
|
|
textline " "
|
|
endif
|
|
if (((per.l(ad:0xFF800000+0x200))&0x03)==0x01)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "CS0BSTCTL,Area 0 Burst Control Register"
|
|
bitfld.long 0x00 11.--13. " A0BST ,Area 0 burst length for burst ROM interface" "No transfer,4,8,16,32,No transfer,No transfer,No transfer"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "CS0BSTCTL,Area 0 Burst Control Register"
|
|
endif
|
|
textline " "
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "CS0BTPH,Area 0 Burst Pitch Set Register"
|
|
bitfld.long 0x00 8. " A0H ,/CS and address hold cycles with respect to the /RD signal for area 0" "0,1"
|
|
bitfld.long 0x00 4.--7. " A0W ,Burst pitch after the first burst cycle for area 0" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " A0B ,Burst pitch after the second burst cycle for area 0" ",1,2,3,4,5,6,7"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x00 "CS1GDST,Area 1 Guard Set Register"
|
|
bitfld.long 0x00 4. " CS1GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Area 1 guard interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif ((!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*")))
|
|
sif (cpu()!="R8A77470")
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "ECS0GDST,Expansion Area 0 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS0GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 0 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "ECS1GDST,Expansion Area 1 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS1GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 1 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "ECS2GDST,Expansion Area 2 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS2GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 2 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "ECS3GDST,Expansion Area 3 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS3GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 3 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "ECS4GDST,Expansion Area 4 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS4GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 4 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "ECS5GDST,Expansion Area 5 Guard Set Register"
|
|
bitfld.long 0x00 4. " ECS5GD ,TIMER_SET setting valid" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--3. " TIMER_SET ,Expansion Area 5 guard (access prohibition) interval between sequential access cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long (0x2F0+0x0)++0x03
|
|
line.long 0x00 "EXDMASET0,LBSC-DMAC Channel 0 Area Assignment Register"
|
|
sif (cpu()!="R8A77470")
|
|
bitfld.long 0x00 7. " DMYECS5 ,LBSC-DMAC channel 0 to expansion area 5 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 6. " DMYECS4 ,LBSC-DMAC channel 0 to expansion area 4 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 5. " DMYECS3 ,LBSC-DMAC channel 0 to expansion area 3 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMYECS2 ,LBSC-DMAC channel 0 to expansion area 2 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 3. " DMYECS1 ,LBSC-DMAC channel 0 to expansion area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " DMYECS0 ,LBSC-DMAC channel 0 to expansion area 0 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " DMYCS1 ,LBSC-DMAC channel 0 to area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " DMYCS0 ,LBSC-DMAC channel 0 to area 0 assign" "Not assigned,Assigned"
|
|
group.long (0x2F0+0x4)++0x03
|
|
line.long 0x00 "EXDMASET1,LBSC-DMAC Channel 1 Area Assignment Register"
|
|
sif (cpu()!="R8A77470")
|
|
bitfld.long 0x00 7. " DMYECS5 ,LBSC-DMAC channel 1 to expansion area 5 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 6. " DMYECS4 ,LBSC-DMAC channel 1 to expansion area 4 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 5. " DMYECS3 ,LBSC-DMAC channel 1 to expansion area 3 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMYECS2 ,LBSC-DMAC channel 1 to expansion area 2 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 3. " DMYECS1 ,LBSC-DMAC channel 1 to expansion area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " DMYECS0 ,LBSC-DMAC channel 1 to expansion area 0 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " DMYCS1 ,LBSC-DMAC channel 1 to area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " DMYCS0 ,LBSC-DMAC channel 1 to area 0 assign" "Not assigned,Assigned"
|
|
group.long (0x2F0+0x8)++0x03
|
|
line.long 0x00 "EXDMASET2,LBSC-DMAC Channel 2 Area Assignment Register"
|
|
sif (cpu()!="R8A77470")
|
|
bitfld.long 0x00 7. " DMYECS5 ,LBSC-DMAC channel 2 to expansion area 5 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 6. " DMYECS4 ,LBSC-DMAC channel 2 to expansion area 4 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 5. " DMYECS3 ,LBSC-DMAC channel 2 to expansion area 3 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMYECS2 ,LBSC-DMAC channel 2 to expansion area 2 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 3. " DMYECS1 ,LBSC-DMAC channel 2 to expansion area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " DMYECS0 ,LBSC-DMAC channel 2 to expansion area 0 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " DMYCS1 ,LBSC-DMAC channel 2 to area 1 assign" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " DMYCS0 ,LBSC-DMAC channel 2 to area 0 assign" "Not assigned,Assigned"
|
|
textline " "
|
|
group.long (0x310+0x0)++0x03
|
|
line.long 0x00 "EXDMCR0,LBSC-DMAC Channel 0 Control Register"
|
|
bitfld.long 0x00 15. " DRST ,DACK signal forcible negation" "Not negated,Negated"
|
|
textline " "
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")||(cpu()=="R8A77440")
|
|
rbitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 12. " DBST ,Continuously assert the DACK signal" "Negated,Asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " EXQL ,DREQ[0] signal low/high level receive" "Low,High"
|
|
bitfld.long 0x00 9. " EXDY ,DREQ[0] signal synchronize" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " EXDS ,DREQ[0] signal at an level/edge detect" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EXRS ,Number of DRACK[0] clock cycles before /CS|DACK[0] asserted" "1,2"
|
|
bitfld.long 0x00 4. " EXRL ,DRACK[0] low/high-active signal output" "High-active,Low-active"
|
|
bitfld.long 0x00 2. " EXAL ,DACK[0] low/high-active signal output" "High-active,Low-active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DAKCTL ,Signals asserted for area where LBSC-DMAC channel 0 is assigned" "/CS & DACK[0],/CS,DACK[0],/CS & DACK[0]"
|
|
group.long (0x310+0x4)++0x03
|
|
line.long 0x00 "EXDMCR1,LBSC-DMAC Channel 1 Control Register"
|
|
bitfld.long 0x00 15. " DRST ,DACK signal forcible negation" "Not negated,Negated"
|
|
textline " "
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")||(cpu()=="R8A77440")
|
|
rbitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 12. " DBST ,Continuously assert the DACK signal" "Negated,Asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " EXQL ,DREQ[1] signal low/high level receive" "Low,High"
|
|
bitfld.long 0x00 9. " EXDY ,DREQ[1] signal synchronize" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " EXDS ,DREQ[1] signal at an level/edge detect" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EXRS ,Number of DRACK[0] clock cycles before /CS|DACK[0] asserted" "1,2"
|
|
bitfld.long 0x00 4. " EXRL ,DRACK[0] low/high-active signal output" "High-active,Low-active"
|
|
bitfld.long 0x00 2. " EXAL ,DACK[1] low/high-active signal output" "High-active,Low-active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DAKCTL ,Signals asserted for area where LBSC-DMAC channel 1 is assigned" "/CS & DACK[1],/CS,DACK[1],/CS & DACK[1]"
|
|
group.long (0x310+0x8)++0x03
|
|
line.long 0x00 "EXDMCR2,LBSC-DMAC Channel 2 Control Register"
|
|
bitfld.long 0x00 15. " DRST ,DACK signal forcible negation" "Not negated,Negated"
|
|
textline " "
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A7792X")||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")||(cpu()=="R8A77440")
|
|
rbitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 13. " DSTS ,DACK signal assert state indication" "Not asserted,Asserted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="R8A7792X")
|
|
bitfld.long 0x00 12. " DBST ,Continuously assert the DACK signal" "Negated,Asserted"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " EXQL ,DREQ[2] signal low/high level receive" "Low,High"
|
|
bitfld.long 0x00 9. " EXDY ,DREQ[2] signal synchronize" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " EXDS ,DREQ[2] signal at an level/edge detect" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EXRS ,Number of DRACK[0] clock cycles before /CS|DACK[0] asserted" "1,2"
|
|
bitfld.long 0x00 4. " EXRL ,DRACK[0] low/high-active signal output" "High-active,Low-active"
|
|
bitfld.long 0x00 2. " EXAL ,DACK[2] low/high-active signal output" "High-active,Low-active"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DAKCTL ,Signals asserted for area where LBSC-DMAC channel 2 is assigned" "/CS & DACK[2],/CS,DACK[2],/CS & DACK[2]"
|
|
endif
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "BCINTSR,BSC Interrupt Source Status Register"
|
|
bitfld.long 0x00 1. " EXWTE ,EX-BUS wait timeout error status" "No error,Error"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470")
|
|
bitfld.long 0x00 0. " ATTE ,ATA wait timeout error status" "No error,Error"
|
|
endif
|
|
wgroup.long 0x334++0x03
|
|
line.long 0x00 "BCINTCR,BSC Interrupt Source Clear Register"
|
|
bitfld.long 0x00 1. " EXWTEC ,EX-BUS wait timeout error status clear" "No effect,Clear"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470")&&(cpu()!="R8A77440")
|
|
bitfld.long 0x00 0. " ATTEC ,ATA wait timeout error status clear" "No effect,Clear"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "BCINTMR,BSC Interrupt Enable Register"
|
|
bitfld.long 0x00 1. " EXWTEM ,EX-BUS wait timeout error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470")
|
|
bitfld.long 0x00 0. " ATTEM ,ATA wait timeout error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EXBATLV,EX_BUS Priority Level Set Register"
|
|
bitfld.long 0x00 0. " EX-BLV ,Priority level setting for EX_BUS arbitration (higher/lower)" "PIO/LBSC-DMAC,LBSC-DMAC/PIO"
|
|
endif
|
|
textline " "
|
|
rgroup.long 0x344++0x03
|
|
line.long 0x00 "EXWTSTS,External Wait Status Register"
|
|
sif ((cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470"))
|
|
bitfld.long 0x00 2. " EXWT2STS ,Indicates the EX_WAIT2 pin state" "Low,High"
|
|
bitfld.long 0x00 1. " EXWT1STS ,Indicates the EX_WAIT1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " EXWT0STS ,Indicates the EX_WAIT0 pin state" "Low,High"
|
|
textline " "
|
|
elif (cpu()=="R8A77470")
|
|
bitfld.long 0x00 1. " EXWT1STS ,Indicates the EX_WAIT1 pin state" "Low,High"
|
|
bitfld.long 0x00 0. " EXWT0STS ,Indicates the EX_WAIT0 pin state" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 0. " EXWT0STS ,Indicates the EX_WAIT0 pin state" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif ((cpu()!="R8A7792X")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77990*"))&&(cpu()!="R8A77470"))
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "ATACSCTRL,ATACS Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A77420")||(cpu()=="R8A77450")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 6. " ATAECS5_EN ,ATACS signal at area 5 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 5. " ATAECS4_EN ,ATACS signal at area 4 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 4. " ATAECS3_EN ,ATACS signal at area 3 in ATA mode" "ATACS0,ATACS1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ATAECS2_EN ,ATACS signal at area 2 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 2. " ATAECS1_EN ,ATACS signal at area 1 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 1. " ATAECS0_EN ,ATACS signal at area 0 in ATA mode" "ATACS0,ATACS1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATACS1_EN ,ATACS signal at area 1 in ATA mode" "ATACS0,ATACS1"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 5. " ATAECS5_EN ,ATACS signal at area 5 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 4. " ATAECS4_EN ,ATACS signal at area 4 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 3. " ATAECS3_EN ,ATACS signal at area 3 in ATA mode" "ATACS0,ATACS1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ATAECS2_EN ,ATACS signal at area 2 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 1. " ATAECS1_EN ,ATACS signal at area 1 in ATA mode" "ATACS0,ATACS1"
|
|
bitfld.long 0x00 0. " ATAECS0_EN ,ATACS signal at area 0 in ATA mode" "ATACS0,ATACS1"
|
|
endif
|
|
endif
|
|
group.long 0x3C0++0x07
|
|
line.long 0x00 "EXBCT,EX-BUS Wait Timeout Detection Base Counter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " EXWB_KEY ,EX-BUS wait timeout detection base counter register write key"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " EXW_TOBCNT ,EX-BUS wait timeout counter setting"
|
|
line.long 0x04 "EXTCT,EX-BUS Wait Timeout Detection Counter Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " EXWB_KEY ,EX-BUS wait timeout detection counter register write key"
|
|
bitfld.long 0x04 16. " EXW_TOEN ,EX-BUS wait timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x04 0.--11. 1. " EXW_TOCNT ,EX-BUS wait timeout counter setting"
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A77940")||(cpu()=="R8A77470")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")||(cpu()=="R8A77440")
|
|
group.long 0x010++0x07
|
|
line.long 0x00 "EXTSR,EX-BUS Wait Timeout Detection Access Source Indication Register"
|
|
eventfld.long 0x00 16. " EXW_TOSHW ,Timeout for access to the EX-BUS from superHyway" "No timeout,Timeout"
|
|
eventfld.long 0x00 2. " EXW_TODC2 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 2" "No timeout,Timeout"
|
|
eventfld.long 0x00 1. " EXW_TODC1 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 1" "No timeout,Timeout"
|
|
textline " "
|
|
eventfld.long 0x00 0. " EXW_TODC0 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 0" "No timeout,Timeout"
|
|
line.long 0x04 "EXTADR,EX-BUS Wait Timeout Detection Address Indication Register"
|
|
elif cpuis("R8J7795*")||cpuis("R8A7795*")||cpu()==("R8A77970")||(cpuis("R8A77960*"))||(cpuis("R8A77965*"))||(cpuis("R8A77990*"))
|
|
group.long 0x010++0x07
|
|
line.long 0x00 "EXTSR,EX-BUS Wait Timeout Detection Access Source Indication Register"
|
|
eventfld.long 0x00 16. " EXW_TOSHW ,Timeout for access to the EX-BUS from SuperHyway" "No timeout,Timeout"
|
|
line.long 0x04 "EXTADR,EX-BUS Wait Timeout Detection Address Indication Register"
|
|
else
|
|
group.long 0x010++0x07
|
|
line.long 0x00 "EXTSR,EX-BUS Wait Timeout Detection Access Source Indication Register"
|
|
bitfld.long 0x00 16. " EXW_TOSHW ,Timeout for access to the EX-BUS from SuperHyway" "No timeout,Timeout"
|
|
bitfld.long 0x00 2. " EXW_TODC2 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 2" "No timeout,Timeout"
|
|
bitfld.long 0x00 1. " EXW_TODC1 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 1" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EXW_TODC0 ,Timeout for access to the EX-BUS from LBSC-DMAC channel 0" "No timeout,Timeout"
|
|
line.long 0x04 "EXTADR,EX-BUS Wait Timeout Detection Address Indication Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "DBSC3 (DDR3-SDRAM Interface)"
|
|
tree "DBSC3_0"
|
|
base ad:0xFE800000
|
|
width 12.
|
|
sif !cpuis("R8A77440")&&!cpuis("R8A77420")&&!cpuis("R8A77450")&&!cpuis("R8A77430")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DBSTATE1,DBSC3 Status Register 1"
|
|
sif cpu()!="R8A77470"
|
|
bitfld.long 0x00 16.--17. " THRML ,External temperature sensor" "Higher than -10 C,Higher/lower than -15 C/-10 C,,-15 C or lower"
|
|
bitfld.long 0x00 8. " ENDN ,Endian monitor" "Big endian,Little endian"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " BKUP ,Power-Supply Backup Monitor" "Low,High"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DBACEN,SDRAM Access Enable Register"
|
|
bitfld.long 0x00 0. " ACCEN ,SDRAM access enable" "Disabled,Enabled"
|
|
line.long 0x04 "DBRFEN,Auto-refresh Enable Register"
|
|
bitfld.long 0x04 0. " ARFEN ,Auto-refresh enable" "Stop,Start"
|
|
if ((((per.l(ad:0xFE800000+0x18))&0x3F000000)==0x28000000)||(((per.l(ad:0xFE800000+0x18))&0x3F000000)==0x29000000)||(((per.l(ad:0xFE800000+0x18))&0x3F000000)==0x2A000000)||(((per.l(ad:0xFE800000+0x18))&0x3F000000)==0x2B000000))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DBCMD,Manual Command-Issuing Register"
|
|
bitfld.long 0x00 24.--29. " OPC ,Operation code" "Wait,,ZQCS,ZQCL,,,,,,,,PREA,Ref,,,PDEn,PDXt,SRXt,,,,,,SREn,SRXt,,,,,,,RstL,RstH,,,,,,,MRS0,MRS1,MRS2,MRS3,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " ARG ,Parameter bits - value to be issued on the address pins of SDRAM"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DBCMD,Manual Command-Issuing Register"
|
|
bitfld.long 0x00 24.--29. " OPC ,Operation code" "Wait,,ZQCS,ZQCL,,,,,,,,PREA,Ref,,,PDEn,PDXt,SRXt,,,,,,SREn,SRXt,,,,,,,RstL,RstH,,,,,,,MRS0,MRS1,MRS2,MRS3,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " ARG ,Parameter bits - minimum interval to issuing of the next command in SDRAM cycles"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DBWAIT,Operation Completion Waiting Register"
|
|
bitfld.long 0x00 0. " WAIT ,Operation completion waiting" "Low,High"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DBKIND,SDRAM Type Setting Register"
|
|
bitfld.long 0x00 0.--2. " DDCG ,SDRAM kind" ",,,,,,,DDR3-SDRAM"
|
|
line.long 0x04 "DBCONF0,SDRAM Configuration Setting Register 0"
|
|
bitfld.long 0x04 24.--28. " AWRW0 ,Row address bit width setting" ",,,,,,,,,,,,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x04 20. " AWRK0 ,Number of ranks setting" "One rank,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " AWBK0 ,Number of banks setting" ",,,Eight banks"
|
|
textline " "
|
|
sif cpuis("R8A77440")||cpuis("R8A77450")||cpuis("R8A77430")||cpuis("R8A77470")||cpuis("R8A77420")
|
|
bitfld.long 0x04 8.--11. " AWCL0 ,Column address bit width setting" ",,,,,,,,,,10 bits,11 bits,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AWCL0 ,Column address bit width setting" ",,,,,,,,,9 bits,10 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0.--1. " DW0 ,External data bus width setting" ",16 bits,32 bits,?..."
|
|
sif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DBPHYTYPE,PHY Type Setting Register"
|
|
bitfld.long 0x00 0.--1. " PHYTYPE ,PHY type setting bits" ",DFI,?..."
|
|
endif
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DBTR0,SDRAM Timing Register 0"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x00 0.--3. " CL ,CAS latency setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " CL ,CAS latency setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x04 "DBTR1,SDRAM Timing Register 1"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x04 0.--3. " CWL ,CAS write latency setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
else
|
|
bitfld.long 0x04 0.--3. " CWL ,CAS write latency setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
endif
|
|
line.long 0x08 "DBTR2,SDRAM Timing Register 2"
|
|
bitfld.long 0x08 0.--3. " AL ,Additive latency setting" "Zero cycles,?..."
|
|
group.long 0x50++0x43
|
|
line.long 0x00 "DBTR3,SDRAM Timing Register 3"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 0.--4. " TRCD ,ACT to READ/ACT to WRITE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
else
|
|
bitfld.long 0x00 0.--3. " TRCD ,ACT to READ/ACT to WRITE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x04 "DBTR4,SDRAM Timing Register 4"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x04 16.--20. " TRPA ,PREA time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
bitfld.long 0x04 0.--4. " TRP ,PRE time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " TRPA ,PREA time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
bitfld.long 0x04 0.--3. " TRP ,PRE time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x08 "DBTR5,SDRAM Timing Register 5"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x08 0.--5. " TRC ,ACT to ACT/ACT to REF interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 0.--5. " TRC ,ACT to ACT/ACT to REF interval setting" ",,,,,,,,,,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,?..."
|
|
textline " "
|
|
endif
|
|
line.long 0x0C "DBTR6,SDRAM Timing Register 6"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x0C 0.--5. " TRAS ,ACT to PRE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,?..."
|
|
else
|
|
bitfld.long 0x0C 0.--5. " TRAS ,ACT to PRE interval setting" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,?..."
|
|
endif
|
|
line.long 0x10 "DBTR7,SDRAM Timing Register 7"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x10 0.--3. " TRRD ,ACT(A) to ACT(B) interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
else
|
|
bitfld.long 0x10 0.--3. " TRRD ,ACT(A) to ACT(B) interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,,,,?..."
|
|
endif
|
|
line.long 0x14 "DBTR8,SDRAM Timing Register 8"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TFAW ,Four activate window length setting"
|
|
line.long 0x18 "DBTR9,SDRAM Timing Register 9"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x18 0.--3. " TRDPR ,READ-PRE interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
else
|
|
bitfld.long 0x18 0.--3. " TRDPR ,READ-PRE interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
endif
|
|
line.long 0x1C "DBTR10,SDRAM Timing Register 10"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x1C 0.--3. " TWR ,Write-recovery period setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,?..."
|
|
else
|
|
bitfld.long 0x1C 0.--3. " TWR ,Write-recovery period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,?..."
|
|
endif
|
|
line.long 0x20 "DBTR11,SDRAM Timing Register 11"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x20 0.--5. " TRDWR ,READ to WRITE interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,?..."
|
|
else
|
|
bitfld.long 0x20 0.--5. " TRDWR ,READ to WRITE interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,?..."
|
|
endif
|
|
line.long 0x24 "DBTR12,SDRAM Timing Register 12"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x24 0.--5. " TWRRD ,WRITE to READ interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,?..."
|
|
else
|
|
bitfld.long 0x24 0.--5. " TWRRD ,WRITE to READ interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,?..."
|
|
endif
|
|
line.long 0x28 "DBTR13,SDRAM Timing Register 13"
|
|
sif cpuis("R8A774*")
|
|
hexmask.long.word 0x28 0.--11. 1. " TRFC ,REF to ACT/ACT to REF interval setting"
|
|
else
|
|
hexmask.long.byte 0x28 0.--7. 1. " TRFC ,REF to ACT/ACT to REF interval setting"
|
|
endif
|
|
line.long 0x2C "DBTR14,SDRAM Timing Register 14"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " TCKEHDLL ,CKEH period setting"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " TCKEH ,CKEH period setting"
|
|
line.long 0x30 "DBTR15,SDRAM Timing Register 15"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x30 16.--19. " TCKESR ,CKESR period setting bits" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x30 0.--3. " TCKEL ,CKEL period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 0.--3. " TCKEL ,CKEL period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
endif
|
|
line.long 0x34 "DBTR16,SDRAM Timing Register 16"
|
|
sif cpuis("R8A77470")
|
|
bitfld.long 0x34 28.--31. " DQIENLTNCY ,Dqienltncy setting" ",One cycle,?..."
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting bits" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " DQENLTNCY ,Dqenltncy setting bits" ",One cycle,?..."
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting bits" ",One cycle,?..."
|
|
elif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
bitfld.long 0x34 28.--31. " DQIENLTNCY ,Dqienltncy setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,?..."
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " DQENLTNCY ,Dqenltncy setting" "Zero cycles,One cycle,2 cycles,3 cycles,4 cycles,5 cycles,?..."
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting" ",One cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
else
|
|
bitfld.long 0x34 28.--29. " DQIENLTNCY ,Dqienltncy setting" ",One cycle,?..."
|
|
bitfld.long 0x34 24.--25. " DQLOFFSET ,Dqltncy offset setting" "Zero cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting" ",,,,,,,,,,,,,,,,,,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,?..."
|
|
bitfld.long 0x34 12.--13. " DQENLTNCY ,Dqenltncy setting" ",One cycle,?..."
|
|
textline " "
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting" ",One cycle,?..."
|
|
endif
|
|
line.long 0x38 "DBTR17,SDRAM Timing Register 17"
|
|
bitfld.long 0x38 16.--21. " TMOD ,MRS time setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,14 cycles,15 cycles,?..."
|
|
textline " "
|
|
sif !cpuis("R8A774*")
|
|
bitfld.long 0x38 0.--5. " TRDMR ,RD-MRS interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,?..."
|
|
endif
|
|
line.long 0x3C "DBTR18,SDRAM Timing Register 18"
|
|
bitfld.long 0x3C 24.--26. " RODTL ,ODT assert period setting at read" "BL/2 cycles,BL/2 + 1 cycles,BL/2 + 2 cycles,BL/2 + 3 cycles,BL/2 + 4 cycles,BL/2 + 5 cycles,BL/2 + 6 cycles,BL/2 + 7 cycles"
|
|
textline " "
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x3C 16.--18. " RODTA ,ODT assert start timing setting bits read" "Simultaneous with the read,One cycle after the read,Two cycles after the read,Three cycles after the read,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x3C 16.--18. " RODTA ,ODT assert start timing setting bits read" "Simultaneous with the read,One cycle after the read,Two cycles after the read,Three cycles after the read,,,,One cycle before the read"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x3C 8.--10. " WODTL ,ODT assert period setting at write" "BL/2 cycles,BL/2 + 1 cycles,BL/2 + 2 cycles,BL/2 + 3 cycles,BL/2 + 4 cycles,BL/2 + 5 cycles,BL/2 + 6 cycles,BL/2 + 7 cycles"
|
|
textline " "
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x3C 0.--2. " WODTA ,ODT assert start timing setting at write" "Simultaneous with the read,1 cycle after the read,2 cycles after the read,3 cycles after the read,?..."
|
|
else
|
|
bitfld.long 0x3C 0.--2. " WODTA ,ODT assert start timing setting at write" "Simultaneous with the read,1 cycle after the read,2 cycles after the read,3 cycles after the read,,,,1 cycle before the read"
|
|
endif
|
|
line.long 0x40 "DBTR19,SDRAM Timing Register 19"
|
|
hexmask.long.byte 0x40 0.--7. 1. " TZQCS ,Calibration period setting"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DBBL,SDRAM Operation Setting Register"
|
|
bitfld.long 0x00 0.--1. " BL ,Burst length setting" "Fixed to 8,?..."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DBADJ0,DBSC3 Operation Adjustment Register 0"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 16.--17. " FREQRATIO ,PHY frequency ratio setting bits" ",DBSC3,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 0. " CAMODE ,Command/Address output mode setting" ",1 command output in 2 clock cycle"
|
|
else
|
|
bitfld.long 0x00 0. " CAMODE ,Command/Address output mode setting" "1 command output in 1 clock cycle,1 command output in 2 clock cycle"
|
|
endif
|
|
sif !cpuis("R8A774*")&&!cpuis("R8A77470")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DBADJ1,DBSC3 Operation Adjustment Register 1"
|
|
bitfld.long 0x00 0. " AOOEN ,Out-of-Order process enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DBADJ2,DBSC3 Operation Adjustment Register 2"
|
|
sif cpuis("R8A77440")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77420")
|
|
hexmask.long.byte 0x00 24.--31. 1. " ACAPC1 ,Bits for setting data cell count acceptable by device control unit (high priority port)"
|
|
bitfld.long 0x00 16.--19. 1. " ACAPX1 ,Bits for setting data cell count acceptable by device control unit (high priority port)" ",,,,fewer,,,,default,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ACAPC0 ,Bits for setting data cell count acceptable by device control unit (low priority port)"
|
|
bitfld.long 0x00 0.--3. " ACAPX0 ,Bits for setting transaction count acceptable by device control unit (low priority port)" ",,,,fewer,,,,default,?..."
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x00 8.--15. 1. " ACAPC0 ,Bits for setting data cell count acceptable by device control unit"
|
|
bitfld.long 0x00 0.--3. " ACAPX0 ,Bits for setting transaction count acceptable by device control unit" ",,,,fewer,,,,default,?..."
|
|
endif
|
|
sif !cpuis("R8A774*")
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "DBADJ3,DBSC3 Operation Adjustment Register 3"
|
|
endif
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "DBRFCNF0,Refresh Configuration Register 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " REFTHF ,Forcible auto-refresh threshold setting"
|
|
line.long 0x04 "DBRFCNF1,Refresh Configuration Register 1"
|
|
sif cpuis("R8A774*")
|
|
hexmask.long.word 0x04 16.--31. 1. " REFPMAX ,Maximum post number of refresh commands setting"
|
|
hexmask.long.word 0x04 0.--15. 1. " REFINT ,Average refresh interval setting"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " REFPMAX ,Maximum post number of refresh commands setting" "Zero cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
hexmask.long.word 0x04 0.--15. 1. " REFINT ,Average refresh interval setting"
|
|
endif
|
|
line.long 0x08 "DBRFCNF2,Refresh Configuration Register 2"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x08 16.--19. " REFPMIN ,Minimum post number of refresh commands setting bits" ",1,?..."
|
|
bitfld.long 0x08 0. " REFINTS ,Average refresh interval adjustment" "REFINT,1/2 REFINT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 0. " REFINTS ,Average refresh interval adjustment" "REFINT,1/2 REFINT"
|
|
endif
|
|
group.long 0xF4++0x07
|
|
line.long 0x00 "DBCALCNF,DDR3-SDRAM Calibration Configuration Register"
|
|
bitfld.long 0x00 24. " CALEN ,DDR3-SDRAM calibration enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " CALINT ,DDR3-SDRAM calibration frequency setting bits "
|
|
line.long 0x04 "DBCALTR,DDR3-SDRAM Calibration Timing Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " TCALRZ ,DDR3-SDRAM calibration timing setting (REF to ZQCS Interval)"
|
|
hexmask.long.word 0x04 0.--11. 1. " TCALZR ,DDR3-SDRAM calibration timing setting (ZQCS to REF Interval)"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DBRNK0,ODT Operation Setting Register"
|
|
bitfld.long 0x00 16. " RODTOUT0 ,Bit for ODT output level setting at read" "0,1"
|
|
bitfld.long 0x00 0. " WODTOUT0 ,Bit for ODT output level setting at write" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DBPDNCNF,Power-down Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PDWAIT ,Power-down wait"
|
|
bitfld.long 0x00 4. " PDDLL ,Power-down DLL control" "Off at precharged power-down/On at active power-down,On at power-down"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PDMODE ,Power-down/self-refresh mode bits" "Disabled,Enabled,?..."
|
|
sif cpuis("R8A77470")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DBPDCNT0,PHY Unit Control Register 0"
|
|
bitfld.long 0x00 31. " BW32 ,PHY unit 32-Bit mode setting" ",32-bit"
|
|
bitfld.long 0x00 20. " ODT_DIS ,Internal ODT enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ODT_TSEL ,Internal ODT impedance setting" ",60 ohms,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DBPDCNT1,PHY Unit Control Register 1"
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "DBPDCNT2,PHY Unit Control Register 2"
|
|
bitfld.long 0x00 26. " NC_SIG[8] ,Fixed control signal setting bit 8 - |M0(/1)RESET" "Not fixed,Fixed"
|
|
bitfld.long 0x00 25. " NC_SIG[7] ,Fixed control signal setting bit 7 - M0(/1)A[15]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NC_SIG[6] ,Fixed control signal setting bit 6 - M0(/1)A[14]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 23. " NC_SIG[5] ,Fixed control signal setting bit 5 - M0(/1)A[13]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " NC_SIG[4] ,Fixed control signal setting bit 4 - M0(/1)BA[2]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 21. " NC_SIG[3] ,Fixed control signal setting bit 3 - |M0(/1)CS[1] and M0(/1)CKE[1] and M0(/1)ODT[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NC_SIG[2] ,Fixed control signal setting bit 2 - |M0(/1)CS[0] and M0(/1)CKE[0] and M0(/1)ODT[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 19. " NC_SIG[1] ,Fixed control signal setting bit 1 - M0(/1)CK[1] and |M0(/1)CK[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NC_SIG[0] ,Fixed control signal setting bit 0 - M0(/1)CK[0] and |M0(/1)CK[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 16.--17. " NC_FIX ,Control signal fixed value setting" "Not fixed,Initial value,Hi-Z state,?..."
|
|
line.long 0x04 "DBPDCNT3,PHY Unit Control Register 3"
|
|
bitfld.long 0x04 31. " PLL2_RESET ,Reset signal bit for PLL2 in PHY unit" "Reset,No reset"
|
|
bitfld.long 0x04 29. " STBY[1] ,Clock signal standby setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x04 28. " STBY[0] ,Clock signal standby setting" "Low,Hi-Z"
|
|
bitfld.long 0x04 27. " COM_HIZ ,Control signal Hi-Z setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x04 24. " DLL_RESET ,DLL reset" "Reset,No reset"
|
|
bitfld.long 0x04 13. " IO_ENABLE ,I/O enable setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CALMODE ,Calibration mode setting" "External control,Automatic calibration"
|
|
bitfld.long 0x04 10. " CALEN ,Automatic calibration setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PTRRST ,Pointer reset" "No reset,Reset"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x00 0.--1. " BKADM ,Bank assignment setting" "One block,?..."
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DBWT0CNF0,AXI Port Setting Register 0"
|
|
bitfld.long 0x00 16.--18. " WASYN ,WASYN field setting" ",,2,?..."
|
|
bitfld.long 0x00 0.--2. " WCN ,AXI clock to memory clock ratio setting bits" "0.5 MCLK<AXICLK<MCLK,MCLK<AXICLK<1.2 MCLK,1.2 MCLK<AXICLK<1.4 MCLK,1.4 MCLK<AXICLK<1.6 MCLK,1.6 MCLK<AXICLK<1.8 MCLK,1.8 MCLK<AXICLK<2 MCLK,?..."
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DBWT0CNF4,AXI Port Setting Register 4"
|
|
bitfld.long 0x00 0.--4. " RDFIIFONUM ,Specifies the capacity of the read data FIFO" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32"
|
|
elif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "DBDFISTAT,DFI Status IF Input Register"
|
|
bitfld.long 0x00 0. " INITCOMPL ,This bit is only used in the initialization sequence" "0,1"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DBDFICNT,DFI Status IF Output Register"
|
|
bitfld.long 0x00 4.--5. " FREQRATIO ,Frequency ratio settings in initialization sequence" "Usual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " INITSTART ,Initialization sequence start" "0,1"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DBPDLCK,PHY Unit Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLOCK ,PHY unit access lock setting"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "DBPDRGA,PHY Unit Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x1 " PRA ,PHY unit address register"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "DBPDRGD,PHY Unit Access Register"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x00 0.--1. " BKADM ,Bank assignment setting" "One block,Two blocks,Three blocks,Four blocks"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DBWT0CNF0,AXI Port Setting Register 0"
|
|
bitfld.long 0x00 16.--19. " WASYN ,WASYN field setting" ",,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WCN ,AXI clock to memory clock ratio setting bits" "0.5 MCLK<AXICLK<MCLK,MCLK<AXICLK<1.2 MCLK,1.2 MCLK<AXICLK<1.4 MCLK,1.4 MCLK<AXICLK<1.6 MCLK,1.6 MCLK<AXICLK<1.8 MCLK,1.8 MCLK<AXICLK<2 MCLK,?..."
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DBWT0CNF4,AXI Port Setting Register 4"
|
|
bitfld.long 0x00 0.--4. " RDFIIFONUM ,Specifies the capacity of the read data FIFO" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "DBSCHECNT0,Scheduler Setting Register 0"
|
|
bitfld.long 0x00 0.--1. " ARBEN ,Latency port enable bits" "Fixed,?..."
|
|
else
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "DBPDCNT0,PHY Unit Control Register 0"
|
|
bitfld.long 0x00 31. " BW32 ,PHY unit 32-Bit mode setting" ",32-bit"
|
|
bitfld.long 0x00 30. " BW16 ,PHY unit 16-Bit mode setting" ",16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 25.--27. " ADDMOD ,Command address signal output delay mode" "Disabled,?..."
|
|
bitfld.long 0x00 22.--24. " CMDMOD ,Bits for command signal output delay mode setting for each rank" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " ODT_MODE ,External ODT output mode switch" "Normal,?..."
|
|
bitfld.long 0x00 20. " ODT_DIS ,Internal ODT Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ODT_EN_SEL ,Bits for internal ODT assert period setting at read" "Normal,?..."
|
|
bitfld.long 0x00 16.--17. " ODT_TSEL ,Internal ODT impedance setting" ",60 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OFFSET ,Additional read latency setting" "No latency,1 latency,2 latency,3 latency,4 latency,5 latency,6 latency,7 latency,8 latency,9 latency,10 latency,11 latency,12 latency,13 latency,14 latency,15 latency"
|
|
line.long 0x04 "DBPDCNT1,PHY Unit Control Register 1"
|
|
bitfld.long 0x04 20. " DIC_RESET ,Reset signal buffer-drive strength setting" "40 ohms,34 ohms"
|
|
bitfld.long 0x04 19. " DIC_DQDM ,Data signal buffer-drive strength setting" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18. " DIC_DQS ,DQS signal buffer-drive strength setting" "40 ohms,34 ohms"
|
|
bitfld.long 0x04 16.--17. " DIC_ADD ,Command address signal buffer-drive strength setting" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " DIC_CMD1 ,Command Signal 1 Buffer-Drive Strength Setting Bits for Each Rank" "40 ohms,?..."
|
|
bitfld.long 0x04 8.--9. " DIC_CMD0 ,Command signal 0 buffer-drive strength setting bits for each rank" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " DIC_CK1 ,Clock signal 1 buffer-drive strength setting" "40 ohms,34 ohms,?..."
|
|
bitfld.long 0x04 0.--1. " DIC_CK0 ,Clock signal 0 buffer-drive strength setting" "40 ohms,34 ohms,?..."
|
|
line.long 0x08 "DBPDCNT2,PHY Unit Control Register 2"
|
|
bitfld.long 0x08 26. " NC_SIG[8] ,Fixed control signal setting bit 8 - |M0(/1)RESET" "Not fixed,Fixed"
|
|
bitfld.long 0x08 25. " NC_SIG[7] ,Fixed control signal setting bit 7 - M0(/1)A[15]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 24. " NC_SIG[6] ,Fixed control signal setting bit 6 - M0(/1)A[14]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 23. " NC_SIG[5] ,Fixed control signal setting bit 5 - M0(/1)A[13]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 22. " NC_SIG[4] ,Fixed control signal setting bit 4 - M0(/1)BA[2]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 21. " NC_SIG[3] ,Fixed control signal setting bit 3 - |M0(/1)CS[1] and M0(/1)CKE[1] and M0(/1)ODT[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 20. " NC_SIG[2] ,Fixed control signal setting bit 2 - |M0(/1)CS[0] and M0(/1)CKE[0] and M0(/1)ODT[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 19. " NC_SIG[1] ,Fixed control signal setting bit 1 - M0(/1)CK[1] and |M0(/1)CK[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 18. " NC_SIG[0] ,Fixed control signal setting bit 0 - M0(/1)CK[0] and |M0(/1)CK[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 16.--17. " NC_FIX ,Control signal fixed value setting" "Not fixed,Initial value,Hi-Z state,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " FREQ ,Frequency range setting" "Normal,?..."
|
|
line.long 0x0C "DBPDCNT3,PHY Unit Control Register 3"
|
|
bitfld.long 0x0C 31. " PLL2_RESET ,Reset signal bit for PLL2 in PHY unit" "Reset,No reset"
|
|
bitfld.long 0x0C 30. " PLL2_BYPASS ,Bypass setting bit for PLL2 in PHY unit" "Used,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0C 28.--29. " STBY ,Clock signal standby setting" "M0(/1)CK[0] and |M0(/1)CK[0],M0(/1)CK[1] and |M0(/1)CK[1],?..."
|
|
bitfld.long 0x0C 27. " COM_HIZ ,Control signal Hi-Z setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " DLL_RESET ,DLL Reset" "Reset,No reset"
|
|
bitfld.long 0x0C 13. " IO_ENABLE ,I/O enable setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CALMODE ,Calibration mode setting" "External control,Automatic calibration"
|
|
bitfld.long 0x0C 10. " CALEN ,Automatic calibration setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " PTRRST ,Pointer reset" "No reset,Reset"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "DBBS0CNT0,Bus Control Unit 0 Control Register 0"
|
|
bitfld.long 0x00 0. " BKCEN ,Bank cache enable" "Disabled,Enabled"
|
|
line.long 0x04 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x04 0.--1. " BKADM ,Bank assignment setting" "One block,Two blocks,Three blocks,Four blocks"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DBSC3_1"
|
|
base ad:0xFEC00000
|
|
width 12.
|
|
sif !cpuis("R8A77440")&&!cpuis("R8A77420")&&!cpuis("R8A77450")&&!cpuis("R8A77430")
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DBSTATE1,DBSC3 Status Register 1"
|
|
sif cpu()!="R8A77470"
|
|
bitfld.long 0x00 16.--17. " THRML ,External temperature sensor" "Higher than -10 C,Higher/lower than -15 C/-10 C,,-15 C or lower"
|
|
bitfld.long 0x00 8. " ENDN ,Endian monitor" "Big endian,Little endian"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " BKUP ,Power-Supply Backup Monitor" "Low,High"
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DBACEN,SDRAM Access Enable Register"
|
|
bitfld.long 0x00 0. " ACCEN ,SDRAM access enable" "Disabled,Enabled"
|
|
line.long 0x04 "DBRFEN,Auto-refresh Enable Register"
|
|
bitfld.long 0x04 0. " ARFEN ,Auto-refresh enable" "Stop,Start"
|
|
if ((((per.l(ad:0xFEC00000+0x18))&0x3F000000)==0x28000000)||(((per.l(ad:0xFEC00000+0x18))&0x3F000000)==0x29000000)||(((per.l(ad:0xFEC00000+0x18))&0x3F000000)==0x2A000000)||(((per.l(ad:0xFEC00000+0x18))&0x3F000000)==0x2B000000))
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DBCMD,Manual Command-Issuing Register"
|
|
bitfld.long 0x00 24.--29. " OPC ,Operation code" "Wait,,ZQCS,ZQCL,,,,,,,,PREA,Ref,,,PDEn,PDXt,SRXt,,,,,,SREn,SRXt,,,,,,,RstL,RstH,,,,,,,MRS0,MRS1,MRS2,MRS3,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " ARG ,Parameter bits - value to be issued on the address pins of SDRAM"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DBCMD,Manual Command-Issuing Register"
|
|
bitfld.long 0x00 24.--29. " OPC ,Operation code" "Wait,,ZQCS,ZQCL,,,,,,,,PREA,Ref,,,PDEn,PDXt,SRXt,,,,,,SREn,SRXt,,,,,,,RstL,RstH,,,,,,,MRS0,MRS1,MRS2,MRS3,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " ARG ,Parameter bits - minimum interval to issuing of the next command in SDRAM cycles"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DBWAIT,Operation Completion Waiting Register"
|
|
bitfld.long 0x00 0. " WAIT ,Operation completion waiting" "Low,High"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DBKIND,SDRAM Type Setting Register"
|
|
bitfld.long 0x00 0.--2. " DDCG ,SDRAM kind" ",,,,,,,DDR3-SDRAM"
|
|
line.long 0x04 "DBCONF0,SDRAM Configuration Setting Register 0"
|
|
bitfld.long 0x04 24.--28. " AWRW0 ,Row address bit width setting" ",,,,,,,,,,,,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x04 20. " AWRK0 ,Number of ranks setting" "One rank,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--17. " AWBK0 ,Number of banks setting" ",,,Eight banks"
|
|
textline " "
|
|
sif cpuis("R8A77440")||cpuis("R8A77450")||cpuis("R8A77430")||cpuis("R8A77470")||cpuis("R8A77420")
|
|
bitfld.long 0x04 8.--11. " AWCL0 ,Column address bit width setting" ",,,,,,,,,,10 bits,11 bits,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 8.--11. " AWCL0 ,Column address bit width setting" ",,,,,,,,,9 bits,10 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0.--1. " DW0 ,External data bus width setting" ",16 bits,32 bits,?..."
|
|
sif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DBPHYTYPE,PHY Type Setting Register"
|
|
bitfld.long 0x00 0.--1. " PHYTYPE ,PHY type setting bits" ",DFI,?..."
|
|
endif
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DBTR0,SDRAM Timing Register 0"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x00 0.--3. " CL ,CAS latency setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,?..."
|
|
else
|
|
bitfld.long 0x00 0.--3. " CL ,CAS latency setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x04 "DBTR1,SDRAM Timing Register 1"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x04 0.--3. " CWL ,CAS write latency setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
else
|
|
bitfld.long 0x04 0.--3. " CWL ,CAS write latency setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
endif
|
|
line.long 0x08 "DBTR2,SDRAM Timing Register 2"
|
|
bitfld.long 0x08 0.--3. " AL ,Additive latency setting" "Zero cycles,?..."
|
|
group.long 0x50++0x43
|
|
line.long 0x00 "DBTR3,SDRAM Timing Register 3"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 0.--4. " TRCD ,ACT to READ/ACT to WRITE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
else
|
|
bitfld.long 0x00 0.--3. " TRCD ,ACT to READ/ACT to WRITE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x04 "DBTR4,SDRAM Timing Register 4"
|
|
sif cpuis("R8A7744*")
|
|
bitfld.long 0x04 16.--20. " TRPA ,PREA time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
bitfld.long 0x04 0.--4. " TRP ,PRE time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " TRPA ,PREA time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
bitfld.long 0x04 0.--3. " TRP ,PRE time setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,?..."
|
|
endif
|
|
line.long 0x08 "DBTR5,SDRAM Timing Register 5"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x08 0.--5. " TRC ,ACT to ACT/ACT to REF interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 0.--5. " TRC ,ACT to ACT/ACT to REF interval setting" ",,,,,,,,,,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,?..."
|
|
textline " "
|
|
endif
|
|
line.long 0x0C "DBTR6,SDRAM Timing Register 6"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x0C 0.--5. " TRAS ,ACT to PRE interval setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,?..."
|
|
else
|
|
bitfld.long 0x0C 0.--5. " TRAS ,ACT to PRE interval setting" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,?..."
|
|
endif
|
|
line.long 0x10 "DBTR7,SDRAM Timing Register 7"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x10 0.--3. " TRRD ,ACT(A) to ACT(B) interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
else
|
|
bitfld.long 0x10 0.--3. " TRRD ,ACT(A) to ACT(B) interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,,,,?..."
|
|
endif
|
|
line.long 0x14 "DBTR8,SDRAM Timing Register 8"
|
|
hexmask.long.byte 0x14 0.--7. 1. " TFAW ,Four activate window length setting"
|
|
line.long 0x18 "DBTR9,SDRAM Timing Register 9"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x18 0.--3. " TRDPR ,READ-PRE interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
else
|
|
bitfld.long 0x18 0.--3. " TRDPR ,READ-PRE interval setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
endif
|
|
line.long 0x1C "DBTR10,SDRAM Timing Register 10"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x1C 0.--3. " TWR ,Write-recovery period setting" ",,,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,?..."
|
|
else
|
|
bitfld.long 0x1C 0.--3. " TWR ,Write-recovery period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,?..."
|
|
endif
|
|
line.long 0x20 "DBTR11,SDRAM Timing Register 11"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x20 0.--5. " TRDWR ,READ to WRITE interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,?..."
|
|
else
|
|
bitfld.long 0x20 0.--5. " TRDWR ,READ to WRITE interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,?..."
|
|
endif
|
|
line.long 0x24 "DBTR12,SDRAM Timing Register 12"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x24 0.--5. " TWRRD ,WRITE to READ interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,?..."
|
|
else
|
|
bitfld.long 0x24 0.--5. " TWRRD ,WRITE to READ interval setting" ",,,,,,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,?..."
|
|
endif
|
|
line.long 0x28 "DBTR13,SDRAM Timing Register 13"
|
|
sif cpuis("R8A774*")
|
|
hexmask.long.word 0x28 0.--11. 1. " TRFC ,REF to ACT/ACT to REF interval setting"
|
|
else
|
|
hexmask.long.byte 0x28 0.--7. 1. " TRFC ,REF to ACT/ACT to REF interval setting"
|
|
endif
|
|
line.long 0x2C "DBTR14,SDRAM Timing Register 14"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " TCKEHDLL ,CKEH period setting"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " TCKEH ,CKEH period setting"
|
|
line.long 0x30 "DBTR15,SDRAM Timing Register 15"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x30 16.--19. " TCKESR ,CKESR period setting bits" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
bitfld.long 0x30 0.--3. " TCKEL ,CKEL period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x30 0.--3. " TCKEL ,CKEL period setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
endif
|
|
line.long 0x34 "DBTR16,SDRAM Timing Register 16"
|
|
sif cpuis("R8A77470")
|
|
bitfld.long 0x34 28.--31. " DQIENLTNCY ,Dqienltncy setting" ",One cycle,?..."
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting bits" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " DQENLTNCY ,Dqenltncy setting bits" ",One cycle,?..."
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting bits" ",One cycle,?..."
|
|
elif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
bitfld.long 0x34 28.--31. " DQIENLTNCY ,Dqienltncy setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,?..."
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting" ",,,,,,,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
|
|
textline " "
|
|
bitfld.long 0x34 12.--15. " DQENLTNCY ,Dqenltncy setting" "Zero cycles,One cycle,2 cycles,3 cycles,4 cycles,5 cycles,?..."
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting" ",One cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
else
|
|
bitfld.long 0x34 28.--29. " DQIENLTNCY ,Dqienltncy setting" ",One cycle,?..."
|
|
bitfld.long 0x34 24.--25. " DQLOFFSET ,Dqltncy offset setting" "Zero cycles,?..."
|
|
textline " "
|
|
bitfld.long 0x34 16.--21. " DQL ,Dqltncy setting" ",,,,,,,,,,,,,,,,,,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,?..."
|
|
bitfld.long 0x34 12.--13. " DQENLTNCY ,Dqenltncy setting" ",One cycle,?..."
|
|
textline " "
|
|
bitfld.long 0x34 0.--3. " WDQL ,Wdqltncy setting" ",One cycle,?..."
|
|
endif
|
|
line.long 0x38 "DBTR17,SDRAM Timing Register 17"
|
|
bitfld.long 0x38 16.--21. " TMOD ,MRS time setting" ",,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,14 cycles,14 cycles,15 cycles,?..."
|
|
textline " "
|
|
sif !cpuis("R8A774*")
|
|
bitfld.long 0x38 0.--5. " TRDMR ,RD-MRS interval setting" ",,,,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,?..."
|
|
endif
|
|
line.long 0x3C "DBTR18,SDRAM Timing Register 18"
|
|
bitfld.long 0x3C 24.--26. " RODTL ,ODT assert period setting at read" "BL/2 cycles,BL/2 + 1 cycles,BL/2 + 2 cycles,BL/2 + 3 cycles,BL/2 + 4 cycles,BL/2 + 5 cycles,BL/2 + 6 cycles,BL/2 + 7 cycles"
|
|
textline " "
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x3C 16.--18. " RODTA ,ODT assert start timing setting bits read" "Simultaneous with the read,One cycle after the read,Two cycles after the read,Three cycles after the read,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x3C 16.--18. " RODTA ,ODT assert start timing setting bits read" "Simultaneous with the read,One cycle after the read,Two cycles after the read,Three cycles after the read,,,,One cycle before the read"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x3C 8.--10. " WODTL ,ODT assert period setting at write" "BL/2 cycles,BL/2 + 1 cycles,BL/2 + 2 cycles,BL/2 + 3 cycles,BL/2 + 4 cycles,BL/2 + 5 cycles,BL/2 + 6 cycles,BL/2 + 7 cycles"
|
|
textline " "
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x3C 0.--2. " WODTA ,ODT assert start timing setting at write" "Simultaneous with the read,1 cycle after the read,2 cycles after the read,3 cycles after the read,?..."
|
|
else
|
|
bitfld.long 0x3C 0.--2. " WODTA ,ODT assert start timing setting at write" "Simultaneous with the read,1 cycle after the read,2 cycles after the read,3 cycles after the read,,,,1 cycle before the read"
|
|
endif
|
|
line.long 0x40 "DBTR19,SDRAM Timing Register 19"
|
|
hexmask.long.byte 0x40 0.--7. 1. " TZQCS ,Calibration period setting"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DBBL,SDRAM Operation Setting Register"
|
|
bitfld.long 0x00 0.--1. " BL ,Burst length setting" "Fixed to 8,?..."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DBADJ0,DBSC3 Operation Adjustment Register 0"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 16.--17. " FREQRATIO ,PHY frequency ratio setting bits" ",DBSC3,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x00 0. " CAMODE ,Command/Address output mode setting" ",1 command output in 2 clock cycle"
|
|
else
|
|
bitfld.long 0x00 0. " CAMODE ,Command/Address output mode setting" "1 command output in 1 clock cycle,1 command output in 2 clock cycle"
|
|
endif
|
|
sif !cpuis("R8A774*")&&!cpuis("R8A77470")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DBADJ1,DBSC3 Operation Adjustment Register 1"
|
|
bitfld.long 0x00 0. " AOOEN ,Out-of-Order process enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DBADJ2,DBSC3 Operation Adjustment Register 2"
|
|
sif cpuis("R8A77440")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77420")
|
|
hexmask.long.byte 0x00 24.--31. 1. " ACAPC1 ,Bits for setting data cell count acceptable by device control unit (high priority port)"
|
|
bitfld.long 0x00 16.--19. 1. " ACAPX1 ,Bits for setting data cell count acceptable by device control unit (high priority port)" ",,,,fewer,,,,default,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ACAPC0 ,Bits for setting data cell count acceptable by device control unit (low priority port)"
|
|
bitfld.long 0x00 0.--3. " ACAPX0 ,Bits for setting transaction count acceptable by device control unit (low priority port)" ",,,,fewer,,,,default,?..."
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x00 8.--15. 1. " ACAPC0 ,Bits for setting data cell count acceptable by device control unit"
|
|
bitfld.long 0x00 0.--3. " ACAPX0 ,Bits for setting transaction count acceptable by device control unit" ",,,,fewer,,,,default,?..."
|
|
endif
|
|
sif !cpuis("R8A774*")
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "DBADJ3,DBSC3 Operation Adjustment Register 3"
|
|
endif
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "DBRFCNF0,Refresh Configuration Register 0"
|
|
hexmask.long.word 0x00 0.--11. 1. " REFTHF ,Forcible auto-refresh threshold setting"
|
|
line.long 0x04 "DBRFCNF1,Refresh Configuration Register 1"
|
|
sif cpuis("R8A774*")
|
|
hexmask.long.word 0x04 16.--31. 1. " REFPMAX ,Maximum post number of refresh commands setting"
|
|
hexmask.long.word 0x04 0.--15. 1. " REFINT ,Average refresh interval setting"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " REFPMAX ,Maximum post number of refresh commands setting" "Zero cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,?..."
|
|
hexmask.long.word 0x04 0.--15. 1. " REFINT ,Average refresh interval setting"
|
|
endif
|
|
line.long 0x08 "DBRFCNF2,Refresh Configuration Register 2"
|
|
sif cpuis("R8A774*")
|
|
bitfld.long 0x08 16.--19. " REFPMIN ,Minimum post number of refresh commands setting bits" ",1,?..."
|
|
bitfld.long 0x08 0. " REFINTS ,Average refresh interval adjustment" "REFINT,1/2 REFINT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x08 0. " REFINTS ,Average refresh interval adjustment" "REFINT,1/2 REFINT"
|
|
endif
|
|
group.long 0xF4++0x07
|
|
line.long 0x00 "DBCALCNF,DDR3-SDRAM Calibration Configuration Register"
|
|
bitfld.long 0x00 24. " CALEN ,DDR3-SDRAM calibration enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " CALINT ,DDR3-SDRAM calibration frequency setting bits "
|
|
line.long 0x04 "DBCALTR,DDR3-SDRAM Calibration Timing Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " TCALRZ ,DDR3-SDRAM calibration timing setting (REF to ZQCS Interval)"
|
|
hexmask.long.word 0x04 0.--11. 1. " TCALZR ,DDR3-SDRAM calibration timing setting (ZQCS to REF Interval)"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DBRNK0,ODT Operation Setting Register"
|
|
bitfld.long 0x00 16. " RODTOUT0 ,Bit for ODT output level setting at read" "0,1"
|
|
bitfld.long 0x00 0. " WODTOUT0 ,Bit for ODT output level setting at write" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DBPDNCNF,Power-down Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PDWAIT ,Power-down wait"
|
|
bitfld.long 0x00 4. " PDDLL ,Power-down DLL control" "Off at precharged power-down/On at active power-down,On at power-down"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PDMODE ,Power-down/self-refresh mode bits" "Disabled,Enabled,?..."
|
|
sif cpuis("R8A77470")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DBPDCNT0,PHY Unit Control Register 0"
|
|
bitfld.long 0x00 31. " BW32 ,PHY unit 32-Bit mode setting" ",32-bit"
|
|
bitfld.long 0x00 20. " ODT_DIS ,Internal ODT enable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " ODT_TSEL ,Internal ODT impedance setting" ",60 ohms,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DBPDCNT1,PHY Unit Control Register 1"
|
|
group.long 0x208++0x07
|
|
line.long 0x00 "DBPDCNT2,PHY Unit Control Register 2"
|
|
bitfld.long 0x00 26. " NC_SIG[8] ,Fixed control signal setting bit 8 - |M0(/1)RESET" "Not fixed,Fixed"
|
|
bitfld.long 0x00 25. " NC_SIG[7] ,Fixed control signal setting bit 7 - M0(/1)A[15]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NC_SIG[6] ,Fixed control signal setting bit 6 - M0(/1)A[14]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 23. " NC_SIG[5] ,Fixed control signal setting bit 5 - M0(/1)A[13]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " NC_SIG[4] ,Fixed control signal setting bit 4 - M0(/1)BA[2]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 21. " NC_SIG[3] ,Fixed control signal setting bit 3 - |M0(/1)CS[1] and M0(/1)CKE[1] and M0(/1)ODT[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " NC_SIG[2] ,Fixed control signal setting bit 2 - |M0(/1)CS[0] and M0(/1)CKE[0] and M0(/1)ODT[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 19. " NC_SIG[1] ,Fixed control signal setting bit 1 - M0(/1)CK[1] and |M0(/1)CK[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x00 18. " NC_SIG[0] ,Fixed control signal setting bit 0 - M0(/1)CK[0] and |M0(/1)CK[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x00 16.--17. " NC_FIX ,Control signal fixed value setting" "Not fixed,Initial value,Hi-Z state,?..."
|
|
line.long 0x04 "DBPDCNT3,PHY Unit Control Register 3"
|
|
bitfld.long 0x04 31. " PLL2_RESET ,Reset signal bit for PLL2 in PHY unit" "Reset,No reset"
|
|
bitfld.long 0x04 29. " STBY[1] ,Clock signal standby setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x04 28. " STBY[0] ,Clock signal standby setting" "Low,Hi-Z"
|
|
bitfld.long 0x04 27. " COM_HIZ ,Control signal Hi-Z setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x04 24. " DLL_RESET ,DLL reset" "Reset,No reset"
|
|
bitfld.long 0x04 13. " IO_ENABLE ,I/O enable setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CALMODE ,Calibration mode setting" "External control,Automatic calibration"
|
|
bitfld.long 0x04 10. " CALEN ,Automatic calibration setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PTRRST ,Pointer reset" "No reset,Reset"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x00 0.--1. " BKADM ,Bank assignment setting" "One block,?..."
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DBWT0CNF0,AXI Port Setting Register 0"
|
|
bitfld.long 0x00 16.--18. " WASYN ,WASYN field setting" ",,2,?..."
|
|
bitfld.long 0x00 0.--2. " WCN ,AXI clock to memory clock ratio setting bits" "0.5 MCLK<AXICLK<MCLK,MCLK<AXICLK<1.2 MCLK,1.2 MCLK<AXICLK<1.4 MCLK,1.4 MCLK<AXICLK<1.6 MCLK,1.6 MCLK<AXICLK<1.8 MCLK,1.8 MCLK<AXICLK<2 MCLK,?..."
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DBWT0CNF4,AXI Port Setting Register 4"
|
|
bitfld.long 0x00 0.--4. " RDFIIFONUM ,Specifies the capacity of the read data FIFO" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32"
|
|
elif cpuis("R8A77420")||cpuis("R8A77430")||cpuis("R8A77450")||cpuis("R8A77440")
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "DBDFISTAT,DFI Status IF Input Register"
|
|
bitfld.long 0x00 0. " INITCOMPL ,This bit is only used in the initialization sequence" "0,1"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "DBDFICNT,DFI Status IF Output Register"
|
|
bitfld.long 0x00 4.--5. " FREQRATIO ,Frequency ratio settings in initialization sequence" "Usual,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " INITSTART ,Initialization sequence start" "0,1"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "DBPDLCK,PHY Unit Lock Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " PLOCK ,PHY unit access lock setting"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "DBPDRGA,PHY Unit Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x1 " PRA ,PHY unit address register"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "DBPDRGD,PHY Unit Access Register"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x00 0.--1. " BKADM ,Bank assignment setting" "One block,Two blocks,Three blocks,Four blocks"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "DBWT0CNF0,AXI Port Setting Register 0"
|
|
bitfld.long 0x00 16.--19. " WASYN ,WASYN field setting" ",,2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " WCN ,AXI clock to memory clock ratio setting bits" "0.5 MCLK<AXICLK<MCLK,MCLK<AXICLK<1.2 MCLK,1.2 MCLK<AXICLK<1.4 MCLK,1.4 MCLK<AXICLK<1.6 MCLK,1.6 MCLK<AXICLK<1.8 MCLK,1.8 MCLK<AXICLK<2 MCLK,?..."
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "DBWT0CNF4,AXI Port Setting Register 4"
|
|
bitfld.long 0x00 0.--4. " RDFIIFONUM ,Specifies the capacity of the read data FIFO" ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,32"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "DBSCHECNT0,Scheduler Setting Register 0"
|
|
bitfld.long 0x00 0.--1. " ARBEN ,Latency port enable bits" "Fixed,?..."
|
|
else
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "DBPDCNT0,PHY Unit Control Register 0"
|
|
bitfld.long 0x00 31. " BW32 ,PHY unit 32-Bit mode setting" ",32-bit"
|
|
bitfld.long 0x00 30. " BW16 ,PHY unit 16-Bit mode setting" ",16-bit"
|
|
textline " "
|
|
bitfld.long 0x00 25.--27. " ADDMOD ,Command address signal output delay mode" "Disabled,?..."
|
|
bitfld.long 0x00 22.--24. " CMDMOD ,Bits for command signal output delay mode setting for each rank" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " ODT_MODE ,External ODT output mode switch" "Normal,?..."
|
|
bitfld.long 0x00 20. " ODT_DIS ,Internal ODT Enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " ODT_EN_SEL ,Bits for internal ODT assert period setting at read" "Normal,?..."
|
|
bitfld.long 0x00 16.--17. " ODT_TSEL ,Internal ODT impedance setting" ",60 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OFFSET ,Additional read latency setting" "No latency,1 latency,2 latency,3 latency,4 latency,5 latency,6 latency,7 latency,8 latency,9 latency,10 latency,11 latency,12 latency,13 latency,14 latency,15 latency"
|
|
line.long 0x04 "DBPDCNT1,PHY Unit Control Register 1"
|
|
bitfld.long 0x04 20. " DIC_RESET ,Reset signal buffer-drive strength setting" "40 ohms,34 ohms"
|
|
bitfld.long 0x04 19. " DIC_DQDM ,Data signal buffer-drive strength setting" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 18. " DIC_DQS ,DQS signal buffer-drive strength setting" "40 ohms,34 ohms"
|
|
bitfld.long 0x04 16.--17. " DIC_ADD ,Command address signal buffer-drive strength setting" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " DIC_CMD1 ,Command Signal 1 Buffer-Drive Strength Setting Bits for Each Rank" "40 ohms,?..."
|
|
bitfld.long 0x04 8.--9. " DIC_CMD0 ,Command signal 0 buffer-drive strength setting bits for each rank" "40 ohms,?..."
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " DIC_CK1 ,Clock signal 1 buffer-drive strength setting" "40 ohms,34 ohms,?..."
|
|
bitfld.long 0x04 0.--1. " DIC_CK0 ,Clock signal 0 buffer-drive strength setting" "40 ohms,34 ohms,?..."
|
|
line.long 0x08 "DBPDCNT2,PHY Unit Control Register 2"
|
|
bitfld.long 0x08 26. " NC_SIG[8] ,Fixed control signal setting bit 8 - |M0(/1)RESET" "Not fixed,Fixed"
|
|
bitfld.long 0x08 25. " NC_SIG[7] ,Fixed control signal setting bit 7 - M0(/1)A[15]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 24. " NC_SIG[6] ,Fixed control signal setting bit 6 - M0(/1)A[14]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 23. " NC_SIG[5] ,Fixed control signal setting bit 5 - M0(/1)A[13]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 22. " NC_SIG[4] ,Fixed control signal setting bit 4 - M0(/1)BA[2]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 21. " NC_SIG[3] ,Fixed control signal setting bit 3 - |M0(/1)CS[1] and M0(/1)CKE[1] and M0(/1)ODT[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 20. " NC_SIG[2] ,Fixed control signal setting bit 2 - |M0(/1)CS[0] and M0(/1)CKE[0] and M0(/1)ODT[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 19. " NC_SIG[1] ,Fixed control signal setting bit 1 - M0(/1)CK[1] and |M0(/1)CK[1]" "Not fixed,Fixed"
|
|
textline " "
|
|
bitfld.long 0x08 18. " NC_SIG[0] ,Fixed control signal setting bit 0 - M0(/1)CK[0] and |M0(/1)CK[0]" "Not fixed,Fixed"
|
|
bitfld.long 0x08 16.--17. " NC_FIX ,Control signal fixed value setting" "Not fixed,Initial value,Hi-Z state,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " FREQ ,Frequency range setting" "Normal,?..."
|
|
line.long 0x0C "DBPDCNT3,PHY Unit Control Register 3"
|
|
bitfld.long 0x0C 31. " PLL2_RESET ,Reset signal bit for PLL2 in PHY unit" "Reset,No reset"
|
|
bitfld.long 0x0C 30. " PLL2_BYPASS ,Bypass setting bit for PLL2 in PHY unit" "Used,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x0C 28.--29. " STBY ,Clock signal standby setting" "M0(/1)CK[0] and |M0(/1)CK[0],M0(/1)CK[1] and |M0(/1)CK[1],?..."
|
|
bitfld.long 0x0C 27. " COM_HIZ ,Control signal Hi-Z setting" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " DLL_RESET ,DLL Reset" "Reset,No reset"
|
|
bitfld.long 0x0C 13. " IO_ENABLE ,I/O enable setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " CALMODE ,Calibration mode setting" "External control,Automatic calibration"
|
|
bitfld.long 0x0C 10. " CALEN ,Automatic calibration setting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " PTRRST ,Pointer reset" "No reset,Reset"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "DBBS0CNT0,Bus Control Unit 0 Control Register 0"
|
|
bitfld.long 0x00 0. " BKCEN ,Bank cache enable" "Disabled,Enabled"
|
|
line.long 0x04 "DBBS0CNT1,Bus Control Unit 0 Control Register 1"
|
|
bitfld.long 0x04 0.--1. " BKADM ,Bank assignment setting" "One block,Two blocks,Three blocks,Four blocks"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SuperHyway-DMAC (Direct Memory Access Controller)"
|
|
base ad:0xFCC00000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DMAOR,DMA operation register"
|
|
bitfld.long 0x00 31. " DMAE ,DMA Master Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "DMASAR0,DMA source address registers 0"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMASAR ,DMA transfer source address"
|
|
group.long (0x20+0x8)++0x3
|
|
line.long 0x00 "DMADAR0,DMA destination address registers 0"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMADAR ,DMA transfer destination address"
|
|
group.long (0x20+0x10)++0x3
|
|
line.long 0x00 "DMABCNTR0,DMA byte count registers 0"
|
|
hexmask.long 0x00 2.--28. 0x2 " BCNT ,DMA transfer byte count"
|
|
group.long (0x20+0x14)++0x7
|
|
line.long 0x00 "DMASBCNTR0,DMA stride count registers 0"
|
|
hexmask.long.word 0x00 18.--31. 1. " SBCINI ,Initial Stride Counter"
|
|
hexmask.long.word 0x00 2.--15. 1. " SBCNT ,Stride Counter"
|
|
line.long 0x04 "DMASTRR0,DMA stride registers 0"
|
|
hexmask.long.word 0x04 18.--31. 0x4 " SS ,Stride Width of Transfer Source Address"
|
|
hexmask.long.word 0x04 2.--15. 0x2 " DS ,Stride Width of Transfer Destination Address"
|
|
group.long (0x20+0x20)++0x03
|
|
line.long 0x00 "DMACCAR0,DMA command chain 0"
|
|
hexmask.long 0x00 5.--31. 1. " CCA ,Command Chain Address"
|
|
group.long (0x20+0x28)++0x07
|
|
line.long 0x00 "DMACHCR0,DMA channel control 0"
|
|
bitfld.long 0x00 31. " CHE ,DMA Channel Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CCRE ,Command Chain Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SASRE ,Transfer Source Address Stride Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DASRE ,Transfer Destination Address Stride Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACHSR0,DMA channel status 0"
|
|
bitfld.long 0x04 27. " SEE ,Transfer Source Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DEE ,Transfer Destination Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 11. " SE ,Transfer Source Transfer Error Flag" "No error,Error"
|
|
eventfld.long 0x04 9. " DE ,Transfer Destination Transfer Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IE ,DMA Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x04 0. " TE ,DMA Transfer End Flag" "No error,Error"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "DMASAR1,DMA source address registers 1"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMASAR ,DMA transfer source address"
|
|
group.long (0x120+0x8)++0x3
|
|
line.long 0x00 "DMADAR1,DMA destination address registers 1"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMADAR ,DMA transfer destination address"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "DMABCNTR1,DMA byte count registers 1"
|
|
hexmask.long 0x00 2.--28. 0x2 " BCNT ,DMA transfer byte count"
|
|
group.long (0x120+0x14)++0x7
|
|
line.long 0x00 "DMASBCNTR1,DMA stride count registers 1"
|
|
hexmask.long.word 0x00 18.--31. 1. " SBCINI ,Initial Stride Counter"
|
|
hexmask.long.word 0x00 2.--15. 1. " SBCNT ,Stride Counter"
|
|
line.long 0x04 "DMASTRR1,DMA stride registers 1"
|
|
hexmask.long.word 0x04 18.--31. 0x4 " SS ,Stride Width of Transfer Source Address"
|
|
hexmask.long.word 0x04 2.--15. 0x2 " DS ,Stride Width of Transfer Destination Address"
|
|
group.long (0x120+0x20)++0x03
|
|
line.long 0x00 "DMACCAR1,DMA command chain 1"
|
|
hexmask.long 0x00 5.--31. 1. " CCA ,Command Chain Address"
|
|
group.long (0x120+0x28)++0x07
|
|
line.long 0x00 "DMACHCR1,DMA channel control 1"
|
|
bitfld.long 0x00 31. " CHE ,DMA Channel Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CCRE ,Command Chain Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SASRE ,Transfer Source Address Stride Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DASRE ,Transfer Destination Address Stride Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACHSR1,DMA channel status 1"
|
|
bitfld.long 0x04 27. " SEE ,Transfer Source Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DEE ,Transfer Destination Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 11. " SE ,Transfer Source Transfer Error Flag" "No error,Error"
|
|
eventfld.long 0x04 9. " DE ,Transfer Destination Transfer Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IE ,DMA Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x04 0. " TE ,DMA Transfer End Flag" "No error,Error"
|
|
group.long 0x220++0x3
|
|
line.long 0x00 "DMASAR2,DMA source address registers 2"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMASAR ,DMA transfer source address"
|
|
group.long (0x220+0x8)++0x3
|
|
line.long 0x00 "DMADAR2,DMA destination address registers 2"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMADAR ,DMA transfer destination address"
|
|
group.long (0x220+0x10)++0x3
|
|
line.long 0x00 "DMABCNTR2,DMA byte count registers 2"
|
|
hexmask.long 0x00 2.--28. 0x2 " BCNT ,DMA transfer byte count"
|
|
group.long (0x220+0x28)++0x07
|
|
line.long 0x00 "DMACHCR2,DMA channel control 2"
|
|
bitfld.long 0x00 29. " CCRE ,Command Chain Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACHSR2,DMA channel status 2"
|
|
bitfld.long 0x04 27. " SEE ,Transfer Source Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DEE ,Transfer Destination Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 11. " SE ,Transfer Source Transfer Error Flag" "No error,Error"
|
|
eventfld.long 0x04 9. " DE ,Transfer Destination Transfer Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IE ,DMA Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x04 0. " TE ,DMA Transfer End Flag" "No error,Error"
|
|
group.long 0x320++0x3
|
|
line.long 0x00 "DMASAR3,DMA source address registers 3"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMASAR ,DMA transfer source address"
|
|
group.long (0x320+0x8)++0x3
|
|
line.long 0x00 "DMADAR3,DMA destination address registers 3"
|
|
hexmask.long 0x00 2.--31. 0x2 " DMADAR ,DMA transfer destination address"
|
|
group.long (0x320+0x10)++0x3
|
|
line.long 0x00 "DMABCNTR3,DMA byte count registers 3"
|
|
hexmask.long 0x00 2.--28. 0x2 " BCNT ,DMA transfer byte count"
|
|
group.long (0x320+0x28)++0x07
|
|
line.long 0x00 "DMACHCR3,DMA channel control 3"
|
|
bitfld.long 0x00 29. " CCRE ,Command Chain Enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMACHSR3,DMA channel status 3"
|
|
bitfld.long 0x04 27. " SEE ,Transfer Source Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " DEE ,Transfer Destination Transfer Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x04 11. " SE ,Transfer Source Transfer Error Flag" "No error,Error"
|
|
eventfld.long 0x04 9. " DE ,Transfer Destination Transfer Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IE ,DMA Transfer End Interrupt Enable" "Disabled,Enabled"
|
|
eventfld.long 0x04 0. " TE ,DMA Transfer End Flag" "No error,Error"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMASTRS2,DMA source transfer size 2"
|
|
bitfld.long 0x00 0.--2. " STRS ,Set the DMA transfer size" "Byte units,Word,Long word,8-byte,,32-byte,?..."
|
|
group.long (0x260+0x10)++0x03
|
|
line.long 0x00 "DMADTRS2, DMA destination transfer 2"
|
|
bitfld.long 0x00 16.--18. " SWAP ,Set the swapping of STORE data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DTRS ,Set the DMA transfer size" "Byte units,Word,Long word,8-byte,,32-byte,?..."
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "DMASTRS3,DMA source transfer size 3"
|
|
bitfld.long 0x00 0.--2. " STRS ,Set the DMA transfer size" "Byte units,Word,Long word,8-byte,,32-byte,?..."
|
|
group.long (0x360+0x10)++0x03
|
|
line.long 0x00 "DMADTRS3, DMA destination transfer 3"
|
|
bitfld.long 0x00 16.--18. " SWAP ,Set the swapping of STORE data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DTRS ,Set the DMA transfer size" "Byte units,Word,Long word,8-byte,,32-byte,?..."
|
|
width 11.
|
|
tree.end
|
|
tree.open "LBSC-DMAC/HPB-DMAC (DMAC within Bus Bridge)"
|
|
tree "LBSC-DMAC"
|
|
tree "LBSC Common Registers"
|
|
base ad:0xff801400
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DTIMR,DMA Timer Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTIM ,DMAC Internal Timer Cycle Set"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DRMSKR,DMA Request Mask Control Register"
|
|
bitfld.long 0x00 8.--11. " DRMSK2 ,Number of clock cycles from the completion of a DMA transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " DRMSK1 ,Number of clock cycles from the completion of a DMA transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DRMSK0 ,Number of clock cycles from the completion of a DMA transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "DMLVLR,DMA Memory Access Priority Level Control Register"
|
|
bitfld.long 0x00 2. " DMLV2 ,External bus arbitration priority group for each DMAC channel" "Level 2,Level 1"
|
|
bitfld.long 0x00 1. " DMLV1 ,External bus arbitration priority group for each DMAC channel" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " DMLV0 ,External bus arbitration priority group for each DMAC channel" "Level 2,Level 1"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "DINTSR,DMA Transfer End Interrupt Register"
|
|
bitfld.long 0x00 2. " DTE2 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " DTE1 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE0 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "DINTCR,DMA Transfer End Interrupt Status Clear Register"
|
|
bitfld.long 0x00 2. " DTEC2 ,DMA Transfer End Interrupt Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " DTEC1 ,DMA Transfer End Interrupt Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " DTEC0 ,DMA Transfer End Interrupt Status Clear" "No effect,Clear"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "DINTMR,DMA Transfer End Interrupt Enable Register"
|
|
bitfld.long 0x00 2. " DTEM2 ,DMA Transfer End Interrupt Output Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTEM1 ,DMA Transfer End Interrupt Output Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTEM0 ,DMA Transfer End Interrupt Output Control" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DACTSR,DMA Activation Status Register"
|
|
bitfld.long 0x00 2. " DS2 ,DMA Channel 2 Status" "Idle,Active"
|
|
bitfld.long 0x00 1. " DS1 ,DMA Channel 1 Status" "Idle,Active"
|
|
bitfld.long 0x00 0. " DS0 ,DMA Channel 0 Status" "Idle,Active"
|
|
group.long 0x24++0x0b
|
|
line.long 0x0 "LSRSTR0,Software-Reset Register 0"
|
|
eventfld.long 0x0 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x4 "LSRSTR1,Software-Reset Register 1"
|
|
eventfld.long 0x4 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x8 "LSRSTR2,Software-Reset Register 2"
|
|
eventfld.long 0x8 0. " SRST ,Software Reset" "No reset,Reset"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DMALGR,External DMA Data Alignment Control Register"
|
|
bitfld.long 0x00 11. " DMLG2[EXBWE] ,EX-BUS data alignment conversion for DMAC channel 2" "Fixed,Variable"
|
|
bitfld.long 0x00 10. " DMLG2[EXAC] ,Endian setting channel 2" "Big,Little"
|
|
bitfld.long 0x00 8.--9. " DMLG2[EXBW] ,Unit for data alignment conversion" "8 bits,16 bits,,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMLG1[EXBWE] ,EXBUS data alignment conversion for DMAC channel 1" "Fixed,Variable"
|
|
bitfld.long 0x00 6. " DMLG1[EXAC] ,Endian setting channel 1" "Big,Little"
|
|
bitfld.long 0x00 4.--5. " DMLG2[EXBW] ,Unit for data alignment conversion" "8 bits,16 bits,,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMLG0[EXBWE] ,EXBUS data alignment conversion for DMAC channel 0" "Fixed,Variable"
|
|
bitfld.long 0x00 2. " DMLG0[EXAC] ,Endian setting channel 0" "Big,Little"
|
|
bitfld.long 0x00 0.--1. " DMLG0[EXBW] ,Unit for data alignment conversion" "8 bits,16 bits,,Invalid"
|
|
sif cpu()=="RCARM2"||cpu()=="RCARV2H"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "LBSC-DMASPR,LBSC-DMA AXI Priority Control Register"
|
|
bitfld.long 0x00 8.--11. " SPRR2 ,AXI bus access priority level for DMAC channel 2" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 4.--7. " SPRR1 ,AXI bus access priority level for DMAC channel 1" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 0.--3. " SPRR0 ,AXI bus access priority level for DMAC channel 0" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "LBSC-DMASPR,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x00 8.--11. " SPRR2 ,SHwy bus access priority level for DMAC channel 2" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 4.--7. " SPRR1 ,SHwy bus access priority level for DMAC channel 1" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 0.--3. " SPRR0 ,SHwy bus access priority level for DMAC channel 0" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
endif
|
|
sif (!cpuis("RCARV2H"))
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "UATMR,Ultra ATA DMA Mode Register"
|
|
bitfld.long 0x00 24.--25. " UTDR1 ,Select the external pin for the DREQ in the Ultra ATA 1" "No external pin,DREQ0,DREQ1,No external pin"
|
|
bitfld.long 0x00 21. " UTWE1 ,Enables or disables data alignment conversion for write operation in the Ultra ATA 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " UTRE1 ,Enables or disables data alignment conversion for read operation in the Ultra ATA 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " UTSL1 ,Select the external pin for the IORDY in the Ultra ATA 1" "No external pin,EX_WAIT0,EX_WAIT1,EX_WAIT2"
|
|
bitfld.long 0x00 16. " UATM1 ,Specifies the Ultra ATA 1 operating mode" "Normal DMA mode,Ultra ATA DMA mode"
|
|
bitfld.long 0x00 8.--9. " UTDR0 ,Select the external pin for the DREQ signal in the Ultra ATA 0" "No external pin,DREQ0,DREQ1,No external pin"
|
|
textline " "
|
|
bitfld.long 0x00 5. " UTWE0 ,Enables or disables data alignment conversion for write operation in the Ultra ATA 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " UTRE0 ,Enables or disables data alignment conversion for read operation in the Ultra ATA 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " UTSL0 ,Select the external pin for the IORDY in the Ultra ATA 0" "No external pin,EX_WAIT0,EX_WAIT1,EX_WAIT2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UATM0 ,Specifies the Ultra ATA 0 operating mode" "Normal DMA mode,Ultra ATA DMA mode"
|
|
line.long 0x04 "UATWCR,Ultra ATA Write Cycle Setting Register"
|
|
bitfld.long 0x04 16.--18. " UATWCYC1 ,Specify the setup and hold clock cycles of the write data in the Ultra ATA 1 [Setup/Hold]]" "1 cycle/1 cycle,2 cycles/1 cycle,2 cycles/2 cycles,3 cycles/2 cycles,3 cycles/3 cycles,4 cycles/3 cycles,4 cycles/4 cycles,5 cycles/4 cycles"
|
|
bitfld.long 0x04 0.--2. " UATWCYC0 ,Specify the setup and hold clock cycles of the write data in the Ultra ATA 0 [Setup/Hold]" "1 cycle/1 cycle,2 cycles/1 cycle,2 cycles/2 cycles,3 cycles/2 cycles,3 cycles/3 cycles,4 cycles/3 cycles,4 cycles/4 cycles,5 cycles/4 cycles"
|
|
group.long 0xC8++0x07
|
|
line.long 0x00 "UATTSR0,Ultra ATA Timeout Period Setting Register 0"
|
|
line.long 0x04 "UATTSR1,Ultra ATA Timeout Period Setting Register 1"
|
|
group.long 0xCC++0x07
|
|
line.long 0x00 "UATTER,Ultra ATA Error Indication Register"
|
|
bitfld.long 0x00 16. " DER1 ,Timeout occurs due to a temporary communication stop in Ultra ATA 1" "No timeout,Timeout"
|
|
bitfld.long 0x00 1. " PER ,PIO access is executed" "No access,Access"
|
|
bitfld.long 0x00 0. " DER0 ,Timeout occurs due to a temporary communication stop in Ultra ATA 0" "No timeout,Timeout"
|
|
line.long 0x04 "UATIER,Ultra ATA Error Interrupt Enable Register"
|
|
bitfld.long 0x04 16. " DERE1 ,DER1 interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " PERE ,PER interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " DERE0 ,DER0 interrupt" "No interrupt,Interrupt"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "UATCRCR,Ultra ATA CRC Code Indication Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CRC1 ,CRC code created from the transfer data in Ultra ATA 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CRC0 ,CRC code created from the transfer data in Ultra ATA 0"
|
|
base ad:0xFF800030
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UATTMR,Ultra ATA Transfer Mode Register"
|
|
bitfld.long 0x00 9. " DTCD1 ,Controls the operating mode for continuation in case of transfer termination in Ultra ATA 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DTCD0 ,Controls the operating mode for continuation in case of transfer termination in Ultra ATA 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DBG0 ,Test Bit" "0,1"
|
|
endif
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 0"
|
|
base ad:0xFF801000
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long 0x08 0.--25. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFF801040
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFF801080
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree "HPB-DMAC"
|
|
tree "HPB Common Registers"
|
|
base ad:0xffc09000
|
|
width 13.
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DTIMR,DMA Timer Control Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTIM ,DMAC Internal Timer Cycle Set"
|
|
rgroup.long 0x0c++0x07
|
|
line.long 0x00 "DINTSR[31:0],DMA Transfer End Interrupt Register"
|
|
bitfld.long 0x00 31. " DTE31 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " DTE30 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " DTE29 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DTE28 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " DTE27 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " DTE26 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DTE25 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " DTE24 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " DTE23 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DTE22 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " DTE21 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " DTE20 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DTE19 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " DTE18 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " DTE17 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTE16 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " DTE15 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " DTE14 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DTE13 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " DTE12 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " DTE11 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DTE10 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " DTE9 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " DTE8 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DTE7 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " DTE6 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " DTE5 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTE4 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DTE3 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " DTE2 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE1 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE0 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
line.long 0x04 "DINTSR[43:32],DMA Transfer End Interrupt Register"
|
|
bitfld.long 0x04 11. " DTE43 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " DTE142 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " DTE41 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DTE40 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " DTE39 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " DTE38 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DTE37 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " DTE36 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " DTE35 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DTE34 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " DTE33 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " DTE32 ,DMA Transfer End Interrupt Status" "No interrupt,Interrupt"
|
|
wgroup.long 0x14++0x07
|
|
line.long 0x00 "DINTCR[31:0],DMA Transfer End Interrupt Status Clear Register"
|
|
bitfld.long 0x00 31. " DTEC31 ,DMA Transfer End Interrupt Status Clear" "No effect,Clear"
|
|
bitfld.long 0x00 30. " DTEC30 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 29. " DTECC29 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DTEC28 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 27. " DTEC27 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 26. " DTEC26 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DTEC25 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 24. " DTEC24 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 23. " DTEC23 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DTEC22 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 21. " DTEC21 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " DTEC20 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DTEC19 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 18. " DTEC18 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 17. " DTEC17 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTEC16 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 15. " DTEC15 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " DTEC14 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DTEC13 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " DTEC12 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 11. " DTEC11 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DTEC10 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " DTEC9 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 8. " DTEC8 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DTEC7 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " DTEC6 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " DTEC5 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTEC4 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " DTEC3 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " DTEC2 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTEC1 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 0. " DTEC0 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
line.long 0x04 "DINTCR[43:32],DMA Transfer End Interrupt Status Clear Register"
|
|
bitfld.long 0x04 11. " DTEC43 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 10. " DTEC42 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 9. " DTEC41 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DTEC40 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 7. " DTEC39 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 6. " DTEC38 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DTEC37 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 4. " DTEC36 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 3. " DTEC35 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DTEC34 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 1. " DTEC33 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " DTEC32 ,DMA Transfer End Interrupt Status Clear" "No effect,Cleared"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "DINTMR[31:0],DMA Transfer End Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " DTEM31 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 30. " DTEM30 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 29. " DTEM29 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DTEM28 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 27. " DTEM27 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 26. " DTEM26 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DTEM25 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 24. " DTEM24 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 23. " DTEM23 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DTEM22 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 21. " DTEM21 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 20. " DTEM20 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DTEM19 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 18. " DTEM18 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 17. " DTEM17 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DTEM16 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 15. " DTEM15 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 14. " DTEM14 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DTEM13 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 12. " DTEM12 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 11. " DTEM11 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DTEM10 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 9. " DTEM9 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 8. " DTEM8 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DTEM7 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 6. " DTEM6 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 5. " DTEM5 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTEM4 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 3. " DTEM3 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 2. " DTEM2 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTEM1 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x00 0. " DTEM0 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
line.long 0x04 "DINTMR[43:32],DMA Transfer End Interrupt Enable Register"
|
|
bitfld.long 0x04 11. " DTEM43 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 10. " DTEM42 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 9. " DTEM41 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DTEM40 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 7. " DTEM39 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 6. " DTEM38 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DTEM37 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 4. " DTEM36 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 3. " DTEM35 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DTEM34 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 1. " DTEM33 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
bitfld.long 0x04 0. " DTEM32 ,DMA Transfer End Interrupt Output Control" "Not out,Out"
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "DACTSR[31:0],DMA Activation Status Register"
|
|
bitfld.long 0x00 31. " DS31 ,DMA Channel 31 Status" "Idle,Active"
|
|
bitfld.long 0x00 30. " DS30 ,DMA Channel 30 Status" "Idle,Active"
|
|
bitfld.long 0x00 29. " DS29 ,DMA Channel 29 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DS28 ,DMA Channel 28 Status" "Idle,Active"
|
|
bitfld.long 0x00 27. " DS27 ,DMA Channel 27 Status" "Idle,Active"
|
|
bitfld.long 0x00 26. " DS26 ,DMA Channel 26 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DS25 ,DMA Channel 25 Status" "Idle,Active"
|
|
bitfld.long 0x00 24. " DS24 ,DMA Channel 24 Status" "Idle,Active"
|
|
bitfld.long 0x00 23. " DS23 ,DMA Channel 23 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS22 ,DMA Channel 22 Status" "Idle,Active"
|
|
bitfld.long 0x00 21. " DS21 ,DMA Channel 21 Status" "Idle,Active"
|
|
bitfld.long 0x00 20. " DS20 ,DMA Channel 20 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DS19 ,DMA Channel 19 Status" "Idle,Active"
|
|
bitfld.long 0x00 18. " DS18 ,DMA Channel 18 Status" "Idle,Active"
|
|
bitfld.long 0x00 17. " DS17 ,DMA Channel 17 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DS16 ,DMA Channel 16 Status" "Idle,Active"
|
|
bitfld.long 0x00 15. " DS15 ,DMA Channel 15 Status" "Idle,Active"
|
|
bitfld.long 0x00 14. " DS14 ,DMA Channel 14 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DS13 ,DMA Channel 13 Status" "Idle,Active"
|
|
bitfld.long 0x00 12. " DS12 ,DMA Channel 12 Status" "Idle,Active"
|
|
bitfld.long 0x00 11. " DS11 ,DMA Channel 11 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DS10 ,DMA Channel 10 Status" "Idle,Active"
|
|
bitfld.long 0x00 9. " DS9 ,DMA Channel 9 Status" "Idle,Active"
|
|
bitfld.long 0x00 8. " DS8 ,DMA Channel 8 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DS7 ,DMA Channel 7 Status" "Idle,Active"
|
|
bitfld.long 0x00 6. " DS6 ,DMA Channel 6 Status" "Idle,Active"
|
|
bitfld.long 0x00 5. " DS5 ,DMA Channel 5 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DS4 ,DMA Channel 4 Status" "Idle,Active"
|
|
bitfld.long 0x00 3. " DS3 ,DMA Channel 3 Status" "Idle,Active"
|
|
bitfld.long 0x00 2. " DS2 ,DMA Channel 2 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DS1 ,DMA Channel 1 Status" "Idle,Active"
|
|
bitfld.long 0x00 0. " DS0 ,DMA Channel 0 Status" "Idle,Active"
|
|
line.long 0x04 "DACTSR[43:32],DMA Activation Status Register"
|
|
bitfld.long 0x04 11. " DS43 ,DMA Channel 43 Status" "Idle,Active"
|
|
bitfld.long 0x04 10. " DS42 ,DMA Channel 42 Status" "Idle,Active"
|
|
bitfld.long 0x04 9. " DS41 ,DMA Channel 41 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DS40 ,DMA Channel 40 Status" "Idle,Active"
|
|
bitfld.long 0x04 7. " DS39 ,DMA Channel 39 Status" "Idle,Active"
|
|
bitfld.long 0x04 6. " DS38 ,DMA Channel 38 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DS37 ,DMA Channel 37 Status" "Idle,Active"
|
|
bitfld.long 0x04 4. " DS36 ,DMA Channel 36 Status" "Idle,Active"
|
|
bitfld.long 0x04 3. " DS35 ,DMA Channel 35 Status" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DS34 ,DMA Channel 34 Status" "Idle,Active"
|
|
bitfld.long 0x04 1. " DS33 ,DMA Channel 33 Status" "Idle,Active"
|
|
bitfld.long 0x04 0. " DS32 ,DMA Channel 32 Status" "Idle,Active"
|
|
group.long 0x40++0xAB
|
|
line.long 0x0 "HSRSTR0,Software-Reset Register 0"
|
|
bitfld.long 0x0 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x4 "HSRSTR1,Software-Reset Register 1"
|
|
bitfld.long 0x4 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x8 "HSRSTR2,Software-Reset Register 2"
|
|
bitfld.long 0x8 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0xC "HSRSTR3,Software-Reset Register 3"
|
|
bitfld.long 0xC 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x10 "HSRSTR4,Software-Reset Register 4"
|
|
bitfld.long 0x10 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x14 "HSRSTR5,Software-Reset Register 5"
|
|
bitfld.long 0x14 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x18 "HSRSTR6,Software-Reset Register 6"
|
|
bitfld.long 0x18 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x1C "HSRSTR7,Software-Reset Register 7"
|
|
bitfld.long 0x1C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x20 "HSRSTR8,Software-Reset Register 8"
|
|
bitfld.long 0x20 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x24 "HSRSTR9,Software-Reset Register 9"
|
|
bitfld.long 0x24 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x28 "HSRSTR10,Software-Reset Register 10"
|
|
bitfld.long 0x28 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x2C "HSRSTR11,Software-Reset Register 11"
|
|
bitfld.long 0x2C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x30 "HSRSTR12,Software-Reset Register 12"
|
|
bitfld.long 0x30 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x34 "HSRSTR13,Software-Reset Register 13"
|
|
bitfld.long 0x34 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x38 "HSRSTR14,Software-Reset Register 14"
|
|
bitfld.long 0x38 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x3C "HSRSTR15,Software-Reset Register 15"
|
|
bitfld.long 0x3C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x40 "HSRSTR16,Software-Reset Register 16"
|
|
bitfld.long 0x40 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x44 "HSRSTR17,Software-Reset Register 17"
|
|
bitfld.long 0x44 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x48 "HSRSTR18,Software-Reset Register 18"
|
|
bitfld.long 0x48 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x4C "HSRSTR19,Software-Reset Register 19"
|
|
bitfld.long 0x4C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x50 "HSRSTR20,Software-Reset Register 20"
|
|
bitfld.long 0x50 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x54 "HSRSTR21,Software-Reset Register 21"
|
|
bitfld.long 0x54 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x58 "HSRSTR22,Software-Reset Register 22"
|
|
bitfld.long 0x58 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x5C "HSRSTR23,Software-Reset Register 23"
|
|
bitfld.long 0x5C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x60 "HSRSTR24,Software-Reset Register 24"
|
|
bitfld.long 0x60 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x64 "HSRSTR25,Software-Reset Register 25"
|
|
bitfld.long 0x64 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x68 "HSRSTR26,Software-Reset Register 26"
|
|
bitfld.long 0x68 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x6C "HSRSTR27,Software-Reset Register 27"
|
|
bitfld.long 0x6C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x70 "HSRSTR28,Software-Reset Register 28"
|
|
bitfld.long 0x70 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x74 "HSRSTR29,Software-Reset Register 29"
|
|
bitfld.long 0x74 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x78 "HSRSTR30,Software-Reset Register 30"
|
|
bitfld.long 0x78 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x7C "HSRSTR31,Software-Reset Register 31"
|
|
bitfld.long 0x7C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x80 "HSRSTR32,Software-Reset Register 32"
|
|
bitfld.long 0x80 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x84 "HSRSTR33,Software-Reset Register 33"
|
|
bitfld.long 0x84 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x88 "HSRSTR34,Software-Reset Register 34"
|
|
bitfld.long 0x88 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x8C "HSRSTR35,Software-Reset Register 35"
|
|
bitfld.long 0x8C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x90 "HSRSTR36,Software-Reset Register 36"
|
|
bitfld.long 0x90 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x94 "HSRSTR37,Software-Reset Register 37"
|
|
bitfld.long 0x94 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x98 "HSRSTR38,Software-Reset Register 38"
|
|
bitfld.long 0x98 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0x9C "HSRSTR39,Software-Reset Register 39"
|
|
bitfld.long 0x9C 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0xA0 "HSRSTR40,Software-Reset Register 40"
|
|
bitfld.long 0xA0 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0xA4 "HSRSTR41,Software-Reset Register 41"
|
|
bitfld.long 0xA4 0. " SRST ,Software Reset" "No reset,Reset"
|
|
line.long 0xA8 "HSRSTR42,Software-Reset Register 42"
|
|
bitfld.long 0xA8 0. " SRST ,Software Reset" "No reset,Reset"
|
|
group.long 0x140++0x17
|
|
line.long 0x00 "LBSC-DMASPR0,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x00 28.--31. " SPRR7 ,SHwy bus access priority level for DMAC channel 7" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 24.--27. " SPRR6 ,SHwy bus access priority level for DMAC channel 6" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 20.--23. " SPRR5 ,SHwy bus access priority level for DMAC channel 5" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SPRR4 ,SHwy bus access priority level for DMAC channel 4" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 12.--15. " SPRR3 ,SHwy bus access priority level for DMAC channel 3" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 8.--11. " SPRR2 ,SHwy bus access priority level for DMAC channel 2" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SPRR1 ,SHwy bus access priority level for DMAC channel 1" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x00 0.--3. " SPRR0 ,SHwy bus access priority level for DMAC channel 0" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
line.long 0x04 "LBSC-DMASPR1,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x04 28.--31. " SPRR15 ,SHwy bus access priority level for DMAC channel 15" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x04 24.--27. " SPRR14 ,SHwy bus access priority level for DMAC channel 14" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x04 20.--23. " SPRR13 ,SHwy bus access priority level for DMAC channel 13" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " SPRR12 ,SHwy bus access priority level for DMAC channel 12" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x04 12.--15. " SPRR11 ,SHwy bus access priority level for DMAC channel 11" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x04 8.--11. " SPRR10 ,SHwy bus access priority level for DMAC channel 10" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " SPRR9 ,SHwy bus access priority level for DMAC channel 9" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x04 0.--3. " SPRR8 ,SHwy bus access priority level for DMAC channel 8" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
line.long 0x08 "LBSC-DMASPR2,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x08 28.--31. " SPRR23 ,SHwy bus access priority level for DMAC channel 23" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x08 24.--27. " SPRR22 ,SHwy bus access priority level for DMAC channel 22" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x08 20.--23. " SPRR21 ,SHwy bus access priority level for DMAC channel 21" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x08 16.--19. " SPRR20 ,SHwy bus access priority level for DMAC channel 20" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x08 12.--15. " SPRR19 ,SHwy bus access priority level for DMAC channel 19" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x08 8.--11. " SPRR18 ,SHwy bus access priority level for DMAC channel 18" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " SPRR17 ,SHwy bus access priority level for DMAC channel 17" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x08 0.--3. " SPRR16 ,SHwy bus access priority level for DMAC channel 16" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
line.long 0x0C "LBSC-DMASPR3,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x0C 28.--31. " SPRR31 ,SHwy bus access priority level for DMAC channel 31" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x0C 24.--27. " SPRR30 ,SHwy bus access priority level for DMAC channel 30" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x0C 20.--23. " SPRR29 ,SHwy bus access priority level for DMAC channel 29" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--19. " SPRR28 ,SHwy bus access priority level for DMAC channel 28" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x0C 12.--15. " SPRR27 ,SHwy bus access priority level for DMAC channel 27" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x0C 8.--11. " SPRR26 ,SHwy bus access priority level for DMAC channel 26" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x0C 4.--7. " SPRR25 ,SHwy bus access priority level for DMAC channel 25" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x0C 0.--3. " SPRR24 ,SHwy bus access priority level for DMAC channel 24" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
line.long 0x10 "LBSC-DMASPR4,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x10 28.--31. " SPRR39 ,SHwy bus access priority level for DMAC channel 39" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x10 24.--27. " SPRR38 ,SHwy bus access priority level for DMAC channel 38" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x10 20.--23. " SPRR37 ,SHwy bus access priority level for DMAC channel 37" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x10 16.--19. " SPRR36 ,SHwy bus access priority level for DMAC channel 36" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x10 12.--15. " SPRR35 ,SHwy bus access priority level for DMAC channel 35" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x10 8.--11. " SPRR34 ,SHwy bus access priority level for DMAC channel 34" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x10 4.--7. " SPRR33 ,SHwy bus access priority level for DMAC channel 33" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x10 0.--3. " SPRR32 ,SHwy bus access priority level for DMAC channel 32" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
line.long 0x14 "LBSC-DMASPR5,LBSC-DMA SHwy Priority Control Register"
|
|
bitfld.long 0x14 12.--15. " SPRR43 ,SHwy bus access priority level for DMAC channel 43" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x14 8.--11. " SPRR42 ,SHwy bus access priority level for DMAC channel 42" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
bitfld.long 0x14 4.--7. " SPRR41 ,SHwy bus access priority level for DMAC channel 41" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
textline " "
|
|
bitfld.long 0x14 0.--3. " SPRR40 ,SHwy bus access priority level for DMAC channel 40" "0(Lowest),1,2,3,4,5,6,7,8,9,10,11,12,13,14,15(Highest)"
|
|
group.long 0x160++0x07
|
|
line.long 0x00 "HPB-DMLVLR0[31:0],HPB-DMA Access Priority Level Control Register 0"
|
|
bitfld.long 0x00 31. " DMLV31 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 30. " DMLV30 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 29. " DMLV29 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " DMLV28 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 27. " DMLV27 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 26. " DMLV26 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DMLV25 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 24. " DMLV24 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 23. " DMLV23 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DMLV22 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 21. " DMLV21 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 20. " DMLV20 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DMLV19 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 18. " DMLV18 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 17. " DMLV17 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DMLV16 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 15. " DMLV15 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 14. " DMLV14 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMLV13 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 12. " DMLV12 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 11. " DMLV11 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DMLV10 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 9. " DMLV9 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 8. " DMLV8 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMLV7 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 6. " DMLV6 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 5. " DMLV5 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMLV4 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 3. " DMLV3 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 2. " DMLV2 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DMLV1 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x00 0. " DMLV0 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
line.long 0x04 "HPB-DMLVLR1[42:32],HPB-DMA Access Priority Level Control Register 1"
|
|
bitfld.long 0x04 11. " DMLV43 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 10. " DMLV42 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 9. " DMLV41 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x04 8. " DMLV40 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 7. " DMLV39 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 6. " DMLV38 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " DMLV37 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 4. " DMLV36 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 3. " DMLV35 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " DMLV34 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 1. " DMLV33 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
bitfld.long 0x04 0. " DMLV32 ,SuperHyway bus and HPB access arbitration priority" "Level 2,Level 1"
|
|
group.long 0x168++0x07
|
|
line.long 0x00 "HPB-DMSHPT0[31:0],HPB-DMA SuperHyway Port Select Register 0"
|
|
bitfld.long 0x00 31. " SHPT31 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 30. " SHPT30 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 29. " SHPT29 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SHPT28 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 27. " SHPT27 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 26. " SHPT26 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SHPT25 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 24. " SHPT24 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 23. " SHPT23 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SHPT22 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 21. " SHPT21 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 20. " SHPT20 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SHPT19 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 18. " SHPT18 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 17. " SHPT17 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SHPT16 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 15. " SHPT15 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 14. " SHPT14 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SHPT13 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 12. " SHPT12 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 11. " SHPT11 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SHPT10 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 9. " SHPT9 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 8. " SHPT8 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SHPT7 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 6. " SHPT6 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 5. " SHPT5 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SHPT4 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 3. " SHPT3 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 2. " SHPT2 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SHPT1 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x00 0. " SHPT0 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
line.long 0x04 "HPB-DMSHPT1[43:32],HPB-DMA SuperHyway Port Select Register 1"
|
|
bitfld.long 0x04 11. " SHPT43 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 10. " SHPT42 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 9. " SHPT41 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SHPT40 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 7. " SHPT39 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 6. " SHPT38 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SHPT37 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 4. " SHPT36 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 3. " SHPT35 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " SHPT34 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 1. " SHPT33 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
bitfld.long 0x04 0. " SHPT32 ,Selects the SuperHyway bus access port" "Port 0,Port 1"
|
|
base ad:0xFFC00300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ASYNCRSTR,Asynchronous Reset Register"
|
|
bitfld.long 0x00 11. " ASRST43 ,Resets the channel 43 (MMC1) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 10. " ASRST41 ,Resets the channel 41 (SDHI3) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 9. " ASRST40 ,Resets the channel 40 (SDHI3) interface block" "Normal operation,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ASRST39 ,Resets the channel 39 (SDHI3) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 7. " ASRST27 ,Resets the channel 27 (SDHI2) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 6. " ASRST26 ,Resets the channel 26 (SDHI2) interface block" "Normal operation,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASRST25 ,Resets the channel 25 (SDHI2) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 4. " ASRST24 ,Resets the channel 24 (MMC0) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 3. " ASRST23 ,Resets the channel 23 (SDHI0) interface block" "Normal operation,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASRST22 ,Resets the channel 22 (SDHI0) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 1. " ASRST21 ,Resets the channel 21 (SDHI0) interface block" "Normal operation,Reset"
|
|
bitfld.long 0x00 0. " ASRST20 ,Resets the channel 20 (SDHI1) interface block" "Normal operation,Reset"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ASYNCMDR,Asynchronous Mode Register"
|
|
bitfld.long 0x00 23. " ASMD43 ,HPB-DMAC channel 43 (MMC1) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 22. " ASBTMD43 ,HPB-DMAC channel 43 (MMC1) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 21. " ASMD24 ,HPB-DMAC channel 24 (MMC0) data transfer mode" "Multiblock,Single block"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ASBTMD24 ,HPB-DMAC channel 24 (MMC0) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 19. " ASMD41 ,HPB-DMAC channel 41 (SDHI3) data transfer mode setting" "Multiblock,Single block"
|
|
bitfld.long 0x00 18. " ASBTMD41 ,HPB-DMAC channel 41 (SDHI3) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ASMD40 ,HPB-DMAC channel 40 (SDHI3) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 16. " ASBTMD40 ,HPB-DMAC channel 40 (SDHI3) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 15. " ASMD39 ,HPB-DMAC channel 39 (SDHI3) data transfer mode" "Multiblock,Single block"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ASBTMD39 ,HPB-DMAC channel 39 (SDHI3) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 13. " ASMD27 ,HPB-DMAC channel 27 (SDHI2) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 12. " ASBTMD27 ,HPB-DMAC channel 27 (SDHI2) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASMD26 ,HPB-DMAC channel 26 (SDHI2) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 10. " ASBTMD26 ,HPB-DMAC channel 26 (SDHI2) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 9. " ASMD25 ,HPB-DMAC channel 25 (SDHI2) data transfer mode" "Multiblock,Single block"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ASBTMD25 ,HPB-DMAC channel 25 (SDHI2) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 7. " ASMD23 ,HPB-DMAC channel 23 (SDHI0) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 6. " ASBTMD23 ,HPB-DMAC channel 23 (SDHI0) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ASMD22 ,HPB-DMAC channel 22 (SDHI0) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 4. " ASBTMD22 ,HPB-DMAC channel 22 (SDHI0) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 3. " ASMD21 ,HPB-DMAC channel 21 (SDHI0) data transfer mode" "Multiblock,Single block"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ASBTMD21 ,HPB-DMAC channel 21 (SDHI0) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
bitfld.long 0x00 1. " ASMD20 ,HPB-DMAC channel 20 (SDHI1) data transfer mode" "Multiblock,Single block"
|
|
bitfld.long 0x00 0. " ASBTMD20 ,HPB-DMAC channel 20 (SDHI1) burst transfer mode" "Non-burst transfer,Burst transfer"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 0"
|
|
base ad:0xFFC08000
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long 0x08 0.--25. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFC08040
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFC08080
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFC080C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,TSIF0,TSIF1,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xFFC08100
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xFFC08140
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0xFFC08180
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0xFFC081C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 8"
|
|
base ad:0xFFC08200
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 9"
|
|
base ad:0xFFC08240
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 10"
|
|
base ad:0xFFC08280
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SCIF0,SCIF1,SCIF2,SCIF3,SCIF4,SCIF5,,,,,HSPI0,HSPI1,,,,,,,,HSPI2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 11"
|
|
base ad:0xFFC082C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP1 Packet reception,MIMLCP2 CPU4 reception,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP0 Packet transmission,,MIMLCP 2 CPU4 transmission,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 12"
|
|
base ad:0xFFC08300
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP1 Packet reception,MIMLCP2 CPU4 reception,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP0 Packet transmission,,MIMLCP 2 CPU4 transmission,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 13"
|
|
base ad:0xFFC08340
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP1 Packet reception,MIMLCP2 CPU4 reception,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,MIMLCP0 Packet transmission,,MIMLCP 2 CPU4 transmission,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 14"
|
|
base ad:0xFFC08380
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "USBF0,USBF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "USBF0,USBF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 15"
|
|
base ad:0xFFC083C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "USBF0,USBF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "USBF0,USBF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 16"
|
|
base ad:0xFFC08400
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 17"
|
|
base ad:0xFFC08440
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 18"
|
|
base ad:0xFFC08480
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 19"
|
|
base ad:0xFFC084C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "HSCIF0,HSCIF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 20"
|
|
base ad:0xFFC08500
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,,,,,,,SDHI1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,,,,,,SDHI1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 21"
|
|
base ad:0xFFC08540
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 22"
|
|
base ad:0xFFC08580
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 23"
|
|
base ad:0xFFC085C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,,,,,SDHI0,,SDHI0 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 24"
|
|
base ad:0xFFC08600
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",MMC0,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "MMC0,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 25"
|
|
base ad:0xFFC08640
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 26"
|
|
base ad:0xFFC08680
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 27"
|
|
base ad:0xFFC086C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,,,,,SDHI2,,SDHI2 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 28"
|
|
base ad:0xFFC08700
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF0,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF0,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 29"
|
|
base ad:0xFFC08740
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 30"
|
|
base ad:0xFFC08780
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF2,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF2,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 31"
|
|
base ad:0xFFC087C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF3,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF3,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 32"
|
|
base ad:0xFFC08800
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF4,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF4,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 33"
|
|
base ad:0xFFC08840
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF5,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF5,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 34"
|
|
base ad:0xFFC08880
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF6,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF6,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 35"
|
|
base ad:0xFFC088C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF7,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF7,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 36"
|
|
base ad:0xFFC08900
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF8,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF8,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 37"
|
|
base ad:0xFFC08940
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 38"
|
|
base ad:0xFFC08980
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 39"
|
|
base ad:0xFFC089C0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,SDHI3,,SDHI3 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,SDHI3,,SDHI3 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 40"
|
|
base ad:0xFFC08A00
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,SDHI3,,SDHI3 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,SDHI3,,SDHI3 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 41"
|
|
base ad:0xFFC08A40
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",,,,,SDHI3,,SDHI3 CPRM,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" ",,,,SDHI3,,SDHI3 CPRM,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 42"
|
|
base ad:0xFFC08A80
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF14,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,SSI8,SSI9,,,,,,,,HPBIF14,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree "Channel 43"
|
|
base ad:0xFFC08AC0
|
|
width 11.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "DSAR0,DMA Source Address Registers 0"
|
|
line.long 0x04 "DDAR0,DMA Destination Address Registers 0"
|
|
line.long 0x08 "DTCR0,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x08 0.--25. 1. " DTC ,DMA transfer count"
|
|
line.long 0x0c "DSAR1,DMA Source Address Registers 1"
|
|
line.long 0x10 "DDAR1,DMA Destination Address Registers 0"
|
|
line.long 0x14 "DTCR1,DMA Transfer Count Registers 0"
|
|
hexmask.long 0x14 0.--25. 1. " DTC ,DMA transfer count"
|
|
rgroup.long 0x18++0x0b
|
|
line.long 0x00 "DSASR,DMA Source Address Status Register"
|
|
line.long 0x04 "DDASR,DMA Destination Address Status Register"
|
|
line.long 0x08 "DTCSR,DMA Transfer Count Status Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " DTCS ,Remaining DMA Transfer Count"
|
|
sif (cpu()!="R8A7790X")&&(cpu()!="R8A7792X")&&(cpu()!="RCARE2")&&(!cpuis("RCARM2*"))
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DPTR,DMA Port Select Register"
|
|
bitfld.long 0x00 8.--12. " SDPT ,Transfer Source Peripheral Access Port Select" ",MMC1,?..."
|
|
bitfld.long 0x00 0.--4. " DDPT ,Transfer Destination Peripheral Access Port Select" "MMC1,?..."
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCR,DMA Control Register"
|
|
bitfld.long 0x00 26. " DTAMD ,Data alignment conversion mode" "Input pin/peripheral bus width,DTAC/DTAU/DTAU1"
|
|
bitfld.long 0x00 25. " DTAC ,Data alignment conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTAU ,Unit for data alignment conversion" "Byte,Word"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DTAU1 ,8-byte data alignment in 4-byte units performed" "Not performed,Performed"
|
|
sif cpu()=="RCARM2"||cpu()=="R8A7792X"
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (AXI bus) access size" "1 byte,4 bytes"
|
|
else
|
|
bitfld.long 0x00 22. " SWMD ,Specifies memory (SuperHyway bus) access size" "1 byte,4 bytes"
|
|
endif
|
|
bitfld.long 0x00 21. " BTMD ,Specifies the burst DMA transfer" "Normal,Burst"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PKMD ,Data packing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CT ,Specifies continuous DMA transfer" "Not continuous,Continuous"
|
|
bitfld.long 0x00 17. " ACMD ,Automatic continuous DMA transfer" "Not transferred,Transferred"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DIP ,Specifies the valid DMA information set(s)" "Repeatedly,Alternately"
|
|
bitfld.long 0x00 13. " SMDL ,Transfer source module" "Memory,Peripheral"
|
|
bitfld.long 0x00 12. " SPDAM ,Fix or increment the transfer source peripheral address" "Fixed,Incremented"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " SDRMD ,DMA request mode for the transfer source" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 8.--9. " SPDS ,Data bus width for the transfer source peripheral" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 5. " DMDL ,Transfer destination module" "Memory,Peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DPDAM ,Fix or increment the transfer destination peripheral address" "Fixed,Incremented"
|
|
bitfld.long 0x00 2.--3. " DDRMD ,DMA request mode for the transfer destination" "Module request,Auto-request,Timer request,?..."
|
|
bitfld.long 0x00 0.--1. " DPDS ,Data bus width for the transfer destination peripheral" "8 bits,16 bits,32 bits,?..."
|
|
wgroup.long 0x2c++0x07
|
|
line.long 0x00 "DCMDR,DMA Command Register"
|
|
bitfld.long 0x00 7. " BDOUT ,Forcibly writes the data read from a peripheral to the SuperHyway bus side" "No effect,Write"
|
|
bitfld.long 0x00 6. " DQSPD ,Temporarily stops transfer in DMA information units" "No effect,Stop"
|
|
bitfld.long 0x00 5. " DQSPC ,Cancels temporary transfer stop in DMA information units" "No effect,Cancel"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMSPD ,Temporarily stops transfer in bus cycle units" "No effect,Stop"
|
|
bitfld.long 0x00 3. " DMSPC ,Cancels temporary transfer stop in bus cycle units" "No effect,Cancel"
|
|
bitfld.long 0x00 2. " DQEND ,Terminates continuous DMA transfer mode" "No effect,Terminate"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DNXT ,Requests the next DMA transfer" "No effect,Request"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA transfer" "No effect,Activate"
|
|
line.long 0x04 "DSTPR,DMA Forced Stop Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Forcibly terminates DMA transfer" "No effect,Terminate"
|
|
textline ""
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "DSTSR,DMA Status Register"
|
|
bitfld.long 0x00 6. " NDP1 ,Next DMA Transfer Information Register Status 1" "Not transferred,Transferred"
|
|
bitfld.long 0x00 5. " NDP0 ,Next DMA Transfer Information Register Status 0" "Not transferred,Transferred"
|
|
bitfld.long 0x00 4. " DQSPS ,Temporary Stop Status of DMA Information Updating" "Normal operation,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DMSPS ,Temporary Stop Status of DMA Transfer" "Normal operation,Stopped"
|
|
bitfld.long 0x00 2. " DQSTS ,DMA Acceptance End Status" "Accepted,Stopped"
|
|
bitfld.long 0x00 1. " DRSTS ,DMA Transfer Request Status" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMSTS ,DMA Status" "Completed,Active"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DDBGR,DMA Channel Debug Register"
|
|
bitfld.long 0x00 31. " DBG02 ,Test bit" "0,1"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2"||cpu()=="R8A7792X")
|
|
rbitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
else
|
|
bitfld.long 0x00 4.--6. " DBG01 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DBG00 ,Test bit" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x04 "DDBGR2,DMA Channel Debug Register 2"
|
|
bitfld.long 0x04 30. " DBG12 ,Test bit" "0,1"
|
|
bitfld.long 0x04 28.--29. " DBG11 ,Test bit" "0,1,2,3"
|
|
hexmask.long 0x04 0.--25. 1. " DBG10 ,Test bit"
|
|
width 0x0b
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "R-GP2D (2D graphics rendering module)"
|
|
base ad:0xFFE80000
|
|
width 11.
|
|
tree "System Control Register"
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "SCLR,System Control Register"
|
|
bitfld.long 0x00 31. " SRES ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RBRK ,Rendering Break" "Not broke,Broke"
|
|
bitfld.long 0x00 0. " RS ,Rendering Start" "Not started,Started"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 28.--31. " VER ,Version Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " BRK ,Rendering Break Flag" "Not broke,Broke"
|
|
bitfld.long 0x00 2. " CER ,Command Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INT ,Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " TRA ,Trap Flag - end of command execution" "Not ended,Ended"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "SRCR,Status Register Clear Register"
|
|
bitfld.long 0x00 3. " BRCL ,Rendering Break Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CECL ,Command Error Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " INCL ,Interrupt Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRCL ,Trap Flag Clear" "No effect,Clear"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " BRE ,Rendering Break Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CEE ,Command Error Flag Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " INE ,Interrupt Flag Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRE ,Trap Flag Enable" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "ICIDR,Interrupt Command ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ICID ,Interrupt Command ID"
|
|
tree.end
|
|
tree "Memory Control Register"
|
|
group.long 0x40++0x2F
|
|
line.long 0x00 "RTN0R,Return Address Register 0"
|
|
hexmask.long 0x00 2.--28. 0x4 " RTN0 ,Return Address 0"
|
|
line.long 0x04 "RTN1R,Return Address Register 1"
|
|
hexmask.long 0x04 2.--28. 0x4 " RTN1 ,Return Address 1"
|
|
line.long 0x08 "DLSAR,Display List Start Address Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " DLSA ,Display List Start Address"
|
|
line.long 0x0c "SSAR,2-Dimensional Source Area Start Address Register"
|
|
hexmask.long 0x0c 4.--28. 0x10 " SSA ,2-Dimensional Source Area Start Address"
|
|
line.long 0x10 "RSAR,Rendering Start Address Register"
|
|
hexmask.long 0x10 4.--28. 0x10 " RSA ,Rendering Start Address"
|
|
line.long 0x14 "WSAR,Work Area Start Address Register"
|
|
hexmask.long 0x14 4.--28. 0x10 " WSA ,Work Area Start Address"
|
|
line.long 0x18 "SSTRR,Source Stride Register"
|
|
hexmask.long.word 0x18 3.--12. 1. " SSTR ,Source Stride"
|
|
line.long 0x1c "DSTRR,Destination Stride Register"
|
|
hexmask.long.word 0x1c 4.--12. 1. " DSTR ,Destination Stride"
|
|
line.long 0x20 "ENDCVR,Endian Conversion Control Register"
|
|
bitfld.long 0x20 3. " LWSWAP ,Longword Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x20 2. " WSWAP ,Word Swap" "Not swapped,Swapped"
|
|
bitfld.long 0x20 1. " BYTESWAP ,Byte Swap" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x20 0. " BITSWAP ,Bit Swap" "Not swapped,Swapped"
|
|
line.long 0x24 "ASAR,Alfa-Map Area Start Address Register"
|
|
hexmask.long 0x24 4.--28. 0x10 " ASA ,Alfa-Map Area Start Address"
|
|
line.long 0x28 "ASTRR,Alfa-Map Stride Register"
|
|
hexmask.long.word 0x28 3.--12. 1. " ASTR ,Alfa-Map Stride"
|
|
line.long 0x2c "ADREXTR,Address Extension Register"
|
|
bitfld.long 0x2c 29.--31. " ADREXT ,Address Extension" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RTNSTKR,Return Address STK Register"
|
|
hexmask.long 0x00 2.--28. 0x4 " RTNSTK ,Return Address STK"
|
|
tree.end
|
|
tree "Color Control Register"
|
|
group.long 0x80++0xF
|
|
line.long 0x00 "STCR,Source Transparent Color Register"
|
|
bitfld.long 0x00 24. " STC1 ,[1-bit/pixel] Source Transparent Color" "Low,High"
|
|
hexmask.long.byte 0x00 16.--23. 1. " [STC8/STC32] ,[8-bit/pixel]|[32-bit/pixel R] Source Transparent Color"
|
|
hexmask.long.word 0x00 0.--15. 1. " [STC16/STC32] ,[16-bit/pixel]|[32-bit/pixel G and B] Source Transparent Color"
|
|
line.long 0x04 "DTCR,Destination Transparent Color Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [DTC8/DTC32] ,[8-bit/pixel]|[32-bit/pixel] R Destination Transparent Color"
|
|
hexmask.long.word 0x04 0.--15. 1. " [DTC16/DTC32] ,[16-bit/pixel]|[32-bit/pixel G and B] Destination Transparent Color 16"
|
|
line.long 0x08 "ALPHR,Alpha Value Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " ALPH ,Alpha Value"
|
|
line.long 0x0C "COFSR,Color Offset Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " COR ,Color Offset R"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " COG ,Color Offset G"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " COB ,Color Offset B"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "AVALUE8R,A Value 8 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AVALUE8 ,A Value 8"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "ATCLR,Alpha Test Control Register"
|
|
bitfld.long 0x00 28.--30. " SATSEL ,Source Alpha Test Mode Select" "ALWAYS,NEVER,LESS,LEQUAL,EQUAL,GEQUAL,GREATER,NEQUAL"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SATRV ,Source Alpha Test Reference Value "
|
|
bitfld.long 0x00 12.--14. " DATSEL ,Destination Alpha Test Mode Select" "ALWAYS,NEVER,LESS,LEQUAL,EQUAL,GEQUAL,GREATER,NEQUAL"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATRV ,Destination Alpha Test Reference Value"
|
|
tree.end
|
|
tree "Rendering Control Register"
|
|
if (((per.l(ad:0xFFE80000+0xC0))&0x40000)==0x00000)
|
|
if (((per.l(ad:0xFFE80000+0x1FC))&0x1000000)==0x0000000)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RCLR,Rendering Control Register"
|
|
bitfld.long 0x00 27. " SAEP ,Source Alpha Enable Polarity [A value for blending/drawing back]" "1/0,0/1"
|
|
bitfld.long 0x00 25. " STP ,Source Transparent Color Polarity" "Match,Unmatch"
|
|
bitfld.long 0x00 24. " DTP ,Destination Transparent Color Polarity" "Match,Unmatch"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPF ,Source Pixel Format" "RGB,"
|
|
bitfld.long 0x00 20. " DPF ,Destination Pixel Format" "RGB,"
|
|
bitfld.long 0x00 18. " GBM ,Graphics Bit Mode" "8-bit/pixel,16-bit/pixel"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SAU ,Source Value A Use" "AVALUE,Value A"
|
|
bitfld.long 0x00 16. " AVALUE ,Value A" "0,1"
|
|
bitfld.long 0x00 12.--13. " BDS ,Thickness Direction Boundary Select" "Boundary A,Boundary B,Boundary C,Boundary D"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LALPHAE ,Line Alpha Enable" "Not performed,,Performed,ARGB=1555 rewritten"
|
|
bitfld.long 0x00 7. " 2DVCLPE ,2-Dimensional Vertex Clipping Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NAA ,New Antialias Mode" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WLM ,Bold Line Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPCE ,Line Pre-Clipping Enable" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " COM ,Connection Drawing Mask" "Drawn,Not drawn"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RCLR,Rendering Control Register"
|
|
bitfld.long 0x00 27. " SAEP ,Source Alpha Enable Polarity [A value for blending/drawing back]" "1/0,0/1"
|
|
bitfld.long 0x00 25. " STP ,Source Transparent Color Polarity" "Match,Unmatch"
|
|
bitfld.long 0x00 24. " DTP ,Destination Transparent Color Polarity" "Match,Unmatch"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPF ,Source Pixel Format" "RGB,"
|
|
bitfld.long 0x00 20. " DPF ,Destination Pixel Format" "RGB,"
|
|
bitfld.long 0x00 18. " GBM ,Graphics Bit Mode" "8-bit/pixel,16-bit/pixel"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SAU ,Source Value A Use" "AVALUE8R,Cmd parameters"
|
|
bitfld.long 0x00 16. " AVALUE ,Value A" "0,1"
|
|
bitfld.long 0x00 12.--13. " BDS ,Thickness Direction Boundary Select" "Boundary A,Boundary B,Boundary C,Boundary D"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LALPHAE ,Line Alpha Enable" "Not performed,,Performed,ARGB=1555 rewritten"
|
|
bitfld.long 0x00 7. " 2DVCLPE ,2-Dimensional Vertex Clipping Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NAA ,New Antialias Mode" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WLM ,Bold Line Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPCE ,Line Pre-Clipping Enable" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " COM ,Connection Drawing Mask" "Drawn,Not drawn"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFE80000+0x1FC))&0x1000000)==0x0000000)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RCLR,Rendering Control Register"
|
|
bitfld.long 0x00 27. " SAEP ,Source Alpha Enable Polarity [A value for blending/drawing back]" "1/0,0/1"
|
|
bitfld.long 0x00 25. " STP ,Source Transparent Color Polarity" "Match,Unmatch"
|
|
bitfld.long 0x00 24. " DTP ,Destination Transparent Color Polarity" "Match,Unmatch"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPF ,Source Pixel Format" "RGB,ARGB"
|
|
bitfld.long 0x00 20. " DPF ,Destination Pixel Format" "RGB,ARGB"
|
|
bitfld.long 0x00 18. " GBM ,Graphics Bit Mode" "8-bit/pixel,16-bit/pixel"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SAU ,Source Value A Use" "AVALUE,Value A"
|
|
bitfld.long 0x00 16. " AVALUE ,Value A" "0,1"
|
|
bitfld.long 0x00 12.--13. " BDS ,Thickness Direction Boundary Select" "Boundary A,Boundary B,Boundary C,Boundary D"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LALPHAE ,Line Alpha Enable" "Not performed,,Performed,ARGB=1555 rewritten"
|
|
bitfld.long 0x00 7. " 2DVCLPE ,2-Dimensional Vertex Clipping Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NAA ,New Antialias Mode" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WLM ,Bold Line Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPCE ,Line Pre-Clipping Enable" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " COM ,Connection Drawing Mask" "Drawn,Not drawn"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RCLR,Rendering Control Register"
|
|
bitfld.long 0x00 27. " SAEP ,Source Alpha Enable Polarity [A value for blending/drawing back]" "1/0,0/1"
|
|
bitfld.long 0x00 25. " STP ,Source Transparent Color Polarity" "Match,Unmatch"
|
|
bitfld.long 0x00 24. " DTP ,Destination Transparent Color Polarity" "Match,Unmatch"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SPF ,Source Pixel Format" "RGB,ARGB"
|
|
bitfld.long 0x00 20. " DPF ,Destination Pixel Format" "RGB,ARGB"
|
|
bitfld.long 0x00 18. " GBM ,Graphics Bit Mode" "8-bit/pixel,16-bit/pixel"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SAU ,Source Value A Use" "AVALUE8R,Cmd parameters"
|
|
bitfld.long 0x00 16. " AVALUE ,Value A" "0,1"
|
|
bitfld.long 0x00 12.--13. " BDS ,Thickness Direction Boundary Select" "Boundary A,Boundary B,Boundary C,Boundary D"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LALPHAE ,Line Alpha Enable" "Not performed,,Performed,ARGB=1555 rewritten"
|
|
bitfld.long 0x00 7. " 2DVCLPE ,2-Dimensional Vertex Clipping Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NAA ,New Antialias Mode" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " WLM ,Bold Line Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPCE ,Line Pre-Clipping Enable" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " COM ,Connection Drawing Mask" "Drawn,Not drawn"
|
|
endif
|
|
endif
|
|
rgroup.long 0xC4++0x1F
|
|
line.long 0x00 "CSTR,Command Status Register"
|
|
hexmask.long 0x00 2.--28. 0x4 " CST ,Command Status"
|
|
line.long 0x04 "CURR,Current Pointer Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " XC ,Current Pointer X"
|
|
hexmask.long.word 0x04 0.--15. 1. " YC ,Current Pointer Y"
|
|
line.long 0x08 "LCOR,Local Offset Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " XO ,Local Offset X"
|
|
hexmask.long.word 0x08 0.--15. 1. " YO ,Local Offset Y"
|
|
line.long 0x0c "SCLMAR,System Clipping Area MAX Register"
|
|
hexmask.long.word 0x0C 16.--27. 1. " SXMAX ,System Clipping XMAX"
|
|
hexmask.long.word 0x0C 0.--11. 1. " SYMAX ,System Clipping YMAX"
|
|
line.long 0x10 "UCLMIR,User Clipping Area MIN Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " UXMIN ,User Clipping XMIN"
|
|
hexmask.long.word 0x10 0.--11. 1. " UYMIN ,User Clipping YMIN"
|
|
line.long 0x14 "UCLMAR,User Clipping Area MAX Register"
|
|
hexmask.long.word 0x14 16.--27. 1. " UXMAX ,User Clipping XMAX"
|
|
hexmask.long.word 0x14 0.--11. 1. " UYMAX ,User Clipping YMAX"
|
|
line.long 0x18 "RUCLMIR,Relative User Clipping Area MIN Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " RUXMIN ,Relative User Clipping XMIN"
|
|
hexmask.long.word 0x18 0.--11. 1. " RUYMIN ,Relative User Clipping YMIN"
|
|
line.long 0x1C "RUCLMAR,Relative User Clipping Area MAX Register"
|
|
hexmask.long.word 0x1C 16.--27. 1. " RUXMAX ,Relative User Clipping XMAX"
|
|
hexmask.long.word 0x1C 0.--11. 1. " RUYMAX ,Relative User Clipping YMAX"
|
|
if (((per.l(ad:0xFFE80000+0x1FC))&0x1000000)==0x0000000)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCL2R,Rendering Control 2 Register"
|
|
bitfld.long 0x00 21. " DAE ,Destination Alpha Enable" "Regardless of value A,Value A"
|
|
bitfld.long 0x00 20. " PSTYLE ,Pattern Style Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " PXSIZE ,Pattern X Size" "8 pixels,16 pixels,32 pixels,64 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PYSIZE ,Pattern Y Size" "8 pixels,16 pixels,32 pixels,64 pixels"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RCL2R,Rendering Control 2 Register"
|
|
bitfld.long 0x00 21. " DAE ,Destination Alpha Enable" "Regardless of value A,Test passed"
|
|
bitfld.long 0x00 20. " PSTYLE ,Pattern Style Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18.--19. " PXSIZE ,Pattern X Size" "8 pixels,16 pixels,32 pixels,64 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PYSIZE ,Pattern Y Size" "8 pixels,16 pixels,32 pixels,64 pixels"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "POFSR,Pattern Offset Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " POFSX ,Pattern Offset X"
|
|
hexmask.long.word 0x00 0.--11. 1. " POFSY ,Pattern Offset Y"
|
|
tree.end
|
|
tree "Coordinate Transformation Control Register"
|
|
group.long 0x100++0x3B
|
|
line.long 0x00 "GTRCR,Coordinate Transformation Control Register"
|
|
bitfld.long 0x00 31. " GTE ,Coordinate Transformation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AFE ,Affine Transformation Enable" "Disabled,Enabled"
|
|
line.long 0x04 "MTRAR,Matrix Parameter A Register"
|
|
line.long 0x08 "MTRBR,Matrix Parameter B Register"
|
|
line.long 0x0c "MTRCR,Matrix Parameter C Register"
|
|
line.long 0x10 "MTRDR,Matrix Parameter D Register"
|
|
line.long 0x14 "MTRER,Matrix Parameter E Register"
|
|
line.long 0x18 "MTRFR,Matrix Parameter F Register"
|
|
line.long 0x1c "MTRGR,Matrix Parameter G Register"
|
|
line.long 0x20 "MTRHR,Matrix Parameter H Register"
|
|
line.long 0x24 "MTRIR,Matrix Parameter I Register"
|
|
line.long 0x28 "GTROFSXR,Coordinate Transformation Offset X Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " GTROFSX ,Coordinate Transformation Offset X"
|
|
line.long 0x2c "GTROFSYR,Coordinate Transformation Offset Y Register"
|
|
hexmask.long.word 0x2C 0.--15. 1. " GTROFSY ,Coordinate Transformation Offset Y"
|
|
line.long 0x30 "ZCLPMINR,Z Clipping Area MIN Register"
|
|
line.long 0x34 "ZCLPMAXR,Z Clipping Area MAX Register"
|
|
line.long 0x38 "ZSATVMINR,Z Saturation Value MIN Register"
|
|
group.long 0x160++0x3
|
|
line.long 0x00 "2DVCEXTR,2-Dimensional Vertex Clip Extension Width Register"
|
|
bitfld.long 0x00 0.--5. " 2DVCEXT ,2-Dimensional Vertex Clip Extension Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
tree "Mode Control Register"
|
|
group.long 0x1FC++0x3
|
|
line.long 0x00 "MD0R,Mode 0 Register"
|
|
bitfld.long 0x00 24. " GBM2 ,Graphic Bit Mode" "In accord with GBM,ARGB8888 format"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ACDE ,Anti-aliasing Coverage Drawing Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DITHERENB ,Dither Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 11.
|
|
tree.end
|
|
tree "SGX (3D Graphics Engine)"
|
|
base ad:0xFFF12000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCR1,SGX Control Register 1"
|
|
bitfld.long 0x00 16. " SCR1_16 ,SGXCORE Frequency Change" "200 MHz,250 MHz"
|
|
width 11.
|
|
tree.end
|
|
tree "DU (Display Unit)"
|
|
base ad:0xFFF80000
|
|
width 8.
|
|
tree "Display Control Registers"
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DSYSR,Display Unit System Control Register"
|
|
bitfld.long 0x00 29. " ILTS ,Input Pad Latch Timing Select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DSEC ,Display Data Endian Change" "Not performed,Performed"
|
|
bitfld.long 0x00 16. " IUPD ,Internal Updating Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DRES/DEN ,Display Reset/Display Enable" "Started (display DOOR),Started (display memory),Stopped,?..."
|
|
bitfld.long 0x00 6.--7. " TVM ,TV Synchronization Mode" "Master mode,Synchronization method switching mode,TV synchronization mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SCM ,Scan Mode" "Non-interlaced mode,,Interlaced sync mode,Interlaced sync & video mode"
|
|
else
|
|
group.long 0x00++0x03 "Display Control Registers"
|
|
line.long 0x00 "DSYSR,Display Unit System Control Register"
|
|
bitfld.long 0x00 20. " DSEC ,Display Data Endian Change" "Not performed,Performed"
|
|
bitfld.long 0x00 16. " IUPD ,Internal Updating Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DRES/DEN ,Display Reset/Display Enable" "Started (display DOOR),Started (display memory),Stopped,?..."
|
|
bitfld.long 0x00 6.--7. " TVM ,TV Synchronization Mode" "Master mode,Synchronization method switching mode,TV synchronization mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SCM ,Scan Mode" "Non-interlaced mode,,Interlaced sync mode,Interlaced sync & video mode"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DSMR,Display Mode Register"
|
|
bitfld.long 0x00 28. " VSPM ,VSYNC Pin Mode" "VSYNC signal,CSYNC signal"
|
|
bitfld.long 0x00 27. " ODPM ,ODDF Pin Mode" "ODDF signal,CLAMP signal"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DIPM ,DISP Pin Mode" "DISP signal,CSYNC signal,,DE signal"
|
|
bitfld.long 0x00 24. " CSPM ,CSYNC Pin Mode" "CSYNC signal,HSYNC signal"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIL ,DISP Polarity Selection" "High-active,Polarity inverted"
|
|
bitfld.long 0x00 18. " VSL ,VSYNC Polarity Selection" "Low-active,Polarity inverted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSL ,HSYNC Polarity Selection" "Low-active,Polarity inverted"
|
|
bitfld.long 0x00 16. " DDIS ,DISP Output Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CDEL ,CDE Polarity Selection" "High-active,Polarity inverted"
|
|
bitfld.long 0x00 13.--14. " CDEM ,CDE Output Mode" "Normal mode,Normal mode,Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CDED ,CDE Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " ODEV ,ODD Signal Polarity Selection" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CSY ,CSYNC Mode" "Mode 0,,Mode 2,Mode 3"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "DSSR,Display Status Register"
|
|
bitfld.long 0x00 30.--31. " VC0FB ,Video Capture Frame Buffer Flag" "PnDSA0R,PnDSA1R,PnDSA2R,Initial state"
|
|
bitfld.long 0x00 28.--29. " VC1FB ,Video Capture Frame Buffer Flag" "PnDSA0R,PnDSA1R,PnDSA2R,Initial state"
|
|
textline " "
|
|
bitfld.long 0x00 25. " DFB10 ,Display Frame Buffer 10 Flag" "AP2DSA0R,AP2DSA1R"
|
|
bitfld.long 0x00 24. " DFB9 ,Display Frame Buffer 9 Flag" "AP1DSA0R,AP1DSA1R"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DFB8 ,Display Frame Buffer 8 Flag" "P8DSA0R,P8DSA1R"
|
|
bitfld.long 0x00 22. " DFB7 ,Display Frame Buffer 7 Flag" "AP7DSA0R,AP7DSA1R"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DFB6 ,Display Frame Buffer 6 Flag" "AP6DSA0R,AP6DSA1R"
|
|
bitfld.long 0x00 22. " DFB5 ,Display Frame Buffer 5 Flag" "AP5DSA0R,AP5DSA1R"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DFB4 ,Display Frame Buffer 4 Flag" "P4DSA0R,P4DSA1R"
|
|
bitfld.long 0x00 18. " DFB3 ,Display Frame Buffer 3 Flag" "P3DSA0R,P3DSA1R"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DFB2 ,Display Frame Buffer 2 Flag" "P2DSA0R,P2DSA1R"
|
|
bitfld.long 0x00 16. " DFB1 ,Display Frame Buffer 1 Flag" "P1DSA0R,P1DSA1R"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TVR ,TV Synchronization Error Flag(EXVSYNC)" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FRM ,Frame Flag" "Low,High"
|
|
bitfld.long 0x00 11. " VBK ,Vertical Blanking Flag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RINT ,Raster Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HBK ,Horizontal Blanking Flag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADC8 ,Auto Rendering Display Change Flag 8" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " ADC7 ,Auto Rendering Display Change Flag 7" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADC6 ,Auto Rendering Display Change Flag 6" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " ADC5 ,Auto Rendering Display Change Flag 5" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADC4 ,Auto Rendering Display Change Flag 4" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " ADC3 ,Auto Rendering Display Change Flag 3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC2 ,Auto Rendering Display Change Flag 2" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " ADC1 ,Auto Rendering Display Change Flag 1" "Not switched,Switched"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "DSRCR,Display Status Register Clear Register"
|
|
bitfld.long 0x00 15. " TVCL ,TV Synchronization Signal Error Flag Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " FRCL ,Frame Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VBCL ,Vertical Blanking Flag Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " RICL ,Raster Interrupt Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HBCL ,Horizontal Blanking Flag Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 7. " ADCL8 ,Auto Rendering Display Change Flag Clear 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADCL7 ,Auto Rendering Display Change Flag Clear 7" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " ADCL6 ,Auto Rendering Display Change Flag Clear 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCL5 ,Auto Rendering Display Change Flag Clear 5" "No effect,Cleared"
|
|
bitfld.long 0x00 3. " ADCL4 ,Auto Rendering Display Change Flag Clear 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADCL3 ,Auto Rendering Display Change Flag Clear 3" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " ADCL2 ,Auto Rendering Display Change Flag Clear 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADCL1 ,Auto Rendering Display Change Flag Clear 1" "No effect,Cleared"
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "DIER,Display Unit Interrupt Enable Register"
|
|
bitfld.long 0x00 15. " TVE ,TV Synchronous Signal Error Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FRE ,Frame Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VBE ,Vertical Blanking Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIE ,Raster Interrupt Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HBE ,HBK Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ADCE8 ,Auto Rendering Display Change Flag 8 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADCE7 ,Auto Rendering Display Change Flag 7 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ADCE6 ,Auto Rendering Display Change Flag 6 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ADCE5 ,Auto Rendering Display Change Flag 5 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ADCE4 ,Auto Rendering Display Change Flag 4 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADCE3 ,Auto Rendering Display Change Flag 3 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ADCE2 ,Auto Rendering Display Change Flag 2 Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADCE1 ,Auto Rendering Display Change Flag 1 Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "CPCR,Color Palette Control Register"
|
|
bitfld.long 0x04 19. " CP4CE ,Color Palette 4 Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CP3CE ,Color Palette 3 Change Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " CP2CE ,Color Palette 2 Change Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CP1CE ,Color Palette 1 Change Enable" "Disabled,Enabled"
|
|
line.long 0x08 "DPPR,Display Plane Priority Register"
|
|
bitfld.long 0x08 31. " DPE8 ,Display Plane Priority 8 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " DPS8 ,Display Plane Priority 8 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 27. " DPE7 ,Display Plane Priority 7 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--26. " DPS7 ,Display Plane Priority 7 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 23. " DPE6 ,Display Plane Priority 6 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20.--22. " DPS6 ,Display Plane Priority 6 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DPE5 ,Display Plane Priority 5 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--18. " DPS5 ,Display Plane Priority 5 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DPE4 ,Display Plane Priority 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--14. " DPS4 ,Display Plane Priority 4 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DPE3 ,Display Plane Priority 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--10. " DPS3 ,Display Plane Priority 3 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DPE2 ,Display Plane Priority 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4.--6. " DPS2 ,Display Plane Priority 2 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DPE1 ,Display Plane Priority 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--2. " DPS1 ,Display Plane Priority 1 Select" "Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DEFR,Display Unit Extensional Function Enable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,DEFR Enabling Code [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EXSL ,External Sync Signal Select" "Post-divison clocks,Pre-divison clocks"
|
|
bitfld.long 0x00 11. " EXVL ,External Vsync Latch Select" "Every clock cycle,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EXUP ,External Updating Mode" "Internal,External"
|
|
bitfld.long 0x00 4. " VCUP ,Vertical Cycle Register Update Timing Select" "Falling VSYNC,Rising VSYNC"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DEFE ,Display Unit Extensional Function Enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "DAPCR,Display Alpha Ratio Plane Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code To make DAPCR accessible [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AP2E ,Alpha Ratio Plane 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AP1E ,Alpha Ratio Plane 1 Enable" "Disabled,Enabled"
|
|
if ((((per.l(ad:0xFFF80000+0x34))&0x1)==0x1)&&(((per.l(ad:0xFFF80000+0x38))&0x1)==0x1))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCPCR,Display Capture Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CA2B ,Display Capture A Bit 2 Function Select" "0,1"
|
|
bitfld.long 0x00 12. " CD2F ,Display Capture Data 2 Format" "RGB565,ARGB1555"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DC2E ,Display Capture 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAB ,Display Capture A Bit Function Select" "0,1"
|
|
bitfld.long 0x00 4. " CDF ,Display Capture Data Format" "RGB565,ARGB1555"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DCE ,Display Capture Enable" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xFFF80000+0x34))&0x1)==0x1))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCPCR,Display Capture Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CAB ,Display Capture A Bit Function Select" "0,1"
|
|
bitfld.long 0x00 4. " CDF ,Display Capture Data Format" "RGB565,ARGB1555"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DCE ,Display Capture Enable" "Disabled,Enabled"
|
|
elif ((((per.l(ad:0xFFF80000+0x38))&0x1)==0x1))
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCPCR,Display Capture Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CA2B ,Display Capture A Bit 2 Function Select" "0,1"
|
|
bitfld.long 0x00 12. " CD2F ,Display Capture Data 2 Format" "RGB565,ARGB1555"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DC2E ,Display Capture 2 Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DCE ,Display Capture Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DCPCR,Display Capture Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7773]"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DCE ,Display Capture Enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DEFR2,Display Unit Extensional Function Enable Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7775]"
|
|
bitfld.long 0x00 0. " DEFE2G ,Display Unit Extensional Function Enable SHNavi2G" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "DEFR3,Display Unit Extensional Function Enable Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7776]"
|
|
bitfld.long 0x00 0. " DEFE3 ,Display Unit Extensional Function Enable from SH-Navi3" "Disabled,Enabled"
|
|
group.long 0x3c++0x03
|
|
line.long 0x00 "DEFR4,Display Unit Extensional Function Enable Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7777]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " LRUO ,LRU Function Off" "No,yes"
|
|
bitfld.long 0x00 4. " SPCE ,SuperHyway Priority Change Enable" "Disabled,Enabled"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "DVCSR,Display Unit Video Capture Status Register"
|
|
bitfld.long 0x00 22.--23. " VC3FB2 ,Video Capture 3 Frame Buffer Flag 2" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
bitfld.long 0x00 20.--21. " VC2FB2 ,Video Capture 2 Frame Buffer Flag 2" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " VC1FB2 ,Video Capture 1 Frame Buffer Flag 2" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
bitfld.long 0x00 16.--17. " VC0FB2 ,Video Capture 0 Frame Buffer Flag 2" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " VC3FB ,Video Capture 3 Frame Buffer Flag" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
bitfld.long 0x00 4.--5. " VC2FB ,Video Capture 2 Frame Buffer Flag" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " VC1FB ,Video Capture 1 Frame Buffer Flag" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
bitfld.long 0x00 0.--1. " VC0FB ,Video Capture 0 Frame Buffer Flag" "PnDSA0R,PnDSA1O,PnDSA2R,Initial state"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DEFR5,Display Unit Extensional Function Enable Register 5"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,DEFR5 Enabling Code [0x66]"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " YCRGB2 ,YC-RGB Select 2" "No conversion,Levels 1/2,Levels 2/3,Levels 3/4"
|
|
bitfld.long 0x00 12.--13. " YCRGB1 ,YC-RGB Select 1" "No conversion,Levels 1/2,Levels 2/3,Levels 3/4"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DEFE5 ,Display Unit Extensional Function Enable 5" "Disabled,Enabled"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DDLTR,Display Data Latency Adjustment Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,DDLTR Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DLAR2 ,Display Data Latency Adjustment RGBYC2" "No delay,Delay"
|
|
bitfld.long 0x00 5. " DLAY2 ,Display Data Latency Adjustment YCRGB2" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DLAY1 ,Display Data Latency Adjustment YCRGB1" "No delay,Delay"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DEFR6,Display Unit Extensional Function Enable Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,DEFR6 Enabling Code [0x7778]"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " ODPM22 ,ODDF Pin Mode 22" "ODMP2,,DISP,CDE"
|
|
bitfld.long 0x00 8.--9. " ODPM12 ,ODDF Pin Mode 12" "ODMP2,,DISP,CDE"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MLOS1 ,DMultiple Output Select 1" "24-bit,12-bit"
|
|
tree.end
|
|
tree "Display Unit 2 Control Registers"
|
|
width 8.
|
|
if (((per.l(ad:0xFFF80000+0x30020))&0x01)==0x01)
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "D2SYSR,Display Unit System Control Register"
|
|
bitfld.long 0x00 29. " ILTS ,Input Pad Latch Timing Select" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DSEC ,Display Data Endian Change" "Not performed,Performed"
|
|
bitfld.long 0x00 6.--7. " TVM ,TV Synchronization Mode" "Master mode,Transitional mode,TV synchronized mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SCM ,Scan Mode" "Non-interlaced mode,,Interlaced sync mode,Interlaced sync & video mode"
|
|
else
|
|
group.long 0x30000++0x03
|
|
line.long 0x00 "D2SYSR,Display Unit System Control Register"
|
|
bitfld.long 0x00 20. " DSEC ,Display Data Endian Change" "Not performed,Performed"
|
|
bitfld.long 0x00 16. " IUPD ,Internal Updating Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " DRES/DEN ,Display Reset/Display Enable" "Started (display DOOR),Started (display memory),Stopped,?..."
|
|
bitfld.long 0x00 6.--7. " TVM ,TV Synchronization Mode" "Master mode,Synchronization method switching mode,TV synchronization mode,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SCM ,Scan Mode" "Non-interlaced mode,,Interlaced sync mode,Interlaced sync & video mode"
|
|
endif
|
|
group.long 0x30004++0x03
|
|
line.long 0x00 "D2SMR,Display Mode Register"
|
|
bitfld.long 0x00 28. " VSPM ,VSYNC Pin Mode" "VSYNC signal,CSYNC signal"
|
|
bitfld.long 0x00 27. " ODPM ,ODDF Pin Mode" "ODDF signal,CLAMP signal"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DIPM ,DISP Pin Mode" "DISP signal,CSYNC signal,,DE signal"
|
|
bitfld.long 0x00 24. " CSPM ,CSYNC Pin Mode" "CSYNC signal,HSYNC signal"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DIL ,DISP Polarity Selection" "High-active,Polarity inverted"
|
|
bitfld.long 0x00 18. " VSL ,VSYNC Polarity Selection" "Low-active,Polarity inverted"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSL ,HSYNC Polarity Selection" "Low-active,Polarity inverted"
|
|
bitfld.long 0x00 16. " DDIS ,DISP Output Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CDEL ,CDE Polarity Selection" "High-active,Polarity inverted"
|
|
bitfld.long 0x00 13.--14. " CDEM ,CDE Output Mode" "Normal mode,Normal mode,Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CDED ,CDE Disable" "No,Yes"
|
|
bitfld.long 0x00 8. " ODEV ,ODD Signal Polarity Selection" "Low level,High level"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CSY ,CSYNC Mode" "Mode 0,,Mode 2,Mode 3"
|
|
rgroup.long 0x30008++0x03
|
|
line.long 0x00 "D2SSR,Display Status Register"
|
|
bitfld.long 0x00 15. " TVR ,TV Synchronization Error Flag(EXVSYNC)" "Detected,Not detected"
|
|
textline " "
|
|
bitfld.long 0x00 14. " FRM ,Frame Flag" "Low,High"
|
|
bitfld.long 0x00 11. " VBK ,Vertical Blanking Flag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RINT ,Raster Interrupt Flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HBK ,Horizontal Blanking Flag" "Low,High"
|
|
wgroup.long 0x3000C++0x03
|
|
line.long 0x00 "D2SRCR,Display Status Register Clear Register"
|
|
bitfld.long 0x00 15. " TVCL ,TV Synchronization Signal Error Flag Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " FRCL ,Frame Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VBCL ,Vertical Blanking Flag Clear" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " RICL ,Raster Interrupt Flag Clear" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HBCL ,Horizontal Blanking Flag Clear" "No effect,Cleared"
|
|
group.long 0x30010++0x03
|
|
line.long 0x00 "D2IER,Display Unit Interrupt Enable Register"
|
|
bitfld.long 0x00 15. " TVE ,TV Synchronous Signal Error Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FRE ,Frame Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VBE ,Vertical Blanking Flag Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RIE ,Raster Interrupt Flag Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HBE ,HBK Flag Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x30020++0x03
|
|
line.long 0x00 "D2EFR,Display Unit Extensional Function Enable Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Register Available Code [0x7773]"
|
|
bitfld.long 0x00 12. " EXSL ,External Sync Signal Select" "Latched by frequency-divided,Acquired by pre-division & latched by frequency-divided"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EXVL ,External Vsync Latch Select" "Each edge,Rising edge"
|
|
tree.end
|
|
tree "Display Timing Generation Registers"
|
|
tree "Channel 1"
|
|
group.long 0x40++0x1f
|
|
line.long 0x00 "HDSR,Horizontal Display Start Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " HDS ,Horizontal Display Start"
|
|
line.long 0x04 "HDER,Horizontal Display End Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " HDE ,Horizontal Display End"
|
|
line.long 0x08 "VDSR,Vertical Display Start Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " VDS ,Vertical Display Start"
|
|
line.long 0x0c "VDER,Vertical Display End Register"
|
|
hexmask.long.word 0x0c 0.--10. 1. " VDE ,Vertical Display End"
|
|
line.long 0x10 "HCR,Horizontal Cycle Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " HC ,Horizontal Cycle"
|
|
line.long 0x14 "HSWR,Horizontal Sync Width Register"
|
|
hexmask.long.word 0x14 0.--8. 1. " HSW ,Horizontal Sync Width"
|
|
line.long 0x18 "VCR,Vertical Cycle Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " VC ,Vertical Cycle"
|
|
line.long 0x1c "VSPR,Vertical Sync Point Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " VSP ,Vertical Sync Point"
|
|
if (((per.l(ad:0xFFF80000+0x04))&0x80)==0x80)
|
|
group.long (0x40+0x20)++0x07
|
|
line.long 0x00 "EQWR,Equal Pulse Width Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EQW ,Equal Pulse Width"
|
|
line.long 0x04 "SPWR,Serration Width Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " SPW ,Serration Width"
|
|
else
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "EQWR,Equal Pulse Width Register"
|
|
hgroup.long (0x40+0x24)++0x03
|
|
hide.long 0x00 "SPWR,Separation Width Register"
|
|
endif
|
|
group.long (0x40+0x30)++0x0f
|
|
line.long 0x00 "CLAMPSR,CLAMP Signal Start Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CLAMPS ,CLAMP Signal Start"
|
|
line.long 0x04 "CLAMPWR,CLAMP Signal Width Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " CLAMPW ,CLAMP Signal Width"
|
|
line.long 0x08 "DESR,DE Signal Start Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " DES ,DE Signal Start"
|
|
line.long 0x0c "DEWR,DE Signal Width Register"
|
|
hexmask.long.word 0x0c 0.--11. 1. " DEW ,DE Signal Width"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x30040++0x1f
|
|
line.long 0x00 "HDSR,Horizontal Display Start Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " HDS ,Horizontal Display Start"
|
|
line.long 0x04 "HDER,Horizontal Display End Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " HDE ,Horizontal Display End"
|
|
line.long 0x08 "VDSR,Vertical Display Start Register"
|
|
hexmask.long.word 0x08 0.--8. 1. " VDS ,Vertical Display Start"
|
|
line.long 0x0c "VDER,Vertical Display End Register"
|
|
hexmask.long.word 0x0c 0.--10. 1. " VDE ,Vertical Display End"
|
|
line.long 0x10 "HCR,Horizontal Cycle Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " HC ,Horizontal Cycle"
|
|
line.long 0x14 "HSWR,Horizontal Sync Width Register"
|
|
hexmask.long.word 0x14 0.--8. 1. " HSW ,Horizontal Sync Width"
|
|
line.long 0x18 "VCR,Vertical Cycle Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " VC ,Vertical Cycle"
|
|
line.long 0x1c "VSPR,Vertical Sync Point Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " VSP ,Vertical Sync Point"
|
|
if (((per.l(ad:0xFFF80000+0x04))&0x80)==0x80)
|
|
group.long (0x30040+0x20)++0x07
|
|
line.long 0x00 "EQWR,Equal Pulse Width Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " EQW ,Equal Pulse Width"
|
|
line.long 0x04 "SPWR,Serration Width Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " SPW ,Serration Width"
|
|
else
|
|
hgroup.long (0x30040+0x20)++0x03
|
|
hide.long 0x00 "EQWR,Equal Pulse Width Register"
|
|
hgroup.long (0x30040+0x24)++0x03
|
|
hide.long 0x00 "SPWR,Separation Width Register"
|
|
endif
|
|
group.long (0x30040+0x30)++0x0f
|
|
line.long 0x00 "CLAMPSR,CLAMP Signal Start Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " CLAMPS ,CLAMP Signal Start"
|
|
line.long 0x04 "CLAMPWR,CLAMP Signal Width Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " CLAMPW ,CLAMP Signal Width"
|
|
line.long 0x08 "DESR,DE Signal Start Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " DES ,DE Signal Start"
|
|
line.long 0x0c "DEWR,DE Signal Width Register"
|
|
hexmask.long.word 0x0c 0.--11. 1. " DEW ,DE Signal Width"
|
|
tree.end
|
|
tree.end
|
|
width 9.
|
|
tree "Display Attribute Registers"
|
|
group.long 0x80++0x0f
|
|
line.long 0x0 "CP1TR,Color Palette Transparent Color Register"
|
|
bitfld.long 0x0 15. " CP1IF ,Color Palette Index F" "Not set,Set"
|
|
bitfld.long 0x0 14. " CP1IE ,Color Palette Index E" "Not set,Set"
|
|
bitfld.long 0x0 13. " CP1ID ,Color Palette Index D" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 12. " CP1IC ,Color Palette Index C" "Not set,Set"
|
|
bitfld.long 0x0 11. " CP1IB ,Color Palette Index B" "Not set,Set"
|
|
bitfld.long 0x0 10. " CP1IA ,Color Palette Index A" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 9. " CP1I9 ,Color Palette Index 9" "Not set,Set"
|
|
bitfld.long 0x0 8. " CP1I8 ,Color Palette Index 8" "Not set,Set"
|
|
bitfld.long 0x0 7. " CP1I7 ,Color Palette Index 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 6. " CP1I6 ,Color Palette Index 6" "Not set,Set"
|
|
bitfld.long 0x0 5. " CP1I5 ,Color Palette Index 5" "Not set,Set"
|
|
bitfld.long 0x0 4. " CP1I4 ,Color Palette Index 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CP1I3 ,Color Palette Index 3" "Not set,Set"
|
|
bitfld.long 0x0 2. " CP1I2 ,Color Palette Index 2" "Not set,Set"
|
|
bitfld.long 0x0 1. " CP1I1 ,Color Palette Index 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CP1I0 ,Color Palette Index 0" "Not set,Set"
|
|
line.long 0x4 "CP2TR,Color Palette Transparent Color Register"
|
|
bitfld.long 0x4 15. " CP2IF ,Color Palette Index F" "Not set,Set"
|
|
bitfld.long 0x4 14. " CP2IE ,Color Palette Index E" "Not set,Set"
|
|
bitfld.long 0x4 13. " CP2ID ,Color Palette Index D" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 12. " CP2IC ,Color Palette Index C" "Not set,Set"
|
|
bitfld.long 0x4 11. " CP2IB ,Color Palette Index B" "Not set,Set"
|
|
bitfld.long 0x4 10. " CP2IA ,Color Palette Index A" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 9. " CP2I9 ,Color Palette Index 9" "Not set,Set"
|
|
bitfld.long 0x4 8. " CP2I8 ,Color Palette Index 8" "Not set,Set"
|
|
bitfld.long 0x4 7. " CP2I7 ,Color Palette Index 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 6. " CP2I6 ,Color Palette Index 6" "Not set,Set"
|
|
bitfld.long 0x4 5. " CP2I5 ,Color Palette Index 5" "Not set,Set"
|
|
bitfld.long 0x4 4. " CP2I4 ,Color Palette Index 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 3. " CP2I3 ,Color Palette Index 3" "Not set,Set"
|
|
bitfld.long 0x4 2. " CP2I2 ,Color Palette Index 2" "Not set,Set"
|
|
bitfld.long 0x4 1. " CP2I1 ,Color Palette Index 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CP2I0 ,Color Palette Index 0" "Not set,Set"
|
|
line.long 0x8 "CP3TR,Color Palette Transparent Color Register"
|
|
bitfld.long 0x8 15. " CP3IF ,Color Palette Index F" "Not set,Set"
|
|
bitfld.long 0x8 14. " CP3IE ,Color Palette Index E" "Not set,Set"
|
|
bitfld.long 0x8 13. " CP3ID ,Color Palette Index D" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x8 12. " CP3IC ,Color Palette Index C" "Not set,Set"
|
|
bitfld.long 0x8 11. " CP3IB ,Color Palette Index B" "Not set,Set"
|
|
bitfld.long 0x8 10. " CP3IA ,Color Palette Index A" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x8 9. " CP3I9 ,Color Palette Index 9" "Not set,Set"
|
|
bitfld.long 0x8 8. " CP3I8 ,Color Palette Index 8" "Not set,Set"
|
|
bitfld.long 0x8 7. " CP3I7 ,Color Palette Index 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x8 6. " CP3I6 ,Color Palette Index 6" "Not set,Set"
|
|
bitfld.long 0x8 5. " CP3I5 ,Color Palette Index 5" "Not set,Set"
|
|
bitfld.long 0x8 4. " CP3I4 ,Color Palette Index 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x8 3. " CP3I3 ,Color Palette Index 3" "Not set,Set"
|
|
bitfld.long 0x8 2. " CP3I2 ,Color Palette Index 2" "Not set,Set"
|
|
bitfld.long 0x8 1. " CP3I1 ,Color Palette Index 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CP3I0 ,Color Palette Index 0" "Not set,Set"
|
|
line.long 0xC "CP4TR,Color Palette Transparent Color Register"
|
|
bitfld.long 0xC 15. " CP4IF ,Color Palette Index F" "Not set,Set"
|
|
bitfld.long 0xC 14. " CP4IE ,Color Palette Index E" "Not set,Set"
|
|
bitfld.long 0xC 13. " CP4ID ,Color Palette Index D" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0xC 12. " CP4IC ,Color Palette Index C" "Not set,Set"
|
|
bitfld.long 0xC 11. " CP4IB ,Color Palette Index B" "Not set,Set"
|
|
bitfld.long 0xC 10. " CP4IA ,Color Palette Index A" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0xC 9. " CP4I9 ,Color Palette Index 9" "Not set,Set"
|
|
bitfld.long 0xC 8. " CP4I8 ,Color Palette Index 8" "Not set,Set"
|
|
bitfld.long 0xC 7. " CP4I7 ,Color Palette Index 7" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0xC 6. " CP4I6 ,Color Palette Index 6" "Not set,Set"
|
|
bitfld.long 0xC 5. " CP4I5 ,Color Palette Index 5" "Not set,Set"
|
|
bitfld.long 0xC 4. " CP4I4 ,Color Palette Index 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0xC 3. " CP4I3 ,Color Palette Index 3" "Not set,Set"
|
|
bitfld.long 0xC 2. " CP4I2 ,Color Palette Index 2" "Not set,Set"
|
|
bitfld.long 0xC 1. " CP4I1 ,Color Palette Index 1" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CP4I0 ,Color Palette Index 0" "Not set,Set"
|
|
tree "Channel 1"
|
|
group.long 0x90++0x0f
|
|
line.long 0x00 "DOOR,Display-Off Mode Output Register"
|
|
hexmask.long.byte 0x00 18.--23. 1. " DOR ,Display Off Mode Output Red"
|
|
hexmask.long.byte 0x00 10.--15. 1. " DOG ,Display Off Mode Output Green"
|
|
hexmask.long.byte 0x00 2.--7. 1. " DOB ,Display Off Mode Output Blue"
|
|
line.long 0x04 "CDER,Color Detection Register"
|
|
hexmask.long.byte 0x04 18.--23. 1. " CDR ,Color Detection Red"
|
|
hexmask.long.byte 0x04 10.--15. 1. " CDG ,Color Detection Green"
|
|
hexmask.long.byte 0x04 2.--7. 1. " CDB ,Color Detection Blue"
|
|
line.long 0x08 "BPOR,Ground Color Register"
|
|
hexmask.long.byte 0x08 18.--23. 1. " BPOR ,Background Plane Output Red"
|
|
hexmask.long.byte 0x08 10.--15. 1. " BPOG ,Background Plane Output Green"
|
|
hexmask.long.byte 0x08 2.--7. 1. " BPOB ,Background Plane Output Blue"
|
|
line.long 0x0c "RINTOFSR,Raster Interrupt Offset Register"
|
|
hexmask.long.word 0x0c 0.--10. 1. " RINTOFS ,Raster Interrupt Offset"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x30090++0x0f
|
|
line.long 0x00 "DOOR,Display-Off Mode Output Register"
|
|
hexmask.long.byte 0x00 18.--23. 1. " DOR ,Display Off Mode Output Red"
|
|
hexmask.long.byte 0x00 10.--15. 1. " DOG ,Display Off Mode Output Green"
|
|
hexmask.long.byte 0x00 2.--7. 1. " DOB ,Display Off Mode Output Blue"
|
|
line.long 0x04 "CDER,Color Detection Register"
|
|
hexmask.long.byte 0x04 18.--23. 1. " CDR ,Color Detection Red"
|
|
hexmask.long.byte 0x04 10.--15. 1. " CDG ,Color Detection Green"
|
|
hexmask.long.byte 0x04 2.--7. 1. " CDB ,Color Detection Blue"
|
|
line.long 0x08 "BPOR,Ground Color Register"
|
|
hexmask.long.byte 0x08 18.--23. 1. " BPOR ,Background Plane Output Red"
|
|
hexmask.long.byte 0x08 10.--15. 1. " BPOG ,Background Plane Output Green"
|
|
hexmask.long.byte 0x08 2.--7. 1. " BPOB ,Background Plane Output Blue"
|
|
line.long 0x0c "RINTOFSR,Raster Interrupt Offset Register"
|
|
hexmask.long.word 0x0c 0.--10. 1. " RINTOFS ,Raster Interrupt Offset"
|
|
tree.end
|
|
group.long 0xc8++0x03
|
|
line.long 0x00 "DSHPR,Display SuperHyway Priority Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PRIH ,Priority High" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PRIL ,Priority Low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Display Planes 1-8"
|
|
tree "Display Plane 1"
|
|
base (ad:0xFFF80000+0x100)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P1MR,Plane 1 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P1VISL ,Plane 1 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P1YCDF ,Plane 1 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P1TC ,Plane 1 Transparent Color" "P1TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P1WAE ,Plane 1 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P1SPM ,Plane 1 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P1CPSL ,Plane 1 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1DC ,Plane 1 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P1BM ,Plane 1 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P1DDF ,Plane 1 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P1MWR,Plane 1 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P1MWX ,Plane 1 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x100))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P1ALPHAR,Plane 1 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P1ABIT ,Plane 1 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P1BRSL ,Plane 1 Blend Ratio Selection" "P1ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P1ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P1ALPHA ,Plane 1 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P1ALPHAR,Plane 1 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P1ABIT ,Plane 1 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P1ALPHA ,Plane 1 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P1DSXR,Plane 1 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P1DSX ,Plane 1 Display Size X"
|
|
line.long 0x04 "P1DSYR,Plane 1 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P1DSY ,Plane 1 Display Size Y"
|
|
line.long 0x08 "P1DPXR,Plane 1 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P1DPX ,Plane 1 Display Position X"
|
|
line.long 0x0C "P1DPYR,Plane 1 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P1DPY ,Plane 1 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P1DSXR,Plane 1 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P1DSX ,Plane 1 Display Size X"
|
|
line.long 0x04 "P1DSYR,Plane 1 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P1DSY ,Plane 1 Display Size Y"
|
|
line.long 0x08 "P1DPXR,Plane 1 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P1DPX ,Plane 1 Display Position X"
|
|
line.long 0x0C "P1DPYR,Plane 1 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P1DPY ,Plane 1 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P1DSA0R,Plane 1 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P1DSA0 ,Plane 1 Display Domain Start Address 0"
|
|
line.long 0x04 "P1DSA1R,Plane 1 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P1DSA1 ,Plane 1 Display Domain Start Address 1"
|
|
line.long 0x08 "P1DSA2R,Plane 1 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P1DSA2 ,Plane 1 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P1DSA0R,Plane 1 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P1DSA0 ,Plane 1 Display Domain Start Address 0"
|
|
line.long 0x04 "P1DSA1R,Plane 1 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P1DSA1 ,Plane 1 Display Domain Start Address 1"
|
|
line.long 0x08 "P1DSA2R,Plane 1 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P1DSA2 ,Plane 1 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P1SPXR,Plane 1 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P1SPX ,Plane 1 Starting Position X"
|
|
line.long 0x04 "P1SPYR,Plane 1 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P1SPY ,Plane 1 Starting Position Y"
|
|
line.long 0x08 "P1WASPR,Plane 1 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P1WASPY ,Plane 1 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P1WAMWR,Plane 1 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P1WAMWY ,Plane 1 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P1BTR,Plane 1 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P1BTA ,Plane 1 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P1BTB ,Plane 1 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P1TC1R,Plane 1 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P1TC1 ,Plane 1 Transparent Color 1"
|
|
line.long 0x04 "P1TC2R,Plane 1 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P1TC2 ,Plane 1 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P1TC3R,Plane 1 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P1TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P1TC3 ,Plane 1 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P1MLR,Plane 1 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P1MLY ,Plane 1 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P1SWAPR,Plane 1 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P1DIGN ,Plane 1 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1SPQW ,Plane 1 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1SPLW ,Plane 1 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1SPWD ,Plane 1 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P1SPBY ,Plane 1 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P1DDCR,Plane 1 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P1DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P1LRGB1 ,Plane 1 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P1LRGB0 ,Plane 1 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P1DDCR2,Plane 1 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P1DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P1NV21 ,Plane 1 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P1Y420 ,Plane 1 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1DIVU ,Plane 1 UV Data from Divided YUV" "P1DDF bit of P1MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P1DIVY ,Plane 1 Y Data from Divided YUV" "P1DDF bit of P1MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P1DDCR4,Plane 1 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P1DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P1SDFS ,Plane 1 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P1EDF ,Plane 1 Extensional Data Format" "P1DDF bit of P1MR/P1LRGB1 or P1LRGB0 bit in P1DDCR/P1DIVU or P1DIVY bit in P1DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 2"
|
|
base (ad:0xFFF80000+0x200)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P2MR,Plane 2 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P2VISL ,Plane 2 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P2YCDF ,Plane 2 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P2TC ,Plane 2 Transparent Color" "P2TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P2WAE ,Plane 2 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P2SPM ,Plane 2 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P2CPSL ,Plane 2 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2DC ,Plane 2 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P2BM ,Plane 2 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P2DDF ,Plane 2 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P2MWR,Plane 2 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P2MWX ,Plane 2 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x200))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P2ALPHAR,Plane 2 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P2ABIT ,Plane 2 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P2BRSL ,Plane 2 Blend Ratio Selection" "P2ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P2ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P2ALPHA ,Plane 2 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P2ALPHAR,Plane 2 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P2ABIT ,Plane 2 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P2ALPHA ,Plane 2 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P2DSXR,Plane 2 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P2DSX ,Plane 2 Display Size X"
|
|
line.long 0x04 "P2DSYR,Plane 2 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P2DSY ,Plane 2 Display Size Y"
|
|
line.long 0x08 "P2DPXR,Plane 2 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P2DPX ,Plane 2 Display Position X"
|
|
line.long 0x0C "P2DPYR,Plane 2 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P2DPY ,Plane 2 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P2DSXR,Plane 2 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P2DSX ,Plane 2 Display Size X"
|
|
line.long 0x04 "P2DSYR,Plane 2 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P2DSY ,Plane 2 Display Size Y"
|
|
line.long 0x08 "P2DPXR,Plane 2 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P2DPX ,Plane 2 Display Position X"
|
|
line.long 0x0C "P2DPYR,Plane 2 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P2DPY ,Plane 2 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P2DSA0R,Plane 2 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P2DSA0 ,Plane 2 Display Domain Start Address 0"
|
|
line.long 0x04 "P2DSA1R,Plane 2 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P2DSA1 ,Plane 2 Display Domain Start Address 1"
|
|
line.long 0x08 "P2DSA2R,Plane 2 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P2DSA2 ,Plane 2 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P2DSA0R,Plane 2 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P2DSA0 ,Plane 2 Display Domain Start Address 0"
|
|
line.long 0x04 "P2DSA1R,Plane 2 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P2DSA1 ,Plane 2 Display Domain Start Address 1"
|
|
line.long 0x08 "P2DSA2R,Plane 2 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P2DSA2 ,Plane 2 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P2SPXR,Plane 2 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P2SPX ,Plane 2 Starting Position X"
|
|
line.long 0x04 "P2SPYR,Plane 2 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P2SPY ,Plane 2 Starting Position Y"
|
|
line.long 0x08 "P2WASPR,Plane 2 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P2WASPY ,Plane 2 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P2WAMWR,Plane 2 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P2WAMWY ,Plane 2 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P2BTR,Plane 2 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P2BTA ,Plane 2 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P2BTB ,Plane 2 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P2TC1R,Plane 2 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P2TC1 ,Plane 2 Transparent Color 1"
|
|
line.long 0x04 "P2TC2R,Plane 2 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P2TC2 ,Plane 2 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P2TC3R,Plane 2 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P2TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P2TC3 ,Plane 2 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P2MLR,Plane 2 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P2MLY ,Plane 2 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P2SWAPR,Plane 2 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P2DIGN ,Plane 2 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2SPQW ,Plane 2 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2SPLW ,Plane 2 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P2SPWD ,Plane 2 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2SPBY ,Plane 2 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P2DDCR,Plane 2 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P2DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2LRGB1 ,Plane 2 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P2LRGB0 ,Plane 2 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P2DDCR2,Plane 2 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P2DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P2NV21 ,Plane 2 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P2Y420 ,Plane 2 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P2DIVU ,Plane 2 UV Data from Divided YUV" "P2DDF bit of P2MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2DIVY ,Plane 2 Y Data from Divided YUV" "P2DDF bit of P2MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P2DDCR4,Plane 2 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P2DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P2SDFS ,Plane 2 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P2EDF ,Plane 2 Extensional Data Format" "P2DDF bit of P2MR/P2LRGB1 or P2LRGB0 bit in P2DDCR/P2DIVU or P2DIVY bit in P2DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 3"
|
|
base (ad:0xFFF80000+0x300)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P3MR,Plane 3 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P3VISL ,Plane 3 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P3YCDF ,Plane 3 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P3TC ,Plane 3 Transparent Color" "P3TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P3WAE ,Plane 3 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P3SPM ,Plane 3 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P3CPSL ,Plane 3 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P3DC ,Plane 3 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P3BM ,Plane 3 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P3DDF ,Plane 3 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P3MWR,Plane 3 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P3MWX ,Plane 3 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x300))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P3ALPHAR,Plane 3 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P3ABIT ,Plane 3 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P3BRSL ,Plane 3 Blend Ratio Selection" "P3ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P3ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P3ALPHA ,Plane 3 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P3ALPHAR,Plane 3 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P3ABIT ,Plane 3 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P3ALPHA ,Plane 3 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P3DSXR,Plane 3 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P3DSX ,Plane 3 Display Size X"
|
|
line.long 0x04 "P3DSYR,Plane 3 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P3DSY ,Plane 3 Display Size Y"
|
|
line.long 0x08 "P3DPXR,Plane 3 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P3DPX ,Plane 3 Display Position X"
|
|
line.long 0x0C "P3DPYR,Plane 3 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P3DPY ,Plane 3 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P3DSXR,Plane 3 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P3DSX ,Plane 3 Display Size X"
|
|
line.long 0x04 "P3DSYR,Plane 3 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P3DSY ,Plane 3 Display Size Y"
|
|
line.long 0x08 "P3DPXR,Plane 3 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P3DPX ,Plane 3 Display Position X"
|
|
line.long 0x0C "P3DPYR,Plane 3 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P3DPY ,Plane 3 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P3DSA0R,Plane 3 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P3DSA0 ,Plane 3 Display Domain Start Address 0"
|
|
line.long 0x04 "P3DSA1R,Plane 3 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P3DSA1 ,Plane 3 Display Domain Start Address 1"
|
|
line.long 0x08 "P3DSA2R,Plane 3 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P3DSA2 ,Plane 3 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P3DSA0R,Plane 3 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P3DSA0 ,Plane 3 Display Domain Start Address 0"
|
|
line.long 0x04 "P3DSA1R,Plane 3 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P3DSA1 ,Plane 3 Display Domain Start Address 1"
|
|
line.long 0x08 "P3DSA2R,Plane 3 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P3DSA2 ,Plane 3 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P3SPXR,Plane 3 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P3SPX ,Plane 3 Starting Position X"
|
|
line.long 0x04 "P3SPYR,Plane 3 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P3SPY ,Plane 3 Starting Position Y"
|
|
line.long 0x08 "P3WASPR,Plane 3 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P3WASPY ,Plane 3 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P3WAMWR,Plane 3 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P3WAMWY ,Plane 3 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P3BTR,Plane 3 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P3BTA ,Plane 3 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P3BTB ,Plane 3 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P3TC1R,Plane 3 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P3TC1 ,Plane 3 Transparent Color 1"
|
|
line.long 0x04 "P3TC2R,Plane 3 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P3TC2 ,Plane 3 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P3TC3R,Plane 3 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P3TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P3TC3 ,Plane 3 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P3MLR,Plane 3 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P3MLY ,Plane 3 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P3SWAPR,Plane 3 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P3DIGN ,Plane 3 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3SPQW ,Plane 3 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P3SPLW ,Plane 3 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P3SPWD ,Plane 3 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P3SPBY ,Plane 3 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P3DDCR,Plane 3 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P3DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P3LRGB1 ,Plane 3 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P3LRGB0 ,Plane 3 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P3DDCR2,Plane 3 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P3DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P3NV21 ,Plane 3 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P3Y420 ,Plane 3 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P3DIVU ,Plane 3 UV Data from Divided YUV" "P3DDF bit of P3MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P3DIVY ,Plane 3 Y Data from Divided YUV" "P3DDF bit of P3MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P3DDCR4,Plane 3 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P3DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P3SDFS ,Plane 3 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P3EDF ,Plane 3 Extensional Data Format" "P3DDF bit of P3MR/P3LRGB1 or P3LRGB0 bit in P3DDCR/P3DIVU or P3DIVY bit in P3DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 4"
|
|
base (ad:0xFFF80000+0x400)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P4MR,Plane 4 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P4VISL ,Plane 4 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P4YCDF ,Plane 4 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P4TC ,Plane 4 Transparent Color" "P4TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P4WAE ,Plane 4 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P4SPM ,Plane 4 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P4CPSL ,Plane 4 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P4DC ,Plane 4 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P4BM ,Plane 4 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P4DDF ,Plane 4 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P4MWR,Plane 4 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P4MWX ,Plane 4 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x400))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P4ALPHAR,Plane 4 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P4ABIT ,Plane 4 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P4BRSL ,Plane 4 Blend Ratio Selection" "P4ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P4ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P4ALPHA ,Plane 4 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P4ALPHAR,Plane 4 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P4ABIT ,Plane 4 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P4ALPHA ,Plane 4 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P4DSXR,Plane 4 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P4DSX ,Plane 4 Display Size X"
|
|
line.long 0x04 "P4DSYR,Plane 4 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P4DSY ,Plane 4 Display Size Y"
|
|
line.long 0x08 "P4DPXR,Plane 4 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P4DPX ,Plane 4 Display Position X"
|
|
line.long 0x0C "P4DPYR,Plane 4 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P4DPY ,Plane 4 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P4DSXR,Plane 4 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P4DSX ,Plane 4 Display Size X"
|
|
line.long 0x04 "P4DSYR,Plane 4 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P4DSY ,Plane 4 Display Size Y"
|
|
line.long 0x08 "P4DPXR,Plane 4 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P4DPX ,Plane 4 Display Position X"
|
|
line.long 0x0C "P4DPYR,Plane 4 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P4DPY ,Plane 4 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P4DSA0R,Plane 4 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P4DSA0 ,Plane 4 Display Domain Start Address 0"
|
|
line.long 0x04 "P4DSA1R,Plane 4 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P4DSA1 ,Plane 4 Display Domain Start Address 1"
|
|
line.long 0x08 "P4DSA2R,Plane 4 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P4DSA2 ,Plane 4 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P4DSA0R,Plane 4 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P4DSA0 ,Plane 4 Display Domain Start Address 0"
|
|
line.long 0x04 "P4DSA1R,Plane 4 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P4DSA1 ,Plane 4 Display Domain Start Address 1"
|
|
line.long 0x08 "P4DSA2R,Plane 4 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P4DSA2 ,Plane 4 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P4SPXR,Plane 4 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P4SPX ,Plane 4 Starting Position X"
|
|
line.long 0x04 "P4SPYR,Plane 4 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P4SPY ,Plane 4 Starting Position Y"
|
|
line.long 0x08 "P4WASPR,Plane 4 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P4WASPY ,Plane 4 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P4WAMWR,Plane 4 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P4WAMWY ,Plane 4 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P4BTR,Plane 4 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P4BTA ,Plane 4 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P4BTB ,Plane 4 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P4TC1R,Plane 4 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P4TC1 ,Plane 4 Transparent Color 1"
|
|
line.long 0x04 "P4TC2R,Plane 4 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P4TC2 ,Plane 4 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P4TC3R,Plane 4 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P4TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P4TC3 ,Plane 4 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P4MLR,Plane 4 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P4MLY ,Plane 4 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P4SWAPR,Plane 4 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4DIGN ,Plane 4 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P4SPQW ,Plane 4 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P4SPLW ,Plane 4 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P4SPWD ,Plane 4 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P4SPBY ,Plane 4 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P4DDCR,Plane 4 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P4DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P4LRGB1 ,Plane 4 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P4LRGB0 ,Plane 4 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P4DDCR2,Plane 4 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P4DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P4NV21 ,Plane 4 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4Y420 ,Plane 4 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P4DIVU ,Plane 4 UV Data from Divided YUV" "P4DDF bit of P4MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P4DIVY ,Plane 4 Y Data from Divided YUV" "P4DDF bit of P4MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P4DDCR4,Plane 4 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P4DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P4SDFS ,Plane 4 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P4EDF ,Plane 4 Extensional Data Format" "P4DDF bit of P4MR/P4LRGB1 or P4LRGB0 bit in P4DDCR/P4DIVU or P4DIVY bit in P4DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 5"
|
|
base (ad:0xFFF80000+0x500)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P5MR,Plane 5 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P5VISL ,Plane 5 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P5YCDF ,Plane 5 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P5TC ,Plane 5 Transparent Color" "P5TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P5WAE ,Plane 5 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P5SPM ,Plane 5 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P5CPSL ,Plane 5 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P5DC ,Plane 5 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P5BM ,Plane 5 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P5DDF ,Plane 5 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P5MWR,Plane 5 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P5MWX ,Plane 5 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x500))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P5ALPHAR,Plane 5 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P5ABIT ,Plane 5 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P5BRSL ,Plane 5 Blend Ratio Selection" "P5ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P5ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P5ALPHA ,Plane 5 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P5ALPHAR,Plane 5 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P5ABIT ,Plane 5 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P5ALPHA ,Plane 5 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P5DSXR,Plane 5 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P5DSX ,Plane 5 Display Size X"
|
|
line.long 0x04 "P5DSYR,Plane 5 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P5DSY ,Plane 5 Display Size Y"
|
|
line.long 0x08 "P5DPXR,Plane 5 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P5DPX ,Plane 5 Display Position X"
|
|
line.long 0x0C "P5DPYR,Plane 5 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P5DPY ,Plane 5 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P5DSXR,Plane 5 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P5DSX ,Plane 5 Display Size X"
|
|
line.long 0x04 "P5DSYR,Plane 5 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P5DSY ,Plane 5 Display Size Y"
|
|
line.long 0x08 "P5DPXR,Plane 5 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P5DPX ,Plane 5 Display Position X"
|
|
line.long 0x0C "P5DPYR,Plane 5 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P5DPY ,Plane 5 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P5DSA0R,Plane 5 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P5DSA0 ,Plane 5 Display Domain Start Address 0"
|
|
line.long 0x04 "P5DSA1R,Plane 5 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P5DSA1 ,Plane 5 Display Domain Start Address 1"
|
|
line.long 0x08 "P5DSA2R,Plane 5 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P5DSA2 ,Plane 5 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P5DSA0R,Plane 5 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P5DSA0 ,Plane 5 Display Domain Start Address 0"
|
|
line.long 0x04 "P5DSA1R,Plane 5 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P5DSA1 ,Plane 5 Display Domain Start Address 1"
|
|
line.long 0x08 "P5DSA2R,Plane 5 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P5DSA2 ,Plane 5 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P5SPXR,Plane 5 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P5SPX ,Plane 5 Starting Position X"
|
|
line.long 0x04 "P5SPYR,Plane 5 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P5SPY ,Plane 5 Starting Position Y"
|
|
line.long 0x08 "P5WASPR,Plane 5 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P5WASPY ,Plane 5 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P5WAMWR,Plane 5 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P5WAMWY ,Plane 5 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P5BTR,Plane 5 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P5BTA ,Plane 5 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P5BTB ,Plane 5 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P5TC1R,Plane 5 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P5TC1 ,Plane 5 Transparent Color 1"
|
|
line.long 0x04 "P5TC2R,Plane 5 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P5TC2 ,Plane 5 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P5TC3R,Plane 5 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P5TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P5TC3 ,Plane 5 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P5MLR,Plane 5 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P5MLY ,Plane 5 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P5SWAPR,Plane 5 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P5DIGN ,Plane 5 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P5SPQW ,Plane 5 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P5SPLW ,Plane 5 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P5SPWD ,Plane 5 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P5SPBY ,Plane 5 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P5DDCR,Plane 5 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P5DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P5LRGB1 ,Plane 5 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P5LRGB0 ,Plane 5 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P5DDCR2,Plane 5 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P5DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5NV21 ,Plane 5 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P5Y420 ,Plane 5 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P5DIVU ,Plane 5 UV Data from Divided YUV" "P5DDF bit of P5MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P5DIVY ,Plane 5 Y Data from Divided YUV" "P5DDF bit of P5MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P5DDCR4,Plane 5 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P5DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P5SDFS ,Plane 5 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P5EDF ,Plane 5 Extensional Data Format" "P5DDF bit of P5MR/P5LRGB1 or P5LRGB0 bit in P5DDCR/P5DIVU or P5DIVY bit in P5DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 6"
|
|
base (ad:0xFFF80000+0x600)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P6MR,Plane 6 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P6VISL ,Plane 6 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P6YCDF ,Plane 6 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P6TC ,Plane 6 Transparent Color" "P6TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P6WAE ,Plane 6 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P6SPM ,Plane 6 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P6CPSL ,Plane 6 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P6DC ,Plane 6 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P6BM ,Plane 6 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P6DDF ,Plane 6 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P6MWR,Plane 6 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P6MWX ,Plane 6 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x600))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P6ALPHAR,Plane 6 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P6ABIT ,Plane 6 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P6BRSL ,Plane 6 Blend Ratio Selection" "P6ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P6ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P6ALPHA ,Plane 6 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P6ALPHAR,Plane 6 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P6ABIT ,Plane 6 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P6ALPHA ,Plane 6 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P6DSXR,Plane 6 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P6DSX ,Plane 6 Display Size X"
|
|
line.long 0x04 "P6DSYR,Plane 6 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P6DSY ,Plane 6 Display Size Y"
|
|
line.long 0x08 "P6DPXR,Plane 6 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P6DPX ,Plane 6 Display Position X"
|
|
line.long 0x0C "P6DPYR,Plane 6 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P6DPY ,Plane 6 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P6DSXR,Plane 6 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P6DSX ,Plane 6 Display Size X"
|
|
line.long 0x04 "P6DSYR,Plane 6 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P6DSY ,Plane 6 Display Size Y"
|
|
line.long 0x08 "P6DPXR,Plane 6 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P6DPX ,Plane 6 Display Position X"
|
|
line.long 0x0C "P6DPYR,Plane 6 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P6DPY ,Plane 6 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P6DSA0R,Plane 6 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P6DSA0 ,Plane 6 Display Domain Start Address 0"
|
|
line.long 0x04 "P6DSA1R,Plane 6 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P6DSA1 ,Plane 6 Display Domain Start Address 1"
|
|
line.long 0x08 "P6DSA2R,Plane 6 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P6DSA2 ,Plane 6 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P6DSA0R,Plane 6 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P6DSA0 ,Plane 6 Display Domain Start Address 0"
|
|
line.long 0x04 "P6DSA1R,Plane 6 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P6DSA1 ,Plane 6 Display Domain Start Address 1"
|
|
line.long 0x08 "P6DSA2R,Plane 6 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P6DSA2 ,Plane 6 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P6SPXR,Plane 6 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P6SPX ,Plane 6 Starting Position X"
|
|
line.long 0x04 "P6SPYR,Plane 6 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P6SPY ,Plane 6 Starting Position Y"
|
|
line.long 0x08 "P6WASPR,Plane 6 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P6WASPY ,Plane 6 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P6WAMWR,Plane 6 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P6WAMWY ,Plane 6 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P6BTR,Plane 6 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P6BTA ,Plane 6 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P6BTB ,Plane 6 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P6TC1R,Plane 6 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P6TC1 ,Plane 6 Transparent Color 1"
|
|
line.long 0x04 "P6TC2R,Plane 6 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P6TC2 ,Plane 6 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P6TC3R,Plane 6 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P6TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P6TC3 ,Plane 6 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P6MLR,Plane 6 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P6MLY ,Plane 6 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P6SWAPR,Plane 6 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P6DIGN ,Plane 6 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P6SPQW ,Plane 6 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P6SPLW ,Plane 6 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P6SPWD ,Plane 6 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P6SPBY ,Plane 6 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P6DDCR,Plane 6 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P6DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P6LRGB1 ,Plane 6 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P6LRGB0 ,Plane 6 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P6DDCR2,Plane 6 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P6DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P6NV21 ,Plane 6 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P6Y420 ,Plane 6 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P6DIVU ,Plane 6 UV Data from Divided YUV" "P6DDF bit of P6MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P6DIVY ,Plane 6 Y Data from Divided YUV" "P6DDF bit of P6MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P6DDCR4,Plane 6 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P6DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P6SDFS ,Plane 6 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P6EDF ,Plane 6 Extensional Data Format" "P6DDF bit of P6MR/P6LRGB1 or P6LRGB0 bit in P6DDCR/P6DIVU or P6DIVY bit in P6DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 7"
|
|
base (ad:0xFFF80000+0x700)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P7MR,Plane 7 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P7VISL ,Plane 7 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P7YCDF ,Plane 7 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P7TC ,Plane 7 Transparent Color" "P7TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P7WAE ,Plane 7 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P7SPM ,Plane 7 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P7CPSL ,Plane 7 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7DC ,Plane 7 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P7BM ,Plane 7 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P7DDF ,Plane 7 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P7MWR,Plane 7 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P7MWX ,Plane 7 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x700))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P7ALPHAR,Plane 7 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P7ABIT ,Plane 7 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P7BRSL ,Plane 7 Blend Ratio Selection" "P7ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P7ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P7ALPHA ,Plane 7 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P7ALPHAR,Plane 7 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P7ABIT ,Plane 7 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P7ALPHA ,Plane 7 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P7DSXR,Plane 7 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P7DSX ,Plane 7 Display Size X"
|
|
line.long 0x04 "P7DSYR,Plane 7 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P7DSY ,Plane 7 Display Size Y"
|
|
line.long 0x08 "P7DPXR,Plane 7 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P7DPX ,Plane 7 Display Position X"
|
|
line.long 0x0C "P7DPYR,Plane 7 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P7DPY ,Plane 7 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P7DSXR,Plane 7 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P7DSX ,Plane 7 Display Size X"
|
|
line.long 0x04 "P7DSYR,Plane 7 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P7DSY ,Plane 7 Display Size Y"
|
|
line.long 0x08 "P7DPXR,Plane 7 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P7DPX ,Plane 7 Display Position X"
|
|
line.long 0x0C "P7DPYR,Plane 7 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P7DPY ,Plane 7 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P7DSA0R,Plane 7 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P7DSA0 ,Plane 7 Display Domain Start Address 0"
|
|
line.long 0x04 "P7DSA1R,Plane 7 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P7DSA1 ,Plane 7 Display Domain Start Address 1"
|
|
line.long 0x08 "P7DSA2R,Plane 7 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P7DSA2 ,Plane 7 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P7DSA0R,Plane 7 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P7DSA0 ,Plane 7 Display Domain Start Address 0"
|
|
line.long 0x04 "P7DSA1R,Plane 7 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P7DSA1 ,Plane 7 Display Domain Start Address 1"
|
|
line.long 0x08 "P7DSA2R,Plane 7 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P7DSA2 ,Plane 7 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P7SPXR,Plane 7 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P7SPX ,Plane 7 Starting Position X"
|
|
line.long 0x04 "P7SPYR,Plane 7 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P7SPY ,Plane 7 Starting Position Y"
|
|
line.long 0x08 "P7WASPR,Plane 7 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P7WASPY ,Plane 7 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P7WAMWR,Plane 7 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P7WAMWY ,Plane 7 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P7BTR,Plane 7 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P7BTA ,Plane 7 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P7BTB ,Plane 7 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P7TC1R,Plane 7 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P7TC1 ,Plane 7 Transparent Color 1"
|
|
line.long 0x04 "P7TC2R,Plane 7 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P7TC2 ,Plane 7 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P7TC3R,Plane 7 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P7TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P7TC3 ,Plane 7 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P7MLR,Plane 7 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P7MLY ,Plane 7 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P7SWAPR,Plane 7 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P7DIGN ,Plane 7 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P7SPQW ,Plane 7 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P7SPLW ,Plane 7 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P7SPWD ,Plane 7 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P7SPBY ,Plane 7 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P7DDCR,Plane 7 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P7DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P7LRGB1 ,Plane 7 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P7LRGB0 ,Plane 7 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P7DDCR2,Plane 7 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P7DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P7NV21 ,Plane 7 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P7Y420 ,Plane 7 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P7DIVU ,Plane 7 UV Data from Divided YUV" "P7DDF bit of P7MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P7DIVY ,Plane 7 Y Data from Divided YUV" "P7DDF bit of P7MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P7DDCR4,Plane 7 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P7DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P7SDFS ,Plane 7 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P7EDF ,Plane 7 Extensional Data Format" "P7DDF bit of P7MR/P7LRGB1 or P7LRGB0 bit in P7DDCR/P7DIVU or P7DIVY bit in P7DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Display Plane 8"
|
|
base (ad:0xFFF80000+0x800)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P8MR,Plane 8 Mode Register"
|
|
bitfld.long 0x00 26.--27. " P8VISL ,Plane 8 Vieo Input Select" "VIN0,VIN1,VIN2,VIN3"
|
|
textline " "
|
|
bitfld.long 0x00 20. " P8YCDF ,Plane 8 YC Data Format" "UYVY,YUYV"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P8TC ,Plane 8 Transparent Color" "P8TC1R,CP1TR/CP4TR"
|
|
textline " "
|
|
bitfld.long 0x00 16. " P8WAE ,Plane 8 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " P8SPM ,Plane 8 Super Impose Mode" "Transparent color processing,Blending/Lower plane,EOR operation/Lower plane,,No transparent processing,Blending/Lower plane,EOR operation/Lower plane,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P8CPSL ,Plane 8 Color Palette Selection" "Palette 1,Palette 2,Palette 3,Palette 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " P8DC ,Plane 8 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P8BM ,Plane 8 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " P8DDF ,Plane 8 Display Data Format" "8bit/pixel,16bit/pixel,ARGB,YC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P8MWR,Plane 8 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P8MWX ,Plane 8 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x800))&0x3)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P8ALPHAR,Plane 8 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P8ABIT ,Plane 8 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " P8BRSL ,Plane 8 Blend Ratio Selection" "P8ALPHA,,PnMR bits 24-31,Display data of plane this bits 0-2,,P8ALPHA,PnMR bits 24-31,Display data of Alpha-ratio plane this bits 0-2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P8ALPHA ,Plane 8 Blend Ratio"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P8ALPHAR,Plane 8 Blend Ratio Register"
|
|
bitfld.long 0x00 12.--13. " P8ABIT ,Plane 8 A Bit Function Select" "A=1,A=0,Regardless A,Regardless A"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " P8ALPHA ,Plane 8 Blend Ratio"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P8DSXR,Plane 8 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P8DSX ,Plane 8 Display Size X"
|
|
line.long 0x04 "P8DSYR,Plane 8 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P8DSY ,Plane 8 Display Size Y"
|
|
line.long 0x08 "P8DPXR,Plane 8 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P8DPX ,Plane 8 Display Position X"
|
|
line.long 0x0C "P8DPYR,Plane 8 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P8DPY ,Plane 8 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P8DSXR,Plane 8 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P8DSX ,Plane 8 Display Size X"
|
|
line.long 0x04 "P8DSYR,Plane 8 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P8DSY ,Plane 8 Display Size Y"
|
|
line.long 0x08 "P8DPXR,Plane 8 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P8DPX ,Plane 8 Display Position X"
|
|
line.long 0x0C "P8DPYR,Plane 8 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P8DPY ,Plane 8 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P8DSA0R,Plane 8 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P8DSA0 ,Plane 8 Display Domain Start Address 0"
|
|
line.long 0x04 "P8DSA1R,Plane 8 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P8DSA1 ,Plane 8 Display Domain Start Address 1"
|
|
line.long 0x08 "P8DSA2R,Plane 8 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P8DSA2 ,Plane 8 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P8DSA0R,Plane 8 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P8DSA0 ,Plane 8 Display Domain Start Address 0"
|
|
line.long 0x04 "P8DSA1R,Plane 8 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P8DSA1 ,Plane 8 Display Domain Start Address 1"
|
|
line.long 0x08 "P8DSA2R,Plane 8 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P8DSA2 ,Plane 8 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P8SPXR,Plane 8 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P8SPX ,Plane 8 Starting Position X"
|
|
line.long 0x04 "P8SPYR,Plane 8 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P8SPY ,Plane 8 Starting Position Y"
|
|
line.long 0x08 "P8WASPR,Plane 8 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P8WASPY ,Plane 8 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P8WAMWR,Plane 8 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P8WAMWY ,Plane 8 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P8BTR,Plane 8 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P8BTA ,Plane 8 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P8BTB ,Plane 8 Blinking Cycle B"
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "P8TC1R,Plane 8 Transparent Color 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " P8TC1 ,Plane 8 Transparent Color 1"
|
|
line.long 0x04 "P8TC2R,Plane 8 Transparent Color 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P8TC2 ,Plane 8 Transparent Color 2"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "P8TC3R,Plane 8 Transparent Color 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CODE ,P8TC3R Enabling Code [0x66]"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " P8TC3 ,Plane 8 Transparent Color 3"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P8MLR,Plane 8 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P8MLY ,Plane 8 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P8SWAPR,Plane 8 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P8DIGN ,Plane 8 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P8SPQW ,Plane 8 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P8SPLW ,Plane 8 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P8SPWD ,Plane 8 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P8SPBY ,Plane 8 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "P8DDCR,Plane 8 Display Data Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P8DDCR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P8LRGB1 ,Plane 8 32 bits/pixel display control 1" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 10. " P8LRGB0 ,Plane 8 32 bits/pixel display control 0" "Not used,Used"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "P8DDCR2,Plane 8 Display Data Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,P8DDCR2 Enabling Code [0x7776]"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P8NV21 ,Plane 8 NV21 Data Format" "NV12 order,NV21 order"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P8Y420 ,Plane 8 YUV420 Data Format" "YUV422,YUV420"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P8DIVU ,Plane 8 UV Data from Divided YUV" "P8DDF bit of P8MR,UV data"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P8DIVY ,Plane 8 Y Data from Divided YUV" "P8DDF bit of P8MR,Y data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P8DDCR4,Plane 8 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P8DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P8SDFS ,Plane 8 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P8EDF ,Plane 8 Extensional Data Format" "P8DDF bit of P8MR/P8LRGB1 or P8LRGB0 bit in P8DDCR/P8DIVU or P8DIVY bit in P8DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "Alpha-Ratio Planes 1-8"
|
|
tree "Alpha-Ratio Plane 1"
|
|
base (ad:0xFFF80000+0xA100)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P1MR,Plane 1 Mode Register"
|
|
bitfld.long 0x00 16. " P1WAE ,Plane 1 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P1DC ,Plane 1 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P1BM ,Plane 1 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P1MWR,Plane 1 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P1MWX ,Plane 1 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P1DSXR,Plane 1 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P1DSX ,Plane 1 Display Size X"
|
|
line.long 0x04 "P1DSYR,Plane 1 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P1DSY ,Plane 1 Display Size Y"
|
|
line.long 0x08 "P1DPXR,Plane 1 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P1DPX ,Plane 1 Display Position X"
|
|
line.long 0x0C "P1DPYR,Plane 1 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P1DPY ,Plane 1 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P1DSXR,Plane 1 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P1DSX ,Plane 1 Display Size X"
|
|
line.long 0x04 "P1DSYR,Plane 1 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P1DSY ,Plane 1 Display Size Y"
|
|
line.long 0x08 "P1DPXR,Plane 1 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P1DPX ,Plane 1 Display Position X"
|
|
line.long 0x0C "P1DPYR,Plane 1 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P1DPY ,Plane 1 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P1DSA0R,Plane 1 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P1DSA0 ,Plane 1 Display Domain Start Address 0"
|
|
line.long 0x04 "P1DSA1R,Plane 1 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P1DSA1 ,Plane 1 Display Domain Start Address 1"
|
|
line.long 0x08 "P1DSA2R,Plane 1 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P1DSA2 ,Plane 1 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P1DSA0R,Plane 1 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P1DSA0 ,Plane 1 Display Domain Start Address 0"
|
|
line.long 0x04 "P1DSA1R,Plane 1 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P1DSA1 ,Plane 1 Display Domain Start Address 1"
|
|
line.long 0x08 "P1DSA2R,Plane 1 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P1DSA2 ,Plane 1 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P1SPXR,Plane 1 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P1SPX ,Plane 1 Starting Position X"
|
|
line.long 0x04 "P1SPYR,Plane 1 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P1SPY ,Plane 1 Starting Position Y"
|
|
line.long 0x08 "P1WASPR,Plane 1 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P1WASPY ,Plane 1 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P1WAMWR,Plane 1 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P1WAMWY ,Plane 1 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P1BTR,Plane 1 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P1BTA ,Plane 1 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P1BTB ,Plane 1 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P1MLR,Plane 1 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P1MLY ,Plane 1 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P1SWAPR,Plane 1 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P1DIGN ,Plane 1 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P1SPQW ,Plane 1 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P1SPLW ,Plane 1 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1SPWD ,Plane 1 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P1SPBY ,Plane 1 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P1DDCR4,Plane 1 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P1DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P1SDFS ,Plane 1 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P1EDF ,Plane 1 Extensional Data Format" "P1DDF bit of P1MR/P1LRGB1 or P1LRGB0 bit in P1DDCR/P1DIVU or P1DIVY bit in P1DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 2"
|
|
base (ad:0xFFF80000+0xA200)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P2MR,Plane 2 Mode Register"
|
|
bitfld.long 0x00 16. " P2WAE ,Plane 2 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P2DC ,Plane 2 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P2BM ,Plane 2 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P2MWR,Plane 2 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P2MWX ,Plane 2 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P2DSXR,Plane 2 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P2DSX ,Plane 2 Display Size X"
|
|
line.long 0x04 "P2DSYR,Plane 2 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P2DSY ,Plane 2 Display Size Y"
|
|
line.long 0x08 "P2DPXR,Plane 2 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P2DPX ,Plane 2 Display Position X"
|
|
line.long 0x0C "P2DPYR,Plane 2 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P2DPY ,Plane 2 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P2DSXR,Plane 2 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P2DSX ,Plane 2 Display Size X"
|
|
line.long 0x04 "P2DSYR,Plane 2 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P2DSY ,Plane 2 Display Size Y"
|
|
line.long 0x08 "P2DPXR,Plane 2 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P2DPX ,Plane 2 Display Position X"
|
|
line.long 0x0C "P2DPYR,Plane 2 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P2DPY ,Plane 2 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P2DSA0R,Plane 2 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P2DSA0 ,Plane 2 Display Domain Start Address 0"
|
|
line.long 0x04 "P2DSA1R,Plane 2 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P2DSA1 ,Plane 2 Display Domain Start Address 1"
|
|
line.long 0x08 "P2DSA2R,Plane 2 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P2DSA2 ,Plane 2 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P2DSA0R,Plane 2 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P2DSA0 ,Plane 2 Display Domain Start Address 0"
|
|
line.long 0x04 "P2DSA1R,Plane 2 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P2DSA1 ,Plane 2 Display Domain Start Address 1"
|
|
line.long 0x08 "P2DSA2R,Plane 2 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P2DSA2 ,Plane 2 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P2SPXR,Plane 2 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P2SPX ,Plane 2 Starting Position X"
|
|
line.long 0x04 "P2SPYR,Plane 2 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P2SPY ,Plane 2 Starting Position Y"
|
|
line.long 0x08 "P2WASPR,Plane 2 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P2WASPY ,Plane 2 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P2WAMWR,Plane 2 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P2WAMWY ,Plane 2 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P2BTR,Plane 2 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P2BTA ,Plane 2 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P2BTB ,Plane 2 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P2MLR,Plane 2 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P2MLY ,Plane 2 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P2SWAPR,Plane 2 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P2DIGN ,Plane 2 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P2SPQW ,Plane 2 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P2SPLW ,Plane 2 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P2SPWD ,Plane 2 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P2SPBY ,Plane 2 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P2DDCR4,Plane 2 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P2DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P2SDFS ,Plane 2 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P2EDF ,Plane 2 Extensional Data Format" "P2DDF bit of P2MR/P2LRGB1 or P2LRGB0 bit in P2DDCR/P2DIVU or P2DIVY bit in P2DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 3"
|
|
base (ad:0xFFF80000+0xA300)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P3MR,Plane 3 Mode Register"
|
|
bitfld.long 0x00 16. " P3WAE ,Plane 3 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P3DC ,Plane 3 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P3BM ,Plane 3 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P3MWR,Plane 3 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P3MWX ,Plane 3 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P3DSXR,Plane 3 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P3DSX ,Plane 3 Display Size X"
|
|
line.long 0x04 "P3DSYR,Plane 3 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P3DSY ,Plane 3 Display Size Y"
|
|
line.long 0x08 "P3DPXR,Plane 3 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P3DPX ,Plane 3 Display Position X"
|
|
line.long 0x0C "P3DPYR,Plane 3 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P3DPY ,Plane 3 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P3DSXR,Plane 3 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P3DSX ,Plane 3 Display Size X"
|
|
line.long 0x04 "P3DSYR,Plane 3 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P3DSY ,Plane 3 Display Size Y"
|
|
line.long 0x08 "P3DPXR,Plane 3 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P3DPX ,Plane 3 Display Position X"
|
|
line.long 0x0C "P3DPYR,Plane 3 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P3DPY ,Plane 3 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P3DSA0R,Plane 3 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P3DSA0 ,Plane 3 Display Domain Start Address 0"
|
|
line.long 0x04 "P3DSA1R,Plane 3 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P3DSA1 ,Plane 3 Display Domain Start Address 1"
|
|
line.long 0x08 "P3DSA2R,Plane 3 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P3DSA2 ,Plane 3 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P3DSA0R,Plane 3 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P3DSA0 ,Plane 3 Display Domain Start Address 0"
|
|
line.long 0x04 "P3DSA1R,Plane 3 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P3DSA1 ,Plane 3 Display Domain Start Address 1"
|
|
line.long 0x08 "P3DSA2R,Plane 3 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P3DSA2 ,Plane 3 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P3SPXR,Plane 3 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P3SPX ,Plane 3 Starting Position X"
|
|
line.long 0x04 "P3SPYR,Plane 3 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P3SPY ,Plane 3 Starting Position Y"
|
|
line.long 0x08 "P3WASPR,Plane 3 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P3WASPY ,Plane 3 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P3WAMWR,Plane 3 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P3WAMWY ,Plane 3 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P3BTR,Plane 3 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P3BTA ,Plane 3 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P3BTB ,Plane 3 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P3MLR,Plane 3 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P3MLY ,Plane 3 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P3SWAPR,Plane 3 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P3DIGN ,Plane 3 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P3SPQW ,Plane 3 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P3SPLW ,Plane 3 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P3SPWD ,Plane 3 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P3SPBY ,Plane 3 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P3DDCR4,Plane 3 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P3DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P3SDFS ,Plane 3 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P3EDF ,Plane 3 Extensional Data Format" "P3DDF bit of P3MR/P3LRGB1 or P3LRGB0 bit in P3DDCR/P3DIVU or P3DIVY bit in P3DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 4"
|
|
base (ad:0xFFF80000+0xA400)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P4MR,Plane 4 Mode Register"
|
|
bitfld.long 0x00 16. " P4WAE ,Plane 4 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P4DC ,Plane 4 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P4BM ,Plane 4 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P4MWR,Plane 4 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P4MWX ,Plane 4 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P4DSXR,Plane 4 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P4DSX ,Plane 4 Display Size X"
|
|
line.long 0x04 "P4DSYR,Plane 4 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P4DSY ,Plane 4 Display Size Y"
|
|
line.long 0x08 "P4DPXR,Plane 4 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P4DPX ,Plane 4 Display Position X"
|
|
line.long 0x0C "P4DPYR,Plane 4 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P4DPY ,Plane 4 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P4DSXR,Plane 4 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P4DSX ,Plane 4 Display Size X"
|
|
line.long 0x04 "P4DSYR,Plane 4 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P4DSY ,Plane 4 Display Size Y"
|
|
line.long 0x08 "P4DPXR,Plane 4 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P4DPX ,Plane 4 Display Position X"
|
|
line.long 0x0C "P4DPYR,Plane 4 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P4DPY ,Plane 4 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P4DSA0R,Plane 4 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P4DSA0 ,Plane 4 Display Domain Start Address 0"
|
|
line.long 0x04 "P4DSA1R,Plane 4 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P4DSA1 ,Plane 4 Display Domain Start Address 1"
|
|
line.long 0x08 "P4DSA2R,Plane 4 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P4DSA2 ,Plane 4 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P4DSA0R,Plane 4 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P4DSA0 ,Plane 4 Display Domain Start Address 0"
|
|
line.long 0x04 "P4DSA1R,Plane 4 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P4DSA1 ,Plane 4 Display Domain Start Address 1"
|
|
line.long 0x08 "P4DSA2R,Plane 4 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P4DSA2 ,Plane 4 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P4SPXR,Plane 4 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P4SPX ,Plane 4 Starting Position X"
|
|
line.long 0x04 "P4SPYR,Plane 4 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P4SPY ,Plane 4 Starting Position Y"
|
|
line.long 0x08 "P4WASPR,Plane 4 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P4WASPY ,Plane 4 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P4WAMWR,Plane 4 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P4WAMWY ,Plane 4 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P4BTR,Plane 4 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P4BTA ,Plane 4 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P4BTB ,Plane 4 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P4MLR,Plane 4 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P4MLY ,Plane 4 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P4SWAPR,Plane 4 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P4DIGN ,Plane 4 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P4SPQW ,Plane 4 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P4SPLW ,Plane 4 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P4SPWD ,Plane 4 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P4SPBY ,Plane 4 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P4DDCR4,Plane 4 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P4DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P4SDFS ,Plane 4 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P4EDF ,Plane 4 Extensional Data Format" "P4DDF bit of P4MR/P4LRGB1 or P4LRGB0 bit in P4DDCR/P4DIVU or P4DIVY bit in P4DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 5"
|
|
base (ad:0xFFF80000+0xA500)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P5MR,Plane 5 Mode Register"
|
|
bitfld.long 0x00 16. " P5WAE ,Plane 5 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P5DC ,Plane 5 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P5BM ,Plane 5 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P5MWR,Plane 5 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P5MWX ,Plane 5 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P5DSXR,Plane 5 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P5DSX ,Plane 5 Display Size X"
|
|
line.long 0x04 "P5DSYR,Plane 5 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P5DSY ,Plane 5 Display Size Y"
|
|
line.long 0x08 "P5DPXR,Plane 5 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P5DPX ,Plane 5 Display Position X"
|
|
line.long 0x0C "P5DPYR,Plane 5 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P5DPY ,Plane 5 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P5DSXR,Plane 5 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P5DSX ,Plane 5 Display Size X"
|
|
line.long 0x04 "P5DSYR,Plane 5 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P5DSY ,Plane 5 Display Size Y"
|
|
line.long 0x08 "P5DPXR,Plane 5 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P5DPX ,Plane 5 Display Position X"
|
|
line.long 0x0C "P5DPYR,Plane 5 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P5DPY ,Plane 5 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P5DSA0R,Plane 5 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P5DSA0 ,Plane 5 Display Domain Start Address 0"
|
|
line.long 0x04 "P5DSA1R,Plane 5 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P5DSA1 ,Plane 5 Display Domain Start Address 1"
|
|
line.long 0x08 "P5DSA2R,Plane 5 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P5DSA2 ,Plane 5 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P5DSA0R,Plane 5 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P5DSA0 ,Plane 5 Display Domain Start Address 0"
|
|
line.long 0x04 "P5DSA1R,Plane 5 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P5DSA1 ,Plane 5 Display Domain Start Address 1"
|
|
line.long 0x08 "P5DSA2R,Plane 5 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P5DSA2 ,Plane 5 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P5SPXR,Plane 5 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P5SPX ,Plane 5 Starting Position X"
|
|
line.long 0x04 "P5SPYR,Plane 5 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P5SPY ,Plane 5 Starting Position Y"
|
|
line.long 0x08 "P5WASPR,Plane 5 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P5WASPY ,Plane 5 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P5WAMWR,Plane 5 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P5WAMWY ,Plane 5 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P5BTR,Plane 5 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P5BTA ,Plane 5 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P5BTB ,Plane 5 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P5MLR,Plane 5 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P5MLY ,Plane 5 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P5SWAPR,Plane 5 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P5DIGN ,Plane 5 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P5SPQW ,Plane 5 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P5SPLW ,Plane 5 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P5SPWD ,Plane 5 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P5SPBY ,Plane 5 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P5DDCR4,Plane 5 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P5DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P5SDFS ,Plane 5 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P5EDF ,Plane 5 Extensional Data Format" "P5DDF bit of P5MR/P5LRGB1 or P5LRGB0 bit in P5DDCR/P5DIVU or P5DIVY bit in P5DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 6"
|
|
base (ad:0xFFF80000+0xA600)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P6MR,Plane 6 Mode Register"
|
|
bitfld.long 0x00 16. " P6WAE ,Plane 6 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P6DC ,Plane 6 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P6BM ,Plane 6 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P6MWR,Plane 6 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P6MWX ,Plane 6 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P6DSXR,Plane 6 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P6DSX ,Plane 6 Display Size X"
|
|
line.long 0x04 "P6DSYR,Plane 6 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P6DSY ,Plane 6 Display Size Y"
|
|
line.long 0x08 "P6DPXR,Plane 6 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P6DPX ,Plane 6 Display Position X"
|
|
line.long 0x0C "P6DPYR,Plane 6 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P6DPY ,Plane 6 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P6DSXR,Plane 6 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P6DSX ,Plane 6 Display Size X"
|
|
line.long 0x04 "P6DSYR,Plane 6 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P6DSY ,Plane 6 Display Size Y"
|
|
line.long 0x08 "P6DPXR,Plane 6 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P6DPX ,Plane 6 Display Position X"
|
|
line.long 0x0C "P6DPYR,Plane 6 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P6DPY ,Plane 6 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P6DSA0R,Plane 6 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P6DSA0 ,Plane 6 Display Domain Start Address 0"
|
|
line.long 0x04 "P6DSA1R,Plane 6 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P6DSA1 ,Plane 6 Display Domain Start Address 1"
|
|
line.long 0x08 "P6DSA2R,Plane 6 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P6DSA2 ,Plane 6 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P6DSA0R,Plane 6 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P6DSA0 ,Plane 6 Display Domain Start Address 0"
|
|
line.long 0x04 "P6DSA1R,Plane 6 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P6DSA1 ,Plane 6 Display Domain Start Address 1"
|
|
line.long 0x08 "P6DSA2R,Plane 6 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P6DSA2 ,Plane 6 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P6SPXR,Plane 6 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P6SPX ,Plane 6 Starting Position X"
|
|
line.long 0x04 "P6SPYR,Plane 6 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P6SPY ,Plane 6 Starting Position Y"
|
|
line.long 0x08 "P6WASPR,Plane 6 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P6WASPY ,Plane 6 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P6WAMWR,Plane 6 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P6WAMWY ,Plane 6 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P6BTR,Plane 6 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P6BTA ,Plane 6 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P6BTB ,Plane 6 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P6MLR,Plane 6 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P6MLY ,Plane 6 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P6SWAPR,Plane 6 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P6DIGN ,Plane 6 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P6SPQW ,Plane 6 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P6SPLW ,Plane 6 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P6SPWD ,Plane 6 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P6SPBY ,Plane 6 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P6DDCR4,Plane 6 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P6DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P6SDFS ,Plane 6 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P6EDF ,Plane 6 Extensional Data Format" "P6DDF bit of P6MR/P6LRGB1 or P6LRGB0 bit in P6DDCR/P6DIVU or P6DIVY bit in P6DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 7"
|
|
base (ad:0xFFF80000+0xA700)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P7MR,Plane 7 Mode Register"
|
|
bitfld.long 0x00 16. " P7WAE ,Plane 7 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P7DC ,Plane 7 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P7BM ,Plane 7 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P7MWR,Plane 7 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P7MWX ,Plane 7 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P7DSXR,Plane 7 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P7DSX ,Plane 7 Display Size X"
|
|
line.long 0x04 "P7DSYR,Plane 7 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P7DSY ,Plane 7 Display Size Y"
|
|
line.long 0x08 "P7DPXR,Plane 7 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P7DPX ,Plane 7 Display Position X"
|
|
line.long 0x0C "P7DPYR,Plane 7 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P7DPY ,Plane 7 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P7DSXR,Plane 7 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P7DSX ,Plane 7 Display Size X"
|
|
line.long 0x04 "P7DSYR,Plane 7 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P7DSY ,Plane 7 Display Size Y"
|
|
line.long 0x08 "P7DPXR,Plane 7 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P7DPX ,Plane 7 Display Position X"
|
|
line.long 0x0C "P7DPYR,Plane 7 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P7DPY ,Plane 7 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P7DSA0R,Plane 7 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P7DSA0 ,Plane 7 Display Domain Start Address 0"
|
|
line.long 0x04 "P7DSA1R,Plane 7 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P7DSA1 ,Plane 7 Display Domain Start Address 1"
|
|
line.long 0x08 "P7DSA2R,Plane 7 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P7DSA2 ,Plane 7 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P7DSA0R,Plane 7 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P7DSA0 ,Plane 7 Display Domain Start Address 0"
|
|
line.long 0x04 "P7DSA1R,Plane 7 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P7DSA1 ,Plane 7 Display Domain Start Address 1"
|
|
line.long 0x08 "P7DSA2R,Plane 7 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P7DSA2 ,Plane 7 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P7SPXR,Plane 7 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P7SPX ,Plane 7 Starting Position X"
|
|
line.long 0x04 "P7SPYR,Plane 7 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P7SPY ,Plane 7 Starting Position Y"
|
|
line.long 0x08 "P7WASPR,Plane 7 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P7WASPY ,Plane 7 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P7WAMWR,Plane 7 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P7WAMWY ,Plane 7 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P7BTR,Plane 7 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P7BTA ,Plane 7 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P7BTB ,Plane 7 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P7MLR,Plane 7 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P7MLY ,Plane 7 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P7SWAPR,Plane 7 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P7DIGN ,Plane 7 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P7SPQW ,Plane 7 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P7SPLW ,Plane 7 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P7SPWD ,Plane 7 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P7SPBY ,Plane 7 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P7DDCR4,Plane 7 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P7DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P7SDFS ,Plane 7 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P7EDF ,Plane 7 Extensional Data Format" "P7DDF bit of P7MR/P7LRGB1 or P7LRGB0 bit in P7DDCR/P7DIVU or P7DIVY bit in P7DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree "Alpha-Ratio Plane 8"
|
|
base (ad:0xFFF80000+0xA800)
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P8MR,Plane 8 Mode Register"
|
|
bitfld.long 0x00 16. " P8WAE ,Plane 8 Wrap Around Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " P8DC ,Plane 8 Display Area Change" "No change,Change"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " P8BM ,Plane 8 Buffer Mode" "Manual display change,Auto rendering,Auto display change,Video capture"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P8MWR,Plane 8 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " P8MWX ,Plane 8 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0xE0))&0x01)==0x01)
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P8DSXR,Plane 8 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P8DSX ,Plane 8 Display Size X"
|
|
line.long 0x04 "P8DSYR,Plane 8 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " P8DSY ,Plane 8 Display Size Y"
|
|
line.long 0x08 "P8DPXR,Plane 8 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--11. 1. " P8DPX ,Plane 8 Display Position X"
|
|
line.long 0x0C "P8DPYR,Plane 8 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--10. 1. " P8DPY ,Plane 8 Display Position Y"
|
|
else
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "P8DSXR,Plane 8 Display Size X Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " P8DSX ,Plane 8 Display Size X"
|
|
line.long 0x04 "P8DSYR,Plane 8 Display Size Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " P8DSY ,Plane 8 Display Size Y"
|
|
line.long 0x08 "P8DPXR,Plane 8 Display Position X Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " P8DPX ,Plane 8 Display Position X"
|
|
line.long 0x0C "P8DPYR,Plane 8 Display Position Y Register"
|
|
hexmask.long.word 0x0C 0.--9. 1. " P8DPY ,Plane 8 Display Position Y"
|
|
endif
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P8DSA0R,Plane 8 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " P8DSA0 ,Plane 8 Display Domain Start Address 0"
|
|
line.long 0x04 "P8DSA1R,Plane 8 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " P8DSA1 ,Plane 8 Display Domain Start Address 1"
|
|
line.long 0x08 "P8DSA2R,Plane 8 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " P8DSA2 ,Plane 8 Display Domain Start Address 2"
|
|
else
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "P8DSA0R,Plane 8 Display Domain Start Address 0 Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " P8DSA0 ,Plane 8 Display Domain Start Address 0"
|
|
line.long 0x04 "P8DSA1R,Plane 8 Display Domain Start Address 1 Register"
|
|
hexmask.long 0x04 4.--28. 0x10 " P8DSA1 ,Plane 8 Display Domain Start Address 1"
|
|
line.long 0x08 "P8DSA2R,Plane 8 Display Domain Start Address 2 Register"
|
|
hexmask.long 0x08 4.--28. 0x10 " P8DSA2 ,Plane 8 Display Domain Start Address 2"
|
|
endif
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "P8SPXR,Plane 8 Starting Position X Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " P8SPX ,Plane 8 Starting Position X"
|
|
line.long 0x04 "P8SPYR,Plane 8 Starting Position Y Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " P8SPY ,Plane 8 Starting Position Y"
|
|
line.long 0x08 "P8WASPR,Plane 8 Wrap Around Starting Position Register"
|
|
hexmask.long.word 0x08 4.--13. 0x10 " P8WASPY ,Plane 8 Wrap Around Starting Position Y"
|
|
line.long 0x0C "P8WAMWR,Plane 8 Wrap Around Memory Width Register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " P8WAMWY ,Plane 8 Wrap Around Memory Width Y"
|
|
line.long 0x10 "P8BTR,Plane 8 Blinking Cycle Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " P8BTA ,Plane 8 Blinking Cycle A"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--7. 1. " P8BTB ,Plane 8 Blinking Cycle B"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "P8MLR,Plane 8 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " P8MLY ,Plane 8 Memory Length Y"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "P8SWAPR,Plane 8 SWAP Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CODE ,PnSWAPR Enabling Code [0x7775]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " P8DIGN ,Plane 8 Display Data Format Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P8SPQW ,Plane 8 Quadword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " P8SPLW ,Plane 8 Longword Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P8SPWD ,Plane 8 Word Swap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " P8SPBY ,Plane 8 Byte Swap Enable" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "P8DDCR4,Plane 8 Display Data Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " Code ,P8DDCR4 Enabling Code [0x7766]"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " P8SDFS ,Plane 8 Superimpose Data Format Select" "RGB composite,RGB composite,RGB composite,RGB composite,,YC composite,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " P8EDF ,Plane 8 Extensional Data Format" "P8DDF bit of P8MR/P8LRGB1 or P8LRGB0 bit in P8DDCR/P8DIVU or P8DIVY bit in P8DDCR2,ARGB8888,RGB888,RGB666,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
base ad:0xFFF80000
|
|
tree "Display Capture Registers"
|
|
tree "Display Capture 1 Registers"
|
|
group.long 0xC104++0x03
|
|
line.long 0x00 "DC1MWR,Display Capture 1 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " DC1MWX ,Display Capture 1 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long (0xC104+0x1c)++0x03
|
|
line.long 0x00 "DC1SAR,Display Capture 1 Area Start Address Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DC1SA ,Display Capture 1 Area Start Address"
|
|
else
|
|
group.long (0xC104+0x1c)++0x03
|
|
line.long 0x00 "DC1SAR,Display Capture 1 Area Start Address Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " DC1SA ,Display Capture 1 Area Start Address"
|
|
endif
|
|
group.long (0xC104+0x4c)++0x03
|
|
line.long 0x00 "DC1MLR,Display Capture 1 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " DC1MLY ,Display Capture 1 Memory Length Y"
|
|
tree.end
|
|
tree "Display Capture 2 Registers"
|
|
group.long 0xC204++0x03
|
|
line.long 0x00 "DC2MWR,Display Capture 2 Memory Width Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " DC2MWX ,Display Capture 2 Memory Width X"
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long (0xC204+0x1c)++0x03
|
|
line.long 0x00 "DC2SAR,Display Capture 2 Area Start Address Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DC2SA ,Display Capture 2 Area Start Address"
|
|
else
|
|
group.long (0xC204+0x1c)++0x03
|
|
line.long 0x00 "DC2SAR,Display Capture 2 Area Start Address Register"
|
|
hexmask.long 0x00 4.--28. 0x10 " DC2SA ,Display Capture 2 Area Start Address"
|
|
endif
|
|
group.long (0xC204+0x4c)++0x03
|
|
line.long 0x00 "DC2MLR,Display Capture 2 Memory Length Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 1. " DC2MLY ,Display Capture 2 Memory Length Y"
|
|
tree.end
|
|
tree.end
|
|
tree "Color Palette 1 Registers"
|
|
width 10.
|
|
group.long 0x1000++0x3ff
|
|
line.long 0x0 "CP1_0R,Color Palette 1 Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " CP1_0A ,Color Palette 1_0 Blend Ratio"
|
|
hexmask.long.byte 0x0 18.--23. 1. " CP1_0R ,Color Palette 1_0 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x0 10.--15. 1. " CP1_0G ,Color Palette 1_0 Green"
|
|
hexmask.long.byte 0x0 2.--7. 1. " CP1_0B ,Color Palette 1_0 Blue"
|
|
line.long 0x4 "CP1_1R,Color Palette 1 Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " CP1_1A ,Color Palette 1_1 Blend Ratio"
|
|
hexmask.long.byte 0x4 18.--23. 1. " CP1_1R ,Color Palette 1_1 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4 10.--15. 1. " CP1_1G ,Color Palette 1_1 Green"
|
|
hexmask.long.byte 0x4 2.--7. 1. " CP1_1B ,Color Palette 1_1 Blue"
|
|
line.long 0x8 "CP1_2R,Color Palette 1 Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " CP1_2A ,Color Palette 1_2 Blend Ratio"
|
|
hexmask.long.byte 0x8 18.--23. 1. " CP1_2R ,Color Palette 1_2 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8 10.--15. 1. " CP1_2G ,Color Palette 1_2 Green"
|
|
hexmask.long.byte 0x8 2.--7. 1. " CP1_2B ,Color Palette 1_2 Blue"
|
|
line.long 0xC "CP1_3R,Color Palette 1 Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " CP1_3A ,Color Palette 1_3 Blend Ratio"
|
|
hexmask.long.byte 0xC 18.--23. 1. " CP1_3R ,Color Palette 1_3 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC 10.--15. 1. " CP1_3G ,Color Palette 1_3 Green"
|
|
hexmask.long.byte 0xC 2.--7. 1. " CP1_3B ,Color Palette 1_3 Blue"
|
|
line.long 0x10 "CP1_4R,Color Palette 1 Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. " CP1_4A ,Color Palette 1_4 Blend Ratio"
|
|
hexmask.long.byte 0x10 18.--23. 1. " CP1_4R ,Color Palette 1_4 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10 10.--15. 1. " CP1_4G ,Color Palette 1_4 Green"
|
|
hexmask.long.byte 0x10 2.--7. 1. " CP1_4B ,Color Palette 1_4 Blue"
|
|
line.long 0x14 "CP1_5R,Color Palette 1 Register 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. " CP1_5A ,Color Palette 1_5 Blend Ratio"
|
|
hexmask.long.byte 0x14 18.--23. 1. " CP1_5R ,Color Palette 1_5 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14 10.--15. 1. " CP1_5G ,Color Palette 1_5 Green"
|
|
hexmask.long.byte 0x14 2.--7. 1. " CP1_5B ,Color Palette 1_5 Blue"
|
|
line.long 0x18 "CP1_6R,Color Palette 1 Register 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. " CP1_6A ,Color Palette 1_6 Blend Ratio"
|
|
hexmask.long.byte 0x18 18.--23. 1. " CP1_6R ,Color Palette 1_6 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18 10.--15. 1. " CP1_6G ,Color Palette 1_6 Green"
|
|
hexmask.long.byte 0x18 2.--7. 1. " CP1_6B ,Color Palette 1_6 Blue"
|
|
line.long 0x1C "CP1_7R,Color Palette 1 Register 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " CP1_7A ,Color Palette 1_7 Blend Ratio"
|
|
hexmask.long.byte 0x1C 18.--23. 1. " CP1_7R ,Color Palette 1_7 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 10.--15. 1. " CP1_7G ,Color Palette 1_7 Green"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " CP1_7B ,Color Palette 1_7 Blue"
|
|
line.long 0x20 "CP1_8R,Color Palette 1 Register 8"
|
|
hexmask.long.byte 0x20 24.--31. 1. " CP1_8A ,Color Palette 1_8 Blend Ratio"
|
|
hexmask.long.byte 0x20 18.--23. 1. " CP1_8R ,Color Palette 1_8 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20 10.--15. 1. " CP1_8G ,Color Palette 1_8 Green"
|
|
hexmask.long.byte 0x20 2.--7. 1. " CP1_8B ,Color Palette 1_8 Blue"
|
|
line.long 0x24 "CP1_9R,Color Palette 1 Register 9"
|
|
hexmask.long.byte 0x24 24.--31. 1. " CP1_9A ,Color Palette 1_9 Blend Ratio"
|
|
hexmask.long.byte 0x24 18.--23. 1. " CP1_9R ,Color Palette 1_9 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24 10.--15. 1. " CP1_9G ,Color Palette 1_9 Green"
|
|
hexmask.long.byte 0x24 2.--7. 1. " CP1_9B ,Color Palette 1_9 Blue"
|
|
line.long 0x28 "CP1_10R,Color Palette 1 Register 10"
|
|
hexmask.long.byte 0x28 24.--31. 1. " CP1_10A ,Color Palette 1_10 Blend Ratio"
|
|
hexmask.long.byte 0x28 18.--23. 1. " CP1_10R ,Color Palette 1_10 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28 10.--15. 1. " CP1_10G ,Color Palette 1_10 Green"
|
|
hexmask.long.byte 0x28 2.--7. 1. " CP1_10B ,Color Palette 1_10 Blue"
|
|
line.long 0x2C "CP1_11R,Color Palette 1 Register 11"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " CP1_11A ,Color Palette 1_11 Blend Ratio"
|
|
hexmask.long.byte 0x2C 18.--23. 1. " CP1_11R ,Color Palette 1_11 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 10.--15. 1. " CP1_11G ,Color Palette 1_11 Green"
|
|
hexmask.long.byte 0x2C 2.--7. 1. " CP1_11B ,Color Palette 1_11 Blue"
|
|
line.long 0x30 "CP1_12R,Color Palette 1 Register 12"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CP1_12A ,Color Palette 1_12 Blend Ratio"
|
|
hexmask.long.byte 0x30 18.--23. 1. " CP1_12R ,Color Palette 1_12 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30 10.--15. 1. " CP1_12G ,Color Palette 1_12 Green"
|
|
hexmask.long.byte 0x30 2.--7. 1. " CP1_12B ,Color Palette 1_12 Blue"
|
|
line.long 0x34 "CP1_13R,Color Palette 1 Register 13"
|
|
hexmask.long.byte 0x34 24.--31. 1. " CP1_13A ,Color Palette 1_13 Blend Ratio"
|
|
hexmask.long.byte 0x34 18.--23. 1. " CP1_13R ,Color Palette 1_13 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34 10.--15. 1. " CP1_13G ,Color Palette 1_13 Green"
|
|
hexmask.long.byte 0x34 2.--7. 1. " CP1_13B ,Color Palette 1_13 Blue"
|
|
line.long 0x38 "CP1_14R,Color Palette 1 Register 14"
|
|
hexmask.long.byte 0x38 24.--31. 1. " CP1_14A ,Color Palette 1_14 Blend Ratio"
|
|
hexmask.long.byte 0x38 18.--23. 1. " CP1_14R ,Color Palette 1_14 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38 10.--15. 1. " CP1_14G ,Color Palette 1_14 Green"
|
|
hexmask.long.byte 0x38 2.--7. 1. " CP1_14B ,Color Palette 1_14 Blue"
|
|
line.long 0x3C "CP1_15R,Color Palette 1 Register 15"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " CP1_15A ,Color Palette 1_15 Blend Ratio"
|
|
hexmask.long.byte 0x3C 18.--23. 1. " CP1_15R ,Color Palette 1_15 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C 10.--15. 1. " CP1_15G ,Color Palette 1_15 Green"
|
|
hexmask.long.byte 0x3C 2.--7. 1. " CP1_15B ,Color Palette 1_15 Blue"
|
|
line.long 0x40 "CP1_16R,Color Palette 1 Register 16"
|
|
hexmask.long.byte 0x40 24.--31. 1. " CP1_16A ,Color Palette 1_16 Blend Ratio"
|
|
hexmask.long.byte 0x40 18.--23. 1. " CP1_16R ,Color Palette 1_16 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x40 10.--15. 1. " CP1_16G ,Color Palette 1_16 Green"
|
|
hexmask.long.byte 0x40 2.--7. 1. " CP1_16B ,Color Palette 1_16 Blue"
|
|
line.long 0x44 "CP1_17R,Color Palette 1 Register 17"
|
|
hexmask.long.byte 0x44 24.--31. 1. " CP1_17A ,Color Palette 1_17 Blend Ratio"
|
|
hexmask.long.byte 0x44 18.--23. 1. " CP1_17R ,Color Palette 1_17 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x44 10.--15. 1. " CP1_17G ,Color Palette 1_17 Green"
|
|
hexmask.long.byte 0x44 2.--7. 1. " CP1_17B ,Color Palette 1_17 Blue"
|
|
line.long 0x48 "CP1_18R,Color Palette 1 Register 18"
|
|
hexmask.long.byte 0x48 24.--31. 1. " CP1_18A ,Color Palette 1_18 Blend Ratio"
|
|
hexmask.long.byte 0x48 18.--23. 1. " CP1_18R ,Color Palette 1_18 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x48 10.--15. 1. " CP1_18G ,Color Palette 1_18 Green"
|
|
hexmask.long.byte 0x48 2.--7. 1. " CP1_18B ,Color Palette 1_18 Blue"
|
|
line.long 0x4C "CP1_19R,Color Palette 1 Register 19"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " CP1_19A ,Color Palette 1_19 Blend Ratio"
|
|
hexmask.long.byte 0x4C 18.--23. 1. " CP1_19R ,Color Palette 1_19 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4C 10.--15. 1. " CP1_19G ,Color Palette 1_19 Green"
|
|
hexmask.long.byte 0x4C 2.--7. 1. " CP1_19B ,Color Palette 1_19 Blue"
|
|
line.long 0x50 "CP1_20R,Color Palette 1 Register 20"
|
|
hexmask.long.byte 0x50 24.--31. 1. " CP1_20A ,Color Palette 1_20 Blend Ratio"
|
|
hexmask.long.byte 0x50 18.--23. 1. " CP1_20R ,Color Palette 1_20 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x50 10.--15. 1. " CP1_20G ,Color Palette 1_20 Green"
|
|
hexmask.long.byte 0x50 2.--7. 1. " CP1_20B ,Color Palette 1_20 Blue"
|
|
line.long 0x54 "CP1_21R,Color Palette 1 Register 21"
|
|
hexmask.long.byte 0x54 24.--31. 1. " CP1_21A ,Color Palette 1_21 Blend Ratio"
|
|
hexmask.long.byte 0x54 18.--23. 1. " CP1_21R ,Color Palette 1_21 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x54 10.--15. 1. " CP1_21G ,Color Palette 1_21 Green"
|
|
hexmask.long.byte 0x54 2.--7. 1. " CP1_21B ,Color Palette 1_21 Blue"
|
|
line.long 0x58 "CP1_22R,Color Palette 1 Register 22"
|
|
hexmask.long.byte 0x58 24.--31. 1. " CP1_22A ,Color Palette 1_22 Blend Ratio"
|
|
hexmask.long.byte 0x58 18.--23. 1. " CP1_22R ,Color Palette 1_22 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x58 10.--15. 1. " CP1_22G ,Color Palette 1_22 Green"
|
|
hexmask.long.byte 0x58 2.--7. 1. " CP1_22B ,Color Palette 1_22 Blue"
|
|
line.long 0x5C "CP1_23R,Color Palette 1 Register 23"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " CP1_23A ,Color Palette 1_23 Blend Ratio"
|
|
hexmask.long.byte 0x5C 18.--23. 1. " CP1_23R ,Color Palette 1_23 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 10.--15. 1. " CP1_23G ,Color Palette 1_23 Green"
|
|
hexmask.long.byte 0x5C 2.--7. 1. " CP1_23B ,Color Palette 1_23 Blue"
|
|
line.long 0x60 "CP1_24R,Color Palette 1 Register 24"
|
|
hexmask.long.byte 0x60 24.--31. 1. " CP1_24A ,Color Palette 1_24 Blend Ratio"
|
|
hexmask.long.byte 0x60 18.--23. 1. " CP1_24R ,Color Palette 1_24 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x60 10.--15. 1. " CP1_24G ,Color Palette 1_24 Green"
|
|
hexmask.long.byte 0x60 2.--7. 1. " CP1_24B ,Color Palette 1_24 Blue"
|
|
line.long 0x64 "CP1_25R,Color Palette 1 Register 25"
|
|
hexmask.long.byte 0x64 24.--31. 1. " CP1_25A ,Color Palette 1_25 Blend Ratio"
|
|
hexmask.long.byte 0x64 18.--23. 1. " CP1_25R ,Color Palette 1_25 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x64 10.--15. 1. " CP1_25G ,Color Palette 1_25 Green"
|
|
hexmask.long.byte 0x64 2.--7. 1. " CP1_25B ,Color Palette 1_25 Blue"
|
|
line.long 0x68 "CP1_26R,Color Palette 1 Register 26"
|
|
hexmask.long.byte 0x68 24.--31. 1. " CP1_26A ,Color Palette 1_26 Blend Ratio"
|
|
hexmask.long.byte 0x68 18.--23. 1. " CP1_26R ,Color Palette 1_26 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x68 10.--15. 1. " CP1_26G ,Color Palette 1_26 Green"
|
|
hexmask.long.byte 0x68 2.--7. 1. " CP1_26B ,Color Palette 1_26 Blue"
|
|
line.long 0x6C "CP1_27R,Color Palette 1 Register 27"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " CP1_27A ,Color Palette 1_27 Blend Ratio"
|
|
hexmask.long.byte 0x6C 18.--23. 1. " CP1_27R ,Color Palette 1_27 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x6C 10.--15. 1. " CP1_27G ,Color Palette 1_27 Green"
|
|
hexmask.long.byte 0x6C 2.--7. 1. " CP1_27B ,Color Palette 1_27 Blue"
|
|
line.long 0x70 "CP1_28R,Color Palette 1 Register 28"
|
|
hexmask.long.byte 0x70 24.--31. 1. " CP1_28A ,Color Palette 1_28 Blend Ratio"
|
|
hexmask.long.byte 0x70 18.--23. 1. " CP1_28R ,Color Palette 1_28 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x70 10.--15. 1. " CP1_28G ,Color Palette 1_28 Green"
|
|
hexmask.long.byte 0x70 2.--7. 1. " CP1_28B ,Color Palette 1_28 Blue"
|
|
line.long 0x74 "CP1_29R,Color Palette 1 Register 29"
|
|
hexmask.long.byte 0x74 24.--31. 1. " CP1_29A ,Color Palette 1_29 Blend Ratio"
|
|
hexmask.long.byte 0x74 18.--23. 1. " CP1_29R ,Color Palette 1_29 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x74 10.--15. 1. " CP1_29G ,Color Palette 1_29 Green"
|
|
hexmask.long.byte 0x74 2.--7. 1. " CP1_29B ,Color Palette 1_29 Blue"
|
|
line.long 0x78 "CP1_30R,Color Palette 1 Register 30"
|
|
hexmask.long.byte 0x78 24.--31. 1. " CP1_30A ,Color Palette 1_30 Blend Ratio"
|
|
hexmask.long.byte 0x78 18.--23. 1. " CP1_30R ,Color Palette 1_30 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x78 10.--15. 1. " CP1_30G ,Color Palette 1_30 Green"
|
|
hexmask.long.byte 0x78 2.--7. 1. " CP1_30B ,Color Palette 1_30 Blue"
|
|
line.long 0x7C "CP1_31R,Color Palette 1 Register 31"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " CP1_31A ,Color Palette 1_31 Blend Ratio"
|
|
hexmask.long.byte 0x7C 18.--23. 1. " CP1_31R ,Color Palette 1_31 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x7C 10.--15. 1. " CP1_31G ,Color Palette 1_31 Green"
|
|
hexmask.long.byte 0x7C 2.--7. 1. " CP1_31B ,Color Palette 1_31 Blue"
|
|
line.long 0x80 "CP1_32R,Color Palette 1 Register 32"
|
|
hexmask.long.byte 0x80 24.--31. 1. " CP1_32A ,Color Palette 1_32 Blend Ratio"
|
|
hexmask.long.byte 0x80 18.--23. 1. " CP1_32R ,Color Palette 1_32 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x80 10.--15. 1. " CP1_32G ,Color Palette 1_32 Green"
|
|
hexmask.long.byte 0x80 2.--7. 1. " CP1_32B ,Color Palette 1_32 Blue"
|
|
line.long 0x84 "CP1_33R,Color Palette 1 Register 33"
|
|
hexmask.long.byte 0x84 24.--31. 1. " CP1_33A ,Color Palette 1_33 Blend Ratio"
|
|
hexmask.long.byte 0x84 18.--23. 1. " CP1_33R ,Color Palette 1_33 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x84 10.--15. 1. " CP1_33G ,Color Palette 1_33 Green"
|
|
hexmask.long.byte 0x84 2.--7. 1. " CP1_33B ,Color Palette 1_33 Blue"
|
|
line.long 0x88 "CP1_34R,Color Palette 1 Register 34"
|
|
hexmask.long.byte 0x88 24.--31. 1. " CP1_34A ,Color Palette 1_34 Blend Ratio"
|
|
hexmask.long.byte 0x88 18.--23. 1. " CP1_34R ,Color Palette 1_34 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x88 10.--15. 1. " CP1_34G ,Color Palette 1_34 Green"
|
|
hexmask.long.byte 0x88 2.--7. 1. " CP1_34B ,Color Palette 1_34 Blue"
|
|
line.long 0x8C "CP1_35R,Color Palette 1 Register 35"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " CP1_35A ,Color Palette 1_35 Blend Ratio"
|
|
hexmask.long.byte 0x8C 18.--23. 1. " CP1_35R ,Color Palette 1_35 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8C 10.--15. 1. " CP1_35G ,Color Palette 1_35 Green"
|
|
hexmask.long.byte 0x8C 2.--7. 1. " CP1_35B ,Color Palette 1_35 Blue"
|
|
line.long 0x90 "CP1_36R,Color Palette 1 Register 36"
|
|
hexmask.long.byte 0x90 24.--31. 1. " CP1_36A ,Color Palette 1_36 Blend Ratio"
|
|
hexmask.long.byte 0x90 18.--23. 1. " CP1_36R ,Color Palette 1_36 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x90 10.--15. 1. " CP1_36G ,Color Palette 1_36 Green"
|
|
hexmask.long.byte 0x90 2.--7. 1. " CP1_36B ,Color Palette 1_36 Blue"
|
|
line.long 0x94 "CP1_37R,Color Palette 1 Register 37"
|
|
hexmask.long.byte 0x94 24.--31. 1. " CP1_37A ,Color Palette 1_37 Blend Ratio"
|
|
hexmask.long.byte 0x94 18.--23. 1. " CP1_37R ,Color Palette 1_37 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x94 10.--15. 1. " CP1_37G ,Color Palette 1_37 Green"
|
|
hexmask.long.byte 0x94 2.--7. 1. " CP1_37B ,Color Palette 1_37 Blue"
|
|
line.long 0x98 "CP1_38R,Color Palette 1 Register 38"
|
|
hexmask.long.byte 0x98 24.--31. 1. " CP1_38A ,Color Palette 1_38 Blend Ratio"
|
|
hexmask.long.byte 0x98 18.--23. 1. " CP1_38R ,Color Palette 1_38 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x98 10.--15. 1. " CP1_38G ,Color Palette 1_38 Green"
|
|
hexmask.long.byte 0x98 2.--7. 1. " CP1_38B ,Color Palette 1_38 Blue"
|
|
line.long 0x9C "CP1_39R,Color Palette 1 Register 39"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " CP1_39A ,Color Palette 1_39 Blend Ratio"
|
|
hexmask.long.byte 0x9C 18.--23. 1. " CP1_39R ,Color Palette 1_39 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x9C 10.--15. 1. " CP1_39G ,Color Palette 1_39 Green"
|
|
hexmask.long.byte 0x9C 2.--7. 1. " CP1_39B ,Color Palette 1_39 Blue"
|
|
line.long 0xA0 "CP1_40R,Color Palette 1 Register 40"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " CP1_40A ,Color Palette 1_40 Blend Ratio"
|
|
hexmask.long.byte 0xA0 18.--23. 1. " CP1_40R ,Color Palette 1_40 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA0 10.--15. 1. " CP1_40G ,Color Palette 1_40 Green"
|
|
hexmask.long.byte 0xA0 2.--7. 1. " CP1_40B ,Color Palette 1_40 Blue"
|
|
line.long 0xA4 "CP1_41R,Color Palette 1 Register 41"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " CP1_41A ,Color Palette 1_41 Blend Ratio"
|
|
hexmask.long.byte 0xA4 18.--23. 1. " CP1_41R ,Color Palette 1_41 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA4 10.--15. 1. " CP1_41G ,Color Palette 1_41 Green"
|
|
hexmask.long.byte 0xA4 2.--7. 1. " CP1_41B ,Color Palette 1_41 Blue"
|
|
line.long 0xA8 "CP1_42R,Color Palette 1 Register 42"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " CP1_42A ,Color Palette 1_42 Blend Ratio"
|
|
hexmask.long.byte 0xA8 18.--23. 1. " CP1_42R ,Color Palette 1_42 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA8 10.--15. 1. " CP1_42G ,Color Palette 1_42 Green"
|
|
hexmask.long.byte 0xA8 2.--7. 1. " CP1_42B ,Color Palette 1_42 Blue"
|
|
line.long 0xAC "CP1_43R,Color Palette 1 Register 43"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " CP1_43A ,Color Palette 1_43 Blend Ratio"
|
|
hexmask.long.byte 0xAC 18.--23. 1. " CP1_43R ,Color Palette 1_43 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xAC 10.--15. 1. " CP1_43G ,Color Palette 1_43 Green"
|
|
hexmask.long.byte 0xAC 2.--7. 1. " CP1_43B ,Color Palette 1_43 Blue"
|
|
line.long 0xB0 "CP1_44R,Color Palette 1 Register 44"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " CP1_44A ,Color Palette 1_44 Blend Ratio"
|
|
hexmask.long.byte 0xB0 18.--23. 1. " CP1_44R ,Color Palette 1_44 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB0 10.--15. 1. " CP1_44G ,Color Palette 1_44 Green"
|
|
hexmask.long.byte 0xB0 2.--7. 1. " CP1_44B ,Color Palette 1_44 Blue"
|
|
line.long 0xB4 "CP1_45R,Color Palette 1 Register 45"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " CP1_45A ,Color Palette 1_45 Blend Ratio"
|
|
hexmask.long.byte 0xB4 18.--23. 1. " CP1_45R ,Color Palette 1_45 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB4 10.--15. 1. " CP1_45G ,Color Palette 1_45 Green"
|
|
hexmask.long.byte 0xB4 2.--7. 1. " CP1_45B ,Color Palette 1_45 Blue"
|
|
line.long 0xB8 "CP1_46R,Color Palette 1 Register 46"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " CP1_46A ,Color Palette 1_46 Blend Ratio"
|
|
hexmask.long.byte 0xB8 18.--23. 1. " CP1_46R ,Color Palette 1_46 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB8 10.--15. 1. " CP1_46G ,Color Palette 1_46 Green"
|
|
hexmask.long.byte 0xB8 2.--7. 1. " CP1_46B ,Color Palette 1_46 Blue"
|
|
line.long 0xBC "CP1_47R,Color Palette 1 Register 47"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " CP1_47A ,Color Palette 1_47 Blend Ratio"
|
|
hexmask.long.byte 0xBC 18.--23. 1. " CP1_47R ,Color Palette 1_47 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xBC 10.--15. 1. " CP1_47G ,Color Palette 1_47 Green"
|
|
hexmask.long.byte 0xBC 2.--7. 1. " CP1_47B ,Color Palette 1_47 Blue"
|
|
line.long 0xC0 "CP1_48R,Color Palette 1 Register 48"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " CP1_48A ,Color Palette 1_48 Blend Ratio"
|
|
hexmask.long.byte 0xC0 18.--23. 1. " CP1_48R ,Color Palette 1_48 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC0 10.--15. 1. " CP1_48G ,Color Palette 1_48 Green"
|
|
hexmask.long.byte 0xC0 2.--7. 1. " CP1_48B ,Color Palette 1_48 Blue"
|
|
line.long 0xC4 "CP1_49R,Color Palette 1 Register 49"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " CP1_49A ,Color Palette 1_49 Blend Ratio"
|
|
hexmask.long.byte 0xC4 18.--23. 1. " CP1_49R ,Color Palette 1_49 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC4 10.--15. 1. " CP1_49G ,Color Palette 1_49 Green"
|
|
hexmask.long.byte 0xC4 2.--7. 1. " CP1_49B ,Color Palette 1_49 Blue"
|
|
line.long 0xC8 "CP1_50R,Color Palette 1 Register 50"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " CP1_50A ,Color Palette 1_50 Blend Ratio"
|
|
hexmask.long.byte 0xC8 18.--23. 1. " CP1_50R ,Color Palette 1_50 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC8 10.--15. 1. " CP1_50G ,Color Palette 1_50 Green"
|
|
hexmask.long.byte 0xC8 2.--7. 1. " CP1_50B ,Color Palette 1_50 Blue"
|
|
line.long 0xCC "CP1_51R,Color Palette 1 Register 51"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " CP1_51A ,Color Palette 1_51 Blend Ratio"
|
|
hexmask.long.byte 0xCC 18.--23. 1. " CP1_51R ,Color Palette 1_51 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xCC 10.--15. 1. " CP1_51G ,Color Palette 1_51 Green"
|
|
hexmask.long.byte 0xCC 2.--7. 1. " CP1_51B ,Color Palette 1_51 Blue"
|
|
line.long 0xD0 "CP1_52R,Color Palette 1 Register 52"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " CP1_52A ,Color Palette 1_52 Blend Ratio"
|
|
hexmask.long.byte 0xD0 18.--23. 1. " CP1_52R ,Color Palette 1_52 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD0 10.--15. 1. " CP1_52G ,Color Palette 1_52 Green"
|
|
hexmask.long.byte 0xD0 2.--7. 1. " CP1_52B ,Color Palette 1_52 Blue"
|
|
line.long 0xD4 "CP1_53R,Color Palette 1 Register 53"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " CP1_53A ,Color Palette 1_53 Blend Ratio"
|
|
hexmask.long.byte 0xD4 18.--23. 1. " CP1_53R ,Color Palette 1_53 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD4 10.--15. 1. " CP1_53G ,Color Palette 1_53 Green"
|
|
hexmask.long.byte 0xD4 2.--7. 1. " CP1_53B ,Color Palette 1_53 Blue"
|
|
line.long 0xD8 "CP1_54R,Color Palette 1 Register 54"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " CP1_54A ,Color Palette 1_54 Blend Ratio"
|
|
hexmask.long.byte 0xD8 18.--23. 1. " CP1_54R ,Color Palette 1_54 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD8 10.--15. 1. " CP1_54G ,Color Palette 1_54 Green"
|
|
hexmask.long.byte 0xD8 2.--7. 1. " CP1_54B ,Color Palette 1_54 Blue"
|
|
line.long 0xDC "CP1_55R,Color Palette 1 Register 55"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " CP1_55A ,Color Palette 1_55 Blend Ratio"
|
|
hexmask.long.byte 0xDC 18.--23. 1. " CP1_55R ,Color Palette 1_55 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xDC 10.--15. 1. " CP1_55G ,Color Palette 1_55 Green"
|
|
hexmask.long.byte 0xDC 2.--7. 1. " CP1_55B ,Color Palette 1_55 Blue"
|
|
line.long 0xE0 "CP1_56R,Color Palette 1 Register 56"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " CP1_56A ,Color Palette 1_56 Blend Ratio"
|
|
hexmask.long.byte 0xE0 18.--23. 1. " CP1_56R ,Color Palette 1_56 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE0 10.--15. 1. " CP1_56G ,Color Palette 1_56 Green"
|
|
hexmask.long.byte 0xE0 2.--7. 1. " CP1_56B ,Color Palette 1_56 Blue"
|
|
line.long 0xE4 "CP1_57R,Color Palette 1 Register 57"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " CP1_57A ,Color Palette 1_57 Blend Ratio"
|
|
hexmask.long.byte 0xE4 18.--23. 1. " CP1_57R ,Color Palette 1_57 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE4 10.--15. 1. " CP1_57G ,Color Palette 1_57 Green"
|
|
hexmask.long.byte 0xE4 2.--7. 1. " CP1_57B ,Color Palette 1_57 Blue"
|
|
line.long 0xE8 "CP1_58R,Color Palette 1 Register 58"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " CP1_58A ,Color Palette 1_58 Blend Ratio"
|
|
hexmask.long.byte 0xE8 18.--23. 1. " CP1_58R ,Color Palette 1_58 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE8 10.--15. 1. " CP1_58G ,Color Palette 1_58 Green"
|
|
hexmask.long.byte 0xE8 2.--7. 1. " CP1_58B ,Color Palette 1_58 Blue"
|
|
line.long 0xEC "CP1_59R,Color Palette 1 Register 59"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " CP1_59A ,Color Palette 1_59 Blend Ratio"
|
|
hexmask.long.byte 0xEC 18.--23. 1. " CP1_59R ,Color Palette 1_59 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xEC 10.--15. 1. " CP1_59G ,Color Palette 1_59 Green"
|
|
hexmask.long.byte 0xEC 2.--7. 1. " CP1_59B ,Color Palette 1_59 Blue"
|
|
line.long 0xF0 "CP1_60R,Color Palette 1 Register 60"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " CP1_60A ,Color Palette 1_60 Blend Ratio"
|
|
hexmask.long.byte 0xF0 18.--23. 1. " CP1_60R ,Color Palette 1_60 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF0 10.--15. 1. " CP1_60G ,Color Palette 1_60 Green"
|
|
hexmask.long.byte 0xF0 2.--7. 1. " CP1_60B ,Color Palette 1_60 Blue"
|
|
line.long 0xF4 "CP1_61R,Color Palette 1 Register 61"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " CP1_61A ,Color Palette 1_61 Blend Ratio"
|
|
hexmask.long.byte 0xF4 18.--23. 1. " CP1_61R ,Color Palette 1_61 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF4 10.--15. 1. " CP1_61G ,Color Palette 1_61 Green"
|
|
hexmask.long.byte 0xF4 2.--7. 1. " CP1_61B ,Color Palette 1_61 Blue"
|
|
line.long 0xF8 "CP1_62R,Color Palette 1 Register 62"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " CP1_62A ,Color Palette 1_62 Blend Ratio"
|
|
hexmask.long.byte 0xF8 18.--23. 1. " CP1_62R ,Color Palette 1_62 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF8 10.--15. 1. " CP1_62G ,Color Palette 1_62 Green"
|
|
hexmask.long.byte 0xF8 2.--7. 1. " CP1_62B ,Color Palette 1_62 Blue"
|
|
line.long 0xFC "CP1_63R,Color Palette 1 Register 63"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " CP1_63A ,Color Palette 1_63 Blend Ratio"
|
|
hexmask.long.byte 0xFC 18.--23. 1. " CP1_63R ,Color Palette 1_63 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xFC 10.--15. 1. " CP1_63G ,Color Palette 1_63 Green"
|
|
hexmask.long.byte 0xFC 2.--7. 1. " CP1_63B ,Color Palette 1_63 Blue"
|
|
line.long 0x100 "CP1_64R,Color Palette 1 Register 64"
|
|
hexmask.long.byte 0x100 24.--31. 1. " CP1_64A ,Color Palette 1_64 Blend Ratio"
|
|
hexmask.long.byte 0x100 18.--23. 1. " CP1_64R ,Color Palette 1_64 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x100 10.--15. 1. " CP1_64G ,Color Palette 1_64 Green"
|
|
hexmask.long.byte 0x100 2.--7. 1. " CP1_64B ,Color Palette 1_64 Blue"
|
|
line.long 0x104 "CP1_65R,Color Palette 1 Register 65"
|
|
hexmask.long.byte 0x104 24.--31. 1. " CP1_65A ,Color Palette 1_65 Blend Ratio"
|
|
hexmask.long.byte 0x104 18.--23. 1. " CP1_65R ,Color Palette 1_65 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x104 10.--15. 1. " CP1_65G ,Color Palette 1_65 Green"
|
|
hexmask.long.byte 0x104 2.--7. 1. " CP1_65B ,Color Palette 1_65 Blue"
|
|
line.long 0x108 "CP1_66R,Color Palette 1 Register 66"
|
|
hexmask.long.byte 0x108 24.--31. 1. " CP1_66A ,Color Palette 1_66 Blend Ratio"
|
|
hexmask.long.byte 0x108 18.--23. 1. " CP1_66R ,Color Palette 1_66 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x108 10.--15. 1. " CP1_66G ,Color Palette 1_66 Green"
|
|
hexmask.long.byte 0x108 2.--7. 1. " CP1_66B ,Color Palette 1_66 Blue"
|
|
line.long 0x10C "CP1_67R,Color Palette 1 Register 67"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " CP1_67A ,Color Palette 1_67 Blend Ratio"
|
|
hexmask.long.byte 0x10C 18.--23. 1. " CP1_67R ,Color Palette 1_67 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10C 10.--15. 1. " CP1_67G ,Color Palette 1_67 Green"
|
|
hexmask.long.byte 0x10C 2.--7. 1. " CP1_67B ,Color Palette 1_67 Blue"
|
|
line.long 0x110 "CP1_68R,Color Palette 1 Register 68"
|
|
hexmask.long.byte 0x110 24.--31. 1. " CP1_68A ,Color Palette 1_68 Blend Ratio"
|
|
hexmask.long.byte 0x110 18.--23. 1. " CP1_68R ,Color Palette 1_68 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x110 10.--15. 1. " CP1_68G ,Color Palette 1_68 Green"
|
|
hexmask.long.byte 0x110 2.--7. 1. " CP1_68B ,Color Palette 1_68 Blue"
|
|
line.long 0x114 "CP1_69R,Color Palette 1 Register 69"
|
|
hexmask.long.byte 0x114 24.--31. 1. " CP1_69A ,Color Palette 1_69 Blend Ratio"
|
|
hexmask.long.byte 0x114 18.--23. 1. " CP1_69R ,Color Palette 1_69 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x114 10.--15. 1. " CP1_69G ,Color Palette 1_69 Green"
|
|
hexmask.long.byte 0x114 2.--7. 1. " CP1_69B ,Color Palette 1_69 Blue"
|
|
line.long 0x118 "CP1_70R,Color Palette 1 Register 70"
|
|
hexmask.long.byte 0x118 24.--31. 1. " CP1_70A ,Color Palette 1_70 Blend Ratio"
|
|
hexmask.long.byte 0x118 18.--23. 1. " CP1_70R ,Color Palette 1_70 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x118 10.--15. 1. " CP1_70G ,Color Palette 1_70 Green"
|
|
hexmask.long.byte 0x118 2.--7. 1. " CP1_70B ,Color Palette 1_70 Blue"
|
|
line.long 0x11C "CP1_71R,Color Palette 1 Register 71"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " CP1_71A ,Color Palette 1_71 Blend Ratio"
|
|
hexmask.long.byte 0x11C 18.--23. 1. " CP1_71R ,Color Palette 1_71 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x11C 10.--15. 1. " CP1_71G ,Color Palette 1_71 Green"
|
|
hexmask.long.byte 0x11C 2.--7. 1. " CP1_71B ,Color Palette 1_71 Blue"
|
|
line.long 0x120 "CP1_72R,Color Palette 1 Register 72"
|
|
hexmask.long.byte 0x120 24.--31. 1. " CP1_72A ,Color Palette 1_72 Blend Ratio"
|
|
hexmask.long.byte 0x120 18.--23. 1. " CP1_72R ,Color Palette 1_72 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x120 10.--15. 1. " CP1_72G ,Color Palette 1_72 Green"
|
|
hexmask.long.byte 0x120 2.--7. 1. " CP1_72B ,Color Palette 1_72 Blue"
|
|
line.long 0x124 "CP1_73R,Color Palette 1 Register 73"
|
|
hexmask.long.byte 0x124 24.--31. 1. " CP1_73A ,Color Palette 1_73 Blend Ratio"
|
|
hexmask.long.byte 0x124 18.--23. 1. " CP1_73R ,Color Palette 1_73 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x124 10.--15. 1. " CP1_73G ,Color Palette 1_73 Green"
|
|
hexmask.long.byte 0x124 2.--7. 1. " CP1_73B ,Color Palette 1_73 Blue"
|
|
line.long 0x128 "CP1_74R,Color Palette 1 Register 74"
|
|
hexmask.long.byte 0x128 24.--31. 1. " CP1_74A ,Color Palette 1_74 Blend Ratio"
|
|
hexmask.long.byte 0x128 18.--23. 1. " CP1_74R ,Color Palette 1_74 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x128 10.--15. 1. " CP1_74G ,Color Palette 1_74 Green"
|
|
hexmask.long.byte 0x128 2.--7. 1. " CP1_74B ,Color Palette 1_74 Blue"
|
|
line.long 0x12C "CP1_75R,Color Palette 1 Register 75"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " CP1_75A ,Color Palette 1_75 Blend Ratio"
|
|
hexmask.long.byte 0x12C 18.--23. 1. " CP1_75R ,Color Palette 1_75 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x12C 10.--15. 1. " CP1_75G ,Color Palette 1_75 Green"
|
|
hexmask.long.byte 0x12C 2.--7. 1. " CP1_75B ,Color Palette 1_75 Blue"
|
|
line.long 0x130 "CP1_76R,Color Palette 1 Register 76"
|
|
hexmask.long.byte 0x130 24.--31. 1. " CP1_76A ,Color Palette 1_76 Blend Ratio"
|
|
hexmask.long.byte 0x130 18.--23. 1. " CP1_76R ,Color Palette 1_76 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x130 10.--15. 1. " CP1_76G ,Color Palette 1_76 Green"
|
|
hexmask.long.byte 0x130 2.--7. 1. " CP1_76B ,Color Palette 1_76 Blue"
|
|
line.long 0x134 "CP1_77R,Color Palette 1 Register 77"
|
|
hexmask.long.byte 0x134 24.--31. 1. " CP1_77A ,Color Palette 1_77 Blend Ratio"
|
|
hexmask.long.byte 0x134 18.--23. 1. " CP1_77R ,Color Palette 1_77 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x134 10.--15. 1. " CP1_77G ,Color Palette 1_77 Green"
|
|
hexmask.long.byte 0x134 2.--7. 1. " CP1_77B ,Color Palette 1_77 Blue"
|
|
line.long 0x138 "CP1_78R,Color Palette 1 Register 78"
|
|
hexmask.long.byte 0x138 24.--31. 1. " CP1_78A ,Color Palette 1_78 Blend Ratio"
|
|
hexmask.long.byte 0x138 18.--23. 1. " CP1_78R ,Color Palette 1_78 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x138 10.--15. 1. " CP1_78G ,Color Palette 1_78 Green"
|
|
hexmask.long.byte 0x138 2.--7. 1. " CP1_78B ,Color Palette 1_78 Blue"
|
|
line.long 0x13C "CP1_79R,Color Palette 1 Register 79"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " CP1_79A ,Color Palette 1_79 Blend Ratio"
|
|
hexmask.long.byte 0x13C 18.--23. 1. " CP1_79R ,Color Palette 1_79 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x13C 10.--15. 1. " CP1_79G ,Color Palette 1_79 Green"
|
|
hexmask.long.byte 0x13C 2.--7. 1. " CP1_79B ,Color Palette 1_79 Blue"
|
|
line.long 0x140 "CP1_80R,Color Palette 1 Register 80"
|
|
hexmask.long.byte 0x140 24.--31. 1. " CP1_80A ,Color Palette 1_80 Blend Ratio"
|
|
hexmask.long.byte 0x140 18.--23. 1. " CP1_80R ,Color Palette 1_80 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x140 10.--15. 1. " CP1_80G ,Color Palette 1_80 Green"
|
|
hexmask.long.byte 0x140 2.--7. 1. " CP1_80B ,Color Palette 1_80 Blue"
|
|
line.long 0x144 "CP1_81R,Color Palette 1 Register 81"
|
|
hexmask.long.byte 0x144 24.--31. 1. " CP1_81A ,Color Palette 1_81 Blend Ratio"
|
|
hexmask.long.byte 0x144 18.--23. 1. " CP1_81R ,Color Palette 1_81 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x144 10.--15. 1. " CP1_81G ,Color Palette 1_81 Green"
|
|
hexmask.long.byte 0x144 2.--7. 1. " CP1_81B ,Color Palette 1_81 Blue"
|
|
line.long 0x148 "CP1_82R,Color Palette 1 Register 82"
|
|
hexmask.long.byte 0x148 24.--31. 1. " CP1_82A ,Color Palette 1_82 Blend Ratio"
|
|
hexmask.long.byte 0x148 18.--23. 1. " CP1_82R ,Color Palette 1_82 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x148 10.--15. 1. " CP1_82G ,Color Palette 1_82 Green"
|
|
hexmask.long.byte 0x148 2.--7. 1. " CP1_82B ,Color Palette 1_82 Blue"
|
|
line.long 0x14C "CP1_83R,Color Palette 1 Register 83"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " CP1_83A ,Color Palette 1_83 Blend Ratio"
|
|
hexmask.long.byte 0x14C 18.--23. 1. " CP1_83R ,Color Palette 1_83 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14C 10.--15. 1. " CP1_83G ,Color Palette 1_83 Green"
|
|
hexmask.long.byte 0x14C 2.--7. 1. " CP1_83B ,Color Palette 1_83 Blue"
|
|
line.long 0x150 "CP1_84R,Color Palette 1 Register 84"
|
|
hexmask.long.byte 0x150 24.--31. 1. " CP1_84A ,Color Palette 1_84 Blend Ratio"
|
|
hexmask.long.byte 0x150 18.--23. 1. " CP1_84R ,Color Palette 1_84 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x150 10.--15. 1. " CP1_84G ,Color Palette 1_84 Green"
|
|
hexmask.long.byte 0x150 2.--7. 1. " CP1_84B ,Color Palette 1_84 Blue"
|
|
line.long 0x154 "CP1_85R,Color Palette 1 Register 85"
|
|
hexmask.long.byte 0x154 24.--31. 1. " CP1_85A ,Color Palette 1_85 Blend Ratio"
|
|
hexmask.long.byte 0x154 18.--23. 1. " CP1_85R ,Color Palette 1_85 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x154 10.--15. 1. " CP1_85G ,Color Palette 1_85 Green"
|
|
hexmask.long.byte 0x154 2.--7. 1. " CP1_85B ,Color Palette 1_85 Blue"
|
|
line.long 0x158 "CP1_86R,Color Palette 1 Register 86"
|
|
hexmask.long.byte 0x158 24.--31. 1. " CP1_86A ,Color Palette 1_86 Blend Ratio"
|
|
hexmask.long.byte 0x158 18.--23. 1. " CP1_86R ,Color Palette 1_86 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x158 10.--15. 1. " CP1_86G ,Color Palette 1_86 Green"
|
|
hexmask.long.byte 0x158 2.--7. 1. " CP1_86B ,Color Palette 1_86 Blue"
|
|
line.long 0x15C "CP1_87R,Color Palette 1 Register 87"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " CP1_87A ,Color Palette 1_87 Blend Ratio"
|
|
hexmask.long.byte 0x15C 18.--23. 1. " CP1_87R ,Color Palette 1_87 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x15C 10.--15. 1. " CP1_87G ,Color Palette 1_87 Green"
|
|
hexmask.long.byte 0x15C 2.--7. 1. " CP1_87B ,Color Palette 1_87 Blue"
|
|
line.long 0x160 "CP1_88R,Color Palette 1 Register 88"
|
|
hexmask.long.byte 0x160 24.--31. 1. " CP1_88A ,Color Palette 1_88 Blend Ratio"
|
|
hexmask.long.byte 0x160 18.--23. 1. " CP1_88R ,Color Palette 1_88 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x160 10.--15. 1. " CP1_88G ,Color Palette 1_88 Green"
|
|
hexmask.long.byte 0x160 2.--7. 1. " CP1_88B ,Color Palette 1_88 Blue"
|
|
line.long 0x164 "CP1_89R,Color Palette 1 Register 89"
|
|
hexmask.long.byte 0x164 24.--31. 1. " CP1_89A ,Color Palette 1_89 Blend Ratio"
|
|
hexmask.long.byte 0x164 18.--23. 1. " CP1_89R ,Color Palette 1_89 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x164 10.--15. 1. " CP1_89G ,Color Palette 1_89 Green"
|
|
hexmask.long.byte 0x164 2.--7. 1. " CP1_89B ,Color Palette 1_89 Blue"
|
|
line.long 0x168 "CP1_90R,Color Palette 1 Register 90"
|
|
hexmask.long.byte 0x168 24.--31. 1. " CP1_90A ,Color Palette 1_90 Blend Ratio"
|
|
hexmask.long.byte 0x168 18.--23. 1. " CP1_90R ,Color Palette 1_90 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x168 10.--15. 1. " CP1_90G ,Color Palette 1_90 Green"
|
|
hexmask.long.byte 0x168 2.--7. 1. " CP1_90B ,Color Palette 1_90 Blue"
|
|
line.long 0x16C "CP1_91R,Color Palette 1 Register 91"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " CP1_91A ,Color Palette 1_91 Blend Ratio"
|
|
hexmask.long.byte 0x16C 18.--23. 1. " CP1_91R ,Color Palette 1_91 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x16C 10.--15. 1. " CP1_91G ,Color Palette 1_91 Green"
|
|
hexmask.long.byte 0x16C 2.--7. 1. " CP1_91B ,Color Palette 1_91 Blue"
|
|
line.long 0x170 "CP1_92R,Color Palette 1 Register 92"
|
|
hexmask.long.byte 0x170 24.--31. 1. " CP1_92A ,Color Palette 1_92 Blend Ratio"
|
|
hexmask.long.byte 0x170 18.--23. 1. " CP1_92R ,Color Palette 1_92 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x170 10.--15. 1. " CP1_92G ,Color Palette 1_92 Green"
|
|
hexmask.long.byte 0x170 2.--7. 1. " CP1_92B ,Color Palette 1_92 Blue"
|
|
line.long 0x174 "CP1_93R,Color Palette 1 Register 93"
|
|
hexmask.long.byte 0x174 24.--31. 1. " CP1_93A ,Color Palette 1_93 Blend Ratio"
|
|
hexmask.long.byte 0x174 18.--23. 1. " CP1_93R ,Color Palette 1_93 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x174 10.--15. 1. " CP1_93G ,Color Palette 1_93 Green"
|
|
hexmask.long.byte 0x174 2.--7. 1. " CP1_93B ,Color Palette 1_93 Blue"
|
|
line.long 0x178 "CP1_94R,Color Palette 1 Register 94"
|
|
hexmask.long.byte 0x178 24.--31. 1. " CP1_94A ,Color Palette 1_94 Blend Ratio"
|
|
hexmask.long.byte 0x178 18.--23. 1. " CP1_94R ,Color Palette 1_94 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x178 10.--15. 1. " CP1_94G ,Color Palette 1_94 Green"
|
|
hexmask.long.byte 0x178 2.--7. 1. " CP1_94B ,Color Palette 1_94 Blue"
|
|
line.long 0x17C "CP1_95R,Color Palette 1 Register 95"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " CP1_95A ,Color Palette 1_95 Blend Ratio"
|
|
hexmask.long.byte 0x17C 18.--23. 1. " CP1_95R ,Color Palette 1_95 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x17C 10.--15. 1. " CP1_95G ,Color Palette 1_95 Green"
|
|
hexmask.long.byte 0x17C 2.--7. 1. " CP1_95B ,Color Palette 1_95 Blue"
|
|
line.long 0x180 "CP1_96R,Color Palette 1 Register 96"
|
|
hexmask.long.byte 0x180 24.--31. 1. " CP1_96A ,Color Palette 1_96 Blend Ratio"
|
|
hexmask.long.byte 0x180 18.--23. 1. " CP1_96R ,Color Palette 1_96 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x180 10.--15. 1. " CP1_96G ,Color Palette 1_96 Green"
|
|
hexmask.long.byte 0x180 2.--7. 1. " CP1_96B ,Color Palette 1_96 Blue"
|
|
line.long 0x184 "CP1_97R,Color Palette 1 Register 97"
|
|
hexmask.long.byte 0x184 24.--31. 1. " CP1_97A ,Color Palette 1_97 Blend Ratio"
|
|
hexmask.long.byte 0x184 18.--23. 1. " CP1_97R ,Color Palette 1_97 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x184 10.--15. 1. " CP1_97G ,Color Palette 1_97 Green"
|
|
hexmask.long.byte 0x184 2.--7. 1. " CP1_97B ,Color Palette 1_97 Blue"
|
|
line.long 0x188 "CP1_98R,Color Palette 1 Register 98"
|
|
hexmask.long.byte 0x188 24.--31. 1. " CP1_98A ,Color Palette 1_98 Blend Ratio"
|
|
hexmask.long.byte 0x188 18.--23. 1. " CP1_98R ,Color Palette 1_98 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x188 10.--15. 1. " CP1_98G ,Color Palette 1_98 Green"
|
|
hexmask.long.byte 0x188 2.--7. 1. " CP1_98B ,Color Palette 1_98 Blue"
|
|
line.long 0x18C "CP1_99R,Color Palette 1 Register 99"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " CP1_99A ,Color Palette 1_99 Blend Ratio"
|
|
hexmask.long.byte 0x18C 18.--23. 1. " CP1_99R ,Color Palette 1_99 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18C 10.--15. 1. " CP1_99G ,Color Palette 1_99 Green"
|
|
hexmask.long.byte 0x18C 2.--7. 1. " CP1_99B ,Color Palette 1_99 Blue"
|
|
line.long 0x190 "CP1_100R,Color Palette 1 Register 100"
|
|
hexmask.long.byte 0x190 24.--31. 1. " CP1_100A ,Color Palette 1_100 Blend Ratio"
|
|
hexmask.long.byte 0x190 18.--23. 1. " CP1_100R ,Color Palette 1_100 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x190 10.--15. 1. " CP1_100G ,Color Palette 1_100 Green"
|
|
hexmask.long.byte 0x190 2.--7. 1. " CP1_100B ,Color Palette 1_100 Blue"
|
|
line.long 0x194 "CP1_101R,Color Palette 1 Register 101"
|
|
hexmask.long.byte 0x194 24.--31. 1. " CP1_101A ,Color Palette 1_101 Blend Ratio"
|
|
hexmask.long.byte 0x194 18.--23. 1. " CP1_101R ,Color Palette 1_101 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x194 10.--15. 1. " CP1_101G ,Color Palette 1_101 Green"
|
|
hexmask.long.byte 0x194 2.--7. 1. " CP1_101B ,Color Palette 1_101 Blue"
|
|
line.long 0x198 "CP1_102R,Color Palette 1 Register 102"
|
|
hexmask.long.byte 0x198 24.--31. 1. " CP1_102A ,Color Palette 1_102 Blend Ratio"
|
|
hexmask.long.byte 0x198 18.--23. 1. " CP1_102R ,Color Palette 1_102 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x198 10.--15. 1. " CP1_102G ,Color Palette 1_102 Green"
|
|
hexmask.long.byte 0x198 2.--7. 1. " CP1_102B ,Color Palette 1_102 Blue"
|
|
line.long 0x19C "CP1_103R,Color Palette 1 Register 103"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " CP1_103A ,Color Palette 1_103 Blend Ratio"
|
|
hexmask.long.byte 0x19C 18.--23. 1. " CP1_103R ,Color Palette 1_103 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x19C 10.--15. 1. " CP1_103G ,Color Palette 1_103 Green"
|
|
hexmask.long.byte 0x19C 2.--7. 1. " CP1_103B ,Color Palette 1_103 Blue"
|
|
line.long 0x1A0 "CP1_104R,Color Palette 1 Register 104"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " CP1_104A ,Color Palette 1_104 Blend Ratio"
|
|
hexmask.long.byte 0x1A0 18.--23. 1. " CP1_104R ,Color Palette 1_104 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A0 10.--15. 1. " CP1_104G ,Color Palette 1_104 Green"
|
|
hexmask.long.byte 0x1A0 2.--7. 1. " CP1_104B ,Color Palette 1_104 Blue"
|
|
line.long 0x1A4 "CP1_105R,Color Palette 1 Register 105"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " CP1_105A ,Color Palette 1_105 Blend Ratio"
|
|
hexmask.long.byte 0x1A4 18.--23. 1. " CP1_105R ,Color Palette 1_105 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A4 10.--15. 1. " CP1_105G ,Color Palette 1_105 Green"
|
|
hexmask.long.byte 0x1A4 2.--7. 1. " CP1_105B ,Color Palette 1_105 Blue"
|
|
line.long 0x1A8 "CP1_106R,Color Palette 1 Register 106"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " CP1_106A ,Color Palette 1_106 Blend Ratio"
|
|
hexmask.long.byte 0x1A8 18.--23. 1. " CP1_106R ,Color Palette 1_106 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A8 10.--15. 1. " CP1_106G ,Color Palette 1_106 Green"
|
|
hexmask.long.byte 0x1A8 2.--7. 1. " CP1_106B ,Color Palette 1_106 Blue"
|
|
line.long 0x1AC "CP1_107R,Color Palette 1 Register 107"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " CP1_107A ,Color Palette 1_107 Blend Ratio"
|
|
hexmask.long.byte 0x1AC 18.--23. 1. " CP1_107R ,Color Palette 1_107 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1AC 10.--15. 1. " CP1_107G ,Color Palette 1_107 Green"
|
|
hexmask.long.byte 0x1AC 2.--7. 1. " CP1_107B ,Color Palette 1_107 Blue"
|
|
line.long 0x1B0 "CP1_108R,Color Palette 1 Register 108"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " CP1_108A ,Color Palette 1_108 Blend Ratio"
|
|
hexmask.long.byte 0x1B0 18.--23. 1. " CP1_108R ,Color Palette 1_108 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B0 10.--15. 1. " CP1_108G ,Color Palette 1_108 Green"
|
|
hexmask.long.byte 0x1B0 2.--7. 1. " CP1_108B ,Color Palette 1_108 Blue"
|
|
line.long 0x1B4 "CP1_109R,Color Palette 1 Register 109"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " CP1_109A ,Color Palette 1_109 Blend Ratio"
|
|
hexmask.long.byte 0x1B4 18.--23. 1. " CP1_109R ,Color Palette 1_109 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B4 10.--15. 1. " CP1_109G ,Color Palette 1_109 Green"
|
|
hexmask.long.byte 0x1B4 2.--7. 1. " CP1_109B ,Color Palette 1_109 Blue"
|
|
line.long 0x1B8 "CP1_110R,Color Palette 1 Register 110"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " CP1_110A ,Color Palette 1_110 Blend Ratio"
|
|
hexmask.long.byte 0x1B8 18.--23. 1. " CP1_110R ,Color Palette 1_110 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B8 10.--15. 1. " CP1_110G ,Color Palette 1_110 Green"
|
|
hexmask.long.byte 0x1B8 2.--7. 1. " CP1_110B ,Color Palette 1_110 Blue"
|
|
line.long 0x1BC "CP1_111R,Color Palette 1 Register 111"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " CP1_111A ,Color Palette 1_111 Blend Ratio"
|
|
hexmask.long.byte 0x1BC 18.--23. 1. " CP1_111R ,Color Palette 1_111 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1BC 10.--15. 1. " CP1_111G ,Color Palette 1_111 Green"
|
|
hexmask.long.byte 0x1BC 2.--7. 1. " CP1_111B ,Color Palette 1_111 Blue"
|
|
line.long 0x1C0 "CP1_112R,Color Palette 1 Register 112"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " CP1_112A ,Color Palette 1_112 Blend Ratio"
|
|
hexmask.long.byte 0x1C0 18.--23. 1. " CP1_112R ,Color Palette 1_112 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C0 10.--15. 1. " CP1_112G ,Color Palette 1_112 Green"
|
|
hexmask.long.byte 0x1C0 2.--7. 1. " CP1_112B ,Color Palette 1_112 Blue"
|
|
line.long 0x1C4 "CP1_113R,Color Palette 1 Register 113"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " CP1_113A ,Color Palette 1_113 Blend Ratio"
|
|
hexmask.long.byte 0x1C4 18.--23. 1. " CP1_113R ,Color Palette 1_113 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C4 10.--15. 1. " CP1_113G ,Color Palette 1_113 Green"
|
|
hexmask.long.byte 0x1C4 2.--7. 1. " CP1_113B ,Color Palette 1_113 Blue"
|
|
line.long 0x1C8 "CP1_114R,Color Palette 1 Register 114"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " CP1_114A ,Color Palette 1_114 Blend Ratio"
|
|
hexmask.long.byte 0x1C8 18.--23. 1. " CP1_114R ,Color Palette 1_114 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C8 10.--15. 1. " CP1_114G ,Color Palette 1_114 Green"
|
|
hexmask.long.byte 0x1C8 2.--7. 1. " CP1_114B ,Color Palette 1_114 Blue"
|
|
line.long 0x1CC "CP1_115R,Color Palette 1 Register 115"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " CP1_115A ,Color Palette 1_115 Blend Ratio"
|
|
hexmask.long.byte 0x1CC 18.--23. 1. " CP1_115R ,Color Palette 1_115 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1CC 10.--15. 1. " CP1_115G ,Color Palette 1_115 Green"
|
|
hexmask.long.byte 0x1CC 2.--7. 1. " CP1_115B ,Color Palette 1_115 Blue"
|
|
line.long 0x1D0 "CP1_116R,Color Palette 1 Register 116"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " CP1_116A ,Color Palette 1_116 Blend Ratio"
|
|
hexmask.long.byte 0x1D0 18.--23. 1. " CP1_116R ,Color Palette 1_116 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D0 10.--15. 1. " CP1_116G ,Color Palette 1_116 Green"
|
|
hexmask.long.byte 0x1D0 2.--7. 1. " CP1_116B ,Color Palette 1_116 Blue"
|
|
line.long 0x1D4 "CP1_117R,Color Palette 1 Register 117"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " CP1_117A ,Color Palette 1_117 Blend Ratio"
|
|
hexmask.long.byte 0x1D4 18.--23. 1. " CP1_117R ,Color Palette 1_117 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D4 10.--15. 1. " CP1_117G ,Color Palette 1_117 Green"
|
|
hexmask.long.byte 0x1D4 2.--7. 1. " CP1_117B ,Color Palette 1_117 Blue"
|
|
line.long 0x1D8 "CP1_118R,Color Palette 1 Register 118"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " CP1_118A ,Color Palette 1_118 Blend Ratio"
|
|
hexmask.long.byte 0x1D8 18.--23. 1. " CP1_118R ,Color Palette 1_118 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D8 10.--15. 1. " CP1_118G ,Color Palette 1_118 Green"
|
|
hexmask.long.byte 0x1D8 2.--7. 1. " CP1_118B ,Color Palette 1_118 Blue"
|
|
line.long 0x1DC "CP1_119R,Color Palette 1 Register 119"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " CP1_119A ,Color Palette 1_119 Blend Ratio"
|
|
hexmask.long.byte 0x1DC 18.--23. 1. " CP1_119R ,Color Palette 1_119 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1DC 10.--15. 1. " CP1_119G ,Color Palette 1_119 Green"
|
|
hexmask.long.byte 0x1DC 2.--7. 1. " CP1_119B ,Color Palette 1_119 Blue"
|
|
line.long 0x1E0 "CP1_120R,Color Palette 1 Register 120"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " CP1_120A ,Color Palette 1_120 Blend Ratio"
|
|
hexmask.long.byte 0x1E0 18.--23. 1. " CP1_120R ,Color Palette 1_120 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E0 10.--15. 1. " CP1_120G ,Color Palette 1_120 Green"
|
|
hexmask.long.byte 0x1E0 2.--7. 1. " CP1_120B ,Color Palette 1_120 Blue"
|
|
line.long 0x1E4 "CP1_121R,Color Palette 1 Register 121"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " CP1_121A ,Color Palette 1_121 Blend Ratio"
|
|
hexmask.long.byte 0x1E4 18.--23. 1. " CP1_121R ,Color Palette 1_121 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E4 10.--15. 1. " CP1_121G ,Color Palette 1_121 Green"
|
|
hexmask.long.byte 0x1E4 2.--7. 1. " CP1_121B ,Color Palette 1_121 Blue"
|
|
line.long 0x1E8 "CP1_122R,Color Palette 1 Register 122"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " CP1_122A ,Color Palette 1_122 Blend Ratio"
|
|
hexmask.long.byte 0x1E8 18.--23. 1. " CP1_122R ,Color Palette 1_122 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E8 10.--15. 1. " CP1_122G ,Color Palette 1_122 Green"
|
|
hexmask.long.byte 0x1E8 2.--7. 1. " CP1_122B ,Color Palette 1_122 Blue"
|
|
line.long 0x1EC "CP1_123R,Color Palette 1 Register 123"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " CP1_123A ,Color Palette 1_123 Blend Ratio"
|
|
hexmask.long.byte 0x1EC 18.--23. 1. " CP1_123R ,Color Palette 1_123 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1EC 10.--15. 1. " CP1_123G ,Color Palette 1_123 Green"
|
|
hexmask.long.byte 0x1EC 2.--7. 1. " CP1_123B ,Color Palette 1_123 Blue"
|
|
line.long 0x1F0 "CP1_124R,Color Palette 1 Register 124"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " CP1_124A ,Color Palette 1_124 Blend Ratio"
|
|
hexmask.long.byte 0x1F0 18.--23. 1. " CP1_124R ,Color Palette 1_124 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F0 10.--15. 1. " CP1_124G ,Color Palette 1_124 Green"
|
|
hexmask.long.byte 0x1F0 2.--7. 1. " CP1_124B ,Color Palette 1_124 Blue"
|
|
line.long 0x1F4 "CP1_125R,Color Palette 1 Register 125"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " CP1_125A ,Color Palette 1_125 Blend Ratio"
|
|
hexmask.long.byte 0x1F4 18.--23. 1. " CP1_125R ,Color Palette 1_125 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F4 10.--15. 1. " CP1_125G ,Color Palette 1_125 Green"
|
|
hexmask.long.byte 0x1F4 2.--7. 1. " CP1_125B ,Color Palette 1_125 Blue"
|
|
line.long 0x1F8 "CP1_126R,Color Palette 1 Register 126"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " CP1_126A ,Color Palette 1_126 Blend Ratio"
|
|
hexmask.long.byte 0x1F8 18.--23. 1. " CP1_126R ,Color Palette 1_126 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F8 10.--15. 1. " CP1_126G ,Color Palette 1_126 Green"
|
|
hexmask.long.byte 0x1F8 2.--7. 1. " CP1_126B ,Color Palette 1_126 Blue"
|
|
line.long 0x1FC "CP1_127R,Color Palette 1 Register 127"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " CP1_127A ,Color Palette 1_127 Blend Ratio"
|
|
hexmask.long.byte 0x1FC 18.--23. 1. " CP1_127R ,Color Palette 1_127 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1FC 10.--15. 1. " CP1_127G ,Color Palette 1_127 Green"
|
|
hexmask.long.byte 0x1FC 2.--7. 1. " CP1_127B ,Color Palette 1_127 Blue"
|
|
line.long 0x200 "CP1_128R,Color Palette 1 Register 128"
|
|
hexmask.long.byte 0x200 24.--31. 1. " CP1_128A ,Color Palette 1_128 Blend Ratio"
|
|
hexmask.long.byte 0x200 18.--23. 1. " CP1_128R ,Color Palette 1_128 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x200 10.--15. 1. " CP1_128G ,Color Palette 1_128 Green"
|
|
hexmask.long.byte 0x200 2.--7. 1. " CP1_128B ,Color Palette 1_128 Blue"
|
|
line.long 0x204 "CP1_129R,Color Palette 1 Register 129"
|
|
hexmask.long.byte 0x204 24.--31. 1. " CP1_129A ,Color Palette 1_129 Blend Ratio"
|
|
hexmask.long.byte 0x204 18.--23. 1. " CP1_129R ,Color Palette 1_129 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x204 10.--15. 1. " CP1_129G ,Color Palette 1_129 Green"
|
|
hexmask.long.byte 0x204 2.--7. 1. " CP1_129B ,Color Palette 1_129 Blue"
|
|
line.long 0x208 "CP1_130R,Color Palette 1 Register 130"
|
|
hexmask.long.byte 0x208 24.--31. 1. " CP1_130A ,Color Palette 1_130 Blend Ratio"
|
|
hexmask.long.byte 0x208 18.--23. 1. " CP1_130R ,Color Palette 1_130 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x208 10.--15. 1. " CP1_130G ,Color Palette 1_130 Green"
|
|
hexmask.long.byte 0x208 2.--7. 1. " CP1_130B ,Color Palette 1_130 Blue"
|
|
line.long 0x20C "CP1_131R,Color Palette 1 Register 131"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " CP1_131A ,Color Palette 1_131 Blend Ratio"
|
|
hexmask.long.byte 0x20C 18.--23. 1. " CP1_131R ,Color Palette 1_131 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20C 10.--15. 1. " CP1_131G ,Color Palette 1_131 Green"
|
|
hexmask.long.byte 0x20C 2.--7. 1. " CP1_131B ,Color Palette 1_131 Blue"
|
|
line.long 0x210 "CP1_132R,Color Palette 1 Register 132"
|
|
hexmask.long.byte 0x210 24.--31. 1. " CP1_132A ,Color Palette 1_132 Blend Ratio"
|
|
hexmask.long.byte 0x210 18.--23. 1. " CP1_132R ,Color Palette 1_132 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x210 10.--15. 1. " CP1_132G ,Color Palette 1_132 Green"
|
|
hexmask.long.byte 0x210 2.--7. 1. " CP1_132B ,Color Palette 1_132 Blue"
|
|
line.long 0x214 "CP1_133R,Color Palette 1 Register 133"
|
|
hexmask.long.byte 0x214 24.--31. 1. " CP1_133A ,Color Palette 1_133 Blend Ratio"
|
|
hexmask.long.byte 0x214 18.--23. 1. " CP1_133R ,Color Palette 1_133 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x214 10.--15. 1. " CP1_133G ,Color Palette 1_133 Green"
|
|
hexmask.long.byte 0x214 2.--7. 1. " CP1_133B ,Color Palette 1_133 Blue"
|
|
line.long 0x218 "CP1_134R,Color Palette 1 Register 134"
|
|
hexmask.long.byte 0x218 24.--31. 1. " CP1_134A ,Color Palette 1_134 Blend Ratio"
|
|
hexmask.long.byte 0x218 18.--23. 1. " CP1_134R ,Color Palette 1_134 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x218 10.--15. 1. " CP1_134G ,Color Palette 1_134 Green"
|
|
hexmask.long.byte 0x218 2.--7. 1. " CP1_134B ,Color Palette 1_134 Blue"
|
|
line.long 0x21C "CP1_135R,Color Palette 1 Register 135"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " CP1_135A ,Color Palette 1_135 Blend Ratio"
|
|
hexmask.long.byte 0x21C 18.--23. 1. " CP1_135R ,Color Palette 1_135 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x21C 10.--15. 1. " CP1_135G ,Color Palette 1_135 Green"
|
|
hexmask.long.byte 0x21C 2.--7. 1. " CP1_135B ,Color Palette 1_135 Blue"
|
|
line.long 0x220 "CP1_136R,Color Palette 1 Register 136"
|
|
hexmask.long.byte 0x220 24.--31. 1. " CP1_136A ,Color Palette 1_136 Blend Ratio"
|
|
hexmask.long.byte 0x220 18.--23. 1. " CP1_136R ,Color Palette 1_136 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x220 10.--15. 1. " CP1_136G ,Color Palette 1_136 Green"
|
|
hexmask.long.byte 0x220 2.--7. 1. " CP1_136B ,Color Palette 1_136 Blue"
|
|
line.long 0x224 "CP1_137R,Color Palette 1 Register 137"
|
|
hexmask.long.byte 0x224 24.--31. 1. " CP1_137A ,Color Palette 1_137 Blend Ratio"
|
|
hexmask.long.byte 0x224 18.--23. 1. " CP1_137R ,Color Palette 1_137 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x224 10.--15. 1. " CP1_137G ,Color Palette 1_137 Green"
|
|
hexmask.long.byte 0x224 2.--7. 1. " CP1_137B ,Color Palette 1_137 Blue"
|
|
line.long 0x228 "CP1_138R,Color Palette 1 Register 138"
|
|
hexmask.long.byte 0x228 24.--31. 1. " CP1_138A ,Color Palette 1_138 Blend Ratio"
|
|
hexmask.long.byte 0x228 18.--23. 1. " CP1_138R ,Color Palette 1_138 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x228 10.--15. 1. " CP1_138G ,Color Palette 1_138 Green"
|
|
hexmask.long.byte 0x228 2.--7. 1. " CP1_138B ,Color Palette 1_138 Blue"
|
|
line.long 0x22C "CP1_139R,Color Palette 1 Register 139"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " CP1_139A ,Color Palette 1_139 Blend Ratio"
|
|
hexmask.long.byte 0x22C 18.--23. 1. " CP1_139R ,Color Palette 1_139 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x22C 10.--15. 1. " CP1_139G ,Color Palette 1_139 Green"
|
|
hexmask.long.byte 0x22C 2.--7. 1. " CP1_139B ,Color Palette 1_139 Blue"
|
|
line.long 0x230 "CP1_140R,Color Palette 1 Register 140"
|
|
hexmask.long.byte 0x230 24.--31. 1. " CP1_140A ,Color Palette 1_140 Blend Ratio"
|
|
hexmask.long.byte 0x230 18.--23. 1. " CP1_140R ,Color Palette 1_140 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x230 10.--15. 1. " CP1_140G ,Color Palette 1_140 Green"
|
|
hexmask.long.byte 0x230 2.--7. 1. " CP1_140B ,Color Palette 1_140 Blue"
|
|
line.long 0x234 "CP1_141R,Color Palette 1 Register 141"
|
|
hexmask.long.byte 0x234 24.--31. 1. " CP1_141A ,Color Palette 1_141 Blend Ratio"
|
|
hexmask.long.byte 0x234 18.--23. 1. " CP1_141R ,Color Palette 1_141 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x234 10.--15. 1. " CP1_141G ,Color Palette 1_141 Green"
|
|
hexmask.long.byte 0x234 2.--7. 1. " CP1_141B ,Color Palette 1_141 Blue"
|
|
line.long 0x238 "CP1_142R,Color Palette 1 Register 142"
|
|
hexmask.long.byte 0x238 24.--31. 1. " CP1_142A ,Color Palette 1_142 Blend Ratio"
|
|
hexmask.long.byte 0x238 18.--23. 1. " CP1_142R ,Color Palette 1_142 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x238 10.--15. 1. " CP1_142G ,Color Palette 1_142 Green"
|
|
hexmask.long.byte 0x238 2.--7. 1. " CP1_142B ,Color Palette 1_142 Blue"
|
|
line.long 0x23C "CP1_143R,Color Palette 1 Register 143"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " CP1_143A ,Color Palette 1_143 Blend Ratio"
|
|
hexmask.long.byte 0x23C 18.--23. 1. " CP1_143R ,Color Palette 1_143 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x23C 10.--15. 1. " CP1_143G ,Color Palette 1_143 Green"
|
|
hexmask.long.byte 0x23C 2.--7. 1. " CP1_143B ,Color Palette 1_143 Blue"
|
|
line.long 0x240 "CP1_144R,Color Palette 1 Register 144"
|
|
hexmask.long.byte 0x240 24.--31. 1. " CP1_144A ,Color Palette 1_144 Blend Ratio"
|
|
hexmask.long.byte 0x240 18.--23. 1. " CP1_144R ,Color Palette 1_144 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x240 10.--15. 1. " CP1_144G ,Color Palette 1_144 Green"
|
|
hexmask.long.byte 0x240 2.--7. 1. " CP1_144B ,Color Palette 1_144 Blue"
|
|
line.long 0x244 "CP1_145R,Color Palette 1 Register 145"
|
|
hexmask.long.byte 0x244 24.--31. 1. " CP1_145A ,Color Palette 1_145 Blend Ratio"
|
|
hexmask.long.byte 0x244 18.--23. 1. " CP1_145R ,Color Palette 1_145 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x244 10.--15. 1. " CP1_145G ,Color Palette 1_145 Green"
|
|
hexmask.long.byte 0x244 2.--7. 1. " CP1_145B ,Color Palette 1_145 Blue"
|
|
line.long 0x248 "CP1_146R,Color Palette 1 Register 146"
|
|
hexmask.long.byte 0x248 24.--31. 1. " CP1_146A ,Color Palette 1_146 Blend Ratio"
|
|
hexmask.long.byte 0x248 18.--23. 1. " CP1_146R ,Color Palette 1_146 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x248 10.--15. 1. " CP1_146G ,Color Palette 1_146 Green"
|
|
hexmask.long.byte 0x248 2.--7. 1. " CP1_146B ,Color Palette 1_146 Blue"
|
|
line.long 0x24C "CP1_147R,Color Palette 1 Register 147"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " CP1_147A ,Color Palette 1_147 Blend Ratio"
|
|
hexmask.long.byte 0x24C 18.--23. 1. " CP1_147R ,Color Palette 1_147 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24C 10.--15. 1. " CP1_147G ,Color Palette 1_147 Green"
|
|
hexmask.long.byte 0x24C 2.--7. 1. " CP1_147B ,Color Palette 1_147 Blue"
|
|
line.long 0x250 "CP1_148R,Color Palette 1 Register 148"
|
|
hexmask.long.byte 0x250 24.--31. 1. " CP1_148A ,Color Palette 1_148 Blend Ratio"
|
|
hexmask.long.byte 0x250 18.--23. 1. " CP1_148R ,Color Palette 1_148 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x250 10.--15. 1. " CP1_148G ,Color Palette 1_148 Green"
|
|
hexmask.long.byte 0x250 2.--7. 1. " CP1_148B ,Color Palette 1_148 Blue"
|
|
line.long 0x254 "CP1_149R,Color Palette 1 Register 149"
|
|
hexmask.long.byte 0x254 24.--31. 1. " CP1_149A ,Color Palette 1_149 Blend Ratio"
|
|
hexmask.long.byte 0x254 18.--23. 1. " CP1_149R ,Color Palette 1_149 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x254 10.--15. 1. " CP1_149G ,Color Palette 1_149 Green"
|
|
hexmask.long.byte 0x254 2.--7. 1. " CP1_149B ,Color Palette 1_149 Blue"
|
|
line.long 0x258 "CP1_150R,Color Palette 1 Register 150"
|
|
hexmask.long.byte 0x258 24.--31. 1. " CP1_150A ,Color Palette 1_150 Blend Ratio"
|
|
hexmask.long.byte 0x258 18.--23. 1. " CP1_150R ,Color Palette 1_150 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x258 10.--15. 1. " CP1_150G ,Color Palette 1_150 Green"
|
|
hexmask.long.byte 0x258 2.--7. 1. " CP1_150B ,Color Palette 1_150 Blue"
|
|
line.long 0x25C "CP1_151R,Color Palette 1 Register 151"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " CP1_151A ,Color Palette 1_151 Blend Ratio"
|
|
hexmask.long.byte 0x25C 18.--23. 1. " CP1_151R ,Color Palette 1_151 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x25C 10.--15. 1. " CP1_151G ,Color Palette 1_151 Green"
|
|
hexmask.long.byte 0x25C 2.--7. 1. " CP1_151B ,Color Palette 1_151 Blue"
|
|
line.long 0x260 "CP1_152R,Color Palette 1 Register 152"
|
|
hexmask.long.byte 0x260 24.--31. 1. " CP1_152A ,Color Palette 1_152 Blend Ratio"
|
|
hexmask.long.byte 0x260 18.--23. 1. " CP1_152R ,Color Palette 1_152 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x260 10.--15. 1. " CP1_152G ,Color Palette 1_152 Green"
|
|
hexmask.long.byte 0x260 2.--7. 1. " CP1_152B ,Color Palette 1_152 Blue"
|
|
line.long 0x264 "CP1_153R,Color Palette 1 Register 153"
|
|
hexmask.long.byte 0x264 24.--31. 1. " CP1_153A ,Color Palette 1_153 Blend Ratio"
|
|
hexmask.long.byte 0x264 18.--23. 1. " CP1_153R ,Color Palette 1_153 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x264 10.--15. 1. " CP1_153G ,Color Palette 1_153 Green"
|
|
hexmask.long.byte 0x264 2.--7. 1. " CP1_153B ,Color Palette 1_153 Blue"
|
|
line.long 0x268 "CP1_154R,Color Palette 1 Register 154"
|
|
hexmask.long.byte 0x268 24.--31. 1. " CP1_154A ,Color Palette 1_154 Blend Ratio"
|
|
hexmask.long.byte 0x268 18.--23. 1. " CP1_154R ,Color Palette 1_154 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x268 10.--15. 1. " CP1_154G ,Color Palette 1_154 Green"
|
|
hexmask.long.byte 0x268 2.--7. 1. " CP1_154B ,Color Palette 1_154 Blue"
|
|
line.long 0x26C "CP1_155R,Color Palette 1 Register 155"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " CP1_155A ,Color Palette 1_155 Blend Ratio"
|
|
hexmask.long.byte 0x26C 18.--23. 1. " CP1_155R ,Color Palette 1_155 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x26C 10.--15. 1. " CP1_155G ,Color Palette 1_155 Green"
|
|
hexmask.long.byte 0x26C 2.--7. 1. " CP1_155B ,Color Palette 1_155 Blue"
|
|
line.long 0x270 "CP1_156R,Color Palette 1 Register 156"
|
|
hexmask.long.byte 0x270 24.--31. 1. " CP1_156A ,Color Palette 1_156 Blend Ratio"
|
|
hexmask.long.byte 0x270 18.--23. 1. " CP1_156R ,Color Palette 1_156 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x270 10.--15. 1. " CP1_156G ,Color Palette 1_156 Green"
|
|
hexmask.long.byte 0x270 2.--7. 1. " CP1_156B ,Color Palette 1_156 Blue"
|
|
line.long 0x274 "CP1_157R,Color Palette 1 Register 157"
|
|
hexmask.long.byte 0x274 24.--31. 1. " CP1_157A ,Color Palette 1_157 Blend Ratio"
|
|
hexmask.long.byte 0x274 18.--23. 1. " CP1_157R ,Color Palette 1_157 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x274 10.--15. 1. " CP1_157G ,Color Palette 1_157 Green"
|
|
hexmask.long.byte 0x274 2.--7. 1. " CP1_157B ,Color Palette 1_157 Blue"
|
|
line.long 0x278 "CP1_158R,Color Palette 1 Register 158"
|
|
hexmask.long.byte 0x278 24.--31. 1. " CP1_158A ,Color Palette 1_158 Blend Ratio"
|
|
hexmask.long.byte 0x278 18.--23. 1. " CP1_158R ,Color Palette 1_158 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x278 10.--15. 1. " CP1_158G ,Color Palette 1_158 Green"
|
|
hexmask.long.byte 0x278 2.--7. 1. " CP1_158B ,Color Palette 1_158 Blue"
|
|
line.long 0x27C "CP1_159R,Color Palette 1 Register 159"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " CP1_159A ,Color Palette 1_159 Blend Ratio"
|
|
hexmask.long.byte 0x27C 18.--23. 1. " CP1_159R ,Color Palette 1_159 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x27C 10.--15. 1. " CP1_159G ,Color Palette 1_159 Green"
|
|
hexmask.long.byte 0x27C 2.--7. 1. " CP1_159B ,Color Palette 1_159 Blue"
|
|
line.long 0x280 "CP1_160R,Color Palette 1 Register 160"
|
|
hexmask.long.byte 0x280 24.--31. 1. " CP1_160A ,Color Palette 1_160 Blend Ratio"
|
|
hexmask.long.byte 0x280 18.--23. 1. " CP1_160R ,Color Palette 1_160 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x280 10.--15. 1. " CP1_160G ,Color Palette 1_160 Green"
|
|
hexmask.long.byte 0x280 2.--7. 1. " CP1_160B ,Color Palette 1_160 Blue"
|
|
line.long 0x284 "CP1_161R,Color Palette 1 Register 161"
|
|
hexmask.long.byte 0x284 24.--31. 1. " CP1_161A ,Color Palette 1_161 Blend Ratio"
|
|
hexmask.long.byte 0x284 18.--23. 1. " CP1_161R ,Color Palette 1_161 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x284 10.--15. 1. " CP1_161G ,Color Palette 1_161 Green"
|
|
hexmask.long.byte 0x284 2.--7. 1. " CP1_161B ,Color Palette 1_161 Blue"
|
|
line.long 0x288 "CP1_162R,Color Palette 1 Register 162"
|
|
hexmask.long.byte 0x288 24.--31. 1. " CP1_162A ,Color Palette 1_162 Blend Ratio"
|
|
hexmask.long.byte 0x288 18.--23. 1. " CP1_162R ,Color Palette 1_162 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x288 10.--15. 1. " CP1_162G ,Color Palette 1_162 Green"
|
|
hexmask.long.byte 0x288 2.--7. 1. " CP1_162B ,Color Palette 1_162 Blue"
|
|
line.long 0x28C "CP1_163R,Color Palette 1 Register 163"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " CP1_163A ,Color Palette 1_163 Blend Ratio"
|
|
hexmask.long.byte 0x28C 18.--23. 1. " CP1_163R ,Color Palette 1_163 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28C 10.--15. 1. " CP1_163G ,Color Palette 1_163 Green"
|
|
hexmask.long.byte 0x28C 2.--7. 1. " CP1_163B ,Color Palette 1_163 Blue"
|
|
line.long 0x290 "CP1_164R,Color Palette 1 Register 164"
|
|
hexmask.long.byte 0x290 24.--31. 1. " CP1_164A ,Color Palette 1_164 Blend Ratio"
|
|
hexmask.long.byte 0x290 18.--23. 1. " CP1_164R ,Color Palette 1_164 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x290 10.--15. 1. " CP1_164G ,Color Palette 1_164 Green"
|
|
hexmask.long.byte 0x290 2.--7. 1. " CP1_164B ,Color Palette 1_164 Blue"
|
|
line.long 0x294 "CP1_165R,Color Palette 1 Register 165"
|
|
hexmask.long.byte 0x294 24.--31. 1. " CP1_165A ,Color Palette 1_165 Blend Ratio"
|
|
hexmask.long.byte 0x294 18.--23. 1. " CP1_165R ,Color Palette 1_165 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x294 10.--15. 1. " CP1_165G ,Color Palette 1_165 Green"
|
|
hexmask.long.byte 0x294 2.--7. 1. " CP1_165B ,Color Palette 1_165 Blue"
|
|
line.long 0x298 "CP1_166R,Color Palette 1 Register 166"
|
|
hexmask.long.byte 0x298 24.--31. 1. " CP1_166A ,Color Palette 1_166 Blend Ratio"
|
|
hexmask.long.byte 0x298 18.--23. 1. " CP1_166R ,Color Palette 1_166 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x298 10.--15. 1. " CP1_166G ,Color Palette 1_166 Green"
|
|
hexmask.long.byte 0x298 2.--7. 1. " CP1_166B ,Color Palette 1_166 Blue"
|
|
line.long 0x29C "CP1_167R,Color Palette 1 Register 167"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " CP1_167A ,Color Palette 1_167 Blend Ratio"
|
|
hexmask.long.byte 0x29C 18.--23. 1. " CP1_167R ,Color Palette 1_167 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x29C 10.--15. 1. " CP1_167G ,Color Palette 1_167 Green"
|
|
hexmask.long.byte 0x29C 2.--7. 1. " CP1_167B ,Color Palette 1_167 Blue"
|
|
line.long 0x2A0 "CP1_168R,Color Palette 1 Register 168"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " CP1_168A ,Color Palette 1_168 Blend Ratio"
|
|
hexmask.long.byte 0x2A0 18.--23. 1. " CP1_168R ,Color Palette 1_168 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A0 10.--15. 1. " CP1_168G ,Color Palette 1_168 Green"
|
|
hexmask.long.byte 0x2A0 2.--7. 1. " CP1_168B ,Color Palette 1_168 Blue"
|
|
line.long 0x2A4 "CP1_169R,Color Palette 1 Register 169"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " CP1_169A ,Color Palette 1_169 Blend Ratio"
|
|
hexmask.long.byte 0x2A4 18.--23. 1. " CP1_169R ,Color Palette 1_169 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A4 10.--15. 1. " CP1_169G ,Color Palette 1_169 Green"
|
|
hexmask.long.byte 0x2A4 2.--7. 1. " CP1_169B ,Color Palette 1_169 Blue"
|
|
line.long 0x2A8 "CP1_170R,Color Palette 1 Register 170"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " CP1_170A ,Color Palette 1_170 Blend Ratio"
|
|
hexmask.long.byte 0x2A8 18.--23. 1. " CP1_170R ,Color Palette 1_170 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A8 10.--15. 1. " CP1_170G ,Color Palette 1_170 Green"
|
|
hexmask.long.byte 0x2A8 2.--7. 1. " CP1_170B ,Color Palette 1_170 Blue"
|
|
line.long 0x2AC "CP1_171R,Color Palette 1 Register 171"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " CP1_171A ,Color Palette 1_171 Blend Ratio"
|
|
hexmask.long.byte 0x2AC 18.--23. 1. " CP1_171R ,Color Palette 1_171 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2AC 10.--15. 1. " CP1_171G ,Color Palette 1_171 Green"
|
|
hexmask.long.byte 0x2AC 2.--7. 1. " CP1_171B ,Color Palette 1_171 Blue"
|
|
line.long 0x2B0 "CP1_172R,Color Palette 1 Register 172"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " CP1_172A ,Color Palette 1_172 Blend Ratio"
|
|
hexmask.long.byte 0x2B0 18.--23. 1. " CP1_172R ,Color Palette 1_172 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B0 10.--15. 1. " CP1_172G ,Color Palette 1_172 Green"
|
|
hexmask.long.byte 0x2B0 2.--7. 1. " CP1_172B ,Color Palette 1_172 Blue"
|
|
line.long 0x2B4 "CP1_173R,Color Palette 1 Register 173"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " CP1_173A ,Color Palette 1_173 Blend Ratio"
|
|
hexmask.long.byte 0x2B4 18.--23. 1. " CP1_173R ,Color Palette 1_173 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B4 10.--15. 1. " CP1_173G ,Color Palette 1_173 Green"
|
|
hexmask.long.byte 0x2B4 2.--7. 1. " CP1_173B ,Color Palette 1_173 Blue"
|
|
line.long 0x2B8 "CP1_174R,Color Palette 1 Register 174"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " CP1_174A ,Color Palette 1_174 Blend Ratio"
|
|
hexmask.long.byte 0x2B8 18.--23. 1. " CP1_174R ,Color Palette 1_174 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B8 10.--15. 1. " CP1_174G ,Color Palette 1_174 Green"
|
|
hexmask.long.byte 0x2B8 2.--7. 1. " CP1_174B ,Color Palette 1_174 Blue"
|
|
line.long 0x2BC "CP1_175R,Color Palette 1 Register 175"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " CP1_175A ,Color Palette 1_175 Blend Ratio"
|
|
hexmask.long.byte 0x2BC 18.--23. 1. " CP1_175R ,Color Palette 1_175 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2BC 10.--15. 1. " CP1_175G ,Color Palette 1_175 Green"
|
|
hexmask.long.byte 0x2BC 2.--7. 1. " CP1_175B ,Color Palette 1_175 Blue"
|
|
line.long 0x2C0 "CP1_176R,Color Palette 1 Register 176"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " CP1_176A ,Color Palette 1_176 Blend Ratio"
|
|
hexmask.long.byte 0x2C0 18.--23. 1. " CP1_176R ,Color Palette 1_176 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C0 10.--15. 1. " CP1_176G ,Color Palette 1_176 Green"
|
|
hexmask.long.byte 0x2C0 2.--7. 1. " CP1_176B ,Color Palette 1_176 Blue"
|
|
line.long 0x2C4 "CP1_177R,Color Palette 1 Register 177"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " CP1_177A ,Color Palette 1_177 Blend Ratio"
|
|
hexmask.long.byte 0x2C4 18.--23. 1. " CP1_177R ,Color Palette 1_177 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C4 10.--15. 1. " CP1_177G ,Color Palette 1_177 Green"
|
|
hexmask.long.byte 0x2C4 2.--7. 1. " CP1_177B ,Color Palette 1_177 Blue"
|
|
line.long 0x2C8 "CP1_178R,Color Palette 1 Register 178"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " CP1_178A ,Color Palette 1_178 Blend Ratio"
|
|
hexmask.long.byte 0x2C8 18.--23. 1. " CP1_178R ,Color Palette 1_178 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C8 10.--15. 1. " CP1_178G ,Color Palette 1_178 Green"
|
|
hexmask.long.byte 0x2C8 2.--7. 1. " CP1_178B ,Color Palette 1_178 Blue"
|
|
line.long 0x2CC "CP1_179R,Color Palette 1 Register 179"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " CP1_179A ,Color Palette 1_179 Blend Ratio"
|
|
hexmask.long.byte 0x2CC 18.--23. 1. " CP1_179R ,Color Palette 1_179 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2CC 10.--15. 1. " CP1_179G ,Color Palette 1_179 Green"
|
|
hexmask.long.byte 0x2CC 2.--7. 1. " CP1_179B ,Color Palette 1_179 Blue"
|
|
line.long 0x2D0 "CP1_180R,Color Palette 1 Register 180"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " CP1_180A ,Color Palette 1_180 Blend Ratio"
|
|
hexmask.long.byte 0x2D0 18.--23. 1. " CP1_180R ,Color Palette 1_180 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D0 10.--15. 1. " CP1_180G ,Color Palette 1_180 Green"
|
|
hexmask.long.byte 0x2D0 2.--7. 1. " CP1_180B ,Color Palette 1_180 Blue"
|
|
line.long 0x2D4 "CP1_181R,Color Palette 1 Register 181"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " CP1_181A ,Color Palette 1_181 Blend Ratio"
|
|
hexmask.long.byte 0x2D4 18.--23. 1. " CP1_181R ,Color Palette 1_181 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D4 10.--15. 1. " CP1_181G ,Color Palette 1_181 Green"
|
|
hexmask.long.byte 0x2D4 2.--7. 1. " CP1_181B ,Color Palette 1_181 Blue"
|
|
line.long 0x2D8 "CP1_182R,Color Palette 1 Register 182"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " CP1_182A ,Color Palette 1_182 Blend Ratio"
|
|
hexmask.long.byte 0x2D8 18.--23. 1. " CP1_182R ,Color Palette 1_182 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D8 10.--15. 1. " CP1_182G ,Color Palette 1_182 Green"
|
|
hexmask.long.byte 0x2D8 2.--7. 1. " CP1_182B ,Color Palette 1_182 Blue"
|
|
line.long 0x2DC "CP1_183R,Color Palette 1 Register 183"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " CP1_183A ,Color Palette 1_183 Blend Ratio"
|
|
hexmask.long.byte 0x2DC 18.--23. 1. " CP1_183R ,Color Palette 1_183 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2DC 10.--15. 1. " CP1_183G ,Color Palette 1_183 Green"
|
|
hexmask.long.byte 0x2DC 2.--7. 1. " CP1_183B ,Color Palette 1_183 Blue"
|
|
line.long 0x2E0 "CP1_184R,Color Palette 1 Register 184"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " CP1_184A ,Color Palette 1_184 Blend Ratio"
|
|
hexmask.long.byte 0x2E0 18.--23. 1. " CP1_184R ,Color Palette 1_184 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E0 10.--15. 1. " CP1_184G ,Color Palette 1_184 Green"
|
|
hexmask.long.byte 0x2E0 2.--7. 1. " CP1_184B ,Color Palette 1_184 Blue"
|
|
line.long 0x2E4 "CP1_185R,Color Palette 1 Register 185"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " CP1_185A ,Color Palette 1_185 Blend Ratio"
|
|
hexmask.long.byte 0x2E4 18.--23. 1. " CP1_185R ,Color Palette 1_185 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E4 10.--15. 1. " CP1_185G ,Color Palette 1_185 Green"
|
|
hexmask.long.byte 0x2E4 2.--7. 1. " CP1_185B ,Color Palette 1_185 Blue"
|
|
line.long 0x2E8 "CP1_186R,Color Palette 1 Register 186"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " CP1_186A ,Color Palette 1_186 Blend Ratio"
|
|
hexmask.long.byte 0x2E8 18.--23. 1. " CP1_186R ,Color Palette 1_186 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E8 10.--15. 1. " CP1_186G ,Color Palette 1_186 Green"
|
|
hexmask.long.byte 0x2E8 2.--7. 1. " CP1_186B ,Color Palette 1_186 Blue"
|
|
line.long 0x2EC "CP1_187R,Color Palette 1 Register 187"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " CP1_187A ,Color Palette 1_187 Blend Ratio"
|
|
hexmask.long.byte 0x2EC 18.--23. 1. " CP1_187R ,Color Palette 1_187 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2EC 10.--15. 1. " CP1_187G ,Color Palette 1_187 Green"
|
|
hexmask.long.byte 0x2EC 2.--7. 1. " CP1_187B ,Color Palette 1_187 Blue"
|
|
line.long 0x2F0 "CP1_188R,Color Palette 1 Register 188"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " CP1_188A ,Color Palette 1_188 Blend Ratio"
|
|
hexmask.long.byte 0x2F0 18.--23. 1. " CP1_188R ,Color Palette 1_188 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F0 10.--15. 1. " CP1_188G ,Color Palette 1_188 Green"
|
|
hexmask.long.byte 0x2F0 2.--7. 1. " CP1_188B ,Color Palette 1_188 Blue"
|
|
line.long 0x2F4 "CP1_189R,Color Palette 1 Register 189"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " CP1_189A ,Color Palette 1_189 Blend Ratio"
|
|
hexmask.long.byte 0x2F4 18.--23. 1. " CP1_189R ,Color Palette 1_189 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F4 10.--15. 1. " CP1_189G ,Color Palette 1_189 Green"
|
|
hexmask.long.byte 0x2F4 2.--7. 1. " CP1_189B ,Color Palette 1_189 Blue"
|
|
line.long 0x2F8 "CP1_190R,Color Palette 1 Register 190"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " CP1_190A ,Color Palette 1_190 Blend Ratio"
|
|
hexmask.long.byte 0x2F8 18.--23. 1. " CP1_190R ,Color Palette 1_190 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F8 10.--15. 1. " CP1_190G ,Color Palette 1_190 Green"
|
|
hexmask.long.byte 0x2F8 2.--7. 1. " CP1_190B ,Color Palette 1_190 Blue"
|
|
line.long 0x2FC "CP1_191R,Color Palette 1 Register 191"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " CP1_191A ,Color Palette 1_191 Blend Ratio"
|
|
hexmask.long.byte 0x2FC 18.--23. 1. " CP1_191R ,Color Palette 1_191 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2FC 10.--15. 1. " CP1_191G ,Color Palette 1_191 Green"
|
|
hexmask.long.byte 0x2FC 2.--7. 1. " CP1_191B ,Color Palette 1_191 Blue"
|
|
line.long 0x300 "CP1_192R,Color Palette 1 Register 192"
|
|
hexmask.long.byte 0x300 24.--31. 1. " CP1_192A ,Color Palette 1_192 Blend Ratio"
|
|
hexmask.long.byte 0x300 18.--23. 1. " CP1_192R ,Color Palette 1_192 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x300 10.--15. 1. " CP1_192G ,Color Palette 1_192 Green"
|
|
hexmask.long.byte 0x300 2.--7. 1. " CP1_192B ,Color Palette 1_192 Blue"
|
|
line.long 0x304 "CP1_193R,Color Palette 1 Register 193"
|
|
hexmask.long.byte 0x304 24.--31. 1. " CP1_193A ,Color Palette 1_193 Blend Ratio"
|
|
hexmask.long.byte 0x304 18.--23. 1. " CP1_193R ,Color Palette 1_193 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x304 10.--15. 1. " CP1_193G ,Color Palette 1_193 Green"
|
|
hexmask.long.byte 0x304 2.--7. 1. " CP1_193B ,Color Palette 1_193 Blue"
|
|
line.long 0x308 "CP1_194R,Color Palette 1 Register 194"
|
|
hexmask.long.byte 0x308 24.--31. 1. " CP1_194A ,Color Palette 1_194 Blend Ratio"
|
|
hexmask.long.byte 0x308 18.--23. 1. " CP1_194R ,Color Palette 1_194 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x308 10.--15. 1. " CP1_194G ,Color Palette 1_194 Green"
|
|
hexmask.long.byte 0x308 2.--7. 1. " CP1_194B ,Color Palette 1_194 Blue"
|
|
line.long 0x30C "CP1_195R,Color Palette 1 Register 195"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " CP1_195A ,Color Palette 1_195 Blend Ratio"
|
|
hexmask.long.byte 0x30C 18.--23. 1. " CP1_195R ,Color Palette 1_195 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30C 10.--15. 1. " CP1_195G ,Color Palette 1_195 Green"
|
|
hexmask.long.byte 0x30C 2.--7. 1. " CP1_195B ,Color Palette 1_195 Blue"
|
|
line.long 0x310 "CP1_196R,Color Palette 1 Register 196"
|
|
hexmask.long.byte 0x310 24.--31. 1. " CP1_196A ,Color Palette 1_196 Blend Ratio"
|
|
hexmask.long.byte 0x310 18.--23. 1. " CP1_196R ,Color Palette 1_196 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x310 10.--15. 1. " CP1_196G ,Color Palette 1_196 Green"
|
|
hexmask.long.byte 0x310 2.--7. 1. " CP1_196B ,Color Palette 1_196 Blue"
|
|
line.long 0x314 "CP1_197R,Color Palette 1 Register 197"
|
|
hexmask.long.byte 0x314 24.--31. 1. " CP1_197A ,Color Palette 1_197 Blend Ratio"
|
|
hexmask.long.byte 0x314 18.--23. 1. " CP1_197R ,Color Palette 1_197 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x314 10.--15. 1. " CP1_197G ,Color Palette 1_197 Green"
|
|
hexmask.long.byte 0x314 2.--7. 1. " CP1_197B ,Color Palette 1_197 Blue"
|
|
line.long 0x318 "CP1_198R,Color Palette 1 Register 198"
|
|
hexmask.long.byte 0x318 24.--31. 1. " CP1_198A ,Color Palette 1_198 Blend Ratio"
|
|
hexmask.long.byte 0x318 18.--23. 1. " CP1_198R ,Color Palette 1_198 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x318 10.--15. 1. " CP1_198G ,Color Palette 1_198 Green"
|
|
hexmask.long.byte 0x318 2.--7. 1. " CP1_198B ,Color Palette 1_198 Blue"
|
|
line.long 0x31C "CP1_199R,Color Palette 1 Register 199"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " CP1_199A ,Color Palette 1_199 Blend Ratio"
|
|
hexmask.long.byte 0x31C 18.--23. 1. " CP1_199R ,Color Palette 1_199 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x31C 10.--15. 1. " CP1_199G ,Color Palette 1_199 Green"
|
|
hexmask.long.byte 0x31C 2.--7. 1. " CP1_199B ,Color Palette 1_199 Blue"
|
|
line.long 0x320 "CP1_200R,Color Palette 1 Register 200"
|
|
hexmask.long.byte 0x320 24.--31. 1. " CP1_200A ,Color Palette 1_200 Blend Ratio"
|
|
hexmask.long.byte 0x320 18.--23. 1. " CP1_200R ,Color Palette 1_200 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x320 10.--15. 1. " CP1_200G ,Color Palette 1_200 Green"
|
|
hexmask.long.byte 0x320 2.--7. 1. " CP1_200B ,Color Palette 1_200 Blue"
|
|
line.long 0x324 "CP1_201R,Color Palette 1 Register 201"
|
|
hexmask.long.byte 0x324 24.--31. 1. " CP1_201A ,Color Palette 1_201 Blend Ratio"
|
|
hexmask.long.byte 0x324 18.--23. 1. " CP1_201R ,Color Palette 1_201 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x324 10.--15. 1. " CP1_201G ,Color Palette 1_201 Green"
|
|
hexmask.long.byte 0x324 2.--7. 1. " CP1_201B ,Color Palette 1_201 Blue"
|
|
line.long 0x328 "CP1_202R,Color Palette 1 Register 202"
|
|
hexmask.long.byte 0x328 24.--31. 1. " CP1_202A ,Color Palette 1_202 Blend Ratio"
|
|
hexmask.long.byte 0x328 18.--23. 1. " CP1_202R ,Color Palette 1_202 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x328 10.--15. 1. " CP1_202G ,Color Palette 1_202 Green"
|
|
hexmask.long.byte 0x328 2.--7. 1. " CP1_202B ,Color Palette 1_202 Blue"
|
|
line.long 0x32C "CP1_203R,Color Palette 1 Register 203"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " CP1_203A ,Color Palette 1_203 Blend Ratio"
|
|
hexmask.long.byte 0x32C 18.--23. 1. " CP1_203R ,Color Palette 1_203 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x32C 10.--15. 1. " CP1_203G ,Color Palette 1_203 Green"
|
|
hexmask.long.byte 0x32C 2.--7. 1. " CP1_203B ,Color Palette 1_203 Blue"
|
|
line.long 0x330 "CP1_204R,Color Palette 1 Register 204"
|
|
hexmask.long.byte 0x330 24.--31. 1. " CP1_204A ,Color Palette 1_204 Blend Ratio"
|
|
hexmask.long.byte 0x330 18.--23. 1. " CP1_204R ,Color Palette 1_204 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x330 10.--15. 1. " CP1_204G ,Color Palette 1_204 Green"
|
|
hexmask.long.byte 0x330 2.--7. 1. " CP1_204B ,Color Palette 1_204 Blue"
|
|
line.long 0x334 "CP1_205R,Color Palette 1 Register 205"
|
|
hexmask.long.byte 0x334 24.--31. 1. " CP1_205A ,Color Palette 1_205 Blend Ratio"
|
|
hexmask.long.byte 0x334 18.--23. 1. " CP1_205R ,Color Palette 1_205 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x334 10.--15. 1. " CP1_205G ,Color Palette 1_205 Green"
|
|
hexmask.long.byte 0x334 2.--7. 1. " CP1_205B ,Color Palette 1_205 Blue"
|
|
line.long 0x338 "CP1_206R,Color Palette 1 Register 206"
|
|
hexmask.long.byte 0x338 24.--31. 1. " CP1_206A ,Color Palette 1_206 Blend Ratio"
|
|
hexmask.long.byte 0x338 18.--23. 1. " CP1_206R ,Color Palette 1_206 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x338 10.--15. 1. " CP1_206G ,Color Palette 1_206 Green"
|
|
hexmask.long.byte 0x338 2.--7. 1. " CP1_206B ,Color Palette 1_206 Blue"
|
|
line.long 0x33C "CP1_207R,Color Palette 1 Register 207"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " CP1_207A ,Color Palette 1_207 Blend Ratio"
|
|
hexmask.long.byte 0x33C 18.--23. 1. " CP1_207R ,Color Palette 1_207 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x33C 10.--15. 1. " CP1_207G ,Color Palette 1_207 Green"
|
|
hexmask.long.byte 0x33C 2.--7. 1. " CP1_207B ,Color Palette 1_207 Blue"
|
|
line.long 0x340 "CP1_208R,Color Palette 1 Register 208"
|
|
hexmask.long.byte 0x340 24.--31. 1. " CP1_208A ,Color Palette 1_208 Blend Ratio"
|
|
hexmask.long.byte 0x340 18.--23. 1. " CP1_208R ,Color Palette 1_208 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x340 10.--15. 1. " CP1_208G ,Color Palette 1_208 Green"
|
|
hexmask.long.byte 0x340 2.--7. 1. " CP1_208B ,Color Palette 1_208 Blue"
|
|
line.long 0x344 "CP1_209R,Color Palette 1 Register 209"
|
|
hexmask.long.byte 0x344 24.--31. 1. " CP1_209A ,Color Palette 1_209 Blend Ratio"
|
|
hexmask.long.byte 0x344 18.--23. 1. " CP1_209R ,Color Palette 1_209 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x344 10.--15. 1. " CP1_209G ,Color Palette 1_209 Green"
|
|
hexmask.long.byte 0x344 2.--7. 1. " CP1_209B ,Color Palette 1_209 Blue"
|
|
line.long 0x348 "CP1_210R,Color Palette 1 Register 210"
|
|
hexmask.long.byte 0x348 24.--31. 1. " CP1_210A ,Color Palette 1_210 Blend Ratio"
|
|
hexmask.long.byte 0x348 18.--23. 1. " CP1_210R ,Color Palette 1_210 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x348 10.--15. 1. " CP1_210G ,Color Palette 1_210 Green"
|
|
hexmask.long.byte 0x348 2.--7. 1. " CP1_210B ,Color Palette 1_210 Blue"
|
|
line.long 0x34C "CP1_211R,Color Palette 1 Register 211"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " CP1_211A ,Color Palette 1_211 Blend Ratio"
|
|
hexmask.long.byte 0x34C 18.--23. 1. " CP1_211R ,Color Palette 1_211 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34C 10.--15. 1. " CP1_211G ,Color Palette 1_211 Green"
|
|
hexmask.long.byte 0x34C 2.--7. 1. " CP1_211B ,Color Palette 1_211 Blue"
|
|
line.long 0x350 "CP1_212R,Color Palette 1 Register 212"
|
|
hexmask.long.byte 0x350 24.--31. 1. " CP1_212A ,Color Palette 1_212 Blend Ratio"
|
|
hexmask.long.byte 0x350 18.--23. 1. " CP1_212R ,Color Palette 1_212 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x350 10.--15. 1. " CP1_212G ,Color Palette 1_212 Green"
|
|
hexmask.long.byte 0x350 2.--7. 1. " CP1_212B ,Color Palette 1_212 Blue"
|
|
line.long 0x354 "CP1_213R,Color Palette 1 Register 213"
|
|
hexmask.long.byte 0x354 24.--31. 1. " CP1_213A ,Color Palette 1_213 Blend Ratio"
|
|
hexmask.long.byte 0x354 18.--23. 1. " CP1_213R ,Color Palette 1_213 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x354 10.--15. 1. " CP1_213G ,Color Palette 1_213 Green"
|
|
hexmask.long.byte 0x354 2.--7. 1. " CP1_213B ,Color Palette 1_213 Blue"
|
|
line.long 0x358 "CP1_214R,Color Palette 1 Register 214"
|
|
hexmask.long.byte 0x358 24.--31. 1. " CP1_214A ,Color Palette 1_214 Blend Ratio"
|
|
hexmask.long.byte 0x358 18.--23. 1. " CP1_214R ,Color Palette 1_214 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x358 10.--15. 1. " CP1_214G ,Color Palette 1_214 Green"
|
|
hexmask.long.byte 0x358 2.--7. 1. " CP1_214B ,Color Palette 1_214 Blue"
|
|
line.long 0x35C "CP1_215R,Color Palette 1 Register 215"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " CP1_215A ,Color Palette 1_215 Blend Ratio"
|
|
hexmask.long.byte 0x35C 18.--23. 1. " CP1_215R ,Color Palette 1_215 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x35C 10.--15. 1. " CP1_215G ,Color Palette 1_215 Green"
|
|
hexmask.long.byte 0x35C 2.--7. 1. " CP1_215B ,Color Palette 1_215 Blue"
|
|
line.long 0x360 "CP1_216R,Color Palette 1 Register 216"
|
|
hexmask.long.byte 0x360 24.--31. 1. " CP1_216A ,Color Palette 1_216 Blend Ratio"
|
|
hexmask.long.byte 0x360 18.--23. 1. " CP1_216R ,Color Palette 1_216 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x360 10.--15. 1. " CP1_216G ,Color Palette 1_216 Green"
|
|
hexmask.long.byte 0x360 2.--7. 1. " CP1_216B ,Color Palette 1_216 Blue"
|
|
line.long 0x364 "CP1_217R,Color Palette 1 Register 217"
|
|
hexmask.long.byte 0x364 24.--31. 1. " CP1_217A ,Color Palette 1_217 Blend Ratio"
|
|
hexmask.long.byte 0x364 18.--23. 1. " CP1_217R ,Color Palette 1_217 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x364 10.--15. 1. " CP1_217G ,Color Palette 1_217 Green"
|
|
hexmask.long.byte 0x364 2.--7. 1. " CP1_217B ,Color Palette 1_217 Blue"
|
|
line.long 0x368 "CP1_218R,Color Palette 1 Register 218"
|
|
hexmask.long.byte 0x368 24.--31. 1. " CP1_218A ,Color Palette 1_218 Blend Ratio"
|
|
hexmask.long.byte 0x368 18.--23. 1. " CP1_218R ,Color Palette 1_218 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x368 10.--15. 1. " CP1_218G ,Color Palette 1_218 Green"
|
|
hexmask.long.byte 0x368 2.--7. 1. " CP1_218B ,Color Palette 1_218 Blue"
|
|
line.long 0x36C "CP1_219R,Color Palette 1 Register 219"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " CP1_219A ,Color Palette 1_219 Blend Ratio"
|
|
hexmask.long.byte 0x36C 18.--23. 1. " CP1_219R ,Color Palette 1_219 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x36C 10.--15. 1. " CP1_219G ,Color Palette 1_219 Green"
|
|
hexmask.long.byte 0x36C 2.--7. 1. " CP1_219B ,Color Palette 1_219 Blue"
|
|
line.long 0x370 "CP1_220R,Color Palette 1 Register 220"
|
|
hexmask.long.byte 0x370 24.--31. 1. " CP1_220A ,Color Palette 1_220 Blend Ratio"
|
|
hexmask.long.byte 0x370 18.--23. 1. " CP1_220R ,Color Palette 1_220 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x370 10.--15. 1. " CP1_220G ,Color Palette 1_220 Green"
|
|
hexmask.long.byte 0x370 2.--7. 1. " CP1_220B ,Color Palette 1_220 Blue"
|
|
line.long 0x374 "CP1_221R,Color Palette 1 Register 221"
|
|
hexmask.long.byte 0x374 24.--31. 1. " CP1_221A ,Color Palette 1_221 Blend Ratio"
|
|
hexmask.long.byte 0x374 18.--23. 1. " CP1_221R ,Color Palette 1_221 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x374 10.--15. 1. " CP1_221G ,Color Palette 1_221 Green"
|
|
hexmask.long.byte 0x374 2.--7. 1. " CP1_221B ,Color Palette 1_221 Blue"
|
|
line.long 0x378 "CP1_222R,Color Palette 1 Register 222"
|
|
hexmask.long.byte 0x378 24.--31. 1. " CP1_222A ,Color Palette 1_222 Blend Ratio"
|
|
hexmask.long.byte 0x378 18.--23. 1. " CP1_222R ,Color Palette 1_222 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x378 10.--15. 1. " CP1_222G ,Color Palette 1_222 Green"
|
|
hexmask.long.byte 0x378 2.--7. 1. " CP1_222B ,Color Palette 1_222 Blue"
|
|
line.long 0x37C "CP1_223R,Color Palette 1 Register 223"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " CP1_223A ,Color Palette 1_223 Blend Ratio"
|
|
hexmask.long.byte 0x37C 18.--23. 1. " CP1_223R ,Color Palette 1_223 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x37C 10.--15. 1. " CP1_223G ,Color Palette 1_223 Green"
|
|
hexmask.long.byte 0x37C 2.--7. 1. " CP1_223B ,Color Palette 1_223 Blue"
|
|
line.long 0x380 "CP1_224R,Color Palette 1 Register 224"
|
|
hexmask.long.byte 0x380 24.--31. 1. " CP1_224A ,Color Palette 1_224 Blend Ratio"
|
|
hexmask.long.byte 0x380 18.--23. 1. " CP1_224R ,Color Palette 1_224 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x380 10.--15. 1. " CP1_224G ,Color Palette 1_224 Green"
|
|
hexmask.long.byte 0x380 2.--7. 1. " CP1_224B ,Color Palette 1_224 Blue"
|
|
line.long 0x384 "CP1_225R,Color Palette 1 Register 225"
|
|
hexmask.long.byte 0x384 24.--31. 1. " CP1_225A ,Color Palette 1_225 Blend Ratio"
|
|
hexmask.long.byte 0x384 18.--23. 1. " CP1_225R ,Color Palette 1_225 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x384 10.--15. 1. " CP1_225G ,Color Palette 1_225 Green"
|
|
hexmask.long.byte 0x384 2.--7. 1. " CP1_225B ,Color Palette 1_225 Blue"
|
|
line.long 0x388 "CP1_226R,Color Palette 1 Register 226"
|
|
hexmask.long.byte 0x388 24.--31. 1. " CP1_226A ,Color Palette 1_226 Blend Ratio"
|
|
hexmask.long.byte 0x388 18.--23. 1. " CP1_226R ,Color Palette 1_226 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x388 10.--15. 1. " CP1_226G ,Color Palette 1_226 Green"
|
|
hexmask.long.byte 0x388 2.--7. 1. " CP1_226B ,Color Palette 1_226 Blue"
|
|
line.long 0x38C "CP1_227R,Color Palette 1 Register 227"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " CP1_227A ,Color Palette 1_227 Blend Ratio"
|
|
hexmask.long.byte 0x38C 18.--23. 1. " CP1_227R ,Color Palette 1_227 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38C 10.--15. 1. " CP1_227G ,Color Palette 1_227 Green"
|
|
hexmask.long.byte 0x38C 2.--7. 1. " CP1_227B ,Color Palette 1_227 Blue"
|
|
line.long 0x390 "CP1_228R,Color Palette 1 Register 228"
|
|
hexmask.long.byte 0x390 24.--31. 1. " CP1_228A ,Color Palette 1_228 Blend Ratio"
|
|
hexmask.long.byte 0x390 18.--23. 1. " CP1_228R ,Color Palette 1_228 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x390 10.--15. 1. " CP1_228G ,Color Palette 1_228 Green"
|
|
hexmask.long.byte 0x390 2.--7. 1. " CP1_228B ,Color Palette 1_228 Blue"
|
|
line.long 0x394 "CP1_229R,Color Palette 1 Register 229"
|
|
hexmask.long.byte 0x394 24.--31. 1. " CP1_229A ,Color Palette 1_229 Blend Ratio"
|
|
hexmask.long.byte 0x394 18.--23. 1. " CP1_229R ,Color Palette 1_229 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x394 10.--15. 1. " CP1_229G ,Color Palette 1_229 Green"
|
|
hexmask.long.byte 0x394 2.--7. 1. " CP1_229B ,Color Palette 1_229 Blue"
|
|
line.long 0x398 "CP1_230R,Color Palette 1 Register 230"
|
|
hexmask.long.byte 0x398 24.--31. 1. " CP1_230A ,Color Palette 1_230 Blend Ratio"
|
|
hexmask.long.byte 0x398 18.--23. 1. " CP1_230R ,Color Palette 1_230 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x398 10.--15. 1. " CP1_230G ,Color Palette 1_230 Green"
|
|
hexmask.long.byte 0x398 2.--7. 1. " CP1_230B ,Color Palette 1_230 Blue"
|
|
line.long 0x39C "CP1_231R,Color Palette 1 Register 231"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " CP1_231A ,Color Palette 1_231 Blend Ratio"
|
|
hexmask.long.byte 0x39C 18.--23. 1. " CP1_231R ,Color Palette 1_231 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x39C 10.--15. 1. " CP1_231G ,Color Palette 1_231 Green"
|
|
hexmask.long.byte 0x39C 2.--7. 1. " CP1_231B ,Color Palette 1_231 Blue"
|
|
line.long 0x3A0 "CP1_232R,Color Palette 1 Register 232"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " CP1_232A ,Color Palette 1_232 Blend Ratio"
|
|
hexmask.long.byte 0x3A0 18.--23. 1. " CP1_232R ,Color Palette 1_232 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A0 10.--15. 1. " CP1_232G ,Color Palette 1_232 Green"
|
|
hexmask.long.byte 0x3A0 2.--7. 1. " CP1_232B ,Color Palette 1_232 Blue"
|
|
line.long 0x3A4 "CP1_233R,Color Palette 1 Register 233"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " CP1_233A ,Color Palette 1_233 Blend Ratio"
|
|
hexmask.long.byte 0x3A4 18.--23. 1. " CP1_233R ,Color Palette 1_233 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A4 10.--15. 1. " CP1_233G ,Color Palette 1_233 Green"
|
|
hexmask.long.byte 0x3A4 2.--7. 1. " CP1_233B ,Color Palette 1_233 Blue"
|
|
line.long 0x3A8 "CP1_234R,Color Palette 1 Register 234"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " CP1_234A ,Color Palette 1_234 Blend Ratio"
|
|
hexmask.long.byte 0x3A8 18.--23. 1. " CP1_234R ,Color Palette 1_234 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A8 10.--15. 1. " CP1_234G ,Color Palette 1_234 Green"
|
|
hexmask.long.byte 0x3A8 2.--7. 1. " CP1_234B ,Color Palette 1_234 Blue"
|
|
line.long 0x3AC "CP1_235R,Color Palette 1 Register 235"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " CP1_235A ,Color Palette 1_235 Blend Ratio"
|
|
hexmask.long.byte 0x3AC 18.--23. 1. " CP1_235R ,Color Palette 1_235 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3AC 10.--15. 1. " CP1_235G ,Color Palette 1_235 Green"
|
|
hexmask.long.byte 0x3AC 2.--7. 1. " CP1_235B ,Color Palette 1_235 Blue"
|
|
line.long 0x3B0 "CP1_236R,Color Palette 1 Register 236"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " CP1_236A ,Color Palette 1_236 Blend Ratio"
|
|
hexmask.long.byte 0x3B0 18.--23. 1. " CP1_236R ,Color Palette 1_236 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B0 10.--15. 1. " CP1_236G ,Color Palette 1_236 Green"
|
|
hexmask.long.byte 0x3B0 2.--7. 1. " CP1_236B ,Color Palette 1_236 Blue"
|
|
line.long 0x3B4 "CP1_237R,Color Palette 1 Register 237"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " CP1_237A ,Color Palette 1_237 Blend Ratio"
|
|
hexmask.long.byte 0x3B4 18.--23. 1. " CP1_237R ,Color Palette 1_237 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B4 10.--15. 1. " CP1_237G ,Color Palette 1_237 Green"
|
|
hexmask.long.byte 0x3B4 2.--7. 1. " CP1_237B ,Color Palette 1_237 Blue"
|
|
line.long 0x3B8 "CP1_238R,Color Palette 1 Register 238"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " CP1_238A ,Color Palette 1_238 Blend Ratio"
|
|
hexmask.long.byte 0x3B8 18.--23. 1. " CP1_238R ,Color Palette 1_238 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B8 10.--15. 1. " CP1_238G ,Color Palette 1_238 Green"
|
|
hexmask.long.byte 0x3B8 2.--7. 1. " CP1_238B ,Color Palette 1_238 Blue"
|
|
line.long 0x3BC "CP1_239R,Color Palette 1 Register 239"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " CP1_239A ,Color Palette 1_239 Blend Ratio"
|
|
hexmask.long.byte 0x3BC 18.--23. 1. " CP1_239R ,Color Palette 1_239 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3BC 10.--15. 1. " CP1_239G ,Color Palette 1_239 Green"
|
|
hexmask.long.byte 0x3BC 2.--7. 1. " CP1_239B ,Color Palette 1_239 Blue"
|
|
line.long 0x3C0 "CP1_240R,Color Palette 1 Register 240"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " CP1_240A ,Color Palette 1_240 Blend Ratio"
|
|
hexmask.long.byte 0x3C0 18.--23. 1. " CP1_240R ,Color Palette 1_240 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C0 10.--15. 1. " CP1_240G ,Color Palette 1_240 Green"
|
|
hexmask.long.byte 0x3C0 2.--7. 1. " CP1_240B ,Color Palette 1_240 Blue"
|
|
line.long 0x3C4 "CP1_241R,Color Palette 1 Register 241"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " CP1_241A ,Color Palette 1_241 Blend Ratio"
|
|
hexmask.long.byte 0x3C4 18.--23. 1. " CP1_241R ,Color Palette 1_241 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C4 10.--15. 1. " CP1_241G ,Color Palette 1_241 Green"
|
|
hexmask.long.byte 0x3C4 2.--7. 1. " CP1_241B ,Color Palette 1_241 Blue"
|
|
line.long 0x3C8 "CP1_242R,Color Palette 1 Register 242"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " CP1_242A ,Color Palette 1_242 Blend Ratio"
|
|
hexmask.long.byte 0x3C8 18.--23. 1. " CP1_242R ,Color Palette 1_242 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C8 10.--15. 1. " CP1_242G ,Color Palette 1_242 Green"
|
|
hexmask.long.byte 0x3C8 2.--7. 1. " CP1_242B ,Color Palette 1_242 Blue"
|
|
line.long 0x3CC "CP1_243R,Color Palette 1 Register 243"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " CP1_243A ,Color Palette 1_243 Blend Ratio"
|
|
hexmask.long.byte 0x3CC 18.--23. 1. " CP1_243R ,Color Palette 1_243 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3CC 10.--15. 1. " CP1_243G ,Color Palette 1_243 Green"
|
|
hexmask.long.byte 0x3CC 2.--7. 1. " CP1_243B ,Color Palette 1_243 Blue"
|
|
line.long 0x3D0 "CP1_244R,Color Palette 1 Register 244"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " CP1_244A ,Color Palette 1_244 Blend Ratio"
|
|
hexmask.long.byte 0x3D0 18.--23. 1. " CP1_244R ,Color Palette 1_244 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D0 10.--15. 1. " CP1_244G ,Color Palette 1_244 Green"
|
|
hexmask.long.byte 0x3D0 2.--7. 1. " CP1_244B ,Color Palette 1_244 Blue"
|
|
line.long 0x3D4 "CP1_245R,Color Palette 1 Register 245"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " CP1_245A ,Color Palette 1_245 Blend Ratio"
|
|
hexmask.long.byte 0x3D4 18.--23. 1. " CP1_245R ,Color Palette 1_245 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D4 10.--15. 1. " CP1_245G ,Color Palette 1_245 Green"
|
|
hexmask.long.byte 0x3D4 2.--7. 1. " CP1_245B ,Color Palette 1_245 Blue"
|
|
line.long 0x3D8 "CP1_246R,Color Palette 1 Register 246"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " CP1_246A ,Color Palette 1_246 Blend Ratio"
|
|
hexmask.long.byte 0x3D8 18.--23. 1. " CP1_246R ,Color Palette 1_246 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D8 10.--15. 1. " CP1_246G ,Color Palette 1_246 Green"
|
|
hexmask.long.byte 0x3D8 2.--7. 1. " CP1_246B ,Color Palette 1_246 Blue"
|
|
line.long 0x3DC "CP1_247R,Color Palette 1 Register 247"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " CP1_247A ,Color Palette 1_247 Blend Ratio"
|
|
hexmask.long.byte 0x3DC 18.--23. 1. " CP1_247R ,Color Palette 1_247 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3DC 10.--15. 1. " CP1_247G ,Color Palette 1_247 Green"
|
|
hexmask.long.byte 0x3DC 2.--7. 1. " CP1_247B ,Color Palette 1_247 Blue"
|
|
line.long 0x3E0 "CP1_248R,Color Palette 1 Register 248"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " CP1_248A ,Color Palette 1_248 Blend Ratio"
|
|
hexmask.long.byte 0x3E0 18.--23. 1. " CP1_248R ,Color Palette 1_248 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E0 10.--15. 1. " CP1_248G ,Color Palette 1_248 Green"
|
|
hexmask.long.byte 0x3E0 2.--7. 1. " CP1_248B ,Color Palette 1_248 Blue"
|
|
line.long 0x3E4 "CP1_249R,Color Palette 1 Register 249"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " CP1_249A ,Color Palette 1_249 Blend Ratio"
|
|
hexmask.long.byte 0x3E4 18.--23. 1. " CP1_249R ,Color Palette 1_249 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E4 10.--15. 1. " CP1_249G ,Color Palette 1_249 Green"
|
|
hexmask.long.byte 0x3E4 2.--7. 1. " CP1_249B ,Color Palette 1_249 Blue"
|
|
line.long 0x3E8 "CP1_250R,Color Palette 1 Register 250"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " CP1_250A ,Color Palette 1_250 Blend Ratio"
|
|
hexmask.long.byte 0x3E8 18.--23. 1. " CP1_250R ,Color Palette 1_250 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E8 10.--15. 1. " CP1_250G ,Color Palette 1_250 Green"
|
|
hexmask.long.byte 0x3E8 2.--7. 1. " CP1_250B ,Color Palette 1_250 Blue"
|
|
line.long 0x3EC "CP1_251R,Color Palette 1 Register 251"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " CP1_251A ,Color Palette 1_251 Blend Ratio"
|
|
hexmask.long.byte 0x3EC 18.--23. 1. " CP1_251R ,Color Palette 1_251 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3EC 10.--15. 1. " CP1_251G ,Color Palette 1_251 Green"
|
|
hexmask.long.byte 0x3EC 2.--7. 1. " CP1_251B ,Color Palette 1_251 Blue"
|
|
line.long 0x3F0 "CP1_252R,Color Palette 1 Register 252"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " CP1_252A ,Color Palette 1_252 Blend Ratio"
|
|
hexmask.long.byte 0x3F0 18.--23. 1. " CP1_252R ,Color Palette 1_252 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F0 10.--15. 1. " CP1_252G ,Color Palette 1_252 Green"
|
|
hexmask.long.byte 0x3F0 2.--7. 1. " CP1_252B ,Color Palette 1_252 Blue"
|
|
line.long 0x3F4 "CP1_253R,Color Palette 1 Register 253"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " CP1_253A ,Color Palette 1_253 Blend Ratio"
|
|
hexmask.long.byte 0x3F4 18.--23. 1. " CP1_253R ,Color Palette 1_253 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F4 10.--15. 1. " CP1_253G ,Color Palette 1_253 Green"
|
|
hexmask.long.byte 0x3F4 2.--7. 1. " CP1_253B ,Color Palette 1_253 Blue"
|
|
line.long 0x3F8 "CP1_254R,Color Palette 1 Register 254"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " CP1_254A ,Color Palette 1_254 Blend Ratio"
|
|
hexmask.long.byte 0x3F8 18.--23. 1. " CP1_254R ,Color Palette 1_254 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F8 10.--15. 1. " CP1_254G ,Color Palette 1_254 Green"
|
|
hexmask.long.byte 0x3F8 2.--7. 1. " CP1_254B ,Color Palette 1_254 Blue"
|
|
line.long 0x3FC "CP1_255R,Color Palette 1 Register 255"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " CP1_255A ,Color Palette 1_255 Blend Ratio"
|
|
hexmask.long.byte 0x3FC 18.--23. 1. " CP1_255R ,Color Palette 1_255 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3FC 10.--15. 1. " CP1_255G ,Color Palette 1_255 Green"
|
|
hexmask.long.byte 0x3FC 2.--7. 1. " CP1_255B ,Color Palette 1_255 Blue"
|
|
tree.end
|
|
tree "Color Palette 2 Registers"
|
|
width 10.
|
|
group.long 0x2000++0x3ff
|
|
line.long 0x0 "CP2_0R,Color Palette 2 Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " CP2_0A ,Color Palette 2_0 Blend Ratio"
|
|
hexmask.long.byte 0x0 18.--23. 1. " CP2_0R ,Color Palette 2_0 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x0 10.--15. 1. " CP2_0G ,Color Palette 2_0 Green"
|
|
hexmask.long.byte 0x0 2.--7. 1. " CP2_0B ,Color Palette 2_0 Blue"
|
|
line.long 0x4 "CP2_1R,Color Palette 2 Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " CP2_1A ,Color Palette 2_1 Blend Ratio"
|
|
hexmask.long.byte 0x4 18.--23. 1. " CP2_1R ,Color Palette 2_1 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4 10.--15. 1. " CP2_1G ,Color Palette 2_1 Green"
|
|
hexmask.long.byte 0x4 2.--7. 1. " CP2_1B ,Color Palette 2_1 Blue"
|
|
line.long 0x8 "CP2_2R,Color Palette 2 Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " CP2_2A ,Color Palette 2_2 Blend Ratio"
|
|
hexmask.long.byte 0x8 18.--23. 1. " CP2_2R ,Color Palette 2_2 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8 10.--15. 1. " CP2_2G ,Color Palette 2_2 Green"
|
|
hexmask.long.byte 0x8 2.--7. 1. " CP2_2B ,Color Palette 2_2 Blue"
|
|
line.long 0xC "CP2_3R,Color Palette 2 Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " CP2_3A ,Color Palette 2_3 Blend Ratio"
|
|
hexmask.long.byte 0xC 18.--23. 1. " CP2_3R ,Color Palette 2_3 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC 10.--15. 1. " CP2_3G ,Color Palette 2_3 Green"
|
|
hexmask.long.byte 0xC 2.--7. 1. " CP2_3B ,Color Palette 2_3 Blue"
|
|
line.long 0x10 "CP2_4R,Color Palette 2 Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. " CP2_4A ,Color Palette 2_4 Blend Ratio"
|
|
hexmask.long.byte 0x10 18.--23. 1. " CP2_4R ,Color Palette 2_4 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10 10.--15. 1. " CP2_4G ,Color Palette 2_4 Green"
|
|
hexmask.long.byte 0x10 2.--7. 1. " CP2_4B ,Color Palette 2_4 Blue"
|
|
line.long 0x14 "CP2_5R,Color Palette 2 Register 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. " CP2_5A ,Color Palette 2_5 Blend Ratio"
|
|
hexmask.long.byte 0x14 18.--23. 1. " CP2_5R ,Color Palette 2_5 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14 10.--15. 1. " CP2_5G ,Color Palette 2_5 Green"
|
|
hexmask.long.byte 0x14 2.--7. 1. " CP2_5B ,Color Palette 2_5 Blue"
|
|
line.long 0x18 "CP2_6R,Color Palette 2 Register 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. " CP2_6A ,Color Palette 2_6 Blend Ratio"
|
|
hexmask.long.byte 0x18 18.--23. 1. " CP2_6R ,Color Palette 2_6 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18 10.--15. 1. " CP2_6G ,Color Palette 2_6 Green"
|
|
hexmask.long.byte 0x18 2.--7. 1. " CP2_6B ,Color Palette 2_6 Blue"
|
|
line.long 0x1C "CP2_7R,Color Palette 2 Register 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " CP2_7A ,Color Palette 2_7 Blend Ratio"
|
|
hexmask.long.byte 0x1C 18.--23. 1. " CP2_7R ,Color Palette 2_7 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 10.--15. 1. " CP2_7G ,Color Palette 2_7 Green"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " CP2_7B ,Color Palette 2_7 Blue"
|
|
line.long 0x20 "CP2_8R,Color Palette 2 Register 8"
|
|
hexmask.long.byte 0x20 24.--31. 1. " CP2_8A ,Color Palette 2_8 Blend Ratio"
|
|
hexmask.long.byte 0x20 18.--23. 1. " CP2_8R ,Color Palette 2_8 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20 10.--15. 1. " CP2_8G ,Color Palette 2_8 Green"
|
|
hexmask.long.byte 0x20 2.--7. 1. " CP2_8B ,Color Palette 2_8 Blue"
|
|
line.long 0x24 "CP2_9R,Color Palette 2 Register 9"
|
|
hexmask.long.byte 0x24 24.--31. 1. " CP2_9A ,Color Palette 2_9 Blend Ratio"
|
|
hexmask.long.byte 0x24 18.--23. 1. " CP2_9R ,Color Palette 2_9 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24 10.--15. 1. " CP2_9G ,Color Palette 2_9 Green"
|
|
hexmask.long.byte 0x24 2.--7. 1. " CP2_9B ,Color Palette 2_9 Blue"
|
|
line.long 0x28 "CP2_10R,Color Palette 2 Register 10"
|
|
hexmask.long.byte 0x28 24.--31. 1. " CP2_10A ,Color Palette 2_10 Blend Ratio"
|
|
hexmask.long.byte 0x28 18.--23. 1. " CP2_10R ,Color Palette 2_10 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28 10.--15. 1. " CP2_10G ,Color Palette 2_10 Green"
|
|
hexmask.long.byte 0x28 2.--7. 1. " CP2_10B ,Color Palette 2_10 Blue"
|
|
line.long 0x2C "CP2_11R,Color Palette 2 Register 11"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " CP2_11A ,Color Palette 2_11 Blend Ratio"
|
|
hexmask.long.byte 0x2C 18.--23. 1. " CP2_11R ,Color Palette 2_11 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 10.--15. 1. " CP2_11G ,Color Palette 2_11 Green"
|
|
hexmask.long.byte 0x2C 2.--7. 1. " CP2_11B ,Color Palette 2_11 Blue"
|
|
line.long 0x30 "CP2_12R,Color Palette 2 Register 12"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CP2_12A ,Color Palette 2_12 Blend Ratio"
|
|
hexmask.long.byte 0x30 18.--23. 1. " CP2_12R ,Color Palette 2_12 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30 10.--15. 1. " CP2_12G ,Color Palette 2_12 Green"
|
|
hexmask.long.byte 0x30 2.--7. 1. " CP2_12B ,Color Palette 2_12 Blue"
|
|
line.long 0x34 "CP2_13R,Color Palette 2 Register 13"
|
|
hexmask.long.byte 0x34 24.--31. 1. " CP2_13A ,Color Palette 2_13 Blend Ratio"
|
|
hexmask.long.byte 0x34 18.--23. 1. " CP2_13R ,Color Palette 2_13 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34 10.--15. 1. " CP2_13G ,Color Palette 2_13 Green"
|
|
hexmask.long.byte 0x34 2.--7. 1. " CP2_13B ,Color Palette 2_13 Blue"
|
|
line.long 0x38 "CP2_14R,Color Palette 2 Register 14"
|
|
hexmask.long.byte 0x38 24.--31. 1. " CP2_14A ,Color Palette 2_14 Blend Ratio"
|
|
hexmask.long.byte 0x38 18.--23. 1. " CP2_14R ,Color Palette 2_14 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38 10.--15. 1. " CP2_14G ,Color Palette 2_14 Green"
|
|
hexmask.long.byte 0x38 2.--7. 1. " CP2_14B ,Color Palette 2_14 Blue"
|
|
line.long 0x3C "CP2_15R,Color Palette 2 Register 15"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " CP2_15A ,Color Palette 2_15 Blend Ratio"
|
|
hexmask.long.byte 0x3C 18.--23. 1. " CP2_15R ,Color Palette 2_15 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C 10.--15. 1. " CP2_15G ,Color Palette 2_15 Green"
|
|
hexmask.long.byte 0x3C 2.--7. 1. " CP2_15B ,Color Palette 2_15 Blue"
|
|
line.long 0x40 "CP2_16R,Color Palette 2 Register 16"
|
|
hexmask.long.byte 0x40 24.--31. 1. " CP2_16A ,Color Palette 2_16 Blend Ratio"
|
|
hexmask.long.byte 0x40 18.--23. 1. " CP2_16R ,Color Palette 2_16 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x40 10.--15. 1. " CP2_16G ,Color Palette 2_16 Green"
|
|
hexmask.long.byte 0x40 2.--7. 1. " CP2_16B ,Color Palette 2_16 Blue"
|
|
line.long 0x44 "CP2_17R,Color Palette 2 Register 17"
|
|
hexmask.long.byte 0x44 24.--31. 1. " CP2_17A ,Color Palette 2_17 Blend Ratio"
|
|
hexmask.long.byte 0x44 18.--23. 1. " CP2_17R ,Color Palette 2_17 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x44 10.--15. 1. " CP2_17G ,Color Palette 2_17 Green"
|
|
hexmask.long.byte 0x44 2.--7. 1. " CP2_17B ,Color Palette 2_17 Blue"
|
|
line.long 0x48 "CP2_18R,Color Palette 2 Register 18"
|
|
hexmask.long.byte 0x48 24.--31. 1. " CP2_18A ,Color Palette 2_18 Blend Ratio"
|
|
hexmask.long.byte 0x48 18.--23. 1. " CP2_18R ,Color Palette 2_18 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x48 10.--15. 1. " CP2_18G ,Color Palette 2_18 Green"
|
|
hexmask.long.byte 0x48 2.--7. 1. " CP2_18B ,Color Palette 2_18 Blue"
|
|
line.long 0x4C "CP2_19R,Color Palette 2 Register 19"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " CP2_19A ,Color Palette 2_19 Blend Ratio"
|
|
hexmask.long.byte 0x4C 18.--23. 1. " CP2_19R ,Color Palette 2_19 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4C 10.--15. 1. " CP2_19G ,Color Palette 2_19 Green"
|
|
hexmask.long.byte 0x4C 2.--7. 1. " CP2_19B ,Color Palette 2_19 Blue"
|
|
line.long 0x50 "CP2_20R,Color Palette 2 Register 20"
|
|
hexmask.long.byte 0x50 24.--31. 1. " CP2_20A ,Color Palette 2_20 Blend Ratio"
|
|
hexmask.long.byte 0x50 18.--23. 1. " CP2_20R ,Color Palette 2_20 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x50 10.--15. 1. " CP2_20G ,Color Palette 2_20 Green"
|
|
hexmask.long.byte 0x50 2.--7. 1. " CP2_20B ,Color Palette 2_20 Blue"
|
|
line.long 0x54 "CP2_21R,Color Palette 2 Register 21"
|
|
hexmask.long.byte 0x54 24.--31. 1. " CP2_21A ,Color Palette 2_21 Blend Ratio"
|
|
hexmask.long.byte 0x54 18.--23. 1. " CP2_21R ,Color Palette 2_21 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x54 10.--15. 1. " CP2_21G ,Color Palette 2_21 Green"
|
|
hexmask.long.byte 0x54 2.--7. 1. " CP2_21B ,Color Palette 2_21 Blue"
|
|
line.long 0x58 "CP2_22R,Color Palette 2 Register 22"
|
|
hexmask.long.byte 0x58 24.--31. 1. " CP2_22A ,Color Palette 2_22 Blend Ratio"
|
|
hexmask.long.byte 0x58 18.--23. 1. " CP2_22R ,Color Palette 2_22 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x58 10.--15. 1. " CP2_22G ,Color Palette 2_22 Green"
|
|
hexmask.long.byte 0x58 2.--7. 1. " CP2_22B ,Color Palette 2_22 Blue"
|
|
line.long 0x5C "CP2_23R,Color Palette 2 Register 23"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " CP2_23A ,Color Palette 2_23 Blend Ratio"
|
|
hexmask.long.byte 0x5C 18.--23. 1. " CP2_23R ,Color Palette 2_23 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 10.--15. 1. " CP2_23G ,Color Palette 2_23 Green"
|
|
hexmask.long.byte 0x5C 2.--7. 1. " CP2_23B ,Color Palette 2_23 Blue"
|
|
line.long 0x60 "CP2_24R,Color Palette 2 Register 24"
|
|
hexmask.long.byte 0x60 24.--31. 1. " CP2_24A ,Color Palette 2_24 Blend Ratio"
|
|
hexmask.long.byte 0x60 18.--23. 1. " CP2_24R ,Color Palette 2_24 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x60 10.--15. 1. " CP2_24G ,Color Palette 2_24 Green"
|
|
hexmask.long.byte 0x60 2.--7. 1. " CP2_24B ,Color Palette 2_24 Blue"
|
|
line.long 0x64 "CP2_25R,Color Palette 2 Register 25"
|
|
hexmask.long.byte 0x64 24.--31. 1. " CP2_25A ,Color Palette 2_25 Blend Ratio"
|
|
hexmask.long.byte 0x64 18.--23. 1. " CP2_25R ,Color Palette 2_25 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x64 10.--15. 1. " CP2_25G ,Color Palette 2_25 Green"
|
|
hexmask.long.byte 0x64 2.--7. 1. " CP2_25B ,Color Palette 2_25 Blue"
|
|
line.long 0x68 "CP2_26R,Color Palette 2 Register 26"
|
|
hexmask.long.byte 0x68 24.--31. 1. " CP2_26A ,Color Palette 2_26 Blend Ratio"
|
|
hexmask.long.byte 0x68 18.--23. 1. " CP2_26R ,Color Palette 2_26 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x68 10.--15. 1. " CP2_26G ,Color Palette 2_26 Green"
|
|
hexmask.long.byte 0x68 2.--7. 1. " CP2_26B ,Color Palette 2_26 Blue"
|
|
line.long 0x6C "CP2_27R,Color Palette 2 Register 27"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " CP2_27A ,Color Palette 2_27 Blend Ratio"
|
|
hexmask.long.byte 0x6C 18.--23. 1. " CP2_27R ,Color Palette 2_27 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x6C 10.--15. 1. " CP2_27G ,Color Palette 2_27 Green"
|
|
hexmask.long.byte 0x6C 2.--7. 1. " CP2_27B ,Color Palette 2_27 Blue"
|
|
line.long 0x70 "CP2_28R,Color Palette 2 Register 28"
|
|
hexmask.long.byte 0x70 24.--31. 1. " CP2_28A ,Color Palette 2_28 Blend Ratio"
|
|
hexmask.long.byte 0x70 18.--23. 1. " CP2_28R ,Color Palette 2_28 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x70 10.--15. 1. " CP2_28G ,Color Palette 2_28 Green"
|
|
hexmask.long.byte 0x70 2.--7. 1. " CP2_28B ,Color Palette 2_28 Blue"
|
|
line.long 0x74 "CP2_29R,Color Palette 2 Register 29"
|
|
hexmask.long.byte 0x74 24.--31. 1. " CP2_29A ,Color Palette 2_29 Blend Ratio"
|
|
hexmask.long.byte 0x74 18.--23. 1. " CP2_29R ,Color Palette 2_29 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x74 10.--15. 1. " CP2_29G ,Color Palette 2_29 Green"
|
|
hexmask.long.byte 0x74 2.--7. 1. " CP2_29B ,Color Palette 2_29 Blue"
|
|
line.long 0x78 "CP2_30R,Color Palette 2 Register 30"
|
|
hexmask.long.byte 0x78 24.--31. 1. " CP2_30A ,Color Palette 2_30 Blend Ratio"
|
|
hexmask.long.byte 0x78 18.--23. 1. " CP2_30R ,Color Palette 2_30 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x78 10.--15. 1. " CP2_30G ,Color Palette 2_30 Green"
|
|
hexmask.long.byte 0x78 2.--7. 1. " CP2_30B ,Color Palette 2_30 Blue"
|
|
line.long 0x7C "CP2_31R,Color Palette 2 Register 31"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " CP2_31A ,Color Palette 2_31 Blend Ratio"
|
|
hexmask.long.byte 0x7C 18.--23. 1. " CP2_31R ,Color Palette 2_31 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x7C 10.--15. 1. " CP2_31G ,Color Palette 2_31 Green"
|
|
hexmask.long.byte 0x7C 2.--7. 1. " CP2_31B ,Color Palette 2_31 Blue"
|
|
line.long 0x80 "CP2_32R,Color Palette 2 Register 32"
|
|
hexmask.long.byte 0x80 24.--31. 1. " CP2_32A ,Color Palette 2_32 Blend Ratio"
|
|
hexmask.long.byte 0x80 18.--23. 1. " CP2_32R ,Color Palette 2_32 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x80 10.--15. 1. " CP2_32G ,Color Palette 2_32 Green"
|
|
hexmask.long.byte 0x80 2.--7. 1. " CP2_32B ,Color Palette 2_32 Blue"
|
|
line.long 0x84 "CP2_33R,Color Palette 2 Register 33"
|
|
hexmask.long.byte 0x84 24.--31. 1. " CP2_33A ,Color Palette 2_33 Blend Ratio"
|
|
hexmask.long.byte 0x84 18.--23. 1. " CP2_33R ,Color Palette 2_33 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x84 10.--15. 1. " CP2_33G ,Color Palette 2_33 Green"
|
|
hexmask.long.byte 0x84 2.--7. 1. " CP2_33B ,Color Palette 2_33 Blue"
|
|
line.long 0x88 "CP2_34R,Color Palette 2 Register 34"
|
|
hexmask.long.byte 0x88 24.--31. 1. " CP2_34A ,Color Palette 2_34 Blend Ratio"
|
|
hexmask.long.byte 0x88 18.--23. 1. " CP2_34R ,Color Palette 2_34 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x88 10.--15. 1. " CP2_34G ,Color Palette 2_34 Green"
|
|
hexmask.long.byte 0x88 2.--7. 1. " CP2_34B ,Color Palette 2_34 Blue"
|
|
line.long 0x8C "CP2_35R,Color Palette 2 Register 35"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " CP2_35A ,Color Palette 2_35 Blend Ratio"
|
|
hexmask.long.byte 0x8C 18.--23. 1. " CP2_35R ,Color Palette 2_35 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8C 10.--15. 1. " CP2_35G ,Color Palette 2_35 Green"
|
|
hexmask.long.byte 0x8C 2.--7. 1. " CP2_35B ,Color Palette 2_35 Blue"
|
|
line.long 0x90 "CP2_36R,Color Palette 2 Register 36"
|
|
hexmask.long.byte 0x90 24.--31. 1. " CP2_36A ,Color Palette 2_36 Blend Ratio"
|
|
hexmask.long.byte 0x90 18.--23. 1. " CP2_36R ,Color Palette 2_36 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x90 10.--15. 1. " CP2_36G ,Color Palette 2_36 Green"
|
|
hexmask.long.byte 0x90 2.--7. 1. " CP2_36B ,Color Palette 2_36 Blue"
|
|
line.long 0x94 "CP2_37R,Color Palette 2 Register 37"
|
|
hexmask.long.byte 0x94 24.--31. 1. " CP2_37A ,Color Palette 2_37 Blend Ratio"
|
|
hexmask.long.byte 0x94 18.--23. 1. " CP2_37R ,Color Palette 2_37 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x94 10.--15. 1. " CP2_37G ,Color Palette 2_37 Green"
|
|
hexmask.long.byte 0x94 2.--7. 1. " CP2_37B ,Color Palette 2_37 Blue"
|
|
line.long 0x98 "CP2_38R,Color Palette 2 Register 38"
|
|
hexmask.long.byte 0x98 24.--31. 1. " CP2_38A ,Color Palette 2_38 Blend Ratio"
|
|
hexmask.long.byte 0x98 18.--23. 1. " CP2_38R ,Color Palette 2_38 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x98 10.--15. 1. " CP2_38G ,Color Palette 2_38 Green"
|
|
hexmask.long.byte 0x98 2.--7. 1. " CP2_38B ,Color Palette 2_38 Blue"
|
|
line.long 0x9C "CP2_39R,Color Palette 2 Register 39"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " CP2_39A ,Color Palette 2_39 Blend Ratio"
|
|
hexmask.long.byte 0x9C 18.--23. 1. " CP2_39R ,Color Palette 2_39 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x9C 10.--15. 1. " CP2_39G ,Color Palette 2_39 Green"
|
|
hexmask.long.byte 0x9C 2.--7. 1. " CP2_39B ,Color Palette 2_39 Blue"
|
|
line.long 0xA0 "CP2_40R,Color Palette 2 Register 40"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " CP2_40A ,Color Palette 2_40 Blend Ratio"
|
|
hexmask.long.byte 0xA0 18.--23. 1. " CP2_40R ,Color Palette 2_40 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA0 10.--15. 1. " CP2_40G ,Color Palette 2_40 Green"
|
|
hexmask.long.byte 0xA0 2.--7. 1. " CP2_40B ,Color Palette 2_40 Blue"
|
|
line.long 0xA4 "CP2_41R,Color Palette 2 Register 41"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " CP2_41A ,Color Palette 2_41 Blend Ratio"
|
|
hexmask.long.byte 0xA4 18.--23. 1. " CP2_41R ,Color Palette 2_41 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA4 10.--15. 1. " CP2_41G ,Color Palette 2_41 Green"
|
|
hexmask.long.byte 0xA4 2.--7. 1. " CP2_41B ,Color Palette 2_41 Blue"
|
|
line.long 0xA8 "CP2_42R,Color Palette 2 Register 42"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " CP2_42A ,Color Palette 2_42 Blend Ratio"
|
|
hexmask.long.byte 0xA8 18.--23. 1. " CP2_42R ,Color Palette 2_42 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA8 10.--15. 1. " CP2_42G ,Color Palette 2_42 Green"
|
|
hexmask.long.byte 0xA8 2.--7. 1. " CP2_42B ,Color Palette 2_42 Blue"
|
|
line.long 0xAC "CP2_43R,Color Palette 2 Register 43"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " CP2_43A ,Color Palette 2_43 Blend Ratio"
|
|
hexmask.long.byte 0xAC 18.--23. 1. " CP2_43R ,Color Palette 2_43 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xAC 10.--15. 1. " CP2_43G ,Color Palette 2_43 Green"
|
|
hexmask.long.byte 0xAC 2.--7. 1. " CP2_43B ,Color Palette 2_43 Blue"
|
|
line.long 0xB0 "CP2_44R,Color Palette 2 Register 44"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " CP2_44A ,Color Palette 2_44 Blend Ratio"
|
|
hexmask.long.byte 0xB0 18.--23. 1. " CP2_44R ,Color Palette 2_44 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB0 10.--15. 1. " CP2_44G ,Color Palette 2_44 Green"
|
|
hexmask.long.byte 0xB0 2.--7. 1. " CP2_44B ,Color Palette 2_44 Blue"
|
|
line.long 0xB4 "CP2_45R,Color Palette 2 Register 45"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " CP2_45A ,Color Palette 2_45 Blend Ratio"
|
|
hexmask.long.byte 0xB4 18.--23. 1. " CP2_45R ,Color Palette 2_45 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB4 10.--15. 1. " CP2_45G ,Color Palette 2_45 Green"
|
|
hexmask.long.byte 0xB4 2.--7. 1. " CP2_45B ,Color Palette 2_45 Blue"
|
|
line.long 0xB8 "CP2_46R,Color Palette 2 Register 46"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " CP2_46A ,Color Palette 2_46 Blend Ratio"
|
|
hexmask.long.byte 0xB8 18.--23. 1. " CP2_46R ,Color Palette 2_46 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB8 10.--15. 1. " CP2_46G ,Color Palette 2_46 Green"
|
|
hexmask.long.byte 0xB8 2.--7. 1. " CP2_46B ,Color Palette 2_46 Blue"
|
|
line.long 0xBC "CP2_47R,Color Palette 2 Register 47"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " CP2_47A ,Color Palette 2_47 Blend Ratio"
|
|
hexmask.long.byte 0xBC 18.--23. 1. " CP2_47R ,Color Palette 2_47 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xBC 10.--15. 1. " CP2_47G ,Color Palette 2_47 Green"
|
|
hexmask.long.byte 0xBC 2.--7. 1. " CP2_47B ,Color Palette 2_47 Blue"
|
|
line.long 0xC0 "CP2_48R,Color Palette 2 Register 48"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " CP2_48A ,Color Palette 2_48 Blend Ratio"
|
|
hexmask.long.byte 0xC0 18.--23. 1. " CP2_48R ,Color Palette 2_48 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC0 10.--15. 1. " CP2_48G ,Color Palette 2_48 Green"
|
|
hexmask.long.byte 0xC0 2.--7. 1. " CP2_48B ,Color Palette 2_48 Blue"
|
|
line.long 0xC4 "CP2_49R,Color Palette 2 Register 49"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " CP2_49A ,Color Palette 2_49 Blend Ratio"
|
|
hexmask.long.byte 0xC4 18.--23. 1. " CP2_49R ,Color Palette 2_49 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC4 10.--15. 1. " CP2_49G ,Color Palette 2_49 Green"
|
|
hexmask.long.byte 0xC4 2.--7. 1. " CP2_49B ,Color Palette 2_49 Blue"
|
|
line.long 0xC8 "CP2_50R,Color Palette 2 Register 50"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " CP2_50A ,Color Palette 2_50 Blend Ratio"
|
|
hexmask.long.byte 0xC8 18.--23. 1. " CP2_50R ,Color Palette 2_50 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC8 10.--15. 1. " CP2_50G ,Color Palette 2_50 Green"
|
|
hexmask.long.byte 0xC8 2.--7. 1. " CP2_50B ,Color Palette 2_50 Blue"
|
|
line.long 0xCC "CP2_51R,Color Palette 2 Register 51"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " CP2_51A ,Color Palette 2_51 Blend Ratio"
|
|
hexmask.long.byte 0xCC 18.--23. 1. " CP2_51R ,Color Palette 2_51 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xCC 10.--15. 1. " CP2_51G ,Color Palette 2_51 Green"
|
|
hexmask.long.byte 0xCC 2.--7. 1. " CP2_51B ,Color Palette 2_51 Blue"
|
|
line.long 0xD0 "CP2_52R,Color Palette 2 Register 52"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " CP2_52A ,Color Palette 2_52 Blend Ratio"
|
|
hexmask.long.byte 0xD0 18.--23. 1. " CP2_52R ,Color Palette 2_52 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD0 10.--15. 1. " CP2_52G ,Color Palette 2_52 Green"
|
|
hexmask.long.byte 0xD0 2.--7. 1. " CP2_52B ,Color Palette 2_52 Blue"
|
|
line.long 0xD4 "CP2_53R,Color Palette 2 Register 53"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " CP2_53A ,Color Palette 2_53 Blend Ratio"
|
|
hexmask.long.byte 0xD4 18.--23. 1. " CP2_53R ,Color Palette 2_53 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD4 10.--15. 1. " CP2_53G ,Color Palette 2_53 Green"
|
|
hexmask.long.byte 0xD4 2.--7. 1. " CP2_53B ,Color Palette 2_53 Blue"
|
|
line.long 0xD8 "CP2_54R,Color Palette 2 Register 54"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " CP2_54A ,Color Palette 2_54 Blend Ratio"
|
|
hexmask.long.byte 0xD8 18.--23. 1. " CP2_54R ,Color Palette 2_54 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD8 10.--15. 1. " CP2_54G ,Color Palette 2_54 Green"
|
|
hexmask.long.byte 0xD8 2.--7. 1. " CP2_54B ,Color Palette 2_54 Blue"
|
|
line.long 0xDC "CP2_55R,Color Palette 2 Register 55"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " CP2_55A ,Color Palette 2_55 Blend Ratio"
|
|
hexmask.long.byte 0xDC 18.--23. 1. " CP2_55R ,Color Palette 2_55 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xDC 10.--15. 1. " CP2_55G ,Color Palette 2_55 Green"
|
|
hexmask.long.byte 0xDC 2.--7. 1. " CP2_55B ,Color Palette 2_55 Blue"
|
|
line.long 0xE0 "CP2_56R,Color Palette 2 Register 56"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " CP2_56A ,Color Palette 2_56 Blend Ratio"
|
|
hexmask.long.byte 0xE0 18.--23. 1. " CP2_56R ,Color Palette 2_56 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE0 10.--15. 1. " CP2_56G ,Color Palette 2_56 Green"
|
|
hexmask.long.byte 0xE0 2.--7. 1. " CP2_56B ,Color Palette 2_56 Blue"
|
|
line.long 0xE4 "CP2_57R,Color Palette 2 Register 57"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " CP2_57A ,Color Palette 2_57 Blend Ratio"
|
|
hexmask.long.byte 0xE4 18.--23. 1. " CP2_57R ,Color Palette 2_57 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE4 10.--15. 1. " CP2_57G ,Color Palette 2_57 Green"
|
|
hexmask.long.byte 0xE4 2.--7. 1. " CP2_57B ,Color Palette 2_57 Blue"
|
|
line.long 0xE8 "CP2_58R,Color Palette 2 Register 58"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " CP2_58A ,Color Palette 2_58 Blend Ratio"
|
|
hexmask.long.byte 0xE8 18.--23. 1. " CP2_58R ,Color Palette 2_58 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE8 10.--15. 1. " CP2_58G ,Color Palette 2_58 Green"
|
|
hexmask.long.byte 0xE8 2.--7. 1. " CP2_58B ,Color Palette 2_58 Blue"
|
|
line.long 0xEC "CP2_59R,Color Palette 2 Register 59"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " CP2_59A ,Color Palette 2_59 Blend Ratio"
|
|
hexmask.long.byte 0xEC 18.--23. 1. " CP2_59R ,Color Palette 2_59 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xEC 10.--15. 1. " CP2_59G ,Color Palette 2_59 Green"
|
|
hexmask.long.byte 0xEC 2.--7. 1. " CP2_59B ,Color Palette 2_59 Blue"
|
|
line.long 0xF0 "CP2_60R,Color Palette 2 Register 60"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " CP2_60A ,Color Palette 2_60 Blend Ratio"
|
|
hexmask.long.byte 0xF0 18.--23. 1. " CP2_60R ,Color Palette 2_60 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF0 10.--15. 1. " CP2_60G ,Color Palette 2_60 Green"
|
|
hexmask.long.byte 0xF0 2.--7. 1. " CP2_60B ,Color Palette 2_60 Blue"
|
|
line.long 0xF4 "CP2_61R,Color Palette 2 Register 61"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " CP2_61A ,Color Palette 2_61 Blend Ratio"
|
|
hexmask.long.byte 0xF4 18.--23. 1. " CP2_61R ,Color Palette 2_61 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF4 10.--15. 1. " CP2_61G ,Color Palette 2_61 Green"
|
|
hexmask.long.byte 0xF4 2.--7. 1. " CP2_61B ,Color Palette 2_61 Blue"
|
|
line.long 0xF8 "CP2_62R,Color Palette 2 Register 62"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " CP2_62A ,Color Palette 2_62 Blend Ratio"
|
|
hexmask.long.byte 0xF8 18.--23. 1. " CP2_62R ,Color Palette 2_62 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF8 10.--15. 1. " CP2_62G ,Color Palette 2_62 Green"
|
|
hexmask.long.byte 0xF8 2.--7. 1. " CP2_62B ,Color Palette 2_62 Blue"
|
|
line.long 0xFC "CP2_63R,Color Palette 2 Register 63"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " CP2_63A ,Color Palette 2_63 Blend Ratio"
|
|
hexmask.long.byte 0xFC 18.--23. 1. " CP2_63R ,Color Palette 2_63 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xFC 10.--15. 1. " CP2_63G ,Color Palette 2_63 Green"
|
|
hexmask.long.byte 0xFC 2.--7. 1. " CP2_63B ,Color Palette 2_63 Blue"
|
|
line.long 0x100 "CP2_64R,Color Palette 2 Register 64"
|
|
hexmask.long.byte 0x100 24.--31. 1. " CP2_64A ,Color Palette 2_64 Blend Ratio"
|
|
hexmask.long.byte 0x100 18.--23. 1. " CP2_64R ,Color Palette 2_64 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x100 10.--15. 1. " CP2_64G ,Color Palette 2_64 Green"
|
|
hexmask.long.byte 0x100 2.--7. 1. " CP2_64B ,Color Palette 2_64 Blue"
|
|
line.long 0x104 "CP2_65R,Color Palette 2 Register 65"
|
|
hexmask.long.byte 0x104 24.--31. 1. " CP2_65A ,Color Palette 2_65 Blend Ratio"
|
|
hexmask.long.byte 0x104 18.--23. 1. " CP2_65R ,Color Palette 2_65 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x104 10.--15. 1. " CP2_65G ,Color Palette 2_65 Green"
|
|
hexmask.long.byte 0x104 2.--7. 1. " CP2_65B ,Color Palette 2_65 Blue"
|
|
line.long 0x108 "CP2_66R,Color Palette 2 Register 66"
|
|
hexmask.long.byte 0x108 24.--31. 1. " CP2_66A ,Color Palette 2_66 Blend Ratio"
|
|
hexmask.long.byte 0x108 18.--23. 1. " CP2_66R ,Color Palette 2_66 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x108 10.--15. 1. " CP2_66G ,Color Palette 2_66 Green"
|
|
hexmask.long.byte 0x108 2.--7. 1. " CP2_66B ,Color Palette 2_66 Blue"
|
|
line.long 0x10C "CP2_67R,Color Palette 2 Register 67"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " CP2_67A ,Color Palette 2_67 Blend Ratio"
|
|
hexmask.long.byte 0x10C 18.--23. 1. " CP2_67R ,Color Palette 2_67 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10C 10.--15. 1. " CP2_67G ,Color Palette 2_67 Green"
|
|
hexmask.long.byte 0x10C 2.--7. 1. " CP2_67B ,Color Palette 2_67 Blue"
|
|
line.long 0x110 "CP2_68R,Color Palette 2 Register 68"
|
|
hexmask.long.byte 0x110 24.--31. 1. " CP2_68A ,Color Palette 2_68 Blend Ratio"
|
|
hexmask.long.byte 0x110 18.--23. 1. " CP2_68R ,Color Palette 2_68 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x110 10.--15. 1. " CP2_68G ,Color Palette 2_68 Green"
|
|
hexmask.long.byte 0x110 2.--7. 1. " CP2_68B ,Color Palette 2_68 Blue"
|
|
line.long 0x114 "CP2_69R,Color Palette 2 Register 69"
|
|
hexmask.long.byte 0x114 24.--31. 1. " CP2_69A ,Color Palette 2_69 Blend Ratio"
|
|
hexmask.long.byte 0x114 18.--23. 1. " CP2_69R ,Color Palette 2_69 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x114 10.--15. 1. " CP2_69G ,Color Palette 2_69 Green"
|
|
hexmask.long.byte 0x114 2.--7. 1. " CP2_69B ,Color Palette 2_69 Blue"
|
|
line.long 0x118 "CP2_70R,Color Palette 2 Register 70"
|
|
hexmask.long.byte 0x118 24.--31. 1. " CP2_70A ,Color Palette 2_70 Blend Ratio"
|
|
hexmask.long.byte 0x118 18.--23. 1. " CP2_70R ,Color Palette 2_70 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x118 10.--15. 1. " CP2_70G ,Color Palette 2_70 Green"
|
|
hexmask.long.byte 0x118 2.--7. 1. " CP2_70B ,Color Palette 2_70 Blue"
|
|
line.long 0x11C "CP2_71R,Color Palette 2 Register 71"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " CP2_71A ,Color Palette 2_71 Blend Ratio"
|
|
hexmask.long.byte 0x11C 18.--23. 1. " CP2_71R ,Color Palette 2_71 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x11C 10.--15. 1. " CP2_71G ,Color Palette 2_71 Green"
|
|
hexmask.long.byte 0x11C 2.--7. 1. " CP2_71B ,Color Palette 2_71 Blue"
|
|
line.long 0x120 "CP2_72R,Color Palette 2 Register 72"
|
|
hexmask.long.byte 0x120 24.--31. 1. " CP2_72A ,Color Palette 2_72 Blend Ratio"
|
|
hexmask.long.byte 0x120 18.--23. 1. " CP2_72R ,Color Palette 2_72 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x120 10.--15. 1. " CP2_72G ,Color Palette 2_72 Green"
|
|
hexmask.long.byte 0x120 2.--7. 1. " CP2_72B ,Color Palette 2_72 Blue"
|
|
line.long 0x124 "CP2_73R,Color Palette 2 Register 73"
|
|
hexmask.long.byte 0x124 24.--31. 1. " CP2_73A ,Color Palette 2_73 Blend Ratio"
|
|
hexmask.long.byte 0x124 18.--23. 1. " CP2_73R ,Color Palette 2_73 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x124 10.--15. 1. " CP2_73G ,Color Palette 2_73 Green"
|
|
hexmask.long.byte 0x124 2.--7. 1. " CP2_73B ,Color Palette 2_73 Blue"
|
|
line.long 0x128 "CP2_74R,Color Palette 2 Register 74"
|
|
hexmask.long.byte 0x128 24.--31. 1. " CP2_74A ,Color Palette 2_74 Blend Ratio"
|
|
hexmask.long.byte 0x128 18.--23. 1. " CP2_74R ,Color Palette 2_74 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x128 10.--15. 1. " CP2_74G ,Color Palette 2_74 Green"
|
|
hexmask.long.byte 0x128 2.--7. 1. " CP2_74B ,Color Palette 2_74 Blue"
|
|
line.long 0x12C "CP2_75R,Color Palette 2 Register 75"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " CP2_75A ,Color Palette 2_75 Blend Ratio"
|
|
hexmask.long.byte 0x12C 18.--23. 1. " CP2_75R ,Color Palette 2_75 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x12C 10.--15. 1. " CP2_75G ,Color Palette 2_75 Green"
|
|
hexmask.long.byte 0x12C 2.--7. 1. " CP2_75B ,Color Palette 2_75 Blue"
|
|
line.long 0x130 "CP2_76R,Color Palette 2 Register 76"
|
|
hexmask.long.byte 0x130 24.--31. 1. " CP2_76A ,Color Palette 2_76 Blend Ratio"
|
|
hexmask.long.byte 0x130 18.--23. 1. " CP2_76R ,Color Palette 2_76 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x130 10.--15. 1. " CP2_76G ,Color Palette 2_76 Green"
|
|
hexmask.long.byte 0x130 2.--7. 1. " CP2_76B ,Color Palette 2_76 Blue"
|
|
line.long 0x134 "CP2_77R,Color Palette 2 Register 77"
|
|
hexmask.long.byte 0x134 24.--31. 1. " CP2_77A ,Color Palette 2_77 Blend Ratio"
|
|
hexmask.long.byte 0x134 18.--23. 1. " CP2_77R ,Color Palette 2_77 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x134 10.--15. 1. " CP2_77G ,Color Palette 2_77 Green"
|
|
hexmask.long.byte 0x134 2.--7. 1. " CP2_77B ,Color Palette 2_77 Blue"
|
|
line.long 0x138 "CP2_78R,Color Palette 2 Register 78"
|
|
hexmask.long.byte 0x138 24.--31. 1. " CP2_78A ,Color Palette 2_78 Blend Ratio"
|
|
hexmask.long.byte 0x138 18.--23. 1. " CP2_78R ,Color Palette 2_78 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x138 10.--15. 1. " CP2_78G ,Color Palette 2_78 Green"
|
|
hexmask.long.byte 0x138 2.--7. 1. " CP2_78B ,Color Palette 2_78 Blue"
|
|
line.long 0x13C "CP2_79R,Color Palette 2 Register 79"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " CP2_79A ,Color Palette 2_79 Blend Ratio"
|
|
hexmask.long.byte 0x13C 18.--23. 1. " CP2_79R ,Color Palette 2_79 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x13C 10.--15. 1. " CP2_79G ,Color Palette 2_79 Green"
|
|
hexmask.long.byte 0x13C 2.--7. 1. " CP2_79B ,Color Palette 2_79 Blue"
|
|
line.long 0x140 "CP2_80R,Color Palette 2 Register 80"
|
|
hexmask.long.byte 0x140 24.--31. 1. " CP2_80A ,Color Palette 2_80 Blend Ratio"
|
|
hexmask.long.byte 0x140 18.--23. 1. " CP2_80R ,Color Palette 2_80 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x140 10.--15. 1. " CP2_80G ,Color Palette 2_80 Green"
|
|
hexmask.long.byte 0x140 2.--7. 1. " CP2_80B ,Color Palette 2_80 Blue"
|
|
line.long 0x144 "CP2_81R,Color Palette 2 Register 81"
|
|
hexmask.long.byte 0x144 24.--31. 1. " CP2_81A ,Color Palette 2_81 Blend Ratio"
|
|
hexmask.long.byte 0x144 18.--23. 1. " CP2_81R ,Color Palette 2_81 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x144 10.--15. 1. " CP2_81G ,Color Palette 2_81 Green"
|
|
hexmask.long.byte 0x144 2.--7. 1. " CP2_81B ,Color Palette 2_81 Blue"
|
|
line.long 0x148 "CP2_82R,Color Palette 2 Register 82"
|
|
hexmask.long.byte 0x148 24.--31. 1. " CP2_82A ,Color Palette 2_82 Blend Ratio"
|
|
hexmask.long.byte 0x148 18.--23. 1. " CP2_82R ,Color Palette 2_82 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x148 10.--15. 1. " CP2_82G ,Color Palette 2_82 Green"
|
|
hexmask.long.byte 0x148 2.--7. 1. " CP2_82B ,Color Palette 2_82 Blue"
|
|
line.long 0x14C "CP2_83R,Color Palette 2 Register 83"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " CP2_83A ,Color Palette 2_83 Blend Ratio"
|
|
hexmask.long.byte 0x14C 18.--23. 1. " CP2_83R ,Color Palette 2_83 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14C 10.--15. 1. " CP2_83G ,Color Palette 2_83 Green"
|
|
hexmask.long.byte 0x14C 2.--7. 1. " CP2_83B ,Color Palette 2_83 Blue"
|
|
line.long 0x150 "CP2_84R,Color Palette 2 Register 84"
|
|
hexmask.long.byte 0x150 24.--31. 1. " CP2_84A ,Color Palette 2_84 Blend Ratio"
|
|
hexmask.long.byte 0x150 18.--23. 1. " CP2_84R ,Color Palette 2_84 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x150 10.--15. 1. " CP2_84G ,Color Palette 2_84 Green"
|
|
hexmask.long.byte 0x150 2.--7. 1. " CP2_84B ,Color Palette 2_84 Blue"
|
|
line.long 0x154 "CP2_85R,Color Palette 2 Register 85"
|
|
hexmask.long.byte 0x154 24.--31. 1. " CP2_85A ,Color Palette 2_85 Blend Ratio"
|
|
hexmask.long.byte 0x154 18.--23. 1. " CP2_85R ,Color Palette 2_85 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x154 10.--15. 1. " CP2_85G ,Color Palette 2_85 Green"
|
|
hexmask.long.byte 0x154 2.--7. 1. " CP2_85B ,Color Palette 2_85 Blue"
|
|
line.long 0x158 "CP2_86R,Color Palette 2 Register 86"
|
|
hexmask.long.byte 0x158 24.--31. 1. " CP2_86A ,Color Palette 2_86 Blend Ratio"
|
|
hexmask.long.byte 0x158 18.--23. 1. " CP2_86R ,Color Palette 2_86 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x158 10.--15. 1. " CP2_86G ,Color Palette 2_86 Green"
|
|
hexmask.long.byte 0x158 2.--7. 1. " CP2_86B ,Color Palette 2_86 Blue"
|
|
line.long 0x15C "CP2_87R,Color Palette 2 Register 87"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " CP2_87A ,Color Palette 2_87 Blend Ratio"
|
|
hexmask.long.byte 0x15C 18.--23. 1. " CP2_87R ,Color Palette 2_87 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x15C 10.--15. 1. " CP2_87G ,Color Palette 2_87 Green"
|
|
hexmask.long.byte 0x15C 2.--7. 1. " CP2_87B ,Color Palette 2_87 Blue"
|
|
line.long 0x160 "CP2_88R,Color Palette 2 Register 88"
|
|
hexmask.long.byte 0x160 24.--31. 1. " CP2_88A ,Color Palette 2_88 Blend Ratio"
|
|
hexmask.long.byte 0x160 18.--23. 1. " CP2_88R ,Color Palette 2_88 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x160 10.--15. 1. " CP2_88G ,Color Palette 2_88 Green"
|
|
hexmask.long.byte 0x160 2.--7. 1. " CP2_88B ,Color Palette 2_88 Blue"
|
|
line.long 0x164 "CP2_89R,Color Palette 2 Register 89"
|
|
hexmask.long.byte 0x164 24.--31. 1. " CP2_89A ,Color Palette 2_89 Blend Ratio"
|
|
hexmask.long.byte 0x164 18.--23. 1. " CP2_89R ,Color Palette 2_89 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x164 10.--15. 1. " CP2_89G ,Color Palette 2_89 Green"
|
|
hexmask.long.byte 0x164 2.--7. 1. " CP2_89B ,Color Palette 2_89 Blue"
|
|
line.long 0x168 "CP2_90R,Color Palette 2 Register 90"
|
|
hexmask.long.byte 0x168 24.--31. 1. " CP2_90A ,Color Palette 2_90 Blend Ratio"
|
|
hexmask.long.byte 0x168 18.--23. 1. " CP2_90R ,Color Palette 2_90 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x168 10.--15. 1. " CP2_90G ,Color Palette 2_90 Green"
|
|
hexmask.long.byte 0x168 2.--7. 1. " CP2_90B ,Color Palette 2_90 Blue"
|
|
line.long 0x16C "CP2_91R,Color Palette 2 Register 91"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " CP2_91A ,Color Palette 2_91 Blend Ratio"
|
|
hexmask.long.byte 0x16C 18.--23. 1. " CP2_91R ,Color Palette 2_91 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x16C 10.--15. 1. " CP2_91G ,Color Palette 2_91 Green"
|
|
hexmask.long.byte 0x16C 2.--7. 1. " CP2_91B ,Color Palette 2_91 Blue"
|
|
line.long 0x170 "CP2_92R,Color Palette 2 Register 92"
|
|
hexmask.long.byte 0x170 24.--31. 1. " CP2_92A ,Color Palette 2_92 Blend Ratio"
|
|
hexmask.long.byte 0x170 18.--23. 1. " CP2_92R ,Color Palette 2_92 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x170 10.--15. 1. " CP2_92G ,Color Palette 2_92 Green"
|
|
hexmask.long.byte 0x170 2.--7. 1. " CP2_92B ,Color Palette 2_92 Blue"
|
|
line.long 0x174 "CP2_93R,Color Palette 2 Register 93"
|
|
hexmask.long.byte 0x174 24.--31. 1. " CP2_93A ,Color Palette 2_93 Blend Ratio"
|
|
hexmask.long.byte 0x174 18.--23. 1. " CP2_93R ,Color Palette 2_93 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x174 10.--15. 1. " CP2_93G ,Color Palette 2_93 Green"
|
|
hexmask.long.byte 0x174 2.--7. 1. " CP2_93B ,Color Palette 2_93 Blue"
|
|
line.long 0x178 "CP2_94R,Color Palette 2 Register 94"
|
|
hexmask.long.byte 0x178 24.--31. 1. " CP2_94A ,Color Palette 2_94 Blend Ratio"
|
|
hexmask.long.byte 0x178 18.--23. 1. " CP2_94R ,Color Palette 2_94 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x178 10.--15. 1. " CP2_94G ,Color Palette 2_94 Green"
|
|
hexmask.long.byte 0x178 2.--7. 1. " CP2_94B ,Color Palette 2_94 Blue"
|
|
line.long 0x17C "CP2_95R,Color Palette 2 Register 95"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " CP2_95A ,Color Palette 2_95 Blend Ratio"
|
|
hexmask.long.byte 0x17C 18.--23. 1. " CP2_95R ,Color Palette 2_95 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x17C 10.--15. 1. " CP2_95G ,Color Palette 2_95 Green"
|
|
hexmask.long.byte 0x17C 2.--7. 1. " CP2_95B ,Color Palette 2_95 Blue"
|
|
line.long 0x180 "CP2_96R,Color Palette 2 Register 96"
|
|
hexmask.long.byte 0x180 24.--31. 1. " CP2_96A ,Color Palette 2_96 Blend Ratio"
|
|
hexmask.long.byte 0x180 18.--23. 1. " CP2_96R ,Color Palette 2_96 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x180 10.--15. 1. " CP2_96G ,Color Palette 2_96 Green"
|
|
hexmask.long.byte 0x180 2.--7. 1. " CP2_96B ,Color Palette 2_96 Blue"
|
|
line.long 0x184 "CP2_97R,Color Palette 2 Register 97"
|
|
hexmask.long.byte 0x184 24.--31. 1. " CP2_97A ,Color Palette 2_97 Blend Ratio"
|
|
hexmask.long.byte 0x184 18.--23. 1. " CP2_97R ,Color Palette 2_97 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x184 10.--15. 1. " CP2_97G ,Color Palette 2_97 Green"
|
|
hexmask.long.byte 0x184 2.--7. 1. " CP2_97B ,Color Palette 2_97 Blue"
|
|
line.long 0x188 "CP2_98R,Color Palette 2 Register 98"
|
|
hexmask.long.byte 0x188 24.--31. 1. " CP2_98A ,Color Palette 2_98 Blend Ratio"
|
|
hexmask.long.byte 0x188 18.--23. 1. " CP2_98R ,Color Palette 2_98 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x188 10.--15. 1. " CP2_98G ,Color Palette 2_98 Green"
|
|
hexmask.long.byte 0x188 2.--7. 1. " CP2_98B ,Color Palette 2_98 Blue"
|
|
line.long 0x18C "CP2_99R,Color Palette 2 Register 99"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " CP2_99A ,Color Palette 2_99 Blend Ratio"
|
|
hexmask.long.byte 0x18C 18.--23. 1. " CP2_99R ,Color Palette 2_99 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18C 10.--15. 1. " CP2_99G ,Color Palette 2_99 Green"
|
|
hexmask.long.byte 0x18C 2.--7. 1. " CP2_99B ,Color Palette 2_99 Blue"
|
|
line.long 0x190 "CP2_100R,Color Palette 2 Register 100"
|
|
hexmask.long.byte 0x190 24.--31. 1. " CP2_100A ,Color Palette 2_100 Blend Ratio"
|
|
hexmask.long.byte 0x190 18.--23. 1. " CP2_100R ,Color Palette 2_100 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x190 10.--15. 1. " CP2_100G ,Color Palette 2_100 Green"
|
|
hexmask.long.byte 0x190 2.--7. 1. " CP2_100B ,Color Palette 2_100 Blue"
|
|
line.long 0x194 "CP2_101R,Color Palette 2 Register 101"
|
|
hexmask.long.byte 0x194 24.--31. 1. " CP2_101A ,Color Palette 2_101 Blend Ratio"
|
|
hexmask.long.byte 0x194 18.--23. 1. " CP2_101R ,Color Palette 2_101 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x194 10.--15. 1. " CP2_101G ,Color Palette 2_101 Green"
|
|
hexmask.long.byte 0x194 2.--7. 1. " CP2_101B ,Color Palette 2_101 Blue"
|
|
line.long 0x198 "CP2_102R,Color Palette 2 Register 102"
|
|
hexmask.long.byte 0x198 24.--31. 1. " CP2_102A ,Color Palette 2_102 Blend Ratio"
|
|
hexmask.long.byte 0x198 18.--23. 1. " CP2_102R ,Color Palette 2_102 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x198 10.--15. 1. " CP2_102G ,Color Palette 2_102 Green"
|
|
hexmask.long.byte 0x198 2.--7. 1. " CP2_102B ,Color Palette 2_102 Blue"
|
|
line.long 0x19C "CP2_103R,Color Palette 2 Register 103"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " CP2_103A ,Color Palette 2_103 Blend Ratio"
|
|
hexmask.long.byte 0x19C 18.--23. 1. " CP2_103R ,Color Palette 2_103 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x19C 10.--15. 1. " CP2_103G ,Color Palette 2_103 Green"
|
|
hexmask.long.byte 0x19C 2.--7. 1. " CP2_103B ,Color Palette 2_103 Blue"
|
|
line.long 0x1A0 "CP2_104R,Color Palette 2 Register 104"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " CP2_104A ,Color Palette 2_104 Blend Ratio"
|
|
hexmask.long.byte 0x1A0 18.--23. 1. " CP2_104R ,Color Palette 2_104 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A0 10.--15. 1. " CP2_104G ,Color Palette 2_104 Green"
|
|
hexmask.long.byte 0x1A0 2.--7. 1. " CP2_104B ,Color Palette 2_104 Blue"
|
|
line.long 0x1A4 "CP2_105R,Color Palette 2 Register 105"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " CP2_105A ,Color Palette 2_105 Blend Ratio"
|
|
hexmask.long.byte 0x1A4 18.--23. 1. " CP2_105R ,Color Palette 2_105 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A4 10.--15. 1. " CP2_105G ,Color Palette 2_105 Green"
|
|
hexmask.long.byte 0x1A4 2.--7. 1. " CP2_105B ,Color Palette 2_105 Blue"
|
|
line.long 0x1A8 "CP2_106R,Color Palette 2 Register 106"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " CP2_106A ,Color Palette 2_106 Blend Ratio"
|
|
hexmask.long.byte 0x1A8 18.--23. 1. " CP2_106R ,Color Palette 2_106 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A8 10.--15. 1. " CP2_106G ,Color Palette 2_106 Green"
|
|
hexmask.long.byte 0x1A8 2.--7. 1. " CP2_106B ,Color Palette 2_106 Blue"
|
|
line.long 0x1AC "CP2_107R,Color Palette 2 Register 107"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " CP2_107A ,Color Palette 2_107 Blend Ratio"
|
|
hexmask.long.byte 0x1AC 18.--23. 1. " CP2_107R ,Color Palette 2_107 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1AC 10.--15. 1. " CP2_107G ,Color Palette 2_107 Green"
|
|
hexmask.long.byte 0x1AC 2.--7. 1. " CP2_107B ,Color Palette 2_107 Blue"
|
|
line.long 0x1B0 "CP2_108R,Color Palette 2 Register 108"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " CP2_108A ,Color Palette 2_108 Blend Ratio"
|
|
hexmask.long.byte 0x1B0 18.--23. 1. " CP2_108R ,Color Palette 2_108 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B0 10.--15. 1. " CP2_108G ,Color Palette 2_108 Green"
|
|
hexmask.long.byte 0x1B0 2.--7. 1. " CP2_108B ,Color Palette 2_108 Blue"
|
|
line.long 0x1B4 "CP2_109R,Color Palette 2 Register 109"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " CP2_109A ,Color Palette 2_109 Blend Ratio"
|
|
hexmask.long.byte 0x1B4 18.--23. 1. " CP2_109R ,Color Palette 2_109 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B4 10.--15. 1. " CP2_109G ,Color Palette 2_109 Green"
|
|
hexmask.long.byte 0x1B4 2.--7. 1. " CP2_109B ,Color Palette 2_109 Blue"
|
|
line.long 0x1B8 "CP2_110R,Color Palette 2 Register 110"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " CP2_110A ,Color Palette 2_110 Blend Ratio"
|
|
hexmask.long.byte 0x1B8 18.--23. 1. " CP2_110R ,Color Palette 2_110 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B8 10.--15. 1. " CP2_110G ,Color Palette 2_110 Green"
|
|
hexmask.long.byte 0x1B8 2.--7. 1. " CP2_110B ,Color Palette 2_110 Blue"
|
|
line.long 0x1BC "CP2_111R,Color Palette 2 Register 111"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " CP2_111A ,Color Palette 2_111 Blend Ratio"
|
|
hexmask.long.byte 0x1BC 18.--23. 1. " CP2_111R ,Color Palette 2_111 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1BC 10.--15. 1. " CP2_111G ,Color Palette 2_111 Green"
|
|
hexmask.long.byte 0x1BC 2.--7. 1. " CP2_111B ,Color Palette 2_111 Blue"
|
|
line.long 0x1C0 "CP2_112R,Color Palette 2 Register 112"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " CP2_112A ,Color Palette 2_112 Blend Ratio"
|
|
hexmask.long.byte 0x1C0 18.--23. 1. " CP2_112R ,Color Palette 2_112 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C0 10.--15. 1. " CP2_112G ,Color Palette 2_112 Green"
|
|
hexmask.long.byte 0x1C0 2.--7. 1. " CP2_112B ,Color Palette 2_112 Blue"
|
|
line.long 0x1C4 "CP2_113R,Color Palette 2 Register 113"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " CP2_113A ,Color Palette 2_113 Blend Ratio"
|
|
hexmask.long.byte 0x1C4 18.--23. 1. " CP2_113R ,Color Palette 2_113 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C4 10.--15. 1. " CP2_113G ,Color Palette 2_113 Green"
|
|
hexmask.long.byte 0x1C4 2.--7. 1. " CP2_113B ,Color Palette 2_113 Blue"
|
|
line.long 0x1C8 "CP2_114R,Color Palette 2 Register 114"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " CP2_114A ,Color Palette 2_114 Blend Ratio"
|
|
hexmask.long.byte 0x1C8 18.--23. 1. " CP2_114R ,Color Palette 2_114 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C8 10.--15. 1. " CP2_114G ,Color Palette 2_114 Green"
|
|
hexmask.long.byte 0x1C8 2.--7. 1. " CP2_114B ,Color Palette 2_114 Blue"
|
|
line.long 0x1CC "CP2_115R,Color Palette 2 Register 115"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " CP2_115A ,Color Palette 2_115 Blend Ratio"
|
|
hexmask.long.byte 0x1CC 18.--23. 1. " CP2_115R ,Color Palette 2_115 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1CC 10.--15. 1. " CP2_115G ,Color Palette 2_115 Green"
|
|
hexmask.long.byte 0x1CC 2.--7. 1. " CP2_115B ,Color Palette 2_115 Blue"
|
|
line.long 0x1D0 "CP2_116R,Color Palette 2 Register 116"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " CP2_116A ,Color Palette 2_116 Blend Ratio"
|
|
hexmask.long.byte 0x1D0 18.--23. 1. " CP2_116R ,Color Palette 2_116 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D0 10.--15. 1. " CP2_116G ,Color Palette 2_116 Green"
|
|
hexmask.long.byte 0x1D0 2.--7. 1. " CP2_116B ,Color Palette 2_116 Blue"
|
|
line.long 0x1D4 "CP2_117R,Color Palette 2 Register 117"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " CP2_117A ,Color Palette 2_117 Blend Ratio"
|
|
hexmask.long.byte 0x1D4 18.--23. 1. " CP2_117R ,Color Palette 2_117 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D4 10.--15. 1. " CP2_117G ,Color Palette 2_117 Green"
|
|
hexmask.long.byte 0x1D4 2.--7. 1. " CP2_117B ,Color Palette 2_117 Blue"
|
|
line.long 0x1D8 "CP2_118R,Color Palette 2 Register 118"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " CP2_118A ,Color Palette 2_118 Blend Ratio"
|
|
hexmask.long.byte 0x1D8 18.--23. 1. " CP2_118R ,Color Palette 2_118 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D8 10.--15. 1. " CP2_118G ,Color Palette 2_118 Green"
|
|
hexmask.long.byte 0x1D8 2.--7. 1. " CP2_118B ,Color Palette 2_118 Blue"
|
|
line.long 0x1DC "CP2_119R,Color Palette 2 Register 119"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " CP2_119A ,Color Palette 2_119 Blend Ratio"
|
|
hexmask.long.byte 0x1DC 18.--23. 1. " CP2_119R ,Color Palette 2_119 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1DC 10.--15. 1. " CP2_119G ,Color Palette 2_119 Green"
|
|
hexmask.long.byte 0x1DC 2.--7. 1. " CP2_119B ,Color Palette 2_119 Blue"
|
|
line.long 0x1E0 "CP2_120R,Color Palette 2 Register 120"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " CP2_120A ,Color Palette 2_120 Blend Ratio"
|
|
hexmask.long.byte 0x1E0 18.--23. 1. " CP2_120R ,Color Palette 2_120 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E0 10.--15. 1. " CP2_120G ,Color Palette 2_120 Green"
|
|
hexmask.long.byte 0x1E0 2.--7. 1. " CP2_120B ,Color Palette 2_120 Blue"
|
|
line.long 0x1E4 "CP2_121R,Color Palette 2 Register 121"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " CP2_121A ,Color Palette 2_121 Blend Ratio"
|
|
hexmask.long.byte 0x1E4 18.--23. 1. " CP2_121R ,Color Palette 2_121 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E4 10.--15. 1. " CP2_121G ,Color Palette 2_121 Green"
|
|
hexmask.long.byte 0x1E4 2.--7. 1. " CP2_121B ,Color Palette 2_121 Blue"
|
|
line.long 0x1E8 "CP2_122R,Color Palette 2 Register 122"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " CP2_122A ,Color Palette 2_122 Blend Ratio"
|
|
hexmask.long.byte 0x1E8 18.--23. 1. " CP2_122R ,Color Palette 2_122 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E8 10.--15. 1. " CP2_122G ,Color Palette 2_122 Green"
|
|
hexmask.long.byte 0x1E8 2.--7. 1. " CP2_122B ,Color Palette 2_122 Blue"
|
|
line.long 0x1EC "CP2_123R,Color Palette 2 Register 123"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " CP2_123A ,Color Palette 2_123 Blend Ratio"
|
|
hexmask.long.byte 0x1EC 18.--23. 1. " CP2_123R ,Color Palette 2_123 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1EC 10.--15. 1. " CP2_123G ,Color Palette 2_123 Green"
|
|
hexmask.long.byte 0x1EC 2.--7. 1. " CP2_123B ,Color Palette 2_123 Blue"
|
|
line.long 0x1F0 "CP2_124R,Color Palette 2 Register 124"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " CP2_124A ,Color Palette 2_124 Blend Ratio"
|
|
hexmask.long.byte 0x1F0 18.--23. 1. " CP2_124R ,Color Palette 2_124 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F0 10.--15. 1. " CP2_124G ,Color Palette 2_124 Green"
|
|
hexmask.long.byte 0x1F0 2.--7. 1. " CP2_124B ,Color Palette 2_124 Blue"
|
|
line.long 0x1F4 "CP2_125R,Color Palette 2 Register 125"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " CP2_125A ,Color Palette 2_125 Blend Ratio"
|
|
hexmask.long.byte 0x1F4 18.--23. 1. " CP2_125R ,Color Palette 2_125 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F4 10.--15. 1. " CP2_125G ,Color Palette 2_125 Green"
|
|
hexmask.long.byte 0x1F4 2.--7. 1. " CP2_125B ,Color Palette 2_125 Blue"
|
|
line.long 0x1F8 "CP2_126R,Color Palette 2 Register 126"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " CP2_126A ,Color Palette 2_126 Blend Ratio"
|
|
hexmask.long.byte 0x1F8 18.--23. 1. " CP2_126R ,Color Palette 2_126 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F8 10.--15. 1. " CP2_126G ,Color Palette 2_126 Green"
|
|
hexmask.long.byte 0x1F8 2.--7. 1. " CP2_126B ,Color Palette 2_126 Blue"
|
|
line.long 0x1FC "CP2_127R,Color Palette 2 Register 127"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " CP2_127A ,Color Palette 2_127 Blend Ratio"
|
|
hexmask.long.byte 0x1FC 18.--23. 1. " CP2_127R ,Color Palette 2_127 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1FC 10.--15. 1. " CP2_127G ,Color Palette 2_127 Green"
|
|
hexmask.long.byte 0x1FC 2.--7. 1. " CP2_127B ,Color Palette 2_127 Blue"
|
|
line.long 0x200 "CP2_128R,Color Palette 2 Register 128"
|
|
hexmask.long.byte 0x200 24.--31. 1. " CP2_128A ,Color Palette 2_128 Blend Ratio"
|
|
hexmask.long.byte 0x200 18.--23. 1. " CP2_128R ,Color Palette 2_128 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x200 10.--15. 1. " CP2_128G ,Color Palette 2_128 Green"
|
|
hexmask.long.byte 0x200 2.--7. 1. " CP2_128B ,Color Palette 2_128 Blue"
|
|
line.long 0x204 "CP2_129R,Color Palette 2 Register 129"
|
|
hexmask.long.byte 0x204 24.--31. 1. " CP2_129A ,Color Palette 2_129 Blend Ratio"
|
|
hexmask.long.byte 0x204 18.--23. 1. " CP2_129R ,Color Palette 2_129 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x204 10.--15. 1. " CP2_129G ,Color Palette 2_129 Green"
|
|
hexmask.long.byte 0x204 2.--7. 1. " CP2_129B ,Color Palette 2_129 Blue"
|
|
line.long 0x208 "CP2_130R,Color Palette 2 Register 130"
|
|
hexmask.long.byte 0x208 24.--31. 1. " CP2_130A ,Color Palette 2_130 Blend Ratio"
|
|
hexmask.long.byte 0x208 18.--23. 1. " CP2_130R ,Color Palette 2_130 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x208 10.--15. 1. " CP2_130G ,Color Palette 2_130 Green"
|
|
hexmask.long.byte 0x208 2.--7. 1. " CP2_130B ,Color Palette 2_130 Blue"
|
|
line.long 0x20C "CP2_131R,Color Palette 2 Register 131"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " CP2_131A ,Color Palette 2_131 Blend Ratio"
|
|
hexmask.long.byte 0x20C 18.--23. 1. " CP2_131R ,Color Palette 2_131 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20C 10.--15. 1. " CP2_131G ,Color Palette 2_131 Green"
|
|
hexmask.long.byte 0x20C 2.--7. 1. " CP2_131B ,Color Palette 2_131 Blue"
|
|
line.long 0x210 "CP2_132R,Color Palette 2 Register 132"
|
|
hexmask.long.byte 0x210 24.--31. 1. " CP2_132A ,Color Palette 2_132 Blend Ratio"
|
|
hexmask.long.byte 0x210 18.--23. 1. " CP2_132R ,Color Palette 2_132 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x210 10.--15. 1. " CP2_132G ,Color Palette 2_132 Green"
|
|
hexmask.long.byte 0x210 2.--7. 1. " CP2_132B ,Color Palette 2_132 Blue"
|
|
line.long 0x214 "CP2_133R,Color Palette 2 Register 133"
|
|
hexmask.long.byte 0x214 24.--31. 1. " CP2_133A ,Color Palette 2_133 Blend Ratio"
|
|
hexmask.long.byte 0x214 18.--23. 1. " CP2_133R ,Color Palette 2_133 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x214 10.--15. 1. " CP2_133G ,Color Palette 2_133 Green"
|
|
hexmask.long.byte 0x214 2.--7. 1. " CP2_133B ,Color Palette 2_133 Blue"
|
|
line.long 0x218 "CP2_134R,Color Palette 2 Register 134"
|
|
hexmask.long.byte 0x218 24.--31. 1. " CP2_134A ,Color Palette 2_134 Blend Ratio"
|
|
hexmask.long.byte 0x218 18.--23. 1. " CP2_134R ,Color Palette 2_134 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x218 10.--15. 1. " CP2_134G ,Color Palette 2_134 Green"
|
|
hexmask.long.byte 0x218 2.--7. 1. " CP2_134B ,Color Palette 2_134 Blue"
|
|
line.long 0x21C "CP2_135R,Color Palette 2 Register 135"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " CP2_135A ,Color Palette 2_135 Blend Ratio"
|
|
hexmask.long.byte 0x21C 18.--23. 1. " CP2_135R ,Color Palette 2_135 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x21C 10.--15. 1. " CP2_135G ,Color Palette 2_135 Green"
|
|
hexmask.long.byte 0x21C 2.--7. 1. " CP2_135B ,Color Palette 2_135 Blue"
|
|
line.long 0x220 "CP2_136R,Color Palette 2 Register 136"
|
|
hexmask.long.byte 0x220 24.--31. 1. " CP2_136A ,Color Palette 2_136 Blend Ratio"
|
|
hexmask.long.byte 0x220 18.--23. 1. " CP2_136R ,Color Palette 2_136 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x220 10.--15. 1. " CP2_136G ,Color Palette 2_136 Green"
|
|
hexmask.long.byte 0x220 2.--7. 1. " CP2_136B ,Color Palette 2_136 Blue"
|
|
line.long 0x224 "CP2_137R,Color Palette 2 Register 137"
|
|
hexmask.long.byte 0x224 24.--31. 1. " CP2_137A ,Color Palette 2_137 Blend Ratio"
|
|
hexmask.long.byte 0x224 18.--23. 1. " CP2_137R ,Color Palette 2_137 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x224 10.--15. 1. " CP2_137G ,Color Palette 2_137 Green"
|
|
hexmask.long.byte 0x224 2.--7. 1. " CP2_137B ,Color Palette 2_137 Blue"
|
|
line.long 0x228 "CP2_138R,Color Palette 2 Register 138"
|
|
hexmask.long.byte 0x228 24.--31. 1. " CP2_138A ,Color Palette 2_138 Blend Ratio"
|
|
hexmask.long.byte 0x228 18.--23. 1. " CP2_138R ,Color Palette 2_138 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x228 10.--15. 1. " CP2_138G ,Color Palette 2_138 Green"
|
|
hexmask.long.byte 0x228 2.--7. 1. " CP2_138B ,Color Palette 2_138 Blue"
|
|
line.long 0x22C "CP2_139R,Color Palette 2 Register 139"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " CP2_139A ,Color Palette 2_139 Blend Ratio"
|
|
hexmask.long.byte 0x22C 18.--23. 1. " CP2_139R ,Color Palette 2_139 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x22C 10.--15. 1. " CP2_139G ,Color Palette 2_139 Green"
|
|
hexmask.long.byte 0x22C 2.--7. 1. " CP2_139B ,Color Palette 2_139 Blue"
|
|
line.long 0x230 "CP2_140R,Color Palette 2 Register 140"
|
|
hexmask.long.byte 0x230 24.--31. 1. " CP2_140A ,Color Palette 2_140 Blend Ratio"
|
|
hexmask.long.byte 0x230 18.--23. 1. " CP2_140R ,Color Palette 2_140 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x230 10.--15. 1. " CP2_140G ,Color Palette 2_140 Green"
|
|
hexmask.long.byte 0x230 2.--7. 1. " CP2_140B ,Color Palette 2_140 Blue"
|
|
line.long 0x234 "CP2_141R,Color Palette 2 Register 141"
|
|
hexmask.long.byte 0x234 24.--31. 1. " CP2_141A ,Color Palette 2_141 Blend Ratio"
|
|
hexmask.long.byte 0x234 18.--23. 1. " CP2_141R ,Color Palette 2_141 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x234 10.--15. 1. " CP2_141G ,Color Palette 2_141 Green"
|
|
hexmask.long.byte 0x234 2.--7. 1. " CP2_141B ,Color Palette 2_141 Blue"
|
|
line.long 0x238 "CP2_142R,Color Palette 2 Register 142"
|
|
hexmask.long.byte 0x238 24.--31. 1. " CP2_142A ,Color Palette 2_142 Blend Ratio"
|
|
hexmask.long.byte 0x238 18.--23. 1. " CP2_142R ,Color Palette 2_142 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x238 10.--15. 1. " CP2_142G ,Color Palette 2_142 Green"
|
|
hexmask.long.byte 0x238 2.--7. 1. " CP2_142B ,Color Palette 2_142 Blue"
|
|
line.long 0x23C "CP2_143R,Color Palette 2 Register 143"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " CP2_143A ,Color Palette 2_143 Blend Ratio"
|
|
hexmask.long.byte 0x23C 18.--23. 1. " CP2_143R ,Color Palette 2_143 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x23C 10.--15. 1. " CP2_143G ,Color Palette 2_143 Green"
|
|
hexmask.long.byte 0x23C 2.--7. 1. " CP2_143B ,Color Palette 2_143 Blue"
|
|
line.long 0x240 "CP2_144R,Color Palette 2 Register 144"
|
|
hexmask.long.byte 0x240 24.--31. 1. " CP2_144A ,Color Palette 2_144 Blend Ratio"
|
|
hexmask.long.byte 0x240 18.--23. 1. " CP2_144R ,Color Palette 2_144 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x240 10.--15. 1. " CP2_144G ,Color Palette 2_144 Green"
|
|
hexmask.long.byte 0x240 2.--7. 1. " CP2_144B ,Color Palette 2_144 Blue"
|
|
line.long 0x244 "CP2_145R,Color Palette 2 Register 145"
|
|
hexmask.long.byte 0x244 24.--31. 1. " CP2_145A ,Color Palette 2_145 Blend Ratio"
|
|
hexmask.long.byte 0x244 18.--23. 1. " CP2_145R ,Color Palette 2_145 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x244 10.--15. 1. " CP2_145G ,Color Palette 2_145 Green"
|
|
hexmask.long.byte 0x244 2.--7. 1. " CP2_145B ,Color Palette 2_145 Blue"
|
|
line.long 0x248 "CP2_146R,Color Palette 2 Register 146"
|
|
hexmask.long.byte 0x248 24.--31. 1. " CP2_146A ,Color Palette 2_146 Blend Ratio"
|
|
hexmask.long.byte 0x248 18.--23. 1. " CP2_146R ,Color Palette 2_146 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x248 10.--15. 1. " CP2_146G ,Color Palette 2_146 Green"
|
|
hexmask.long.byte 0x248 2.--7. 1. " CP2_146B ,Color Palette 2_146 Blue"
|
|
line.long 0x24C "CP2_147R,Color Palette 2 Register 147"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " CP2_147A ,Color Palette 2_147 Blend Ratio"
|
|
hexmask.long.byte 0x24C 18.--23. 1. " CP2_147R ,Color Palette 2_147 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24C 10.--15. 1. " CP2_147G ,Color Palette 2_147 Green"
|
|
hexmask.long.byte 0x24C 2.--7. 1. " CP2_147B ,Color Palette 2_147 Blue"
|
|
line.long 0x250 "CP2_148R,Color Palette 2 Register 148"
|
|
hexmask.long.byte 0x250 24.--31. 1. " CP2_148A ,Color Palette 2_148 Blend Ratio"
|
|
hexmask.long.byte 0x250 18.--23. 1. " CP2_148R ,Color Palette 2_148 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x250 10.--15. 1. " CP2_148G ,Color Palette 2_148 Green"
|
|
hexmask.long.byte 0x250 2.--7. 1. " CP2_148B ,Color Palette 2_148 Blue"
|
|
line.long 0x254 "CP2_149R,Color Palette 2 Register 149"
|
|
hexmask.long.byte 0x254 24.--31. 1. " CP2_149A ,Color Palette 2_149 Blend Ratio"
|
|
hexmask.long.byte 0x254 18.--23. 1. " CP2_149R ,Color Palette 2_149 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x254 10.--15. 1. " CP2_149G ,Color Palette 2_149 Green"
|
|
hexmask.long.byte 0x254 2.--7. 1. " CP2_149B ,Color Palette 2_149 Blue"
|
|
line.long 0x258 "CP2_150R,Color Palette 2 Register 150"
|
|
hexmask.long.byte 0x258 24.--31. 1. " CP2_150A ,Color Palette 2_150 Blend Ratio"
|
|
hexmask.long.byte 0x258 18.--23. 1. " CP2_150R ,Color Palette 2_150 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x258 10.--15. 1. " CP2_150G ,Color Palette 2_150 Green"
|
|
hexmask.long.byte 0x258 2.--7. 1. " CP2_150B ,Color Palette 2_150 Blue"
|
|
line.long 0x25C "CP2_151R,Color Palette 2 Register 151"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " CP2_151A ,Color Palette 2_151 Blend Ratio"
|
|
hexmask.long.byte 0x25C 18.--23. 1. " CP2_151R ,Color Palette 2_151 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x25C 10.--15. 1. " CP2_151G ,Color Palette 2_151 Green"
|
|
hexmask.long.byte 0x25C 2.--7. 1. " CP2_151B ,Color Palette 2_151 Blue"
|
|
line.long 0x260 "CP2_152R,Color Palette 2 Register 152"
|
|
hexmask.long.byte 0x260 24.--31. 1. " CP2_152A ,Color Palette 2_152 Blend Ratio"
|
|
hexmask.long.byte 0x260 18.--23. 1. " CP2_152R ,Color Palette 2_152 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x260 10.--15. 1. " CP2_152G ,Color Palette 2_152 Green"
|
|
hexmask.long.byte 0x260 2.--7. 1. " CP2_152B ,Color Palette 2_152 Blue"
|
|
line.long 0x264 "CP2_153R,Color Palette 2 Register 153"
|
|
hexmask.long.byte 0x264 24.--31. 1. " CP2_153A ,Color Palette 2_153 Blend Ratio"
|
|
hexmask.long.byte 0x264 18.--23. 1. " CP2_153R ,Color Palette 2_153 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x264 10.--15. 1. " CP2_153G ,Color Palette 2_153 Green"
|
|
hexmask.long.byte 0x264 2.--7. 1. " CP2_153B ,Color Palette 2_153 Blue"
|
|
line.long 0x268 "CP2_154R,Color Palette 2 Register 154"
|
|
hexmask.long.byte 0x268 24.--31. 1. " CP2_154A ,Color Palette 2_154 Blend Ratio"
|
|
hexmask.long.byte 0x268 18.--23. 1. " CP2_154R ,Color Palette 2_154 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x268 10.--15. 1. " CP2_154G ,Color Palette 2_154 Green"
|
|
hexmask.long.byte 0x268 2.--7. 1. " CP2_154B ,Color Palette 2_154 Blue"
|
|
line.long 0x26C "CP2_155R,Color Palette 2 Register 155"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " CP2_155A ,Color Palette 2_155 Blend Ratio"
|
|
hexmask.long.byte 0x26C 18.--23. 1. " CP2_155R ,Color Palette 2_155 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x26C 10.--15. 1. " CP2_155G ,Color Palette 2_155 Green"
|
|
hexmask.long.byte 0x26C 2.--7. 1. " CP2_155B ,Color Palette 2_155 Blue"
|
|
line.long 0x270 "CP2_156R,Color Palette 2 Register 156"
|
|
hexmask.long.byte 0x270 24.--31. 1. " CP2_156A ,Color Palette 2_156 Blend Ratio"
|
|
hexmask.long.byte 0x270 18.--23. 1. " CP2_156R ,Color Palette 2_156 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x270 10.--15. 1. " CP2_156G ,Color Palette 2_156 Green"
|
|
hexmask.long.byte 0x270 2.--7. 1. " CP2_156B ,Color Palette 2_156 Blue"
|
|
line.long 0x274 "CP2_157R,Color Palette 2 Register 157"
|
|
hexmask.long.byte 0x274 24.--31. 1. " CP2_157A ,Color Palette 2_157 Blend Ratio"
|
|
hexmask.long.byte 0x274 18.--23. 1. " CP2_157R ,Color Palette 2_157 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x274 10.--15. 1. " CP2_157G ,Color Palette 2_157 Green"
|
|
hexmask.long.byte 0x274 2.--7. 1. " CP2_157B ,Color Palette 2_157 Blue"
|
|
line.long 0x278 "CP2_158R,Color Palette 2 Register 158"
|
|
hexmask.long.byte 0x278 24.--31. 1. " CP2_158A ,Color Palette 2_158 Blend Ratio"
|
|
hexmask.long.byte 0x278 18.--23. 1. " CP2_158R ,Color Palette 2_158 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x278 10.--15. 1. " CP2_158G ,Color Palette 2_158 Green"
|
|
hexmask.long.byte 0x278 2.--7. 1. " CP2_158B ,Color Palette 2_158 Blue"
|
|
line.long 0x27C "CP2_159R,Color Palette 2 Register 159"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " CP2_159A ,Color Palette 2_159 Blend Ratio"
|
|
hexmask.long.byte 0x27C 18.--23. 1. " CP2_159R ,Color Palette 2_159 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x27C 10.--15. 1. " CP2_159G ,Color Palette 2_159 Green"
|
|
hexmask.long.byte 0x27C 2.--7. 1. " CP2_159B ,Color Palette 2_159 Blue"
|
|
line.long 0x280 "CP2_160R,Color Palette 2 Register 160"
|
|
hexmask.long.byte 0x280 24.--31. 1. " CP2_160A ,Color Palette 2_160 Blend Ratio"
|
|
hexmask.long.byte 0x280 18.--23. 1. " CP2_160R ,Color Palette 2_160 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x280 10.--15. 1. " CP2_160G ,Color Palette 2_160 Green"
|
|
hexmask.long.byte 0x280 2.--7. 1. " CP2_160B ,Color Palette 2_160 Blue"
|
|
line.long 0x284 "CP2_161R,Color Palette 2 Register 161"
|
|
hexmask.long.byte 0x284 24.--31. 1. " CP2_161A ,Color Palette 2_161 Blend Ratio"
|
|
hexmask.long.byte 0x284 18.--23. 1. " CP2_161R ,Color Palette 2_161 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x284 10.--15. 1. " CP2_161G ,Color Palette 2_161 Green"
|
|
hexmask.long.byte 0x284 2.--7. 1. " CP2_161B ,Color Palette 2_161 Blue"
|
|
line.long 0x288 "CP2_162R,Color Palette 2 Register 162"
|
|
hexmask.long.byte 0x288 24.--31. 1. " CP2_162A ,Color Palette 2_162 Blend Ratio"
|
|
hexmask.long.byte 0x288 18.--23. 1. " CP2_162R ,Color Palette 2_162 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x288 10.--15. 1. " CP2_162G ,Color Palette 2_162 Green"
|
|
hexmask.long.byte 0x288 2.--7. 1. " CP2_162B ,Color Palette 2_162 Blue"
|
|
line.long 0x28C "CP2_163R,Color Palette 2 Register 163"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " CP2_163A ,Color Palette 2_163 Blend Ratio"
|
|
hexmask.long.byte 0x28C 18.--23. 1. " CP2_163R ,Color Palette 2_163 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28C 10.--15. 1. " CP2_163G ,Color Palette 2_163 Green"
|
|
hexmask.long.byte 0x28C 2.--7. 1. " CP2_163B ,Color Palette 2_163 Blue"
|
|
line.long 0x290 "CP2_164R,Color Palette 2 Register 164"
|
|
hexmask.long.byte 0x290 24.--31. 1. " CP2_164A ,Color Palette 2_164 Blend Ratio"
|
|
hexmask.long.byte 0x290 18.--23. 1. " CP2_164R ,Color Palette 2_164 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x290 10.--15. 1. " CP2_164G ,Color Palette 2_164 Green"
|
|
hexmask.long.byte 0x290 2.--7. 1. " CP2_164B ,Color Palette 2_164 Blue"
|
|
line.long 0x294 "CP2_165R,Color Palette 2 Register 165"
|
|
hexmask.long.byte 0x294 24.--31. 1. " CP2_165A ,Color Palette 2_165 Blend Ratio"
|
|
hexmask.long.byte 0x294 18.--23. 1. " CP2_165R ,Color Palette 2_165 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x294 10.--15. 1. " CP2_165G ,Color Palette 2_165 Green"
|
|
hexmask.long.byte 0x294 2.--7. 1. " CP2_165B ,Color Palette 2_165 Blue"
|
|
line.long 0x298 "CP2_166R,Color Palette 2 Register 166"
|
|
hexmask.long.byte 0x298 24.--31. 1. " CP2_166A ,Color Palette 2_166 Blend Ratio"
|
|
hexmask.long.byte 0x298 18.--23. 1. " CP2_166R ,Color Palette 2_166 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x298 10.--15. 1. " CP2_166G ,Color Palette 2_166 Green"
|
|
hexmask.long.byte 0x298 2.--7. 1. " CP2_166B ,Color Palette 2_166 Blue"
|
|
line.long 0x29C "CP2_167R,Color Palette 2 Register 167"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " CP2_167A ,Color Palette 2_167 Blend Ratio"
|
|
hexmask.long.byte 0x29C 18.--23. 1. " CP2_167R ,Color Palette 2_167 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x29C 10.--15. 1. " CP2_167G ,Color Palette 2_167 Green"
|
|
hexmask.long.byte 0x29C 2.--7. 1. " CP2_167B ,Color Palette 2_167 Blue"
|
|
line.long 0x2A0 "CP2_168R,Color Palette 2 Register 168"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " CP2_168A ,Color Palette 2_168 Blend Ratio"
|
|
hexmask.long.byte 0x2A0 18.--23. 1. " CP2_168R ,Color Palette 2_168 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A0 10.--15. 1. " CP2_168G ,Color Palette 2_168 Green"
|
|
hexmask.long.byte 0x2A0 2.--7. 1. " CP2_168B ,Color Palette 2_168 Blue"
|
|
line.long 0x2A4 "CP2_169R,Color Palette 2 Register 169"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " CP2_169A ,Color Palette 2_169 Blend Ratio"
|
|
hexmask.long.byte 0x2A4 18.--23. 1. " CP2_169R ,Color Palette 2_169 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A4 10.--15. 1. " CP2_169G ,Color Palette 2_169 Green"
|
|
hexmask.long.byte 0x2A4 2.--7. 1. " CP2_169B ,Color Palette 2_169 Blue"
|
|
line.long 0x2A8 "CP2_170R,Color Palette 2 Register 170"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " CP2_170A ,Color Palette 2_170 Blend Ratio"
|
|
hexmask.long.byte 0x2A8 18.--23. 1. " CP2_170R ,Color Palette 2_170 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A8 10.--15. 1. " CP2_170G ,Color Palette 2_170 Green"
|
|
hexmask.long.byte 0x2A8 2.--7. 1. " CP2_170B ,Color Palette 2_170 Blue"
|
|
line.long 0x2AC "CP2_171R,Color Palette 2 Register 171"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " CP2_171A ,Color Palette 2_171 Blend Ratio"
|
|
hexmask.long.byte 0x2AC 18.--23. 1. " CP2_171R ,Color Palette 2_171 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2AC 10.--15. 1. " CP2_171G ,Color Palette 2_171 Green"
|
|
hexmask.long.byte 0x2AC 2.--7. 1. " CP2_171B ,Color Palette 2_171 Blue"
|
|
line.long 0x2B0 "CP2_172R,Color Palette 2 Register 172"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " CP2_172A ,Color Palette 2_172 Blend Ratio"
|
|
hexmask.long.byte 0x2B0 18.--23. 1. " CP2_172R ,Color Palette 2_172 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B0 10.--15. 1. " CP2_172G ,Color Palette 2_172 Green"
|
|
hexmask.long.byte 0x2B0 2.--7. 1. " CP2_172B ,Color Palette 2_172 Blue"
|
|
line.long 0x2B4 "CP2_173R,Color Palette 2 Register 173"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " CP2_173A ,Color Palette 2_173 Blend Ratio"
|
|
hexmask.long.byte 0x2B4 18.--23. 1. " CP2_173R ,Color Palette 2_173 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B4 10.--15. 1. " CP2_173G ,Color Palette 2_173 Green"
|
|
hexmask.long.byte 0x2B4 2.--7. 1. " CP2_173B ,Color Palette 2_173 Blue"
|
|
line.long 0x2B8 "CP2_174R,Color Palette 2 Register 174"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " CP2_174A ,Color Palette 2_174 Blend Ratio"
|
|
hexmask.long.byte 0x2B8 18.--23. 1. " CP2_174R ,Color Palette 2_174 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B8 10.--15. 1. " CP2_174G ,Color Palette 2_174 Green"
|
|
hexmask.long.byte 0x2B8 2.--7. 1. " CP2_174B ,Color Palette 2_174 Blue"
|
|
line.long 0x2BC "CP2_175R,Color Palette 2 Register 175"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " CP2_175A ,Color Palette 2_175 Blend Ratio"
|
|
hexmask.long.byte 0x2BC 18.--23. 1. " CP2_175R ,Color Palette 2_175 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2BC 10.--15. 1. " CP2_175G ,Color Palette 2_175 Green"
|
|
hexmask.long.byte 0x2BC 2.--7. 1. " CP2_175B ,Color Palette 2_175 Blue"
|
|
line.long 0x2C0 "CP2_176R,Color Palette 2 Register 176"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " CP2_176A ,Color Palette 2_176 Blend Ratio"
|
|
hexmask.long.byte 0x2C0 18.--23. 1. " CP2_176R ,Color Palette 2_176 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C0 10.--15. 1. " CP2_176G ,Color Palette 2_176 Green"
|
|
hexmask.long.byte 0x2C0 2.--7. 1. " CP2_176B ,Color Palette 2_176 Blue"
|
|
line.long 0x2C4 "CP2_177R,Color Palette 2 Register 177"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " CP2_177A ,Color Palette 2_177 Blend Ratio"
|
|
hexmask.long.byte 0x2C4 18.--23. 1. " CP2_177R ,Color Palette 2_177 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C4 10.--15. 1. " CP2_177G ,Color Palette 2_177 Green"
|
|
hexmask.long.byte 0x2C4 2.--7. 1. " CP2_177B ,Color Palette 2_177 Blue"
|
|
line.long 0x2C8 "CP2_178R,Color Palette 2 Register 178"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " CP2_178A ,Color Palette 2_178 Blend Ratio"
|
|
hexmask.long.byte 0x2C8 18.--23. 1. " CP2_178R ,Color Palette 2_178 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C8 10.--15. 1. " CP2_178G ,Color Palette 2_178 Green"
|
|
hexmask.long.byte 0x2C8 2.--7. 1. " CP2_178B ,Color Palette 2_178 Blue"
|
|
line.long 0x2CC "CP2_179R,Color Palette 2 Register 179"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " CP2_179A ,Color Palette 2_179 Blend Ratio"
|
|
hexmask.long.byte 0x2CC 18.--23. 1. " CP2_179R ,Color Palette 2_179 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2CC 10.--15. 1. " CP2_179G ,Color Palette 2_179 Green"
|
|
hexmask.long.byte 0x2CC 2.--7. 1. " CP2_179B ,Color Palette 2_179 Blue"
|
|
line.long 0x2D0 "CP2_180R,Color Palette 2 Register 180"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " CP2_180A ,Color Palette 2_180 Blend Ratio"
|
|
hexmask.long.byte 0x2D0 18.--23. 1. " CP2_180R ,Color Palette 2_180 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D0 10.--15. 1. " CP2_180G ,Color Palette 2_180 Green"
|
|
hexmask.long.byte 0x2D0 2.--7. 1. " CP2_180B ,Color Palette 2_180 Blue"
|
|
line.long 0x2D4 "CP2_181R,Color Palette 2 Register 181"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " CP2_181A ,Color Palette 2_181 Blend Ratio"
|
|
hexmask.long.byte 0x2D4 18.--23. 1. " CP2_181R ,Color Palette 2_181 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D4 10.--15. 1. " CP2_181G ,Color Palette 2_181 Green"
|
|
hexmask.long.byte 0x2D4 2.--7. 1. " CP2_181B ,Color Palette 2_181 Blue"
|
|
line.long 0x2D8 "CP2_182R,Color Palette 2 Register 182"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " CP2_182A ,Color Palette 2_182 Blend Ratio"
|
|
hexmask.long.byte 0x2D8 18.--23. 1. " CP2_182R ,Color Palette 2_182 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D8 10.--15. 1. " CP2_182G ,Color Palette 2_182 Green"
|
|
hexmask.long.byte 0x2D8 2.--7. 1. " CP2_182B ,Color Palette 2_182 Blue"
|
|
line.long 0x2DC "CP2_183R,Color Palette 2 Register 183"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " CP2_183A ,Color Palette 2_183 Blend Ratio"
|
|
hexmask.long.byte 0x2DC 18.--23. 1. " CP2_183R ,Color Palette 2_183 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2DC 10.--15. 1. " CP2_183G ,Color Palette 2_183 Green"
|
|
hexmask.long.byte 0x2DC 2.--7. 1. " CP2_183B ,Color Palette 2_183 Blue"
|
|
line.long 0x2E0 "CP2_184R,Color Palette 2 Register 184"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " CP2_184A ,Color Palette 2_184 Blend Ratio"
|
|
hexmask.long.byte 0x2E0 18.--23. 1. " CP2_184R ,Color Palette 2_184 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E0 10.--15. 1. " CP2_184G ,Color Palette 2_184 Green"
|
|
hexmask.long.byte 0x2E0 2.--7. 1. " CP2_184B ,Color Palette 2_184 Blue"
|
|
line.long 0x2E4 "CP2_185R,Color Palette 2 Register 185"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " CP2_185A ,Color Palette 2_185 Blend Ratio"
|
|
hexmask.long.byte 0x2E4 18.--23. 1. " CP2_185R ,Color Palette 2_185 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E4 10.--15. 1. " CP2_185G ,Color Palette 2_185 Green"
|
|
hexmask.long.byte 0x2E4 2.--7. 1. " CP2_185B ,Color Palette 2_185 Blue"
|
|
line.long 0x2E8 "CP2_186R,Color Palette 2 Register 186"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " CP2_186A ,Color Palette 2_186 Blend Ratio"
|
|
hexmask.long.byte 0x2E8 18.--23. 1. " CP2_186R ,Color Palette 2_186 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E8 10.--15. 1. " CP2_186G ,Color Palette 2_186 Green"
|
|
hexmask.long.byte 0x2E8 2.--7. 1. " CP2_186B ,Color Palette 2_186 Blue"
|
|
line.long 0x2EC "CP2_187R,Color Palette 2 Register 187"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " CP2_187A ,Color Palette 2_187 Blend Ratio"
|
|
hexmask.long.byte 0x2EC 18.--23. 1. " CP2_187R ,Color Palette 2_187 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2EC 10.--15. 1. " CP2_187G ,Color Palette 2_187 Green"
|
|
hexmask.long.byte 0x2EC 2.--7. 1. " CP2_187B ,Color Palette 2_187 Blue"
|
|
line.long 0x2F0 "CP2_188R,Color Palette 2 Register 188"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " CP2_188A ,Color Palette 2_188 Blend Ratio"
|
|
hexmask.long.byte 0x2F0 18.--23. 1. " CP2_188R ,Color Palette 2_188 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F0 10.--15. 1. " CP2_188G ,Color Palette 2_188 Green"
|
|
hexmask.long.byte 0x2F0 2.--7. 1. " CP2_188B ,Color Palette 2_188 Blue"
|
|
line.long 0x2F4 "CP2_189R,Color Palette 2 Register 189"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " CP2_189A ,Color Palette 2_189 Blend Ratio"
|
|
hexmask.long.byte 0x2F4 18.--23. 1. " CP2_189R ,Color Palette 2_189 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F4 10.--15. 1. " CP2_189G ,Color Palette 2_189 Green"
|
|
hexmask.long.byte 0x2F4 2.--7. 1. " CP2_189B ,Color Palette 2_189 Blue"
|
|
line.long 0x2F8 "CP2_190R,Color Palette 2 Register 190"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " CP2_190A ,Color Palette 2_190 Blend Ratio"
|
|
hexmask.long.byte 0x2F8 18.--23. 1. " CP2_190R ,Color Palette 2_190 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F8 10.--15. 1. " CP2_190G ,Color Palette 2_190 Green"
|
|
hexmask.long.byte 0x2F8 2.--7. 1. " CP2_190B ,Color Palette 2_190 Blue"
|
|
line.long 0x2FC "CP2_191R,Color Palette 2 Register 191"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " CP2_191A ,Color Palette 2_191 Blend Ratio"
|
|
hexmask.long.byte 0x2FC 18.--23. 1. " CP2_191R ,Color Palette 2_191 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2FC 10.--15. 1. " CP2_191G ,Color Palette 2_191 Green"
|
|
hexmask.long.byte 0x2FC 2.--7. 1. " CP2_191B ,Color Palette 2_191 Blue"
|
|
line.long 0x300 "CP2_192R,Color Palette 2 Register 192"
|
|
hexmask.long.byte 0x300 24.--31. 1. " CP2_192A ,Color Palette 2_192 Blend Ratio"
|
|
hexmask.long.byte 0x300 18.--23. 1. " CP2_192R ,Color Palette 2_192 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x300 10.--15. 1. " CP2_192G ,Color Palette 2_192 Green"
|
|
hexmask.long.byte 0x300 2.--7. 1. " CP2_192B ,Color Palette 2_192 Blue"
|
|
line.long 0x304 "CP2_193R,Color Palette 2 Register 193"
|
|
hexmask.long.byte 0x304 24.--31. 1. " CP2_193A ,Color Palette 2_193 Blend Ratio"
|
|
hexmask.long.byte 0x304 18.--23. 1. " CP2_193R ,Color Palette 2_193 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x304 10.--15. 1. " CP2_193G ,Color Palette 2_193 Green"
|
|
hexmask.long.byte 0x304 2.--7. 1. " CP2_193B ,Color Palette 2_193 Blue"
|
|
line.long 0x308 "CP2_194R,Color Palette 2 Register 194"
|
|
hexmask.long.byte 0x308 24.--31. 1. " CP2_194A ,Color Palette 2_194 Blend Ratio"
|
|
hexmask.long.byte 0x308 18.--23. 1. " CP2_194R ,Color Palette 2_194 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x308 10.--15. 1. " CP2_194G ,Color Palette 2_194 Green"
|
|
hexmask.long.byte 0x308 2.--7. 1. " CP2_194B ,Color Palette 2_194 Blue"
|
|
line.long 0x30C "CP2_195R,Color Palette 2 Register 195"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " CP2_195A ,Color Palette 2_195 Blend Ratio"
|
|
hexmask.long.byte 0x30C 18.--23. 1. " CP2_195R ,Color Palette 2_195 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30C 10.--15. 1. " CP2_195G ,Color Palette 2_195 Green"
|
|
hexmask.long.byte 0x30C 2.--7. 1. " CP2_195B ,Color Palette 2_195 Blue"
|
|
line.long 0x310 "CP2_196R,Color Palette 2 Register 196"
|
|
hexmask.long.byte 0x310 24.--31. 1. " CP2_196A ,Color Palette 2_196 Blend Ratio"
|
|
hexmask.long.byte 0x310 18.--23. 1. " CP2_196R ,Color Palette 2_196 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x310 10.--15. 1. " CP2_196G ,Color Palette 2_196 Green"
|
|
hexmask.long.byte 0x310 2.--7. 1. " CP2_196B ,Color Palette 2_196 Blue"
|
|
line.long 0x314 "CP2_197R,Color Palette 2 Register 197"
|
|
hexmask.long.byte 0x314 24.--31. 1. " CP2_197A ,Color Palette 2_197 Blend Ratio"
|
|
hexmask.long.byte 0x314 18.--23. 1. " CP2_197R ,Color Palette 2_197 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x314 10.--15. 1. " CP2_197G ,Color Palette 2_197 Green"
|
|
hexmask.long.byte 0x314 2.--7. 1. " CP2_197B ,Color Palette 2_197 Blue"
|
|
line.long 0x318 "CP2_198R,Color Palette 2 Register 198"
|
|
hexmask.long.byte 0x318 24.--31. 1. " CP2_198A ,Color Palette 2_198 Blend Ratio"
|
|
hexmask.long.byte 0x318 18.--23. 1. " CP2_198R ,Color Palette 2_198 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x318 10.--15. 1. " CP2_198G ,Color Palette 2_198 Green"
|
|
hexmask.long.byte 0x318 2.--7. 1. " CP2_198B ,Color Palette 2_198 Blue"
|
|
line.long 0x31C "CP2_199R,Color Palette 2 Register 199"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " CP2_199A ,Color Palette 2_199 Blend Ratio"
|
|
hexmask.long.byte 0x31C 18.--23. 1. " CP2_199R ,Color Palette 2_199 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x31C 10.--15. 1. " CP2_199G ,Color Palette 2_199 Green"
|
|
hexmask.long.byte 0x31C 2.--7. 1. " CP2_199B ,Color Palette 2_199 Blue"
|
|
line.long 0x320 "CP2_200R,Color Palette 2 Register 200"
|
|
hexmask.long.byte 0x320 24.--31. 1. " CP2_200A ,Color Palette 2_200 Blend Ratio"
|
|
hexmask.long.byte 0x320 18.--23. 1. " CP2_200R ,Color Palette 2_200 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x320 10.--15. 1. " CP2_200G ,Color Palette 2_200 Green"
|
|
hexmask.long.byte 0x320 2.--7. 1. " CP2_200B ,Color Palette 2_200 Blue"
|
|
line.long 0x324 "CP2_201R,Color Palette 2 Register 201"
|
|
hexmask.long.byte 0x324 24.--31. 1. " CP2_201A ,Color Palette 2_201 Blend Ratio"
|
|
hexmask.long.byte 0x324 18.--23. 1. " CP2_201R ,Color Palette 2_201 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x324 10.--15. 1. " CP2_201G ,Color Palette 2_201 Green"
|
|
hexmask.long.byte 0x324 2.--7. 1. " CP2_201B ,Color Palette 2_201 Blue"
|
|
line.long 0x328 "CP2_202R,Color Palette 2 Register 202"
|
|
hexmask.long.byte 0x328 24.--31. 1. " CP2_202A ,Color Palette 2_202 Blend Ratio"
|
|
hexmask.long.byte 0x328 18.--23. 1. " CP2_202R ,Color Palette 2_202 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x328 10.--15. 1. " CP2_202G ,Color Palette 2_202 Green"
|
|
hexmask.long.byte 0x328 2.--7. 1. " CP2_202B ,Color Palette 2_202 Blue"
|
|
line.long 0x32C "CP2_203R,Color Palette 2 Register 203"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " CP2_203A ,Color Palette 2_203 Blend Ratio"
|
|
hexmask.long.byte 0x32C 18.--23. 1. " CP2_203R ,Color Palette 2_203 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x32C 10.--15. 1. " CP2_203G ,Color Palette 2_203 Green"
|
|
hexmask.long.byte 0x32C 2.--7. 1. " CP2_203B ,Color Palette 2_203 Blue"
|
|
line.long 0x330 "CP2_204R,Color Palette 2 Register 204"
|
|
hexmask.long.byte 0x330 24.--31. 1. " CP2_204A ,Color Palette 2_204 Blend Ratio"
|
|
hexmask.long.byte 0x330 18.--23. 1. " CP2_204R ,Color Palette 2_204 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x330 10.--15. 1. " CP2_204G ,Color Palette 2_204 Green"
|
|
hexmask.long.byte 0x330 2.--7. 1. " CP2_204B ,Color Palette 2_204 Blue"
|
|
line.long 0x334 "CP2_205R,Color Palette 2 Register 205"
|
|
hexmask.long.byte 0x334 24.--31. 1. " CP2_205A ,Color Palette 2_205 Blend Ratio"
|
|
hexmask.long.byte 0x334 18.--23. 1. " CP2_205R ,Color Palette 2_205 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x334 10.--15. 1. " CP2_205G ,Color Palette 2_205 Green"
|
|
hexmask.long.byte 0x334 2.--7. 1. " CP2_205B ,Color Palette 2_205 Blue"
|
|
line.long 0x338 "CP2_206R,Color Palette 2 Register 206"
|
|
hexmask.long.byte 0x338 24.--31. 1. " CP2_206A ,Color Palette 2_206 Blend Ratio"
|
|
hexmask.long.byte 0x338 18.--23. 1. " CP2_206R ,Color Palette 2_206 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x338 10.--15. 1. " CP2_206G ,Color Palette 2_206 Green"
|
|
hexmask.long.byte 0x338 2.--7. 1. " CP2_206B ,Color Palette 2_206 Blue"
|
|
line.long 0x33C "CP2_207R,Color Palette 2 Register 207"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " CP2_207A ,Color Palette 2_207 Blend Ratio"
|
|
hexmask.long.byte 0x33C 18.--23. 1. " CP2_207R ,Color Palette 2_207 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x33C 10.--15. 1. " CP2_207G ,Color Palette 2_207 Green"
|
|
hexmask.long.byte 0x33C 2.--7. 1. " CP2_207B ,Color Palette 2_207 Blue"
|
|
line.long 0x340 "CP2_208R,Color Palette 2 Register 208"
|
|
hexmask.long.byte 0x340 24.--31. 1. " CP2_208A ,Color Palette 2_208 Blend Ratio"
|
|
hexmask.long.byte 0x340 18.--23. 1. " CP2_208R ,Color Palette 2_208 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x340 10.--15. 1. " CP2_208G ,Color Palette 2_208 Green"
|
|
hexmask.long.byte 0x340 2.--7. 1. " CP2_208B ,Color Palette 2_208 Blue"
|
|
line.long 0x344 "CP2_209R,Color Palette 2 Register 209"
|
|
hexmask.long.byte 0x344 24.--31. 1. " CP2_209A ,Color Palette 2_209 Blend Ratio"
|
|
hexmask.long.byte 0x344 18.--23. 1. " CP2_209R ,Color Palette 2_209 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x344 10.--15. 1. " CP2_209G ,Color Palette 2_209 Green"
|
|
hexmask.long.byte 0x344 2.--7. 1. " CP2_209B ,Color Palette 2_209 Blue"
|
|
line.long 0x348 "CP2_210R,Color Palette 2 Register 210"
|
|
hexmask.long.byte 0x348 24.--31. 1. " CP2_210A ,Color Palette 2_210 Blend Ratio"
|
|
hexmask.long.byte 0x348 18.--23. 1. " CP2_210R ,Color Palette 2_210 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x348 10.--15. 1. " CP2_210G ,Color Palette 2_210 Green"
|
|
hexmask.long.byte 0x348 2.--7. 1. " CP2_210B ,Color Palette 2_210 Blue"
|
|
line.long 0x34C "CP2_211R,Color Palette 2 Register 211"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " CP2_211A ,Color Palette 2_211 Blend Ratio"
|
|
hexmask.long.byte 0x34C 18.--23. 1. " CP2_211R ,Color Palette 2_211 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34C 10.--15. 1. " CP2_211G ,Color Palette 2_211 Green"
|
|
hexmask.long.byte 0x34C 2.--7. 1. " CP2_211B ,Color Palette 2_211 Blue"
|
|
line.long 0x350 "CP2_212R,Color Palette 2 Register 212"
|
|
hexmask.long.byte 0x350 24.--31. 1. " CP2_212A ,Color Palette 2_212 Blend Ratio"
|
|
hexmask.long.byte 0x350 18.--23. 1. " CP2_212R ,Color Palette 2_212 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x350 10.--15. 1. " CP2_212G ,Color Palette 2_212 Green"
|
|
hexmask.long.byte 0x350 2.--7. 1. " CP2_212B ,Color Palette 2_212 Blue"
|
|
line.long 0x354 "CP2_213R,Color Palette 2 Register 213"
|
|
hexmask.long.byte 0x354 24.--31. 1. " CP2_213A ,Color Palette 2_213 Blend Ratio"
|
|
hexmask.long.byte 0x354 18.--23. 1. " CP2_213R ,Color Palette 2_213 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x354 10.--15. 1. " CP2_213G ,Color Palette 2_213 Green"
|
|
hexmask.long.byte 0x354 2.--7. 1. " CP2_213B ,Color Palette 2_213 Blue"
|
|
line.long 0x358 "CP2_214R,Color Palette 2 Register 214"
|
|
hexmask.long.byte 0x358 24.--31. 1. " CP2_214A ,Color Palette 2_214 Blend Ratio"
|
|
hexmask.long.byte 0x358 18.--23. 1. " CP2_214R ,Color Palette 2_214 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x358 10.--15. 1. " CP2_214G ,Color Palette 2_214 Green"
|
|
hexmask.long.byte 0x358 2.--7. 1. " CP2_214B ,Color Palette 2_214 Blue"
|
|
line.long 0x35C "CP2_215R,Color Palette 2 Register 215"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " CP2_215A ,Color Palette 2_215 Blend Ratio"
|
|
hexmask.long.byte 0x35C 18.--23. 1. " CP2_215R ,Color Palette 2_215 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x35C 10.--15. 1. " CP2_215G ,Color Palette 2_215 Green"
|
|
hexmask.long.byte 0x35C 2.--7. 1. " CP2_215B ,Color Palette 2_215 Blue"
|
|
line.long 0x360 "CP2_216R,Color Palette 2 Register 216"
|
|
hexmask.long.byte 0x360 24.--31. 1. " CP2_216A ,Color Palette 2_216 Blend Ratio"
|
|
hexmask.long.byte 0x360 18.--23. 1. " CP2_216R ,Color Palette 2_216 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x360 10.--15. 1. " CP2_216G ,Color Palette 2_216 Green"
|
|
hexmask.long.byte 0x360 2.--7. 1. " CP2_216B ,Color Palette 2_216 Blue"
|
|
line.long 0x364 "CP2_217R,Color Palette 2 Register 217"
|
|
hexmask.long.byte 0x364 24.--31. 1. " CP2_217A ,Color Palette 2_217 Blend Ratio"
|
|
hexmask.long.byte 0x364 18.--23. 1. " CP2_217R ,Color Palette 2_217 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x364 10.--15. 1. " CP2_217G ,Color Palette 2_217 Green"
|
|
hexmask.long.byte 0x364 2.--7. 1. " CP2_217B ,Color Palette 2_217 Blue"
|
|
line.long 0x368 "CP2_218R,Color Palette 2 Register 218"
|
|
hexmask.long.byte 0x368 24.--31. 1. " CP2_218A ,Color Palette 2_218 Blend Ratio"
|
|
hexmask.long.byte 0x368 18.--23. 1. " CP2_218R ,Color Palette 2_218 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x368 10.--15. 1. " CP2_218G ,Color Palette 2_218 Green"
|
|
hexmask.long.byte 0x368 2.--7. 1. " CP2_218B ,Color Palette 2_218 Blue"
|
|
line.long 0x36C "CP2_219R,Color Palette 2 Register 219"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " CP2_219A ,Color Palette 2_219 Blend Ratio"
|
|
hexmask.long.byte 0x36C 18.--23. 1. " CP2_219R ,Color Palette 2_219 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x36C 10.--15. 1. " CP2_219G ,Color Palette 2_219 Green"
|
|
hexmask.long.byte 0x36C 2.--7. 1. " CP2_219B ,Color Palette 2_219 Blue"
|
|
line.long 0x370 "CP2_220R,Color Palette 2 Register 220"
|
|
hexmask.long.byte 0x370 24.--31. 1. " CP2_220A ,Color Palette 2_220 Blend Ratio"
|
|
hexmask.long.byte 0x370 18.--23. 1. " CP2_220R ,Color Palette 2_220 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x370 10.--15. 1. " CP2_220G ,Color Palette 2_220 Green"
|
|
hexmask.long.byte 0x370 2.--7. 1. " CP2_220B ,Color Palette 2_220 Blue"
|
|
line.long 0x374 "CP2_221R,Color Palette 2 Register 221"
|
|
hexmask.long.byte 0x374 24.--31. 1. " CP2_221A ,Color Palette 2_221 Blend Ratio"
|
|
hexmask.long.byte 0x374 18.--23. 1. " CP2_221R ,Color Palette 2_221 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x374 10.--15. 1. " CP2_221G ,Color Palette 2_221 Green"
|
|
hexmask.long.byte 0x374 2.--7. 1. " CP2_221B ,Color Palette 2_221 Blue"
|
|
line.long 0x378 "CP2_222R,Color Palette 2 Register 222"
|
|
hexmask.long.byte 0x378 24.--31. 1. " CP2_222A ,Color Palette 2_222 Blend Ratio"
|
|
hexmask.long.byte 0x378 18.--23. 1. " CP2_222R ,Color Palette 2_222 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x378 10.--15. 1. " CP2_222G ,Color Palette 2_222 Green"
|
|
hexmask.long.byte 0x378 2.--7. 1. " CP2_222B ,Color Palette 2_222 Blue"
|
|
line.long 0x37C "CP2_223R,Color Palette 2 Register 223"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " CP2_223A ,Color Palette 2_223 Blend Ratio"
|
|
hexmask.long.byte 0x37C 18.--23. 1. " CP2_223R ,Color Palette 2_223 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x37C 10.--15. 1. " CP2_223G ,Color Palette 2_223 Green"
|
|
hexmask.long.byte 0x37C 2.--7. 1. " CP2_223B ,Color Palette 2_223 Blue"
|
|
line.long 0x380 "CP2_224R,Color Palette 2 Register 224"
|
|
hexmask.long.byte 0x380 24.--31. 1. " CP2_224A ,Color Palette 2_224 Blend Ratio"
|
|
hexmask.long.byte 0x380 18.--23. 1. " CP2_224R ,Color Palette 2_224 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x380 10.--15. 1. " CP2_224G ,Color Palette 2_224 Green"
|
|
hexmask.long.byte 0x380 2.--7. 1. " CP2_224B ,Color Palette 2_224 Blue"
|
|
line.long 0x384 "CP2_225R,Color Palette 2 Register 225"
|
|
hexmask.long.byte 0x384 24.--31. 1. " CP2_225A ,Color Palette 2_225 Blend Ratio"
|
|
hexmask.long.byte 0x384 18.--23. 1. " CP2_225R ,Color Palette 2_225 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x384 10.--15. 1. " CP2_225G ,Color Palette 2_225 Green"
|
|
hexmask.long.byte 0x384 2.--7. 1. " CP2_225B ,Color Palette 2_225 Blue"
|
|
line.long 0x388 "CP2_226R,Color Palette 2 Register 226"
|
|
hexmask.long.byte 0x388 24.--31. 1. " CP2_226A ,Color Palette 2_226 Blend Ratio"
|
|
hexmask.long.byte 0x388 18.--23. 1. " CP2_226R ,Color Palette 2_226 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x388 10.--15. 1. " CP2_226G ,Color Palette 2_226 Green"
|
|
hexmask.long.byte 0x388 2.--7. 1. " CP2_226B ,Color Palette 2_226 Blue"
|
|
line.long 0x38C "CP2_227R,Color Palette 2 Register 227"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " CP2_227A ,Color Palette 2_227 Blend Ratio"
|
|
hexmask.long.byte 0x38C 18.--23. 1. " CP2_227R ,Color Palette 2_227 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38C 10.--15. 1. " CP2_227G ,Color Palette 2_227 Green"
|
|
hexmask.long.byte 0x38C 2.--7. 1. " CP2_227B ,Color Palette 2_227 Blue"
|
|
line.long 0x390 "CP2_228R,Color Palette 2 Register 228"
|
|
hexmask.long.byte 0x390 24.--31. 1. " CP2_228A ,Color Palette 2_228 Blend Ratio"
|
|
hexmask.long.byte 0x390 18.--23. 1. " CP2_228R ,Color Palette 2_228 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x390 10.--15. 1. " CP2_228G ,Color Palette 2_228 Green"
|
|
hexmask.long.byte 0x390 2.--7. 1. " CP2_228B ,Color Palette 2_228 Blue"
|
|
line.long 0x394 "CP2_229R,Color Palette 2 Register 229"
|
|
hexmask.long.byte 0x394 24.--31. 1. " CP2_229A ,Color Palette 2_229 Blend Ratio"
|
|
hexmask.long.byte 0x394 18.--23. 1. " CP2_229R ,Color Palette 2_229 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x394 10.--15. 1. " CP2_229G ,Color Palette 2_229 Green"
|
|
hexmask.long.byte 0x394 2.--7. 1. " CP2_229B ,Color Palette 2_229 Blue"
|
|
line.long 0x398 "CP2_230R,Color Palette 2 Register 230"
|
|
hexmask.long.byte 0x398 24.--31. 1. " CP2_230A ,Color Palette 2_230 Blend Ratio"
|
|
hexmask.long.byte 0x398 18.--23. 1. " CP2_230R ,Color Palette 2_230 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x398 10.--15. 1. " CP2_230G ,Color Palette 2_230 Green"
|
|
hexmask.long.byte 0x398 2.--7. 1. " CP2_230B ,Color Palette 2_230 Blue"
|
|
line.long 0x39C "CP2_231R,Color Palette 2 Register 231"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " CP2_231A ,Color Palette 2_231 Blend Ratio"
|
|
hexmask.long.byte 0x39C 18.--23. 1. " CP2_231R ,Color Palette 2_231 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x39C 10.--15. 1. " CP2_231G ,Color Palette 2_231 Green"
|
|
hexmask.long.byte 0x39C 2.--7. 1. " CP2_231B ,Color Palette 2_231 Blue"
|
|
line.long 0x3A0 "CP2_232R,Color Palette 2 Register 232"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " CP2_232A ,Color Palette 2_232 Blend Ratio"
|
|
hexmask.long.byte 0x3A0 18.--23. 1. " CP2_232R ,Color Palette 2_232 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A0 10.--15. 1. " CP2_232G ,Color Palette 2_232 Green"
|
|
hexmask.long.byte 0x3A0 2.--7. 1. " CP2_232B ,Color Palette 2_232 Blue"
|
|
line.long 0x3A4 "CP2_233R,Color Palette 2 Register 233"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " CP2_233A ,Color Palette 2_233 Blend Ratio"
|
|
hexmask.long.byte 0x3A4 18.--23. 1. " CP2_233R ,Color Palette 2_233 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A4 10.--15. 1. " CP2_233G ,Color Palette 2_233 Green"
|
|
hexmask.long.byte 0x3A4 2.--7. 1. " CP2_233B ,Color Palette 2_233 Blue"
|
|
line.long 0x3A8 "CP2_234R,Color Palette 2 Register 234"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " CP2_234A ,Color Palette 2_234 Blend Ratio"
|
|
hexmask.long.byte 0x3A8 18.--23. 1. " CP2_234R ,Color Palette 2_234 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A8 10.--15. 1. " CP2_234G ,Color Palette 2_234 Green"
|
|
hexmask.long.byte 0x3A8 2.--7. 1. " CP2_234B ,Color Palette 2_234 Blue"
|
|
line.long 0x3AC "CP2_235R,Color Palette 2 Register 235"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " CP2_235A ,Color Palette 2_235 Blend Ratio"
|
|
hexmask.long.byte 0x3AC 18.--23. 1. " CP2_235R ,Color Palette 2_235 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3AC 10.--15. 1. " CP2_235G ,Color Palette 2_235 Green"
|
|
hexmask.long.byte 0x3AC 2.--7. 1. " CP2_235B ,Color Palette 2_235 Blue"
|
|
line.long 0x3B0 "CP2_236R,Color Palette 2 Register 236"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " CP2_236A ,Color Palette 2_236 Blend Ratio"
|
|
hexmask.long.byte 0x3B0 18.--23. 1. " CP2_236R ,Color Palette 2_236 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B0 10.--15. 1. " CP2_236G ,Color Palette 2_236 Green"
|
|
hexmask.long.byte 0x3B0 2.--7. 1. " CP2_236B ,Color Palette 2_236 Blue"
|
|
line.long 0x3B4 "CP2_237R,Color Palette 2 Register 237"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " CP2_237A ,Color Palette 2_237 Blend Ratio"
|
|
hexmask.long.byte 0x3B4 18.--23. 1. " CP2_237R ,Color Palette 2_237 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B4 10.--15. 1. " CP2_237G ,Color Palette 2_237 Green"
|
|
hexmask.long.byte 0x3B4 2.--7. 1. " CP2_237B ,Color Palette 2_237 Blue"
|
|
line.long 0x3B8 "CP2_238R,Color Palette 2 Register 238"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " CP2_238A ,Color Palette 2_238 Blend Ratio"
|
|
hexmask.long.byte 0x3B8 18.--23. 1. " CP2_238R ,Color Palette 2_238 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B8 10.--15. 1. " CP2_238G ,Color Palette 2_238 Green"
|
|
hexmask.long.byte 0x3B8 2.--7. 1. " CP2_238B ,Color Palette 2_238 Blue"
|
|
line.long 0x3BC "CP2_239R,Color Palette 2 Register 239"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " CP2_239A ,Color Palette 2_239 Blend Ratio"
|
|
hexmask.long.byte 0x3BC 18.--23. 1. " CP2_239R ,Color Palette 2_239 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3BC 10.--15. 1. " CP2_239G ,Color Palette 2_239 Green"
|
|
hexmask.long.byte 0x3BC 2.--7. 1. " CP2_239B ,Color Palette 2_239 Blue"
|
|
line.long 0x3C0 "CP2_240R,Color Palette 2 Register 240"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " CP2_240A ,Color Palette 2_240 Blend Ratio"
|
|
hexmask.long.byte 0x3C0 18.--23. 1. " CP2_240R ,Color Palette 2_240 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C0 10.--15. 1. " CP2_240G ,Color Palette 2_240 Green"
|
|
hexmask.long.byte 0x3C0 2.--7. 1. " CP2_240B ,Color Palette 2_240 Blue"
|
|
line.long 0x3C4 "CP2_241R,Color Palette 2 Register 241"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " CP2_241A ,Color Palette 2_241 Blend Ratio"
|
|
hexmask.long.byte 0x3C4 18.--23. 1. " CP2_241R ,Color Palette 2_241 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C4 10.--15. 1. " CP2_241G ,Color Palette 2_241 Green"
|
|
hexmask.long.byte 0x3C4 2.--7. 1. " CP2_241B ,Color Palette 2_241 Blue"
|
|
line.long 0x3C8 "CP2_242R,Color Palette 2 Register 242"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " CP2_242A ,Color Palette 2_242 Blend Ratio"
|
|
hexmask.long.byte 0x3C8 18.--23. 1. " CP2_242R ,Color Palette 2_242 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C8 10.--15. 1. " CP2_242G ,Color Palette 2_242 Green"
|
|
hexmask.long.byte 0x3C8 2.--7. 1. " CP2_242B ,Color Palette 2_242 Blue"
|
|
line.long 0x3CC "CP2_243R,Color Palette 2 Register 243"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " CP2_243A ,Color Palette 2_243 Blend Ratio"
|
|
hexmask.long.byte 0x3CC 18.--23. 1. " CP2_243R ,Color Palette 2_243 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3CC 10.--15. 1. " CP2_243G ,Color Palette 2_243 Green"
|
|
hexmask.long.byte 0x3CC 2.--7. 1. " CP2_243B ,Color Palette 2_243 Blue"
|
|
line.long 0x3D0 "CP2_244R,Color Palette 2 Register 244"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " CP2_244A ,Color Palette 2_244 Blend Ratio"
|
|
hexmask.long.byte 0x3D0 18.--23. 1. " CP2_244R ,Color Palette 2_244 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D0 10.--15. 1. " CP2_244G ,Color Palette 2_244 Green"
|
|
hexmask.long.byte 0x3D0 2.--7. 1. " CP2_244B ,Color Palette 2_244 Blue"
|
|
line.long 0x3D4 "CP2_245R,Color Palette 2 Register 245"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " CP2_245A ,Color Palette 2_245 Blend Ratio"
|
|
hexmask.long.byte 0x3D4 18.--23. 1. " CP2_245R ,Color Palette 2_245 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D4 10.--15. 1. " CP2_245G ,Color Palette 2_245 Green"
|
|
hexmask.long.byte 0x3D4 2.--7. 1. " CP2_245B ,Color Palette 2_245 Blue"
|
|
line.long 0x3D8 "CP2_246R,Color Palette 2 Register 246"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " CP2_246A ,Color Palette 2_246 Blend Ratio"
|
|
hexmask.long.byte 0x3D8 18.--23. 1. " CP2_246R ,Color Palette 2_246 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D8 10.--15. 1. " CP2_246G ,Color Palette 2_246 Green"
|
|
hexmask.long.byte 0x3D8 2.--7. 1. " CP2_246B ,Color Palette 2_246 Blue"
|
|
line.long 0x3DC "CP2_247R,Color Palette 2 Register 247"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " CP2_247A ,Color Palette 2_247 Blend Ratio"
|
|
hexmask.long.byte 0x3DC 18.--23. 1. " CP2_247R ,Color Palette 2_247 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3DC 10.--15. 1. " CP2_247G ,Color Palette 2_247 Green"
|
|
hexmask.long.byte 0x3DC 2.--7. 1. " CP2_247B ,Color Palette 2_247 Blue"
|
|
line.long 0x3E0 "CP2_248R,Color Palette 2 Register 248"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " CP2_248A ,Color Palette 2_248 Blend Ratio"
|
|
hexmask.long.byte 0x3E0 18.--23. 1. " CP2_248R ,Color Palette 2_248 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E0 10.--15. 1. " CP2_248G ,Color Palette 2_248 Green"
|
|
hexmask.long.byte 0x3E0 2.--7. 1. " CP2_248B ,Color Palette 2_248 Blue"
|
|
line.long 0x3E4 "CP2_249R,Color Palette 2 Register 249"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " CP2_249A ,Color Palette 2_249 Blend Ratio"
|
|
hexmask.long.byte 0x3E4 18.--23. 1. " CP2_249R ,Color Palette 2_249 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E4 10.--15. 1. " CP2_249G ,Color Palette 2_249 Green"
|
|
hexmask.long.byte 0x3E4 2.--7. 1. " CP2_249B ,Color Palette 2_249 Blue"
|
|
line.long 0x3E8 "CP2_250R,Color Palette 2 Register 250"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " CP2_250A ,Color Palette 2_250 Blend Ratio"
|
|
hexmask.long.byte 0x3E8 18.--23. 1. " CP2_250R ,Color Palette 2_250 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E8 10.--15. 1. " CP2_250G ,Color Palette 2_250 Green"
|
|
hexmask.long.byte 0x3E8 2.--7. 1. " CP2_250B ,Color Palette 2_250 Blue"
|
|
line.long 0x3EC "CP2_251R,Color Palette 2 Register 251"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " CP2_251A ,Color Palette 2_251 Blend Ratio"
|
|
hexmask.long.byte 0x3EC 18.--23. 1. " CP2_251R ,Color Palette 2_251 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3EC 10.--15. 1. " CP2_251G ,Color Palette 2_251 Green"
|
|
hexmask.long.byte 0x3EC 2.--7. 1. " CP2_251B ,Color Palette 2_251 Blue"
|
|
line.long 0x3F0 "CP2_252R,Color Palette 2 Register 252"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " CP2_252A ,Color Palette 2_252 Blend Ratio"
|
|
hexmask.long.byte 0x3F0 18.--23. 1. " CP2_252R ,Color Palette 2_252 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F0 10.--15. 1. " CP2_252G ,Color Palette 2_252 Green"
|
|
hexmask.long.byte 0x3F0 2.--7. 1. " CP2_252B ,Color Palette 2_252 Blue"
|
|
line.long 0x3F4 "CP2_253R,Color Palette 2 Register 253"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " CP2_253A ,Color Palette 2_253 Blend Ratio"
|
|
hexmask.long.byte 0x3F4 18.--23. 1. " CP2_253R ,Color Palette 2_253 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F4 10.--15. 1. " CP2_253G ,Color Palette 2_253 Green"
|
|
hexmask.long.byte 0x3F4 2.--7. 1. " CP2_253B ,Color Palette 2_253 Blue"
|
|
line.long 0x3F8 "CP2_254R,Color Palette 2 Register 254"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " CP2_254A ,Color Palette 2_254 Blend Ratio"
|
|
hexmask.long.byte 0x3F8 18.--23. 1. " CP2_254R ,Color Palette 2_254 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F8 10.--15. 1. " CP2_254G ,Color Palette 2_254 Green"
|
|
hexmask.long.byte 0x3F8 2.--7. 1. " CP2_254B ,Color Palette 2_254 Blue"
|
|
line.long 0x3FC "CP2_255R,Color Palette 2 Register 255"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " CP2_255A ,Color Palette 2_255 Blend Ratio"
|
|
hexmask.long.byte 0x3FC 18.--23. 1. " CP2_255R ,Color Palette 2_255 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3FC 10.--15. 1. " CP2_255G ,Color Palette 2_255 Green"
|
|
hexmask.long.byte 0x3FC 2.--7. 1. " CP2_255B ,Color Palette 2_255 Blue"
|
|
tree.end
|
|
tree "Color Palette 3 Registers"
|
|
width 10.
|
|
group.long 0x3000++0x3ff
|
|
line.long 0x0 "CP3_0R,Color Palette 3 Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. " CP3_0A ,Color Palette 3_0 Blend Ratio"
|
|
hexmask.long.byte 0x0 18.--23. 1. " CP3_0R ,Color Palette 3_0 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x0 10.--15. 1. " CP3_0G ,Color Palette 3_0 Green"
|
|
hexmask.long.byte 0x0 2.--7. 1. " CP3_0B ,Color Palette 3_0 Blue"
|
|
line.long 0x4 "CP3_1R,Color Palette 3 Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. " CP3_1A ,Color Palette 3_1 Blend Ratio"
|
|
hexmask.long.byte 0x4 18.--23. 1. " CP3_1R ,Color Palette 3_1 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4 10.--15. 1. " CP3_1G ,Color Palette 3_1 Green"
|
|
hexmask.long.byte 0x4 2.--7. 1. " CP3_1B ,Color Palette 3_1 Blue"
|
|
line.long 0x8 "CP3_2R,Color Palette 3 Register 2"
|
|
hexmask.long.byte 0x8 24.--31. 1. " CP3_2A ,Color Palette 3_2 Blend Ratio"
|
|
hexmask.long.byte 0x8 18.--23. 1. " CP3_2R ,Color Palette 3_2 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8 10.--15. 1. " CP3_2G ,Color Palette 3_2 Green"
|
|
hexmask.long.byte 0x8 2.--7. 1. " CP3_2B ,Color Palette 3_2 Blue"
|
|
line.long 0xC "CP3_3R,Color Palette 3 Register 3"
|
|
hexmask.long.byte 0xC 24.--31. 1. " CP3_3A ,Color Palette 3_3 Blend Ratio"
|
|
hexmask.long.byte 0xC 18.--23. 1. " CP3_3R ,Color Palette 3_3 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC 10.--15. 1. " CP3_3G ,Color Palette 3_3 Green"
|
|
hexmask.long.byte 0xC 2.--7. 1. " CP3_3B ,Color Palette 3_3 Blue"
|
|
line.long 0x10 "CP3_4R,Color Palette 3 Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. " CP3_4A ,Color Palette 3_4 Blend Ratio"
|
|
hexmask.long.byte 0x10 18.--23. 1. " CP3_4R ,Color Palette 3_4 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10 10.--15. 1. " CP3_4G ,Color Palette 3_4 Green"
|
|
hexmask.long.byte 0x10 2.--7. 1. " CP3_4B ,Color Palette 3_4 Blue"
|
|
line.long 0x14 "CP3_5R,Color Palette 3 Register 5"
|
|
hexmask.long.byte 0x14 24.--31. 1. " CP3_5A ,Color Palette 3_5 Blend Ratio"
|
|
hexmask.long.byte 0x14 18.--23. 1. " CP3_5R ,Color Palette 3_5 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14 10.--15. 1. " CP3_5G ,Color Palette 3_5 Green"
|
|
hexmask.long.byte 0x14 2.--7. 1. " CP3_5B ,Color Palette 3_5 Blue"
|
|
line.long 0x18 "CP3_6R,Color Palette 3 Register 6"
|
|
hexmask.long.byte 0x18 24.--31. 1. " CP3_6A ,Color Palette 3_6 Blend Ratio"
|
|
hexmask.long.byte 0x18 18.--23. 1. " CP3_6R ,Color Palette 3_6 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18 10.--15. 1. " CP3_6G ,Color Palette 3_6 Green"
|
|
hexmask.long.byte 0x18 2.--7. 1. " CP3_6B ,Color Palette 3_6 Blue"
|
|
line.long 0x1C "CP3_7R,Color Palette 3 Register 7"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " CP3_7A ,Color Palette 3_7 Blend Ratio"
|
|
hexmask.long.byte 0x1C 18.--23. 1. " CP3_7R ,Color Palette 3_7 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 10.--15. 1. " CP3_7G ,Color Palette 3_7 Green"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " CP3_7B ,Color Palette 3_7 Blue"
|
|
line.long 0x20 "CP3_8R,Color Palette 3 Register 8"
|
|
hexmask.long.byte 0x20 24.--31. 1. " CP3_8A ,Color Palette 3_8 Blend Ratio"
|
|
hexmask.long.byte 0x20 18.--23. 1. " CP3_8R ,Color Palette 3_8 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20 10.--15. 1. " CP3_8G ,Color Palette 3_8 Green"
|
|
hexmask.long.byte 0x20 2.--7. 1. " CP3_8B ,Color Palette 3_8 Blue"
|
|
line.long 0x24 "CP3_9R,Color Palette 3 Register 9"
|
|
hexmask.long.byte 0x24 24.--31. 1. " CP3_9A ,Color Palette 3_9 Blend Ratio"
|
|
hexmask.long.byte 0x24 18.--23. 1. " CP3_9R ,Color Palette 3_9 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24 10.--15. 1. " CP3_9G ,Color Palette 3_9 Green"
|
|
hexmask.long.byte 0x24 2.--7. 1. " CP3_9B ,Color Palette 3_9 Blue"
|
|
line.long 0x28 "CP3_10R,Color Palette 3 Register 10"
|
|
hexmask.long.byte 0x28 24.--31. 1. " CP3_10A ,Color Palette 3_10 Blend Ratio"
|
|
hexmask.long.byte 0x28 18.--23. 1. " CP3_10R ,Color Palette 3_10 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28 10.--15. 1. " CP3_10G ,Color Palette 3_10 Green"
|
|
hexmask.long.byte 0x28 2.--7. 1. " CP3_10B ,Color Palette 3_10 Blue"
|
|
line.long 0x2C "CP3_11R,Color Palette 3 Register 11"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " CP3_11A ,Color Palette 3_11 Blend Ratio"
|
|
hexmask.long.byte 0x2C 18.--23. 1. " CP3_11R ,Color Palette 3_11 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 10.--15. 1. " CP3_11G ,Color Palette 3_11 Green"
|
|
hexmask.long.byte 0x2C 2.--7. 1. " CP3_11B ,Color Palette 3_11 Blue"
|
|
line.long 0x30 "CP3_12R,Color Palette 3 Register 12"
|
|
hexmask.long.byte 0x30 24.--31. 1. " CP3_12A ,Color Palette 3_12 Blend Ratio"
|
|
hexmask.long.byte 0x30 18.--23. 1. " CP3_12R ,Color Palette 3_12 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30 10.--15. 1. " CP3_12G ,Color Palette 3_12 Green"
|
|
hexmask.long.byte 0x30 2.--7. 1. " CP3_12B ,Color Palette 3_12 Blue"
|
|
line.long 0x34 "CP3_13R,Color Palette 3 Register 13"
|
|
hexmask.long.byte 0x34 24.--31. 1. " CP3_13A ,Color Palette 3_13 Blend Ratio"
|
|
hexmask.long.byte 0x34 18.--23. 1. " CP3_13R ,Color Palette 3_13 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34 10.--15. 1. " CP3_13G ,Color Palette 3_13 Green"
|
|
hexmask.long.byte 0x34 2.--7. 1. " CP3_13B ,Color Palette 3_13 Blue"
|
|
line.long 0x38 "CP3_14R,Color Palette 3 Register 14"
|
|
hexmask.long.byte 0x38 24.--31. 1. " CP3_14A ,Color Palette 3_14 Blend Ratio"
|
|
hexmask.long.byte 0x38 18.--23. 1. " CP3_14R ,Color Palette 3_14 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38 10.--15. 1. " CP3_14G ,Color Palette 3_14 Green"
|
|
hexmask.long.byte 0x38 2.--7. 1. " CP3_14B ,Color Palette 3_14 Blue"
|
|
line.long 0x3C "CP3_15R,Color Palette 3 Register 15"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " CP3_15A ,Color Palette 3_15 Blend Ratio"
|
|
hexmask.long.byte 0x3C 18.--23. 1. " CP3_15R ,Color Palette 3_15 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C 10.--15. 1. " CP3_15G ,Color Palette 3_15 Green"
|
|
hexmask.long.byte 0x3C 2.--7. 1. " CP3_15B ,Color Palette 3_15 Blue"
|
|
line.long 0x40 "CP3_16R,Color Palette 3 Register 16"
|
|
hexmask.long.byte 0x40 24.--31. 1. " CP3_16A ,Color Palette 3_16 Blend Ratio"
|
|
hexmask.long.byte 0x40 18.--23. 1. " CP3_16R ,Color Palette 3_16 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x40 10.--15. 1. " CP3_16G ,Color Palette 3_16 Green"
|
|
hexmask.long.byte 0x40 2.--7. 1. " CP3_16B ,Color Palette 3_16 Blue"
|
|
line.long 0x44 "CP3_17R,Color Palette 3 Register 17"
|
|
hexmask.long.byte 0x44 24.--31. 1. " CP3_17A ,Color Palette 3_17 Blend Ratio"
|
|
hexmask.long.byte 0x44 18.--23. 1. " CP3_17R ,Color Palette 3_17 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x44 10.--15. 1. " CP3_17G ,Color Palette 3_17 Green"
|
|
hexmask.long.byte 0x44 2.--7. 1. " CP3_17B ,Color Palette 3_17 Blue"
|
|
line.long 0x48 "CP3_18R,Color Palette 3 Register 18"
|
|
hexmask.long.byte 0x48 24.--31. 1. " CP3_18A ,Color Palette 3_18 Blend Ratio"
|
|
hexmask.long.byte 0x48 18.--23. 1. " CP3_18R ,Color Palette 3_18 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x48 10.--15. 1. " CP3_18G ,Color Palette 3_18 Green"
|
|
hexmask.long.byte 0x48 2.--7. 1. " CP3_18B ,Color Palette 3_18 Blue"
|
|
line.long 0x4C "CP3_19R,Color Palette 3 Register 19"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " CP3_19A ,Color Palette 3_19 Blend Ratio"
|
|
hexmask.long.byte 0x4C 18.--23. 1. " CP3_19R ,Color Palette 3_19 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x4C 10.--15. 1. " CP3_19G ,Color Palette 3_19 Green"
|
|
hexmask.long.byte 0x4C 2.--7. 1. " CP3_19B ,Color Palette 3_19 Blue"
|
|
line.long 0x50 "CP3_20R,Color Palette 3 Register 20"
|
|
hexmask.long.byte 0x50 24.--31. 1. " CP3_20A ,Color Palette 3_20 Blend Ratio"
|
|
hexmask.long.byte 0x50 18.--23. 1. " CP3_20R ,Color Palette 3_20 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x50 10.--15. 1. " CP3_20G ,Color Palette 3_20 Green"
|
|
hexmask.long.byte 0x50 2.--7. 1. " CP3_20B ,Color Palette 3_20 Blue"
|
|
line.long 0x54 "CP3_21R,Color Palette 3 Register 21"
|
|
hexmask.long.byte 0x54 24.--31. 1. " CP3_21A ,Color Palette 3_21 Blend Ratio"
|
|
hexmask.long.byte 0x54 18.--23. 1. " CP3_21R ,Color Palette 3_21 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x54 10.--15. 1. " CP3_21G ,Color Palette 3_21 Green"
|
|
hexmask.long.byte 0x54 2.--7. 1. " CP3_21B ,Color Palette 3_21 Blue"
|
|
line.long 0x58 "CP3_22R,Color Palette 3 Register 22"
|
|
hexmask.long.byte 0x58 24.--31. 1. " CP3_22A ,Color Palette 3_22 Blend Ratio"
|
|
hexmask.long.byte 0x58 18.--23. 1. " CP3_22R ,Color Palette 3_22 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x58 10.--15. 1. " CP3_22G ,Color Palette 3_22 Green"
|
|
hexmask.long.byte 0x58 2.--7. 1. " CP3_22B ,Color Palette 3_22 Blue"
|
|
line.long 0x5C "CP3_23R,Color Palette 3 Register 23"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " CP3_23A ,Color Palette 3_23 Blend Ratio"
|
|
hexmask.long.byte 0x5C 18.--23. 1. " CP3_23R ,Color Palette 3_23 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x5C 10.--15. 1. " CP3_23G ,Color Palette 3_23 Green"
|
|
hexmask.long.byte 0x5C 2.--7. 1. " CP3_23B ,Color Palette 3_23 Blue"
|
|
line.long 0x60 "CP3_24R,Color Palette 3 Register 24"
|
|
hexmask.long.byte 0x60 24.--31. 1. " CP3_24A ,Color Palette 3_24 Blend Ratio"
|
|
hexmask.long.byte 0x60 18.--23. 1. " CP3_24R ,Color Palette 3_24 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x60 10.--15. 1. " CP3_24G ,Color Palette 3_24 Green"
|
|
hexmask.long.byte 0x60 2.--7. 1. " CP3_24B ,Color Palette 3_24 Blue"
|
|
line.long 0x64 "CP3_25R,Color Palette 3 Register 25"
|
|
hexmask.long.byte 0x64 24.--31. 1. " CP3_25A ,Color Palette 3_25 Blend Ratio"
|
|
hexmask.long.byte 0x64 18.--23. 1. " CP3_25R ,Color Palette 3_25 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x64 10.--15. 1. " CP3_25G ,Color Palette 3_25 Green"
|
|
hexmask.long.byte 0x64 2.--7. 1. " CP3_25B ,Color Palette 3_25 Blue"
|
|
line.long 0x68 "CP3_26R,Color Palette 3 Register 26"
|
|
hexmask.long.byte 0x68 24.--31. 1. " CP3_26A ,Color Palette 3_26 Blend Ratio"
|
|
hexmask.long.byte 0x68 18.--23. 1. " CP3_26R ,Color Palette 3_26 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x68 10.--15. 1. " CP3_26G ,Color Palette 3_26 Green"
|
|
hexmask.long.byte 0x68 2.--7. 1. " CP3_26B ,Color Palette 3_26 Blue"
|
|
line.long 0x6C "CP3_27R,Color Palette 3 Register 27"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " CP3_27A ,Color Palette 3_27 Blend Ratio"
|
|
hexmask.long.byte 0x6C 18.--23. 1. " CP3_27R ,Color Palette 3_27 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x6C 10.--15. 1. " CP3_27G ,Color Palette 3_27 Green"
|
|
hexmask.long.byte 0x6C 2.--7. 1. " CP3_27B ,Color Palette 3_27 Blue"
|
|
line.long 0x70 "CP3_28R,Color Palette 3 Register 28"
|
|
hexmask.long.byte 0x70 24.--31. 1. " CP3_28A ,Color Palette 3_28 Blend Ratio"
|
|
hexmask.long.byte 0x70 18.--23. 1. " CP3_28R ,Color Palette 3_28 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x70 10.--15. 1. " CP3_28G ,Color Palette 3_28 Green"
|
|
hexmask.long.byte 0x70 2.--7. 1. " CP3_28B ,Color Palette 3_28 Blue"
|
|
line.long 0x74 "CP3_29R,Color Palette 3 Register 29"
|
|
hexmask.long.byte 0x74 24.--31. 1. " CP3_29A ,Color Palette 3_29 Blend Ratio"
|
|
hexmask.long.byte 0x74 18.--23. 1. " CP3_29R ,Color Palette 3_29 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x74 10.--15. 1. " CP3_29G ,Color Palette 3_29 Green"
|
|
hexmask.long.byte 0x74 2.--7. 1. " CP3_29B ,Color Palette 3_29 Blue"
|
|
line.long 0x78 "CP3_30R,Color Palette 3 Register 30"
|
|
hexmask.long.byte 0x78 24.--31. 1. " CP3_30A ,Color Palette 3_30 Blend Ratio"
|
|
hexmask.long.byte 0x78 18.--23. 1. " CP3_30R ,Color Palette 3_30 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x78 10.--15. 1. " CP3_30G ,Color Palette 3_30 Green"
|
|
hexmask.long.byte 0x78 2.--7. 1. " CP3_30B ,Color Palette 3_30 Blue"
|
|
line.long 0x7C "CP3_31R,Color Palette 3 Register 31"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " CP3_31A ,Color Palette 3_31 Blend Ratio"
|
|
hexmask.long.byte 0x7C 18.--23. 1. " CP3_31R ,Color Palette 3_31 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x7C 10.--15. 1. " CP3_31G ,Color Palette 3_31 Green"
|
|
hexmask.long.byte 0x7C 2.--7. 1. " CP3_31B ,Color Palette 3_31 Blue"
|
|
line.long 0x80 "CP3_32R,Color Palette 3 Register 32"
|
|
hexmask.long.byte 0x80 24.--31. 1. " CP3_32A ,Color Palette 3_32 Blend Ratio"
|
|
hexmask.long.byte 0x80 18.--23. 1. " CP3_32R ,Color Palette 3_32 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x80 10.--15. 1. " CP3_32G ,Color Palette 3_32 Green"
|
|
hexmask.long.byte 0x80 2.--7. 1. " CP3_32B ,Color Palette 3_32 Blue"
|
|
line.long 0x84 "CP3_33R,Color Palette 3 Register 33"
|
|
hexmask.long.byte 0x84 24.--31. 1. " CP3_33A ,Color Palette 3_33 Blend Ratio"
|
|
hexmask.long.byte 0x84 18.--23. 1. " CP3_33R ,Color Palette 3_33 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x84 10.--15. 1. " CP3_33G ,Color Palette 3_33 Green"
|
|
hexmask.long.byte 0x84 2.--7. 1. " CP3_33B ,Color Palette 3_33 Blue"
|
|
line.long 0x88 "CP3_34R,Color Palette 3 Register 34"
|
|
hexmask.long.byte 0x88 24.--31. 1. " CP3_34A ,Color Palette 3_34 Blend Ratio"
|
|
hexmask.long.byte 0x88 18.--23. 1. " CP3_34R ,Color Palette 3_34 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x88 10.--15. 1. " CP3_34G ,Color Palette 3_34 Green"
|
|
hexmask.long.byte 0x88 2.--7. 1. " CP3_34B ,Color Palette 3_34 Blue"
|
|
line.long 0x8C "CP3_35R,Color Palette 3 Register 35"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " CP3_35A ,Color Palette 3_35 Blend Ratio"
|
|
hexmask.long.byte 0x8C 18.--23. 1. " CP3_35R ,Color Palette 3_35 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x8C 10.--15. 1. " CP3_35G ,Color Palette 3_35 Green"
|
|
hexmask.long.byte 0x8C 2.--7. 1. " CP3_35B ,Color Palette 3_35 Blue"
|
|
line.long 0x90 "CP3_36R,Color Palette 3 Register 36"
|
|
hexmask.long.byte 0x90 24.--31. 1. " CP3_36A ,Color Palette 3_36 Blend Ratio"
|
|
hexmask.long.byte 0x90 18.--23. 1. " CP3_36R ,Color Palette 3_36 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x90 10.--15. 1. " CP3_36G ,Color Palette 3_36 Green"
|
|
hexmask.long.byte 0x90 2.--7. 1. " CP3_36B ,Color Palette 3_36 Blue"
|
|
line.long 0x94 "CP3_37R,Color Palette 3 Register 37"
|
|
hexmask.long.byte 0x94 24.--31. 1. " CP3_37A ,Color Palette 3_37 Blend Ratio"
|
|
hexmask.long.byte 0x94 18.--23. 1. " CP3_37R ,Color Palette 3_37 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x94 10.--15. 1. " CP3_37G ,Color Palette 3_37 Green"
|
|
hexmask.long.byte 0x94 2.--7. 1. " CP3_37B ,Color Palette 3_37 Blue"
|
|
line.long 0x98 "CP3_38R,Color Palette 3 Register 38"
|
|
hexmask.long.byte 0x98 24.--31. 1. " CP3_38A ,Color Palette 3_38 Blend Ratio"
|
|
hexmask.long.byte 0x98 18.--23. 1. " CP3_38R ,Color Palette 3_38 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x98 10.--15. 1. " CP3_38G ,Color Palette 3_38 Green"
|
|
hexmask.long.byte 0x98 2.--7. 1. " CP3_38B ,Color Palette 3_38 Blue"
|
|
line.long 0x9C "CP3_39R,Color Palette 3 Register 39"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " CP3_39A ,Color Palette 3_39 Blend Ratio"
|
|
hexmask.long.byte 0x9C 18.--23. 1. " CP3_39R ,Color Palette 3_39 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x9C 10.--15. 1. " CP3_39G ,Color Palette 3_39 Green"
|
|
hexmask.long.byte 0x9C 2.--7. 1. " CP3_39B ,Color Palette 3_39 Blue"
|
|
line.long 0xA0 "CP3_40R,Color Palette 3 Register 40"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " CP3_40A ,Color Palette 3_40 Blend Ratio"
|
|
hexmask.long.byte 0xA0 18.--23. 1. " CP3_40R ,Color Palette 3_40 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA0 10.--15. 1. " CP3_40G ,Color Palette 3_40 Green"
|
|
hexmask.long.byte 0xA0 2.--7. 1. " CP3_40B ,Color Palette 3_40 Blue"
|
|
line.long 0xA4 "CP3_41R,Color Palette 3 Register 41"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " CP3_41A ,Color Palette 3_41 Blend Ratio"
|
|
hexmask.long.byte 0xA4 18.--23. 1. " CP3_41R ,Color Palette 3_41 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA4 10.--15. 1. " CP3_41G ,Color Palette 3_41 Green"
|
|
hexmask.long.byte 0xA4 2.--7. 1. " CP3_41B ,Color Palette 3_41 Blue"
|
|
line.long 0xA8 "CP3_42R,Color Palette 3 Register 42"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " CP3_42A ,Color Palette 3_42 Blend Ratio"
|
|
hexmask.long.byte 0xA8 18.--23. 1. " CP3_42R ,Color Palette 3_42 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xA8 10.--15. 1. " CP3_42G ,Color Palette 3_42 Green"
|
|
hexmask.long.byte 0xA8 2.--7. 1. " CP3_42B ,Color Palette 3_42 Blue"
|
|
line.long 0xAC "CP3_43R,Color Palette 3 Register 43"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " CP3_43A ,Color Palette 3_43 Blend Ratio"
|
|
hexmask.long.byte 0xAC 18.--23. 1. " CP3_43R ,Color Palette 3_43 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xAC 10.--15. 1. " CP3_43G ,Color Palette 3_43 Green"
|
|
hexmask.long.byte 0xAC 2.--7. 1. " CP3_43B ,Color Palette 3_43 Blue"
|
|
line.long 0xB0 "CP3_44R,Color Palette 3 Register 44"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " CP3_44A ,Color Palette 3_44 Blend Ratio"
|
|
hexmask.long.byte 0xB0 18.--23. 1. " CP3_44R ,Color Palette 3_44 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB0 10.--15. 1. " CP3_44G ,Color Palette 3_44 Green"
|
|
hexmask.long.byte 0xB0 2.--7. 1. " CP3_44B ,Color Palette 3_44 Blue"
|
|
line.long 0xB4 "CP3_45R,Color Palette 3 Register 45"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " CP3_45A ,Color Palette 3_45 Blend Ratio"
|
|
hexmask.long.byte 0xB4 18.--23. 1. " CP3_45R ,Color Palette 3_45 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB4 10.--15. 1. " CP3_45G ,Color Palette 3_45 Green"
|
|
hexmask.long.byte 0xB4 2.--7. 1. " CP3_45B ,Color Palette 3_45 Blue"
|
|
line.long 0xB8 "CP3_46R,Color Palette 3 Register 46"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " CP3_46A ,Color Palette 3_46 Blend Ratio"
|
|
hexmask.long.byte 0xB8 18.--23. 1. " CP3_46R ,Color Palette 3_46 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xB8 10.--15. 1. " CP3_46G ,Color Palette 3_46 Green"
|
|
hexmask.long.byte 0xB8 2.--7. 1. " CP3_46B ,Color Palette 3_46 Blue"
|
|
line.long 0xBC "CP3_47R,Color Palette 3 Register 47"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " CP3_47A ,Color Palette 3_47 Blend Ratio"
|
|
hexmask.long.byte 0xBC 18.--23. 1. " CP3_47R ,Color Palette 3_47 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xBC 10.--15. 1. " CP3_47G ,Color Palette 3_47 Green"
|
|
hexmask.long.byte 0xBC 2.--7. 1. " CP3_47B ,Color Palette 3_47 Blue"
|
|
line.long 0xC0 "CP3_48R,Color Palette 3 Register 48"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " CP3_48A ,Color Palette 3_48 Blend Ratio"
|
|
hexmask.long.byte 0xC0 18.--23. 1. " CP3_48R ,Color Palette 3_48 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC0 10.--15. 1. " CP3_48G ,Color Palette 3_48 Green"
|
|
hexmask.long.byte 0xC0 2.--7. 1. " CP3_48B ,Color Palette 3_48 Blue"
|
|
line.long 0xC4 "CP3_49R,Color Palette 3 Register 49"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " CP3_49A ,Color Palette 3_49 Blend Ratio"
|
|
hexmask.long.byte 0xC4 18.--23. 1. " CP3_49R ,Color Palette 3_49 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC4 10.--15. 1. " CP3_49G ,Color Palette 3_49 Green"
|
|
hexmask.long.byte 0xC4 2.--7. 1. " CP3_49B ,Color Palette 3_49 Blue"
|
|
line.long 0xC8 "CP3_50R,Color Palette 3 Register 50"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " CP3_50A ,Color Palette 3_50 Blend Ratio"
|
|
hexmask.long.byte 0xC8 18.--23. 1. " CP3_50R ,Color Palette 3_50 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xC8 10.--15. 1. " CP3_50G ,Color Palette 3_50 Green"
|
|
hexmask.long.byte 0xC8 2.--7. 1. " CP3_50B ,Color Palette 3_50 Blue"
|
|
line.long 0xCC "CP3_51R,Color Palette 3 Register 51"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " CP3_51A ,Color Palette 3_51 Blend Ratio"
|
|
hexmask.long.byte 0xCC 18.--23. 1. " CP3_51R ,Color Palette 3_51 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xCC 10.--15. 1. " CP3_51G ,Color Palette 3_51 Green"
|
|
hexmask.long.byte 0xCC 2.--7. 1. " CP3_51B ,Color Palette 3_51 Blue"
|
|
line.long 0xD0 "CP3_52R,Color Palette 3 Register 52"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " CP3_52A ,Color Palette 3_52 Blend Ratio"
|
|
hexmask.long.byte 0xD0 18.--23. 1. " CP3_52R ,Color Palette 3_52 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD0 10.--15. 1. " CP3_52G ,Color Palette 3_52 Green"
|
|
hexmask.long.byte 0xD0 2.--7. 1. " CP3_52B ,Color Palette 3_52 Blue"
|
|
line.long 0xD4 "CP3_53R,Color Palette 3 Register 53"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " CP3_53A ,Color Palette 3_53 Blend Ratio"
|
|
hexmask.long.byte 0xD4 18.--23. 1. " CP3_53R ,Color Palette 3_53 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD4 10.--15. 1. " CP3_53G ,Color Palette 3_53 Green"
|
|
hexmask.long.byte 0xD4 2.--7. 1. " CP3_53B ,Color Palette 3_53 Blue"
|
|
line.long 0xD8 "CP3_54R,Color Palette 3 Register 54"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " CP3_54A ,Color Palette 3_54 Blend Ratio"
|
|
hexmask.long.byte 0xD8 18.--23. 1. " CP3_54R ,Color Palette 3_54 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xD8 10.--15. 1. " CP3_54G ,Color Palette 3_54 Green"
|
|
hexmask.long.byte 0xD8 2.--7. 1. " CP3_54B ,Color Palette 3_54 Blue"
|
|
line.long 0xDC "CP3_55R,Color Palette 3 Register 55"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " CP3_55A ,Color Palette 3_55 Blend Ratio"
|
|
hexmask.long.byte 0xDC 18.--23. 1. " CP3_55R ,Color Palette 3_55 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xDC 10.--15. 1. " CP3_55G ,Color Palette 3_55 Green"
|
|
hexmask.long.byte 0xDC 2.--7. 1. " CP3_55B ,Color Palette 3_55 Blue"
|
|
line.long 0xE0 "CP3_56R,Color Palette 3 Register 56"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " CP3_56A ,Color Palette 3_56 Blend Ratio"
|
|
hexmask.long.byte 0xE0 18.--23. 1. " CP3_56R ,Color Palette 3_56 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE0 10.--15. 1. " CP3_56G ,Color Palette 3_56 Green"
|
|
hexmask.long.byte 0xE0 2.--7. 1. " CP3_56B ,Color Palette 3_56 Blue"
|
|
line.long 0xE4 "CP3_57R,Color Palette 3 Register 57"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " CP3_57A ,Color Palette 3_57 Blend Ratio"
|
|
hexmask.long.byte 0xE4 18.--23. 1. " CP3_57R ,Color Palette 3_57 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE4 10.--15. 1. " CP3_57G ,Color Palette 3_57 Green"
|
|
hexmask.long.byte 0xE4 2.--7. 1. " CP3_57B ,Color Palette 3_57 Blue"
|
|
line.long 0xE8 "CP3_58R,Color Palette 3 Register 58"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " CP3_58A ,Color Palette 3_58 Blend Ratio"
|
|
hexmask.long.byte 0xE8 18.--23. 1. " CP3_58R ,Color Palette 3_58 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xE8 10.--15. 1. " CP3_58G ,Color Palette 3_58 Green"
|
|
hexmask.long.byte 0xE8 2.--7. 1. " CP3_58B ,Color Palette 3_58 Blue"
|
|
line.long 0xEC "CP3_59R,Color Palette 3 Register 59"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " CP3_59A ,Color Palette 3_59 Blend Ratio"
|
|
hexmask.long.byte 0xEC 18.--23. 1. " CP3_59R ,Color Palette 3_59 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xEC 10.--15. 1. " CP3_59G ,Color Palette 3_59 Green"
|
|
hexmask.long.byte 0xEC 2.--7. 1. " CP3_59B ,Color Palette 3_59 Blue"
|
|
line.long 0xF0 "CP3_60R,Color Palette 3 Register 60"
|
|
hexmask.long.byte 0xF0 24.--31. 1. " CP3_60A ,Color Palette 3_60 Blend Ratio"
|
|
hexmask.long.byte 0xF0 18.--23. 1. " CP3_60R ,Color Palette 3_60 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF0 10.--15. 1. " CP3_60G ,Color Palette 3_60 Green"
|
|
hexmask.long.byte 0xF0 2.--7. 1. " CP3_60B ,Color Palette 3_60 Blue"
|
|
line.long 0xF4 "CP3_61R,Color Palette 3 Register 61"
|
|
hexmask.long.byte 0xF4 24.--31. 1. " CP3_61A ,Color Palette 3_61 Blend Ratio"
|
|
hexmask.long.byte 0xF4 18.--23. 1. " CP3_61R ,Color Palette 3_61 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF4 10.--15. 1. " CP3_61G ,Color Palette 3_61 Green"
|
|
hexmask.long.byte 0xF4 2.--7. 1. " CP3_61B ,Color Palette 3_61 Blue"
|
|
line.long 0xF8 "CP3_62R,Color Palette 3 Register 62"
|
|
hexmask.long.byte 0xF8 24.--31. 1. " CP3_62A ,Color Palette 3_62 Blend Ratio"
|
|
hexmask.long.byte 0xF8 18.--23. 1. " CP3_62R ,Color Palette 3_62 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xF8 10.--15. 1. " CP3_62G ,Color Palette 3_62 Green"
|
|
hexmask.long.byte 0xF8 2.--7. 1. " CP3_62B ,Color Palette 3_62 Blue"
|
|
line.long 0xFC "CP3_63R,Color Palette 3 Register 63"
|
|
hexmask.long.byte 0xFC 24.--31. 1. " CP3_63A ,Color Palette 3_63 Blend Ratio"
|
|
hexmask.long.byte 0xFC 18.--23. 1. " CP3_63R ,Color Palette 3_63 Red"
|
|
textline " "
|
|
hexmask.long.byte 0xFC 10.--15. 1. " CP3_63G ,Color Palette 3_63 Green"
|
|
hexmask.long.byte 0xFC 2.--7. 1. " CP3_63B ,Color Palette 3_63 Blue"
|
|
line.long 0x100 "CP3_64R,Color Palette 3 Register 64"
|
|
hexmask.long.byte 0x100 24.--31. 1. " CP3_64A ,Color Palette 3_64 Blend Ratio"
|
|
hexmask.long.byte 0x100 18.--23. 1. " CP3_64R ,Color Palette 3_64 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x100 10.--15. 1. " CP3_64G ,Color Palette 3_64 Green"
|
|
hexmask.long.byte 0x100 2.--7. 1. " CP3_64B ,Color Palette 3_64 Blue"
|
|
line.long 0x104 "CP3_65R,Color Palette 3 Register 65"
|
|
hexmask.long.byte 0x104 24.--31. 1. " CP3_65A ,Color Palette 3_65 Blend Ratio"
|
|
hexmask.long.byte 0x104 18.--23. 1. " CP3_65R ,Color Palette 3_65 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x104 10.--15. 1. " CP3_65G ,Color Palette 3_65 Green"
|
|
hexmask.long.byte 0x104 2.--7. 1. " CP3_65B ,Color Palette 3_65 Blue"
|
|
line.long 0x108 "CP3_66R,Color Palette 3 Register 66"
|
|
hexmask.long.byte 0x108 24.--31. 1. " CP3_66A ,Color Palette 3_66 Blend Ratio"
|
|
hexmask.long.byte 0x108 18.--23. 1. " CP3_66R ,Color Palette 3_66 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x108 10.--15. 1. " CP3_66G ,Color Palette 3_66 Green"
|
|
hexmask.long.byte 0x108 2.--7. 1. " CP3_66B ,Color Palette 3_66 Blue"
|
|
line.long 0x10C "CP3_67R,Color Palette 3 Register 67"
|
|
hexmask.long.byte 0x10C 24.--31. 1. " CP3_67A ,Color Palette 3_67 Blend Ratio"
|
|
hexmask.long.byte 0x10C 18.--23. 1. " CP3_67R ,Color Palette 3_67 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x10C 10.--15. 1. " CP3_67G ,Color Palette 3_67 Green"
|
|
hexmask.long.byte 0x10C 2.--7. 1. " CP3_67B ,Color Palette 3_67 Blue"
|
|
line.long 0x110 "CP3_68R,Color Palette 3 Register 68"
|
|
hexmask.long.byte 0x110 24.--31. 1. " CP3_68A ,Color Palette 3_68 Blend Ratio"
|
|
hexmask.long.byte 0x110 18.--23. 1. " CP3_68R ,Color Palette 3_68 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x110 10.--15. 1. " CP3_68G ,Color Palette 3_68 Green"
|
|
hexmask.long.byte 0x110 2.--7. 1. " CP3_68B ,Color Palette 3_68 Blue"
|
|
line.long 0x114 "CP3_69R,Color Palette 3 Register 69"
|
|
hexmask.long.byte 0x114 24.--31. 1. " CP3_69A ,Color Palette 3_69 Blend Ratio"
|
|
hexmask.long.byte 0x114 18.--23. 1. " CP3_69R ,Color Palette 3_69 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x114 10.--15. 1. " CP3_69G ,Color Palette 3_69 Green"
|
|
hexmask.long.byte 0x114 2.--7. 1. " CP3_69B ,Color Palette 3_69 Blue"
|
|
line.long 0x118 "CP3_70R,Color Palette 3 Register 70"
|
|
hexmask.long.byte 0x118 24.--31. 1. " CP3_70A ,Color Palette 3_70 Blend Ratio"
|
|
hexmask.long.byte 0x118 18.--23. 1. " CP3_70R ,Color Palette 3_70 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x118 10.--15. 1. " CP3_70G ,Color Palette 3_70 Green"
|
|
hexmask.long.byte 0x118 2.--7. 1. " CP3_70B ,Color Palette 3_70 Blue"
|
|
line.long 0x11C "CP3_71R,Color Palette 3 Register 71"
|
|
hexmask.long.byte 0x11C 24.--31. 1. " CP3_71A ,Color Palette 3_71 Blend Ratio"
|
|
hexmask.long.byte 0x11C 18.--23. 1. " CP3_71R ,Color Palette 3_71 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x11C 10.--15. 1. " CP3_71G ,Color Palette 3_71 Green"
|
|
hexmask.long.byte 0x11C 2.--7. 1. " CP3_71B ,Color Palette 3_71 Blue"
|
|
line.long 0x120 "CP3_72R,Color Palette 3 Register 72"
|
|
hexmask.long.byte 0x120 24.--31. 1. " CP3_72A ,Color Palette 3_72 Blend Ratio"
|
|
hexmask.long.byte 0x120 18.--23. 1. " CP3_72R ,Color Palette 3_72 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x120 10.--15. 1. " CP3_72G ,Color Palette 3_72 Green"
|
|
hexmask.long.byte 0x120 2.--7. 1. " CP3_72B ,Color Palette 3_72 Blue"
|
|
line.long 0x124 "CP3_73R,Color Palette 3 Register 73"
|
|
hexmask.long.byte 0x124 24.--31. 1. " CP3_73A ,Color Palette 3_73 Blend Ratio"
|
|
hexmask.long.byte 0x124 18.--23. 1. " CP3_73R ,Color Palette 3_73 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x124 10.--15. 1. " CP3_73G ,Color Palette 3_73 Green"
|
|
hexmask.long.byte 0x124 2.--7. 1. " CP3_73B ,Color Palette 3_73 Blue"
|
|
line.long 0x128 "CP3_74R,Color Palette 3 Register 74"
|
|
hexmask.long.byte 0x128 24.--31. 1. " CP3_74A ,Color Palette 3_74 Blend Ratio"
|
|
hexmask.long.byte 0x128 18.--23. 1. " CP3_74R ,Color Palette 3_74 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x128 10.--15. 1. " CP3_74G ,Color Palette 3_74 Green"
|
|
hexmask.long.byte 0x128 2.--7. 1. " CP3_74B ,Color Palette 3_74 Blue"
|
|
line.long 0x12C "CP3_75R,Color Palette 3 Register 75"
|
|
hexmask.long.byte 0x12C 24.--31. 1. " CP3_75A ,Color Palette 3_75 Blend Ratio"
|
|
hexmask.long.byte 0x12C 18.--23. 1. " CP3_75R ,Color Palette 3_75 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x12C 10.--15. 1. " CP3_75G ,Color Palette 3_75 Green"
|
|
hexmask.long.byte 0x12C 2.--7. 1. " CP3_75B ,Color Palette 3_75 Blue"
|
|
line.long 0x130 "CP3_76R,Color Palette 3 Register 76"
|
|
hexmask.long.byte 0x130 24.--31. 1. " CP3_76A ,Color Palette 3_76 Blend Ratio"
|
|
hexmask.long.byte 0x130 18.--23. 1. " CP3_76R ,Color Palette 3_76 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x130 10.--15. 1. " CP3_76G ,Color Palette 3_76 Green"
|
|
hexmask.long.byte 0x130 2.--7. 1. " CP3_76B ,Color Palette 3_76 Blue"
|
|
line.long 0x134 "CP3_77R,Color Palette 3 Register 77"
|
|
hexmask.long.byte 0x134 24.--31. 1. " CP3_77A ,Color Palette 3_77 Blend Ratio"
|
|
hexmask.long.byte 0x134 18.--23. 1. " CP3_77R ,Color Palette 3_77 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x134 10.--15. 1. " CP3_77G ,Color Palette 3_77 Green"
|
|
hexmask.long.byte 0x134 2.--7. 1. " CP3_77B ,Color Palette 3_77 Blue"
|
|
line.long 0x138 "CP3_78R,Color Palette 3 Register 78"
|
|
hexmask.long.byte 0x138 24.--31. 1. " CP3_78A ,Color Palette 3_78 Blend Ratio"
|
|
hexmask.long.byte 0x138 18.--23. 1. " CP3_78R ,Color Palette 3_78 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x138 10.--15. 1. " CP3_78G ,Color Palette 3_78 Green"
|
|
hexmask.long.byte 0x138 2.--7. 1. " CP3_78B ,Color Palette 3_78 Blue"
|
|
line.long 0x13C "CP3_79R,Color Palette 3 Register 79"
|
|
hexmask.long.byte 0x13C 24.--31. 1. " CP3_79A ,Color Palette 3_79 Blend Ratio"
|
|
hexmask.long.byte 0x13C 18.--23. 1. " CP3_79R ,Color Palette 3_79 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x13C 10.--15. 1. " CP3_79G ,Color Palette 3_79 Green"
|
|
hexmask.long.byte 0x13C 2.--7. 1. " CP3_79B ,Color Palette 3_79 Blue"
|
|
line.long 0x140 "CP3_80R,Color Palette 3 Register 80"
|
|
hexmask.long.byte 0x140 24.--31. 1. " CP3_80A ,Color Palette 3_80 Blend Ratio"
|
|
hexmask.long.byte 0x140 18.--23. 1. " CP3_80R ,Color Palette 3_80 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x140 10.--15. 1. " CP3_80G ,Color Palette 3_80 Green"
|
|
hexmask.long.byte 0x140 2.--7. 1. " CP3_80B ,Color Palette 3_80 Blue"
|
|
line.long 0x144 "CP3_81R,Color Palette 3 Register 81"
|
|
hexmask.long.byte 0x144 24.--31. 1. " CP3_81A ,Color Palette 3_81 Blend Ratio"
|
|
hexmask.long.byte 0x144 18.--23. 1. " CP3_81R ,Color Palette 3_81 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x144 10.--15. 1. " CP3_81G ,Color Palette 3_81 Green"
|
|
hexmask.long.byte 0x144 2.--7. 1. " CP3_81B ,Color Palette 3_81 Blue"
|
|
line.long 0x148 "CP3_82R,Color Palette 3 Register 82"
|
|
hexmask.long.byte 0x148 24.--31. 1. " CP3_82A ,Color Palette 3_82 Blend Ratio"
|
|
hexmask.long.byte 0x148 18.--23. 1. " CP3_82R ,Color Palette 3_82 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x148 10.--15. 1. " CP3_82G ,Color Palette 3_82 Green"
|
|
hexmask.long.byte 0x148 2.--7. 1. " CP3_82B ,Color Palette 3_82 Blue"
|
|
line.long 0x14C "CP3_83R,Color Palette 3 Register 83"
|
|
hexmask.long.byte 0x14C 24.--31. 1. " CP3_83A ,Color Palette 3_83 Blend Ratio"
|
|
hexmask.long.byte 0x14C 18.--23. 1. " CP3_83R ,Color Palette 3_83 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x14C 10.--15. 1. " CP3_83G ,Color Palette 3_83 Green"
|
|
hexmask.long.byte 0x14C 2.--7. 1. " CP3_83B ,Color Palette 3_83 Blue"
|
|
line.long 0x150 "CP3_84R,Color Palette 3 Register 84"
|
|
hexmask.long.byte 0x150 24.--31. 1. " CP3_84A ,Color Palette 3_84 Blend Ratio"
|
|
hexmask.long.byte 0x150 18.--23. 1. " CP3_84R ,Color Palette 3_84 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x150 10.--15. 1. " CP3_84G ,Color Palette 3_84 Green"
|
|
hexmask.long.byte 0x150 2.--7. 1. " CP3_84B ,Color Palette 3_84 Blue"
|
|
line.long 0x154 "CP3_85R,Color Palette 3 Register 85"
|
|
hexmask.long.byte 0x154 24.--31. 1. " CP3_85A ,Color Palette 3_85 Blend Ratio"
|
|
hexmask.long.byte 0x154 18.--23. 1. " CP3_85R ,Color Palette 3_85 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x154 10.--15. 1. " CP3_85G ,Color Palette 3_85 Green"
|
|
hexmask.long.byte 0x154 2.--7. 1. " CP3_85B ,Color Palette 3_85 Blue"
|
|
line.long 0x158 "CP3_86R,Color Palette 3 Register 86"
|
|
hexmask.long.byte 0x158 24.--31. 1. " CP3_86A ,Color Palette 3_86 Blend Ratio"
|
|
hexmask.long.byte 0x158 18.--23. 1. " CP3_86R ,Color Palette 3_86 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x158 10.--15. 1. " CP3_86G ,Color Palette 3_86 Green"
|
|
hexmask.long.byte 0x158 2.--7. 1. " CP3_86B ,Color Palette 3_86 Blue"
|
|
line.long 0x15C "CP3_87R,Color Palette 3 Register 87"
|
|
hexmask.long.byte 0x15C 24.--31. 1. " CP3_87A ,Color Palette 3_87 Blend Ratio"
|
|
hexmask.long.byte 0x15C 18.--23. 1. " CP3_87R ,Color Palette 3_87 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x15C 10.--15. 1. " CP3_87G ,Color Palette 3_87 Green"
|
|
hexmask.long.byte 0x15C 2.--7. 1. " CP3_87B ,Color Palette 3_87 Blue"
|
|
line.long 0x160 "CP3_88R,Color Palette 3 Register 88"
|
|
hexmask.long.byte 0x160 24.--31. 1. " CP3_88A ,Color Palette 3_88 Blend Ratio"
|
|
hexmask.long.byte 0x160 18.--23. 1. " CP3_88R ,Color Palette 3_88 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x160 10.--15. 1. " CP3_88G ,Color Palette 3_88 Green"
|
|
hexmask.long.byte 0x160 2.--7. 1. " CP3_88B ,Color Palette 3_88 Blue"
|
|
line.long 0x164 "CP3_89R,Color Palette 3 Register 89"
|
|
hexmask.long.byte 0x164 24.--31. 1. " CP3_89A ,Color Palette 3_89 Blend Ratio"
|
|
hexmask.long.byte 0x164 18.--23. 1. " CP3_89R ,Color Palette 3_89 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x164 10.--15. 1. " CP3_89G ,Color Palette 3_89 Green"
|
|
hexmask.long.byte 0x164 2.--7. 1. " CP3_89B ,Color Palette 3_89 Blue"
|
|
line.long 0x168 "CP3_90R,Color Palette 3 Register 90"
|
|
hexmask.long.byte 0x168 24.--31. 1. " CP3_90A ,Color Palette 3_90 Blend Ratio"
|
|
hexmask.long.byte 0x168 18.--23. 1. " CP3_90R ,Color Palette 3_90 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x168 10.--15. 1. " CP3_90G ,Color Palette 3_90 Green"
|
|
hexmask.long.byte 0x168 2.--7. 1. " CP3_90B ,Color Palette 3_90 Blue"
|
|
line.long 0x16C "CP3_91R,Color Palette 3 Register 91"
|
|
hexmask.long.byte 0x16C 24.--31. 1. " CP3_91A ,Color Palette 3_91 Blend Ratio"
|
|
hexmask.long.byte 0x16C 18.--23. 1. " CP3_91R ,Color Palette 3_91 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x16C 10.--15. 1. " CP3_91G ,Color Palette 3_91 Green"
|
|
hexmask.long.byte 0x16C 2.--7. 1. " CP3_91B ,Color Palette 3_91 Blue"
|
|
line.long 0x170 "CP3_92R,Color Palette 3 Register 92"
|
|
hexmask.long.byte 0x170 24.--31. 1. " CP3_92A ,Color Palette 3_92 Blend Ratio"
|
|
hexmask.long.byte 0x170 18.--23. 1. " CP3_92R ,Color Palette 3_92 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x170 10.--15. 1. " CP3_92G ,Color Palette 3_92 Green"
|
|
hexmask.long.byte 0x170 2.--7. 1. " CP3_92B ,Color Palette 3_92 Blue"
|
|
line.long 0x174 "CP3_93R,Color Palette 3 Register 93"
|
|
hexmask.long.byte 0x174 24.--31. 1. " CP3_93A ,Color Palette 3_93 Blend Ratio"
|
|
hexmask.long.byte 0x174 18.--23. 1. " CP3_93R ,Color Palette 3_93 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x174 10.--15. 1. " CP3_93G ,Color Palette 3_93 Green"
|
|
hexmask.long.byte 0x174 2.--7. 1. " CP3_93B ,Color Palette 3_93 Blue"
|
|
line.long 0x178 "CP3_94R,Color Palette 3 Register 94"
|
|
hexmask.long.byte 0x178 24.--31. 1. " CP3_94A ,Color Palette 3_94 Blend Ratio"
|
|
hexmask.long.byte 0x178 18.--23. 1. " CP3_94R ,Color Palette 3_94 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x178 10.--15. 1. " CP3_94G ,Color Palette 3_94 Green"
|
|
hexmask.long.byte 0x178 2.--7. 1. " CP3_94B ,Color Palette 3_94 Blue"
|
|
line.long 0x17C "CP3_95R,Color Palette 3 Register 95"
|
|
hexmask.long.byte 0x17C 24.--31. 1. " CP3_95A ,Color Palette 3_95 Blend Ratio"
|
|
hexmask.long.byte 0x17C 18.--23. 1. " CP3_95R ,Color Palette 3_95 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x17C 10.--15. 1. " CP3_95G ,Color Palette 3_95 Green"
|
|
hexmask.long.byte 0x17C 2.--7. 1. " CP3_95B ,Color Palette 3_95 Blue"
|
|
line.long 0x180 "CP3_96R,Color Palette 3 Register 96"
|
|
hexmask.long.byte 0x180 24.--31. 1. " CP3_96A ,Color Palette 3_96 Blend Ratio"
|
|
hexmask.long.byte 0x180 18.--23. 1. " CP3_96R ,Color Palette 3_96 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x180 10.--15. 1. " CP3_96G ,Color Palette 3_96 Green"
|
|
hexmask.long.byte 0x180 2.--7. 1. " CP3_96B ,Color Palette 3_96 Blue"
|
|
line.long 0x184 "CP3_97R,Color Palette 3 Register 97"
|
|
hexmask.long.byte 0x184 24.--31. 1. " CP3_97A ,Color Palette 3_97 Blend Ratio"
|
|
hexmask.long.byte 0x184 18.--23. 1. " CP3_97R ,Color Palette 3_97 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x184 10.--15. 1. " CP3_97G ,Color Palette 3_97 Green"
|
|
hexmask.long.byte 0x184 2.--7. 1. " CP3_97B ,Color Palette 3_97 Blue"
|
|
line.long 0x188 "CP3_98R,Color Palette 3 Register 98"
|
|
hexmask.long.byte 0x188 24.--31. 1. " CP3_98A ,Color Palette 3_98 Blend Ratio"
|
|
hexmask.long.byte 0x188 18.--23. 1. " CP3_98R ,Color Palette 3_98 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x188 10.--15. 1. " CP3_98G ,Color Palette 3_98 Green"
|
|
hexmask.long.byte 0x188 2.--7. 1. " CP3_98B ,Color Palette 3_98 Blue"
|
|
line.long 0x18C "CP3_99R,Color Palette 3 Register 99"
|
|
hexmask.long.byte 0x18C 24.--31. 1. " CP3_99A ,Color Palette 3_99 Blend Ratio"
|
|
hexmask.long.byte 0x18C 18.--23. 1. " CP3_99R ,Color Palette 3_99 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x18C 10.--15. 1. " CP3_99G ,Color Palette 3_99 Green"
|
|
hexmask.long.byte 0x18C 2.--7. 1. " CP3_99B ,Color Palette 3_99 Blue"
|
|
line.long 0x190 "CP3_100R,Color Palette 3 Register 100"
|
|
hexmask.long.byte 0x190 24.--31. 1. " CP3_100A ,Color Palette 3_100 Blend Ratio"
|
|
hexmask.long.byte 0x190 18.--23. 1. " CP3_100R ,Color Palette 3_100 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x190 10.--15. 1. " CP3_100G ,Color Palette 3_100 Green"
|
|
hexmask.long.byte 0x190 2.--7. 1. " CP3_100B ,Color Palette 3_100 Blue"
|
|
line.long 0x194 "CP3_101R,Color Palette 3 Register 101"
|
|
hexmask.long.byte 0x194 24.--31. 1. " CP3_101A ,Color Palette 3_101 Blend Ratio"
|
|
hexmask.long.byte 0x194 18.--23. 1. " CP3_101R ,Color Palette 3_101 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x194 10.--15. 1. " CP3_101G ,Color Palette 3_101 Green"
|
|
hexmask.long.byte 0x194 2.--7. 1. " CP3_101B ,Color Palette 3_101 Blue"
|
|
line.long 0x198 "CP3_102R,Color Palette 3 Register 102"
|
|
hexmask.long.byte 0x198 24.--31. 1. " CP3_102A ,Color Palette 3_102 Blend Ratio"
|
|
hexmask.long.byte 0x198 18.--23. 1. " CP3_102R ,Color Palette 3_102 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x198 10.--15. 1. " CP3_102G ,Color Palette 3_102 Green"
|
|
hexmask.long.byte 0x198 2.--7. 1. " CP3_102B ,Color Palette 3_102 Blue"
|
|
line.long 0x19C "CP3_103R,Color Palette 3 Register 103"
|
|
hexmask.long.byte 0x19C 24.--31. 1. " CP3_103A ,Color Palette 3_103 Blend Ratio"
|
|
hexmask.long.byte 0x19C 18.--23. 1. " CP3_103R ,Color Palette 3_103 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x19C 10.--15. 1. " CP3_103G ,Color Palette 3_103 Green"
|
|
hexmask.long.byte 0x19C 2.--7. 1. " CP3_103B ,Color Palette 3_103 Blue"
|
|
line.long 0x1A0 "CP3_104R,Color Palette 3 Register 104"
|
|
hexmask.long.byte 0x1A0 24.--31. 1. " CP3_104A ,Color Palette 3_104 Blend Ratio"
|
|
hexmask.long.byte 0x1A0 18.--23. 1. " CP3_104R ,Color Palette 3_104 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A0 10.--15. 1. " CP3_104G ,Color Palette 3_104 Green"
|
|
hexmask.long.byte 0x1A0 2.--7. 1. " CP3_104B ,Color Palette 3_104 Blue"
|
|
line.long 0x1A4 "CP3_105R,Color Palette 3 Register 105"
|
|
hexmask.long.byte 0x1A4 24.--31. 1. " CP3_105A ,Color Palette 3_105 Blend Ratio"
|
|
hexmask.long.byte 0x1A4 18.--23. 1. " CP3_105R ,Color Palette 3_105 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A4 10.--15. 1. " CP3_105G ,Color Palette 3_105 Green"
|
|
hexmask.long.byte 0x1A4 2.--7. 1. " CP3_105B ,Color Palette 3_105 Blue"
|
|
line.long 0x1A8 "CP3_106R,Color Palette 3 Register 106"
|
|
hexmask.long.byte 0x1A8 24.--31. 1. " CP3_106A ,Color Palette 3_106 Blend Ratio"
|
|
hexmask.long.byte 0x1A8 18.--23. 1. " CP3_106R ,Color Palette 3_106 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1A8 10.--15. 1. " CP3_106G ,Color Palette 3_106 Green"
|
|
hexmask.long.byte 0x1A8 2.--7. 1. " CP3_106B ,Color Palette 3_106 Blue"
|
|
line.long 0x1AC "CP3_107R,Color Palette 3 Register 107"
|
|
hexmask.long.byte 0x1AC 24.--31. 1. " CP3_107A ,Color Palette 3_107 Blend Ratio"
|
|
hexmask.long.byte 0x1AC 18.--23. 1. " CP3_107R ,Color Palette 3_107 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1AC 10.--15. 1. " CP3_107G ,Color Palette 3_107 Green"
|
|
hexmask.long.byte 0x1AC 2.--7. 1. " CP3_107B ,Color Palette 3_107 Blue"
|
|
line.long 0x1B0 "CP3_108R,Color Palette 3 Register 108"
|
|
hexmask.long.byte 0x1B0 24.--31. 1. " CP3_108A ,Color Palette 3_108 Blend Ratio"
|
|
hexmask.long.byte 0x1B0 18.--23. 1. " CP3_108R ,Color Palette 3_108 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B0 10.--15. 1. " CP3_108G ,Color Palette 3_108 Green"
|
|
hexmask.long.byte 0x1B0 2.--7. 1. " CP3_108B ,Color Palette 3_108 Blue"
|
|
line.long 0x1B4 "CP3_109R,Color Palette 3 Register 109"
|
|
hexmask.long.byte 0x1B4 24.--31. 1. " CP3_109A ,Color Palette 3_109 Blend Ratio"
|
|
hexmask.long.byte 0x1B4 18.--23. 1. " CP3_109R ,Color Palette 3_109 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B4 10.--15. 1. " CP3_109G ,Color Palette 3_109 Green"
|
|
hexmask.long.byte 0x1B4 2.--7. 1. " CP3_109B ,Color Palette 3_109 Blue"
|
|
line.long 0x1B8 "CP3_110R,Color Palette 3 Register 110"
|
|
hexmask.long.byte 0x1B8 24.--31. 1. " CP3_110A ,Color Palette 3_110 Blend Ratio"
|
|
hexmask.long.byte 0x1B8 18.--23. 1. " CP3_110R ,Color Palette 3_110 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1B8 10.--15. 1. " CP3_110G ,Color Palette 3_110 Green"
|
|
hexmask.long.byte 0x1B8 2.--7. 1. " CP3_110B ,Color Palette 3_110 Blue"
|
|
line.long 0x1BC "CP3_111R,Color Palette 3 Register 111"
|
|
hexmask.long.byte 0x1BC 24.--31. 1. " CP3_111A ,Color Palette 3_111 Blend Ratio"
|
|
hexmask.long.byte 0x1BC 18.--23. 1. " CP3_111R ,Color Palette 3_111 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1BC 10.--15. 1. " CP3_111G ,Color Palette 3_111 Green"
|
|
hexmask.long.byte 0x1BC 2.--7. 1. " CP3_111B ,Color Palette 3_111 Blue"
|
|
line.long 0x1C0 "CP3_112R,Color Palette 3 Register 112"
|
|
hexmask.long.byte 0x1C0 24.--31. 1. " CP3_112A ,Color Palette 3_112 Blend Ratio"
|
|
hexmask.long.byte 0x1C0 18.--23. 1. " CP3_112R ,Color Palette 3_112 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C0 10.--15. 1. " CP3_112G ,Color Palette 3_112 Green"
|
|
hexmask.long.byte 0x1C0 2.--7. 1. " CP3_112B ,Color Palette 3_112 Blue"
|
|
line.long 0x1C4 "CP3_113R,Color Palette 3 Register 113"
|
|
hexmask.long.byte 0x1C4 24.--31. 1. " CP3_113A ,Color Palette 3_113 Blend Ratio"
|
|
hexmask.long.byte 0x1C4 18.--23. 1. " CP3_113R ,Color Palette 3_113 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C4 10.--15. 1. " CP3_113G ,Color Palette 3_113 Green"
|
|
hexmask.long.byte 0x1C4 2.--7. 1. " CP3_113B ,Color Palette 3_113 Blue"
|
|
line.long 0x1C8 "CP3_114R,Color Palette 3 Register 114"
|
|
hexmask.long.byte 0x1C8 24.--31. 1. " CP3_114A ,Color Palette 3_114 Blend Ratio"
|
|
hexmask.long.byte 0x1C8 18.--23. 1. " CP3_114R ,Color Palette 3_114 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1C8 10.--15. 1. " CP3_114G ,Color Palette 3_114 Green"
|
|
hexmask.long.byte 0x1C8 2.--7. 1. " CP3_114B ,Color Palette 3_114 Blue"
|
|
line.long 0x1CC "CP3_115R,Color Palette 3 Register 115"
|
|
hexmask.long.byte 0x1CC 24.--31. 1. " CP3_115A ,Color Palette 3_115 Blend Ratio"
|
|
hexmask.long.byte 0x1CC 18.--23. 1. " CP3_115R ,Color Palette 3_115 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1CC 10.--15. 1. " CP3_115G ,Color Palette 3_115 Green"
|
|
hexmask.long.byte 0x1CC 2.--7. 1. " CP3_115B ,Color Palette 3_115 Blue"
|
|
line.long 0x1D0 "CP3_116R,Color Palette 3 Register 116"
|
|
hexmask.long.byte 0x1D0 24.--31. 1. " CP3_116A ,Color Palette 3_116 Blend Ratio"
|
|
hexmask.long.byte 0x1D0 18.--23. 1. " CP3_116R ,Color Palette 3_116 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D0 10.--15. 1. " CP3_116G ,Color Palette 3_116 Green"
|
|
hexmask.long.byte 0x1D0 2.--7. 1. " CP3_116B ,Color Palette 3_116 Blue"
|
|
line.long 0x1D4 "CP3_117R,Color Palette 3 Register 117"
|
|
hexmask.long.byte 0x1D4 24.--31. 1. " CP3_117A ,Color Palette 3_117 Blend Ratio"
|
|
hexmask.long.byte 0x1D4 18.--23. 1. " CP3_117R ,Color Palette 3_117 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D4 10.--15. 1. " CP3_117G ,Color Palette 3_117 Green"
|
|
hexmask.long.byte 0x1D4 2.--7. 1. " CP3_117B ,Color Palette 3_117 Blue"
|
|
line.long 0x1D8 "CP3_118R,Color Palette 3 Register 118"
|
|
hexmask.long.byte 0x1D8 24.--31. 1. " CP3_118A ,Color Palette 3_118 Blend Ratio"
|
|
hexmask.long.byte 0x1D8 18.--23. 1. " CP3_118R ,Color Palette 3_118 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1D8 10.--15. 1. " CP3_118G ,Color Palette 3_118 Green"
|
|
hexmask.long.byte 0x1D8 2.--7. 1. " CP3_118B ,Color Palette 3_118 Blue"
|
|
line.long 0x1DC "CP3_119R,Color Palette 3 Register 119"
|
|
hexmask.long.byte 0x1DC 24.--31. 1. " CP3_119A ,Color Palette 3_119 Blend Ratio"
|
|
hexmask.long.byte 0x1DC 18.--23. 1. " CP3_119R ,Color Palette 3_119 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1DC 10.--15. 1. " CP3_119G ,Color Palette 3_119 Green"
|
|
hexmask.long.byte 0x1DC 2.--7. 1. " CP3_119B ,Color Palette 3_119 Blue"
|
|
line.long 0x1E0 "CP3_120R,Color Palette 3 Register 120"
|
|
hexmask.long.byte 0x1E0 24.--31. 1. " CP3_120A ,Color Palette 3_120 Blend Ratio"
|
|
hexmask.long.byte 0x1E0 18.--23. 1. " CP3_120R ,Color Palette 3_120 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E0 10.--15. 1. " CP3_120G ,Color Palette 3_120 Green"
|
|
hexmask.long.byte 0x1E0 2.--7. 1. " CP3_120B ,Color Palette 3_120 Blue"
|
|
line.long 0x1E4 "CP3_121R,Color Palette 3 Register 121"
|
|
hexmask.long.byte 0x1E4 24.--31. 1. " CP3_121A ,Color Palette 3_121 Blend Ratio"
|
|
hexmask.long.byte 0x1E4 18.--23. 1. " CP3_121R ,Color Palette 3_121 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E4 10.--15. 1. " CP3_121G ,Color Palette 3_121 Green"
|
|
hexmask.long.byte 0x1E4 2.--7. 1. " CP3_121B ,Color Palette 3_121 Blue"
|
|
line.long 0x1E8 "CP3_122R,Color Palette 3 Register 122"
|
|
hexmask.long.byte 0x1E8 24.--31. 1. " CP3_122A ,Color Palette 3_122 Blend Ratio"
|
|
hexmask.long.byte 0x1E8 18.--23. 1. " CP3_122R ,Color Palette 3_122 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1E8 10.--15. 1. " CP3_122G ,Color Palette 3_122 Green"
|
|
hexmask.long.byte 0x1E8 2.--7. 1. " CP3_122B ,Color Palette 3_122 Blue"
|
|
line.long 0x1EC "CP3_123R,Color Palette 3 Register 123"
|
|
hexmask.long.byte 0x1EC 24.--31. 1. " CP3_123A ,Color Palette 3_123 Blend Ratio"
|
|
hexmask.long.byte 0x1EC 18.--23. 1. " CP3_123R ,Color Palette 3_123 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1EC 10.--15. 1. " CP3_123G ,Color Palette 3_123 Green"
|
|
hexmask.long.byte 0x1EC 2.--7. 1. " CP3_123B ,Color Palette 3_123 Blue"
|
|
line.long 0x1F0 "CP3_124R,Color Palette 3 Register 124"
|
|
hexmask.long.byte 0x1F0 24.--31. 1. " CP3_124A ,Color Palette 3_124 Blend Ratio"
|
|
hexmask.long.byte 0x1F0 18.--23. 1. " CP3_124R ,Color Palette 3_124 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F0 10.--15. 1. " CP3_124G ,Color Palette 3_124 Green"
|
|
hexmask.long.byte 0x1F0 2.--7. 1. " CP3_124B ,Color Palette 3_124 Blue"
|
|
line.long 0x1F4 "CP3_125R,Color Palette 3 Register 125"
|
|
hexmask.long.byte 0x1F4 24.--31. 1. " CP3_125A ,Color Palette 3_125 Blend Ratio"
|
|
hexmask.long.byte 0x1F4 18.--23. 1. " CP3_125R ,Color Palette 3_125 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F4 10.--15. 1. " CP3_125G ,Color Palette 3_125 Green"
|
|
hexmask.long.byte 0x1F4 2.--7. 1. " CP3_125B ,Color Palette 3_125 Blue"
|
|
line.long 0x1F8 "CP3_126R,Color Palette 3 Register 126"
|
|
hexmask.long.byte 0x1F8 24.--31. 1. " CP3_126A ,Color Palette 3_126 Blend Ratio"
|
|
hexmask.long.byte 0x1F8 18.--23. 1. " CP3_126R ,Color Palette 3_126 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1F8 10.--15. 1. " CP3_126G ,Color Palette 3_126 Green"
|
|
hexmask.long.byte 0x1F8 2.--7. 1. " CP3_126B ,Color Palette 3_126 Blue"
|
|
line.long 0x1FC "CP3_127R,Color Palette 3 Register 127"
|
|
hexmask.long.byte 0x1FC 24.--31. 1. " CP3_127A ,Color Palette 3_127 Blend Ratio"
|
|
hexmask.long.byte 0x1FC 18.--23. 1. " CP3_127R ,Color Palette 3_127 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x1FC 10.--15. 1. " CP3_127G ,Color Palette 3_127 Green"
|
|
hexmask.long.byte 0x1FC 2.--7. 1. " CP3_127B ,Color Palette 3_127 Blue"
|
|
line.long 0x200 "CP3_128R,Color Palette 3 Register 128"
|
|
hexmask.long.byte 0x200 24.--31. 1. " CP3_128A ,Color Palette 3_128 Blend Ratio"
|
|
hexmask.long.byte 0x200 18.--23. 1. " CP3_128R ,Color Palette 3_128 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x200 10.--15. 1. " CP3_128G ,Color Palette 3_128 Green"
|
|
hexmask.long.byte 0x200 2.--7. 1. " CP3_128B ,Color Palette 3_128 Blue"
|
|
line.long 0x204 "CP3_129R,Color Palette 3 Register 129"
|
|
hexmask.long.byte 0x204 24.--31. 1. " CP3_129A ,Color Palette 3_129 Blend Ratio"
|
|
hexmask.long.byte 0x204 18.--23. 1. " CP3_129R ,Color Palette 3_129 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x204 10.--15. 1. " CP3_129G ,Color Palette 3_129 Green"
|
|
hexmask.long.byte 0x204 2.--7. 1. " CP3_129B ,Color Palette 3_129 Blue"
|
|
line.long 0x208 "CP3_130R,Color Palette 3 Register 130"
|
|
hexmask.long.byte 0x208 24.--31. 1. " CP3_130A ,Color Palette 3_130 Blend Ratio"
|
|
hexmask.long.byte 0x208 18.--23. 1. " CP3_130R ,Color Palette 3_130 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x208 10.--15. 1. " CP3_130G ,Color Palette 3_130 Green"
|
|
hexmask.long.byte 0x208 2.--7. 1. " CP3_130B ,Color Palette 3_130 Blue"
|
|
line.long 0x20C "CP3_131R,Color Palette 3 Register 131"
|
|
hexmask.long.byte 0x20C 24.--31. 1. " CP3_131A ,Color Palette 3_131 Blend Ratio"
|
|
hexmask.long.byte 0x20C 18.--23. 1. " CP3_131R ,Color Palette 3_131 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x20C 10.--15. 1. " CP3_131G ,Color Palette 3_131 Green"
|
|
hexmask.long.byte 0x20C 2.--7. 1. " CP3_131B ,Color Palette 3_131 Blue"
|
|
line.long 0x210 "CP3_132R,Color Palette 3 Register 132"
|
|
hexmask.long.byte 0x210 24.--31. 1. " CP3_132A ,Color Palette 3_132 Blend Ratio"
|
|
hexmask.long.byte 0x210 18.--23. 1. " CP3_132R ,Color Palette 3_132 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x210 10.--15. 1. " CP3_132G ,Color Palette 3_132 Green"
|
|
hexmask.long.byte 0x210 2.--7. 1. " CP3_132B ,Color Palette 3_132 Blue"
|
|
line.long 0x214 "CP3_133R,Color Palette 3 Register 133"
|
|
hexmask.long.byte 0x214 24.--31. 1. " CP3_133A ,Color Palette 3_133 Blend Ratio"
|
|
hexmask.long.byte 0x214 18.--23. 1. " CP3_133R ,Color Palette 3_133 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x214 10.--15. 1. " CP3_133G ,Color Palette 3_133 Green"
|
|
hexmask.long.byte 0x214 2.--7. 1. " CP3_133B ,Color Palette 3_133 Blue"
|
|
line.long 0x218 "CP3_134R,Color Palette 3 Register 134"
|
|
hexmask.long.byte 0x218 24.--31. 1. " CP3_134A ,Color Palette 3_134 Blend Ratio"
|
|
hexmask.long.byte 0x218 18.--23. 1. " CP3_134R ,Color Palette 3_134 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x218 10.--15. 1. " CP3_134G ,Color Palette 3_134 Green"
|
|
hexmask.long.byte 0x218 2.--7. 1. " CP3_134B ,Color Palette 3_134 Blue"
|
|
line.long 0x21C "CP3_135R,Color Palette 3 Register 135"
|
|
hexmask.long.byte 0x21C 24.--31. 1. " CP3_135A ,Color Palette 3_135 Blend Ratio"
|
|
hexmask.long.byte 0x21C 18.--23. 1. " CP3_135R ,Color Palette 3_135 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x21C 10.--15. 1. " CP3_135G ,Color Palette 3_135 Green"
|
|
hexmask.long.byte 0x21C 2.--7. 1. " CP3_135B ,Color Palette 3_135 Blue"
|
|
line.long 0x220 "CP3_136R,Color Palette 3 Register 136"
|
|
hexmask.long.byte 0x220 24.--31. 1. " CP3_136A ,Color Palette 3_136 Blend Ratio"
|
|
hexmask.long.byte 0x220 18.--23. 1. " CP3_136R ,Color Palette 3_136 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x220 10.--15. 1. " CP3_136G ,Color Palette 3_136 Green"
|
|
hexmask.long.byte 0x220 2.--7. 1. " CP3_136B ,Color Palette 3_136 Blue"
|
|
line.long 0x224 "CP3_137R,Color Palette 3 Register 137"
|
|
hexmask.long.byte 0x224 24.--31. 1. " CP3_137A ,Color Palette 3_137 Blend Ratio"
|
|
hexmask.long.byte 0x224 18.--23. 1. " CP3_137R ,Color Palette 3_137 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x224 10.--15. 1. " CP3_137G ,Color Palette 3_137 Green"
|
|
hexmask.long.byte 0x224 2.--7. 1. " CP3_137B ,Color Palette 3_137 Blue"
|
|
line.long 0x228 "CP3_138R,Color Palette 3 Register 138"
|
|
hexmask.long.byte 0x228 24.--31. 1. " CP3_138A ,Color Palette 3_138 Blend Ratio"
|
|
hexmask.long.byte 0x228 18.--23. 1. " CP3_138R ,Color Palette 3_138 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x228 10.--15. 1. " CP3_138G ,Color Palette 3_138 Green"
|
|
hexmask.long.byte 0x228 2.--7. 1. " CP3_138B ,Color Palette 3_138 Blue"
|
|
line.long 0x22C "CP3_139R,Color Palette 3 Register 139"
|
|
hexmask.long.byte 0x22C 24.--31. 1. " CP3_139A ,Color Palette 3_139 Blend Ratio"
|
|
hexmask.long.byte 0x22C 18.--23. 1. " CP3_139R ,Color Palette 3_139 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x22C 10.--15. 1. " CP3_139G ,Color Palette 3_139 Green"
|
|
hexmask.long.byte 0x22C 2.--7. 1. " CP3_139B ,Color Palette 3_139 Blue"
|
|
line.long 0x230 "CP3_140R,Color Palette 3 Register 140"
|
|
hexmask.long.byte 0x230 24.--31. 1. " CP3_140A ,Color Palette 3_140 Blend Ratio"
|
|
hexmask.long.byte 0x230 18.--23. 1. " CP3_140R ,Color Palette 3_140 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x230 10.--15. 1. " CP3_140G ,Color Palette 3_140 Green"
|
|
hexmask.long.byte 0x230 2.--7. 1. " CP3_140B ,Color Palette 3_140 Blue"
|
|
line.long 0x234 "CP3_141R,Color Palette 3 Register 141"
|
|
hexmask.long.byte 0x234 24.--31. 1. " CP3_141A ,Color Palette 3_141 Blend Ratio"
|
|
hexmask.long.byte 0x234 18.--23. 1. " CP3_141R ,Color Palette 3_141 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x234 10.--15. 1. " CP3_141G ,Color Palette 3_141 Green"
|
|
hexmask.long.byte 0x234 2.--7. 1. " CP3_141B ,Color Palette 3_141 Blue"
|
|
line.long 0x238 "CP3_142R,Color Palette 3 Register 142"
|
|
hexmask.long.byte 0x238 24.--31. 1. " CP3_142A ,Color Palette 3_142 Blend Ratio"
|
|
hexmask.long.byte 0x238 18.--23. 1. " CP3_142R ,Color Palette 3_142 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x238 10.--15. 1. " CP3_142G ,Color Palette 3_142 Green"
|
|
hexmask.long.byte 0x238 2.--7. 1. " CP3_142B ,Color Palette 3_142 Blue"
|
|
line.long 0x23C "CP3_143R,Color Palette 3 Register 143"
|
|
hexmask.long.byte 0x23C 24.--31. 1. " CP3_143A ,Color Palette 3_143 Blend Ratio"
|
|
hexmask.long.byte 0x23C 18.--23. 1. " CP3_143R ,Color Palette 3_143 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x23C 10.--15. 1. " CP3_143G ,Color Palette 3_143 Green"
|
|
hexmask.long.byte 0x23C 2.--7. 1. " CP3_143B ,Color Palette 3_143 Blue"
|
|
line.long 0x240 "CP3_144R,Color Palette 3 Register 144"
|
|
hexmask.long.byte 0x240 24.--31. 1. " CP3_144A ,Color Palette 3_144 Blend Ratio"
|
|
hexmask.long.byte 0x240 18.--23. 1. " CP3_144R ,Color Palette 3_144 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x240 10.--15. 1. " CP3_144G ,Color Palette 3_144 Green"
|
|
hexmask.long.byte 0x240 2.--7. 1. " CP3_144B ,Color Palette 3_144 Blue"
|
|
line.long 0x244 "CP3_145R,Color Palette 3 Register 145"
|
|
hexmask.long.byte 0x244 24.--31. 1. " CP3_145A ,Color Palette 3_145 Blend Ratio"
|
|
hexmask.long.byte 0x244 18.--23. 1. " CP3_145R ,Color Palette 3_145 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x244 10.--15. 1. " CP3_145G ,Color Palette 3_145 Green"
|
|
hexmask.long.byte 0x244 2.--7. 1. " CP3_145B ,Color Palette 3_145 Blue"
|
|
line.long 0x248 "CP3_146R,Color Palette 3 Register 146"
|
|
hexmask.long.byte 0x248 24.--31. 1. " CP3_146A ,Color Palette 3_146 Blend Ratio"
|
|
hexmask.long.byte 0x248 18.--23. 1. " CP3_146R ,Color Palette 3_146 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x248 10.--15. 1. " CP3_146G ,Color Palette 3_146 Green"
|
|
hexmask.long.byte 0x248 2.--7. 1. " CP3_146B ,Color Palette 3_146 Blue"
|
|
line.long 0x24C "CP3_147R,Color Palette 3 Register 147"
|
|
hexmask.long.byte 0x24C 24.--31. 1. " CP3_147A ,Color Palette 3_147 Blend Ratio"
|
|
hexmask.long.byte 0x24C 18.--23. 1. " CP3_147R ,Color Palette 3_147 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x24C 10.--15. 1. " CP3_147G ,Color Palette 3_147 Green"
|
|
hexmask.long.byte 0x24C 2.--7. 1. " CP3_147B ,Color Palette 3_147 Blue"
|
|
line.long 0x250 "CP3_148R,Color Palette 3 Register 148"
|
|
hexmask.long.byte 0x250 24.--31. 1. " CP3_148A ,Color Palette 3_148 Blend Ratio"
|
|
hexmask.long.byte 0x250 18.--23. 1. " CP3_148R ,Color Palette 3_148 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x250 10.--15. 1. " CP3_148G ,Color Palette 3_148 Green"
|
|
hexmask.long.byte 0x250 2.--7. 1. " CP3_148B ,Color Palette 3_148 Blue"
|
|
line.long 0x254 "CP3_149R,Color Palette 3 Register 149"
|
|
hexmask.long.byte 0x254 24.--31. 1. " CP3_149A ,Color Palette 3_149 Blend Ratio"
|
|
hexmask.long.byte 0x254 18.--23. 1. " CP3_149R ,Color Palette 3_149 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x254 10.--15. 1. " CP3_149G ,Color Palette 3_149 Green"
|
|
hexmask.long.byte 0x254 2.--7. 1. " CP3_149B ,Color Palette 3_149 Blue"
|
|
line.long 0x258 "CP3_150R,Color Palette 3 Register 150"
|
|
hexmask.long.byte 0x258 24.--31. 1. " CP3_150A ,Color Palette 3_150 Blend Ratio"
|
|
hexmask.long.byte 0x258 18.--23. 1. " CP3_150R ,Color Palette 3_150 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x258 10.--15. 1. " CP3_150G ,Color Palette 3_150 Green"
|
|
hexmask.long.byte 0x258 2.--7. 1. " CP3_150B ,Color Palette 3_150 Blue"
|
|
line.long 0x25C "CP3_151R,Color Palette 3 Register 151"
|
|
hexmask.long.byte 0x25C 24.--31. 1. " CP3_151A ,Color Palette 3_151 Blend Ratio"
|
|
hexmask.long.byte 0x25C 18.--23. 1. " CP3_151R ,Color Palette 3_151 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x25C 10.--15. 1. " CP3_151G ,Color Palette 3_151 Green"
|
|
hexmask.long.byte 0x25C 2.--7. 1. " CP3_151B ,Color Palette 3_151 Blue"
|
|
line.long 0x260 "CP3_152R,Color Palette 3 Register 152"
|
|
hexmask.long.byte 0x260 24.--31. 1. " CP3_152A ,Color Palette 3_152 Blend Ratio"
|
|
hexmask.long.byte 0x260 18.--23. 1. " CP3_152R ,Color Palette 3_152 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x260 10.--15. 1. " CP3_152G ,Color Palette 3_152 Green"
|
|
hexmask.long.byte 0x260 2.--7. 1. " CP3_152B ,Color Palette 3_152 Blue"
|
|
line.long 0x264 "CP3_153R,Color Palette 3 Register 153"
|
|
hexmask.long.byte 0x264 24.--31. 1. " CP3_153A ,Color Palette 3_153 Blend Ratio"
|
|
hexmask.long.byte 0x264 18.--23. 1. " CP3_153R ,Color Palette 3_153 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x264 10.--15. 1. " CP3_153G ,Color Palette 3_153 Green"
|
|
hexmask.long.byte 0x264 2.--7. 1. " CP3_153B ,Color Palette 3_153 Blue"
|
|
line.long 0x268 "CP3_154R,Color Palette 3 Register 154"
|
|
hexmask.long.byte 0x268 24.--31. 1. " CP3_154A ,Color Palette 3_154 Blend Ratio"
|
|
hexmask.long.byte 0x268 18.--23. 1. " CP3_154R ,Color Palette 3_154 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x268 10.--15. 1. " CP3_154G ,Color Palette 3_154 Green"
|
|
hexmask.long.byte 0x268 2.--7. 1. " CP3_154B ,Color Palette 3_154 Blue"
|
|
line.long 0x26C "CP3_155R,Color Palette 3 Register 155"
|
|
hexmask.long.byte 0x26C 24.--31. 1. " CP3_155A ,Color Palette 3_155 Blend Ratio"
|
|
hexmask.long.byte 0x26C 18.--23. 1. " CP3_155R ,Color Palette 3_155 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x26C 10.--15. 1. " CP3_155G ,Color Palette 3_155 Green"
|
|
hexmask.long.byte 0x26C 2.--7. 1. " CP3_155B ,Color Palette 3_155 Blue"
|
|
line.long 0x270 "CP3_156R,Color Palette 3 Register 156"
|
|
hexmask.long.byte 0x270 24.--31. 1. " CP3_156A ,Color Palette 3_156 Blend Ratio"
|
|
hexmask.long.byte 0x270 18.--23. 1. " CP3_156R ,Color Palette 3_156 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x270 10.--15. 1. " CP3_156G ,Color Palette 3_156 Green"
|
|
hexmask.long.byte 0x270 2.--7. 1. " CP3_156B ,Color Palette 3_156 Blue"
|
|
line.long 0x274 "CP3_157R,Color Palette 3 Register 157"
|
|
hexmask.long.byte 0x274 24.--31. 1. " CP3_157A ,Color Palette 3_157 Blend Ratio"
|
|
hexmask.long.byte 0x274 18.--23. 1. " CP3_157R ,Color Palette 3_157 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x274 10.--15. 1. " CP3_157G ,Color Palette 3_157 Green"
|
|
hexmask.long.byte 0x274 2.--7. 1. " CP3_157B ,Color Palette 3_157 Blue"
|
|
line.long 0x278 "CP3_158R,Color Palette 3 Register 158"
|
|
hexmask.long.byte 0x278 24.--31. 1. " CP3_158A ,Color Palette 3_158 Blend Ratio"
|
|
hexmask.long.byte 0x278 18.--23. 1. " CP3_158R ,Color Palette 3_158 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x278 10.--15. 1. " CP3_158G ,Color Palette 3_158 Green"
|
|
hexmask.long.byte 0x278 2.--7. 1. " CP3_158B ,Color Palette 3_158 Blue"
|
|
line.long 0x27C "CP3_159R,Color Palette 3 Register 159"
|
|
hexmask.long.byte 0x27C 24.--31. 1. " CP3_159A ,Color Palette 3_159 Blend Ratio"
|
|
hexmask.long.byte 0x27C 18.--23. 1. " CP3_159R ,Color Palette 3_159 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x27C 10.--15. 1. " CP3_159G ,Color Palette 3_159 Green"
|
|
hexmask.long.byte 0x27C 2.--7. 1. " CP3_159B ,Color Palette 3_159 Blue"
|
|
line.long 0x280 "CP3_160R,Color Palette 3 Register 160"
|
|
hexmask.long.byte 0x280 24.--31. 1. " CP3_160A ,Color Palette 3_160 Blend Ratio"
|
|
hexmask.long.byte 0x280 18.--23. 1. " CP3_160R ,Color Palette 3_160 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x280 10.--15. 1. " CP3_160G ,Color Palette 3_160 Green"
|
|
hexmask.long.byte 0x280 2.--7. 1. " CP3_160B ,Color Palette 3_160 Blue"
|
|
line.long 0x284 "CP3_161R,Color Palette 3 Register 161"
|
|
hexmask.long.byte 0x284 24.--31. 1. " CP3_161A ,Color Palette 3_161 Blend Ratio"
|
|
hexmask.long.byte 0x284 18.--23. 1. " CP3_161R ,Color Palette 3_161 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x284 10.--15. 1. " CP3_161G ,Color Palette 3_161 Green"
|
|
hexmask.long.byte 0x284 2.--7. 1. " CP3_161B ,Color Palette 3_161 Blue"
|
|
line.long 0x288 "CP3_162R,Color Palette 3 Register 162"
|
|
hexmask.long.byte 0x288 24.--31. 1. " CP3_162A ,Color Palette 3_162 Blend Ratio"
|
|
hexmask.long.byte 0x288 18.--23. 1. " CP3_162R ,Color Palette 3_162 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x288 10.--15. 1. " CP3_162G ,Color Palette 3_162 Green"
|
|
hexmask.long.byte 0x288 2.--7. 1. " CP3_162B ,Color Palette 3_162 Blue"
|
|
line.long 0x28C "CP3_163R,Color Palette 3 Register 163"
|
|
hexmask.long.byte 0x28C 24.--31. 1. " CP3_163A ,Color Palette 3_163 Blend Ratio"
|
|
hexmask.long.byte 0x28C 18.--23. 1. " CP3_163R ,Color Palette 3_163 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x28C 10.--15. 1. " CP3_163G ,Color Palette 3_163 Green"
|
|
hexmask.long.byte 0x28C 2.--7. 1. " CP3_163B ,Color Palette 3_163 Blue"
|
|
line.long 0x290 "CP3_164R,Color Palette 3 Register 164"
|
|
hexmask.long.byte 0x290 24.--31. 1. " CP3_164A ,Color Palette 3_164 Blend Ratio"
|
|
hexmask.long.byte 0x290 18.--23. 1. " CP3_164R ,Color Palette 3_164 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x290 10.--15. 1. " CP3_164G ,Color Palette 3_164 Green"
|
|
hexmask.long.byte 0x290 2.--7. 1. " CP3_164B ,Color Palette 3_164 Blue"
|
|
line.long 0x294 "CP3_165R,Color Palette 3 Register 165"
|
|
hexmask.long.byte 0x294 24.--31. 1. " CP3_165A ,Color Palette 3_165 Blend Ratio"
|
|
hexmask.long.byte 0x294 18.--23. 1. " CP3_165R ,Color Palette 3_165 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x294 10.--15. 1. " CP3_165G ,Color Palette 3_165 Green"
|
|
hexmask.long.byte 0x294 2.--7. 1. " CP3_165B ,Color Palette 3_165 Blue"
|
|
line.long 0x298 "CP3_166R,Color Palette 3 Register 166"
|
|
hexmask.long.byte 0x298 24.--31. 1. " CP3_166A ,Color Palette 3_166 Blend Ratio"
|
|
hexmask.long.byte 0x298 18.--23. 1. " CP3_166R ,Color Palette 3_166 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x298 10.--15. 1. " CP3_166G ,Color Palette 3_166 Green"
|
|
hexmask.long.byte 0x298 2.--7. 1. " CP3_166B ,Color Palette 3_166 Blue"
|
|
line.long 0x29C "CP3_167R,Color Palette 3 Register 167"
|
|
hexmask.long.byte 0x29C 24.--31. 1. " CP3_167A ,Color Palette 3_167 Blend Ratio"
|
|
hexmask.long.byte 0x29C 18.--23. 1. " CP3_167R ,Color Palette 3_167 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x29C 10.--15. 1. " CP3_167G ,Color Palette 3_167 Green"
|
|
hexmask.long.byte 0x29C 2.--7. 1. " CP3_167B ,Color Palette 3_167 Blue"
|
|
line.long 0x2A0 "CP3_168R,Color Palette 3 Register 168"
|
|
hexmask.long.byte 0x2A0 24.--31. 1. " CP3_168A ,Color Palette 3_168 Blend Ratio"
|
|
hexmask.long.byte 0x2A0 18.--23. 1. " CP3_168R ,Color Palette 3_168 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A0 10.--15. 1. " CP3_168G ,Color Palette 3_168 Green"
|
|
hexmask.long.byte 0x2A0 2.--7. 1. " CP3_168B ,Color Palette 3_168 Blue"
|
|
line.long 0x2A4 "CP3_169R,Color Palette 3 Register 169"
|
|
hexmask.long.byte 0x2A4 24.--31. 1. " CP3_169A ,Color Palette 3_169 Blend Ratio"
|
|
hexmask.long.byte 0x2A4 18.--23. 1. " CP3_169R ,Color Palette 3_169 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A4 10.--15. 1. " CP3_169G ,Color Palette 3_169 Green"
|
|
hexmask.long.byte 0x2A4 2.--7. 1. " CP3_169B ,Color Palette 3_169 Blue"
|
|
line.long 0x2A8 "CP3_170R,Color Palette 3 Register 170"
|
|
hexmask.long.byte 0x2A8 24.--31. 1. " CP3_170A ,Color Palette 3_170 Blend Ratio"
|
|
hexmask.long.byte 0x2A8 18.--23. 1. " CP3_170R ,Color Palette 3_170 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2A8 10.--15. 1. " CP3_170G ,Color Palette 3_170 Green"
|
|
hexmask.long.byte 0x2A8 2.--7. 1. " CP3_170B ,Color Palette 3_170 Blue"
|
|
line.long 0x2AC "CP3_171R,Color Palette 3 Register 171"
|
|
hexmask.long.byte 0x2AC 24.--31. 1. " CP3_171A ,Color Palette 3_171 Blend Ratio"
|
|
hexmask.long.byte 0x2AC 18.--23. 1. " CP3_171R ,Color Palette 3_171 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2AC 10.--15. 1. " CP3_171G ,Color Palette 3_171 Green"
|
|
hexmask.long.byte 0x2AC 2.--7. 1. " CP3_171B ,Color Palette 3_171 Blue"
|
|
line.long 0x2B0 "CP3_172R,Color Palette 3 Register 172"
|
|
hexmask.long.byte 0x2B0 24.--31. 1. " CP3_172A ,Color Palette 3_172 Blend Ratio"
|
|
hexmask.long.byte 0x2B0 18.--23. 1. " CP3_172R ,Color Palette 3_172 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B0 10.--15. 1. " CP3_172G ,Color Palette 3_172 Green"
|
|
hexmask.long.byte 0x2B0 2.--7. 1. " CP3_172B ,Color Palette 3_172 Blue"
|
|
line.long 0x2B4 "CP3_173R,Color Palette 3 Register 173"
|
|
hexmask.long.byte 0x2B4 24.--31. 1. " CP3_173A ,Color Palette 3_173 Blend Ratio"
|
|
hexmask.long.byte 0x2B4 18.--23. 1. " CP3_173R ,Color Palette 3_173 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B4 10.--15. 1. " CP3_173G ,Color Palette 3_173 Green"
|
|
hexmask.long.byte 0x2B4 2.--7. 1. " CP3_173B ,Color Palette 3_173 Blue"
|
|
line.long 0x2B8 "CP3_174R,Color Palette 3 Register 174"
|
|
hexmask.long.byte 0x2B8 24.--31. 1. " CP3_174A ,Color Palette 3_174 Blend Ratio"
|
|
hexmask.long.byte 0x2B8 18.--23. 1. " CP3_174R ,Color Palette 3_174 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2B8 10.--15. 1. " CP3_174G ,Color Palette 3_174 Green"
|
|
hexmask.long.byte 0x2B8 2.--7. 1. " CP3_174B ,Color Palette 3_174 Blue"
|
|
line.long 0x2BC "CP3_175R,Color Palette 3 Register 175"
|
|
hexmask.long.byte 0x2BC 24.--31. 1. " CP3_175A ,Color Palette 3_175 Blend Ratio"
|
|
hexmask.long.byte 0x2BC 18.--23. 1. " CP3_175R ,Color Palette 3_175 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2BC 10.--15. 1. " CP3_175G ,Color Palette 3_175 Green"
|
|
hexmask.long.byte 0x2BC 2.--7. 1. " CP3_175B ,Color Palette 3_175 Blue"
|
|
line.long 0x2C0 "CP3_176R,Color Palette 3 Register 176"
|
|
hexmask.long.byte 0x2C0 24.--31. 1. " CP3_176A ,Color Palette 3_176 Blend Ratio"
|
|
hexmask.long.byte 0x2C0 18.--23. 1. " CP3_176R ,Color Palette 3_176 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C0 10.--15. 1. " CP3_176G ,Color Palette 3_176 Green"
|
|
hexmask.long.byte 0x2C0 2.--7. 1. " CP3_176B ,Color Palette 3_176 Blue"
|
|
line.long 0x2C4 "CP3_177R,Color Palette 3 Register 177"
|
|
hexmask.long.byte 0x2C4 24.--31. 1. " CP3_177A ,Color Palette 3_177 Blend Ratio"
|
|
hexmask.long.byte 0x2C4 18.--23. 1. " CP3_177R ,Color Palette 3_177 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C4 10.--15. 1. " CP3_177G ,Color Palette 3_177 Green"
|
|
hexmask.long.byte 0x2C4 2.--7. 1. " CP3_177B ,Color Palette 3_177 Blue"
|
|
line.long 0x2C8 "CP3_178R,Color Palette 3 Register 178"
|
|
hexmask.long.byte 0x2C8 24.--31. 1. " CP3_178A ,Color Palette 3_178 Blend Ratio"
|
|
hexmask.long.byte 0x2C8 18.--23. 1. " CP3_178R ,Color Palette 3_178 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2C8 10.--15. 1. " CP3_178G ,Color Palette 3_178 Green"
|
|
hexmask.long.byte 0x2C8 2.--7. 1. " CP3_178B ,Color Palette 3_178 Blue"
|
|
line.long 0x2CC "CP3_179R,Color Palette 3 Register 179"
|
|
hexmask.long.byte 0x2CC 24.--31. 1. " CP3_179A ,Color Palette 3_179 Blend Ratio"
|
|
hexmask.long.byte 0x2CC 18.--23. 1. " CP3_179R ,Color Palette 3_179 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2CC 10.--15. 1. " CP3_179G ,Color Palette 3_179 Green"
|
|
hexmask.long.byte 0x2CC 2.--7. 1. " CP3_179B ,Color Palette 3_179 Blue"
|
|
line.long 0x2D0 "CP3_180R,Color Palette 3 Register 180"
|
|
hexmask.long.byte 0x2D0 24.--31. 1. " CP3_180A ,Color Palette 3_180 Blend Ratio"
|
|
hexmask.long.byte 0x2D0 18.--23. 1. " CP3_180R ,Color Palette 3_180 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D0 10.--15. 1. " CP3_180G ,Color Palette 3_180 Green"
|
|
hexmask.long.byte 0x2D0 2.--7. 1. " CP3_180B ,Color Palette 3_180 Blue"
|
|
line.long 0x2D4 "CP3_181R,Color Palette 3 Register 181"
|
|
hexmask.long.byte 0x2D4 24.--31. 1. " CP3_181A ,Color Palette 3_181 Blend Ratio"
|
|
hexmask.long.byte 0x2D4 18.--23. 1. " CP3_181R ,Color Palette 3_181 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D4 10.--15. 1. " CP3_181G ,Color Palette 3_181 Green"
|
|
hexmask.long.byte 0x2D4 2.--7. 1. " CP3_181B ,Color Palette 3_181 Blue"
|
|
line.long 0x2D8 "CP3_182R,Color Palette 3 Register 182"
|
|
hexmask.long.byte 0x2D8 24.--31. 1. " CP3_182A ,Color Palette 3_182 Blend Ratio"
|
|
hexmask.long.byte 0x2D8 18.--23. 1. " CP3_182R ,Color Palette 3_182 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2D8 10.--15. 1. " CP3_182G ,Color Palette 3_182 Green"
|
|
hexmask.long.byte 0x2D8 2.--7. 1. " CP3_182B ,Color Palette 3_182 Blue"
|
|
line.long 0x2DC "CP3_183R,Color Palette 3 Register 183"
|
|
hexmask.long.byte 0x2DC 24.--31. 1. " CP3_183A ,Color Palette 3_183 Blend Ratio"
|
|
hexmask.long.byte 0x2DC 18.--23. 1. " CP3_183R ,Color Palette 3_183 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2DC 10.--15. 1. " CP3_183G ,Color Palette 3_183 Green"
|
|
hexmask.long.byte 0x2DC 2.--7. 1. " CP3_183B ,Color Palette 3_183 Blue"
|
|
line.long 0x2E0 "CP3_184R,Color Palette 3 Register 184"
|
|
hexmask.long.byte 0x2E0 24.--31. 1. " CP3_184A ,Color Palette 3_184 Blend Ratio"
|
|
hexmask.long.byte 0x2E0 18.--23. 1. " CP3_184R ,Color Palette 3_184 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E0 10.--15. 1. " CP3_184G ,Color Palette 3_184 Green"
|
|
hexmask.long.byte 0x2E0 2.--7. 1. " CP3_184B ,Color Palette 3_184 Blue"
|
|
line.long 0x2E4 "CP3_185R,Color Palette 3 Register 185"
|
|
hexmask.long.byte 0x2E4 24.--31. 1. " CP3_185A ,Color Palette 3_185 Blend Ratio"
|
|
hexmask.long.byte 0x2E4 18.--23. 1. " CP3_185R ,Color Palette 3_185 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E4 10.--15. 1. " CP3_185G ,Color Palette 3_185 Green"
|
|
hexmask.long.byte 0x2E4 2.--7. 1. " CP3_185B ,Color Palette 3_185 Blue"
|
|
line.long 0x2E8 "CP3_186R,Color Palette 3 Register 186"
|
|
hexmask.long.byte 0x2E8 24.--31. 1. " CP3_186A ,Color Palette 3_186 Blend Ratio"
|
|
hexmask.long.byte 0x2E8 18.--23. 1. " CP3_186R ,Color Palette 3_186 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2E8 10.--15. 1. " CP3_186G ,Color Palette 3_186 Green"
|
|
hexmask.long.byte 0x2E8 2.--7. 1. " CP3_186B ,Color Palette 3_186 Blue"
|
|
line.long 0x2EC "CP3_187R,Color Palette 3 Register 187"
|
|
hexmask.long.byte 0x2EC 24.--31. 1. " CP3_187A ,Color Palette 3_187 Blend Ratio"
|
|
hexmask.long.byte 0x2EC 18.--23. 1. " CP3_187R ,Color Palette 3_187 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2EC 10.--15. 1. " CP3_187G ,Color Palette 3_187 Green"
|
|
hexmask.long.byte 0x2EC 2.--7. 1. " CP3_187B ,Color Palette 3_187 Blue"
|
|
line.long 0x2F0 "CP3_188R,Color Palette 3 Register 188"
|
|
hexmask.long.byte 0x2F0 24.--31. 1. " CP3_188A ,Color Palette 3_188 Blend Ratio"
|
|
hexmask.long.byte 0x2F0 18.--23. 1. " CP3_188R ,Color Palette 3_188 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F0 10.--15. 1. " CP3_188G ,Color Palette 3_188 Green"
|
|
hexmask.long.byte 0x2F0 2.--7. 1. " CP3_188B ,Color Palette 3_188 Blue"
|
|
line.long 0x2F4 "CP3_189R,Color Palette 3 Register 189"
|
|
hexmask.long.byte 0x2F4 24.--31. 1. " CP3_189A ,Color Palette 3_189 Blend Ratio"
|
|
hexmask.long.byte 0x2F4 18.--23. 1. " CP3_189R ,Color Palette 3_189 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F4 10.--15. 1. " CP3_189G ,Color Palette 3_189 Green"
|
|
hexmask.long.byte 0x2F4 2.--7. 1. " CP3_189B ,Color Palette 3_189 Blue"
|
|
line.long 0x2F8 "CP3_190R,Color Palette 3 Register 190"
|
|
hexmask.long.byte 0x2F8 24.--31. 1. " CP3_190A ,Color Palette 3_190 Blend Ratio"
|
|
hexmask.long.byte 0x2F8 18.--23. 1. " CP3_190R ,Color Palette 3_190 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2F8 10.--15. 1. " CP3_190G ,Color Palette 3_190 Green"
|
|
hexmask.long.byte 0x2F8 2.--7. 1. " CP3_190B ,Color Palette 3_190 Blue"
|
|
line.long 0x2FC "CP3_191R,Color Palette 3 Register 191"
|
|
hexmask.long.byte 0x2FC 24.--31. 1. " CP3_191A ,Color Palette 3_191 Blend Ratio"
|
|
hexmask.long.byte 0x2FC 18.--23. 1. " CP3_191R ,Color Palette 3_191 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x2FC 10.--15. 1. " CP3_191G ,Color Palette 3_191 Green"
|
|
hexmask.long.byte 0x2FC 2.--7. 1. " CP3_191B ,Color Palette 3_191 Blue"
|
|
line.long 0x300 "CP3_192R,Color Palette 3 Register 192"
|
|
hexmask.long.byte 0x300 24.--31. 1. " CP3_192A ,Color Palette 3_192 Blend Ratio"
|
|
hexmask.long.byte 0x300 18.--23. 1. " CP3_192R ,Color Palette 3_192 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x300 10.--15. 1. " CP3_192G ,Color Palette 3_192 Green"
|
|
hexmask.long.byte 0x300 2.--7. 1. " CP3_192B ,Color Palette 3_192 Blue"
|
|
line.long 0x304 "CP3_193R,Color Palette 3 Register 193"
|
|
hexmask.long.byte 0x304 24.--31. 1. " CP3_193A ,Color Palette 3_193 Blend Ratio"
|
|
hexmask.long.byte 0x304 18.--23. 1. " CP3_193R ,Color Palette 3_193 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x304 10.--15. 1. " CP3_193G ,Color Palette 3_193 Green"
|
|
hexmask.long.byte 0x304 2.--7. 1. " CP3_193B ,Color Palette 3_193 Blue"
|
|
line.long 0x308 "CP3_194R,Color Palette 3 Register 194"
|
|
hexmask.long.byte 0x308 24.--31. 1. " CP3_194A ,Color Palette 3_194 Blend Ratio"
|
|
hexmask.long.byte 0x308 18.--23. 1. " CP3_194R ,Color Palette 3_194 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x308 10.--15. 1. " CP3_194G ,Color Palette 3_194 Green"
|
|
hexmask.long.byte 0x308 2.--7. 1. " CP3_194B ,Color Palette 3_194 Blue"
|
|
line.long 0x30C "CP3_195R,Color Palette 3 Register 195"
|
|
hexmask.long.byte 0x30C 24.--31. 1. " CP3_195A ,Color Palette 3_195 Blend Ratio"
|
|
hexmask.long.byte 0x30C 18.--23. 1. " CP3_195R ,Color Palette 3_195 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x30C 10.--15. 1. " CP3_195G ,Color Palette 3_195 Green"
|
|
hexmask.long.byte 0x30C 2.--7. 1. " CP3_195B ,Color Palette 3_195 Blue"
|
|
line.long 0x310 "CP3_196R,Color Palette 3 Register 196"
|
|
hexmask.long.byte 0x310 24.--31. 1. " CP3_196A ,Color Palette 3_196 Blend Ratio"
|
|
hexmask.long.byte 0x310 18.--23. 1. " CP3_196R ,Color Palette 3_196 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x310 10.--15. 1. " CP3_196G ,Color Palette 3_196 Green"
|
|
hexmask.long.byte 0x310 2.--7. 1. " CP3_196B ,Color Palette 3_196 Blue"
|
|
line.long 0x314 "CP3_197R,Color Palette 3 Register 197"
|
|
hexmask.long.byte 0x314 24.--31. 1. " CP3_197A ,Color Palette 3_197 Blend Ratio"
|
|
hexmask.long.byte 0x314 18.--23. 1. " CP3_197R ,Color Palette 3_197 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x314 10.--15. 1. " CP3_197G ,Color Palette 3_197 Green"
|
|
hexmask.long.byte 0x314 2.--7. 1. " CP3_197B ,Color Palette 3_197 Blue"
|
|
line.long 0x318 "CP3_198R,Color Palette 3 Register 198"
|
|
hexmask.long.byte 0x318 24.--31. 1. " CP3_198A ,Color Palette 3_198 Blend Ratio"
|
|
hexmask.long.byte 0x318 18.--23. 1. " CP3_198R ,Color Palette 3_198 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x318 10.--15. 1. " CP3_198G ,Color Palette 3_198 Green"
|
|
hexmask.long.byte 0x318 2.--7. 1. " CP3_198B ,Color Palette 3_198 Blue"
|
|
line.long 0x31C "CP3_199R,Color Palette 3 Register 199"
|
|
hexmask.long.byte 0x31C 24.--31. 1. " CP3_199A ,Color Palette 3_199 Blend Ratio"
|
|
hexmask.long.byte 0x31C 18.--23. 1. " CP3_199R ,Color Palette 3_199 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x31C 10.--15. 1. " CP3_199G ,Color Palette 3_199 Green"
|
|
hexmask.long.byte 0x31C 2.--7. 1. " CP3_199B ,Color Palette 3_199 Blue"
|
|
line.long 0x320 "CP3_200R,Color Palette 3 Register 200"
|
|
hexmask.long.byte 0x320 24.--31. 1. " CP3_200A ,Color Palette 3_200 Blend Ratio"
|
|
hexmask.long.byte 0x320 18.--23. 1. " CP3_200R ,Color Palette 3_200 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x320 10.--15. 1. " CP3_200G ,Color Palette 3_200 Green"
|
|
hexmask.long.byte 0x320 2.--7. 1. " CP3_200B ,Color Palette 3_200 Blue"
|
|
line.long 0x324 "CP3_201R,Color Palette 3 Register 201"
|
|
hexmask.long.byte 0x324 24.--31. 1. " CP3_201A ,Color Palette 3_201 Blend Ratio"
|
|
hexmask.long.byte 0x324 18.--23. 1. " CP3_201R ,Color Palette 3_201 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x324 10.--15. 1. " CP3_201G ,Color Palette 3_201 Green"
|
|
hexmask.long.byte 0x324 2.--7. 1. " CP3_201B ,Color Palette 3_201 Blue"
|
|
line.long 0x328 "CP3_202R,Color Palette 3 Register 202"
|
|
hexmask.long.byte 0x328 24.--31. 1. " CP3_202A ,Color Palette 3_202 Blend Ratio"
|
|
hexmask.long.byte 0x328 18.--23. 1. " CP3_202R ,Color Palette 3_202 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x328 10.--15. 1. " CP3_202G ,Color Palette 3_202 Green"
|
|
hexmask.long.byte 0x328 2.--7. 1. " CP3_202B ,Color Palette 3_202 Blue"
|
|
line.long 0x32C "CP3_203R,Color Palette 3 Register 203"
|
|
hexmask.long.byte 0x32C 24.--31. 1. " CP3_203A ,Color Palette 3_203 Blend Ratio"
|
|
hexmask.long.byte 0x32C 18.--23. 1. " CP3_203R ,Color Palette 3_203 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x32C 10.--15. 1. " CP3_203G ,Color Palette 3_203 Green"
|
|
hexmask.long.byte 0x32C 2.--7. 1. " CP3_203B ,Color Palette 3_203 Blue"
|
|
line.long 0x330 "CP3_204R,Color Palette 3 Register 204"
|
|
hexmask.long.byte 0x330 24.--31. 1. " CP3_204A ,Color Palette 3_204 Blend Ratio"
|
|
hexmask.long.byte 0x330 18.--23. 1. " CP3_204R ,Color Palette 3_204 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x330 10.--15. 1. " CP3_204G ,Color Palette 3_204 Green"
|
|
hexmask.long.byte 0x330 2.--7. 1. " CP3_204B ,Color Palette 3_204 Blue"
|
|
line.long 0x334 "CP3_205R,Color Palette 3 Register 205"
|
|
hexmask.long.byte 0x334 24.--31. 1. " CP3_205A ,Color Palette 3_205 Blend Ratio"
|
|
hexmask.long.byte 0x334 18.--23. 1. " CP3_205R ,Color Palette 3_205 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x334 10.--15. 1. " CP3_205G ,Color Palette 3_205 Green"
|
|
hexmask.long.byte 0x334 2.--7. 1. " CP3_205B ,Color Palette 3_205 Blue"
|
|
line.long 0x338 "CP3_206R,Color Palette 3 Register 206"
|
|
hexmask.long.byte 0x338 24.--31. 1. " CP3_206A ,Color Palette 3_206 Blend Ratio"
|
|
hexmask.long.byte 0x338 18.--23. 1. " CP3_206R ,Color Palette 3_206 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x338 10.--15. 1. " CP3_206G ,Color Palette 3_206 Green"
|
|
hexmask.long.byte 0x338 2.--7. 1. " CP3_206B ,Color Palette 3_206 Blue"
|
|
line.long 0x33C "CP3_207R,Color Palette 3 Register 207"
|
|
hexmask.long.byte 0x33C 24.--31. 1. " CP3_207A ,Color Palette 3_207 Blend Ratio"
|
|
hexmask.long.byte 0x33C 18.--23. 1. " CP3_207R ,Color Palette 3_207 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x33C 10.--15. 1. " CP3_207G ,Color Palette 3_207 Green"
|
|
hexmask.long.byte 0x33C 2.--7. 1. " CP3_207B ,Color Palette 3_207 Blue"
|
|
line.long 0x340 "CP3_208R,Color Palette 3 Register 208"
|
|
hexmask.long.byte 0x340 24.--31. 1. " CP3_208A ,Color Palette 3_208 Blend Ratio"
|
|
hexmask.long.byte 0x340 18.--23. 1. " CP3_208R ,Color Palette 3_208 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x340 10.--15. 1. " CP3_208G ,Color Palette 3_208 Green"
|
|
hexmask.long.byte 0x340 2.--7. 1. " CP3_208B ,Color Palette 3_208 Blue"
|
|
line.long 0x344 "CP3_209R,Color Palette 3 Register 209"
|
|
hexmask.long.byte 0x344 24.--31. 1. " CP3_209A ,Color Palette 3_209 Blend Ratio"
|
|
hexmask.long.byte 0x344 18.--23. 1. " CP3_209R ,Color Palette 3_209 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x344 10.--15. 1. " CP3_209G ,Color Palette 3_209 Green"
|
|
hexmask.long.byte 0x344 2.--7. 1. " CP3_209B ,Color Palette 3_209 Blue"
|
|
line.long 0x348 "CP3_210R,Color Palette 3 Register 210"
|
|
hexmask.long.byte 0x348 24.--31. 1. " CP3_210A ,Color Palette 3_210 Blend Ratio"
|
|
hexmask.long.byte 0x348 18.--23. 1. " CP3_210R ,Color Palette 3_210 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x348 10.--15. 1. " CP3_210G ,Color Palette 3_210 Green"
|
|
hexmask.long.byte 0x348 2.--7. 1. " CP3_210B ,Color Palette 3_210 Blue"
|
|
line.long 0x34C "CP3_211R,Color Palette 3 Register 211"
|
|
hexmask.long.byte 0x34C 24.--31. 1. " CP3_211A ,Color Palette 3_211 Blend Ratio"
|
|
hexmask.long.byte 0x34C 18.--23. 1. " CP3_211R ,Color Palette 3_211 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x34C 10.--15. 1. " CP3_211G ,Color Palette 3_211 Green"
|
|
hexmask.long.byte 0x34C 2.--7. 1. " CP3_211B ,Color Palette 3_211 Blue"
|
|
line.long 0x350 "CP3_212R,Color Palette 3 Register 212"
|
|
hexmask.long.byte 0x350 24.--31. 1. " CP3_212A ,Color Palette 3_212 Blend Ratio"
|
|
hexmask.long.byte 0x350 18.--23. 1. " CP3_212R ,Color Palette 3_212 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x350 10.--15. 1. " CP3_212G ,Color Palette 3_212 Green"
|
|
hexmask.long.byte 0x350 2.--7. 1. " CP3_212B ,Color Palette 3_212 Blue"
|
|
line.long 0x354 "CP3_213R,Color Palette 3 Register 213"
|
|
hexmask.long.byte 0x354 24.--31. 1. " CP3_213A ,Color Palette 3_213 Blend Ratio"
|
|
hexmask.long.byte 0x354 18.--23. 1. " CP3_213R ,Color Palette 3_213 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x354 10.--15. 1. " CP3_213G ,Color Palette 3_213 Green"
|
|
hexmask.long.byte 0x354 2.--7. 1. " CP3_213B ,Color Palette 3_213 Blue"
|
|
line.long 0x358 "CP3_214R,Color Palette 3 Register 214"
|
|
hexmask.long.byte 0x358 24.--31. 1. " CP3_214A ,Color Palette 3_214 Blend Ratio"
|
|
hexmask.long.byte 0x358 18.--23. 1. " CP3_214R ,Color Palette 3_214 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x358 10.--15. 1. " CP3_214G ,Color Palette 3_214 Green"
|
|
hexmask.long.byte 0x358 2.--7. 1. " CP3_214B ,Color Palette 3_214 Blue"
|
|
line.long 0x35C "CP3_215R,Color Palette 3 Register 215"
|
|
hexmask.long.byte 0x35C 24.--31. 1. " CP3_215A ,Color Palette 3_215 Blend Ratio"
|
|
hexmask.long.byte 0x35C 18.--23. 1. " CP3_215R ,Color Palette 3_215 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x35C 10.--15. 1. " CP3_215G ,Color Palette 3_215 Green"
|
|
hexmask.long.byte 0x35C 2.--7. 1. " CP3_215B ,Color Palette 3_215 Blue"
|
|
line.long 0x360 "CP3_216R,Color Palette 3 Register 216"
|
|
hexmask.long.byte 0x360 24.--31. 1. " CP3_216A ,Color Palette 3_216 Blend Ratio"
|
|
hexmask.long.byte 0x360 18.--23. 1. " CP3_216R ,Color Palette 3_216 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x360 10.--15. 1. " CP3_216G ,Color Palette 3_216 Green"
|
|
hexmask.long.byte 0x360 2.--7. 1. " CP3_216B ,Color Palette 3_216 Blue"
|
|
line.long 0x364 "CP3_217R,Color Palette 3 Register 217"
|
|
hexmask.long.byte 0x364 24.--31. 1. " CP3_217A ,Color Palette 3_217 Blend Ratio"
|
|
hexmask.long.byte 0x364 18.--23. 1. " CP3_217R ,Color Palette 3_217 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x364 10.--15. 1. " CP3_217G ,Color Palette 3_217 Green"
|
|
hexmask.long.byte 0x364 2.--7. 1. " CP3_217B ,Color Palette 3_217 Blue"
|
|
line.long 0x368 "CP3_218R,Color Palette 3 Register 218"
|
|
hexmask.long.byte 0x368 24.--31. 1. " CP3_218A ,Color Palette 3_218 Blend Ratio"
|
|
hexmask.long.byte 0x368 18.--23. 1. " CP3_218R ,Color Palette 3_218 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x368 10.--15. 1. " CP3_218G ,Color Palette 3_218 Green"
|
|
hexmask.long.byte 0x368 2.--7. 1. " CP3_218B ,Color Palette 3_218 Blue"
|
|
line.long 0x36C "CP3_219R,Color Palette 3 Register 219"
|
|
hexmask.long.byte 0x36C 24.--31. 1. " CP3_219A ,Color Palette 3_219 Blend Ratio"
|
|
hexmask.long.byte 0x36C 18.--23. 1. " CP3_219R ,Color Palette 3_219 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x36C 10.--15. 1. " CP3_219G ,Color Palette 3_219 Green"
|
|
hexmask.long.byte 0x36C 2.--7. 1. " CP3_219B ,Color Palette 3_219 Blue"
|
|
line.long 0x370 "CP3_220R,Color Palette 3 Register 220"
|
|
hexmask.long.byte 0x370 24.--31. 1. " CP3_220A ,Color Palette 3_220 Blend Ratio"
|
|
hexmask.long.byte 0x370 18.--23. 1. " CP3_220R ,Color Palette 3_220 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x370 10.--15. 1. " CP3_220G ,Color Palette 3_220 Green"
|
|
hexmask.long.byte 0x370 2.--7. 1. " CP3_220B ,Color Palette 3_220 Blue"
|
|
line.long 0x374 "CP3_221R,Color Palette 3 Register 221"
|
|
hexmask.long.byte 0x374 24.--31. 1. " CP3_221A ,Color Palette 3_221 Blend Ratio"
|
|
hexmask.long.byte 0x374 18.--23. 1. " CP3_221R ,Color Palette 3_221 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x374 10.--15. 1. " CP3_221G ,Color Palette 3_221 Green"
|
|
hexmask.long.byte 0x374 2.--7. 1. " CP3_221B ,Color Palette 3_221 Blue"
|
|
line.long 0x378 "CP3_222R,Color Palette 3 Register 222"
|
|
hexmask.long.byte 0x378 24.--31. 1. " CP3_222A ,Color Palette 3_222 Blend Ratio"
|
|
hexmask.long.byte 0x378 18.--23. 1. " CP3_222R ,Color Palette 3_222 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x378 10.--15. 1. " CP3_222G ,Color Palette 3_222 Green"
|
|
hexmask.long.byte 0x378 2.--7. 1. " CP3_222B ,Color Palette 3_222 Blue"
|
|
line.long 0x37C "CP3_223R,Color Palette 3 Register 223"
|
|
hexmask.long.byte 0x37C 24.--31. 1. " CP3_223A ,Color Palette 3_223 Blend Ratio"
|
|
hexmask.long.byte 0x37C 18.--23. 1. " CP3_223R ,Color Palette 3_223 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x37C 10.--15. 1. " CP3_223G ,Color Palette 3_223 Green"
|
|
hexmask.long.byte 0x37C 2.--7. 1. " CP3_223B ,Color Palette 3_223 Blue"
|
|
line.long 0x380 "CP3_224R,Color Palette 3 Register 224"
|
|
hexmask.long.byte 0x380 24.--31. 1. " CP3_224A ,Color Palette 3_224 Blend Ratio"
|
|
hexmask.long.byte 0x380 18.--23. 1. " CP3_224R ,Color Palette 3_224 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x380 10.--15. 1. " CP3_224G ,Color Palette 3_224 Green"
|
|
hexmask.long.byte 0x380 2.--7. 1. " CP3_224B ,Color Palette 3_224 Blue"
|
|
line.long 0x384 "CP3_225R,Color Palette 3 Register 225"
|
|
hexmask.long.byte 0x384 24.--31. 1. " CP3_225A ,Color Palette 3_225 Blend Ratio"
|
|
hexmask.long.byte 0x384 18.--23. 1. " CP3_225R ,Color Palette 3_225 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x384 10.--15. 1. " CP3_225G ,Color Palette 3_225 Green"
|
|
hexmask.long.byte 0x384 2.--7. 1. " CP3_225B ,Color Palette 3_225 Blue"
|
|
line.long 0x388 "CP3_226R,Color Palette 3 Register 226"
|
|
hexmask.long.byte 0x388 24.--31. 1. " CP3_226A ,Color Palette 3_226 Blend Ratio"
|
|
hexmask.long.byte 0x388 18.--23. 1. " CP3_226R ,Color Palette 3_226 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x388 10.--15. 1. " CP3_226G ,Color Palette 3_226 Green"
|
|
hexmask.long.byte 0x388 2.--7. 1. " CP3_226B ,Color Palette 3_226 Blue"
|
|
line.long 0x38C "CP3_227R,Color Palette 3 Register 227"
|
|
hexmask.long.byte 0x38C 24.--31. 1. " CP3_227A ,Color Palette 3_227 Blend Ratio"
|
|
hexmask.long.byte 0x38C 18.--23. 1. " CP3_227R ,Color Palette 3_227 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x38C 10.--15. 1. " CP3_227G ,Color Palette 3_227 Green"
|
|
hexmask.long.byte 0x38C 2.--7. 1. " CP3_227B ,Color Palette 3_227 Blue"
|
|
line.long 0x390 "CP3_228R,Color Palette 3 Register 228"
|
|
hexmask.long.byte 0x390 24.--31. 1. " CP3_228A ,Color Palette 3_228 Blend Ratio"
|
|
hexmask.long.byte 0x390 18.--23. 1. " CP3_228R ,Color Palette 3_228 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x390 10.--15. 1. " CP3_228G ,Color Palette 3_228 Green"
|
|
hexmask.long.byte 0x390 2.--7. 1. " CP3_228B ,Color Palette 3_228 Blue"
|
|
line.long 0x394 "CP3_229R,Color Palette 3 Register 229"
|
|
hexmask.long.byte 0x394 24.--31. 1. " CP3_229A ,Color Palette 3_229 Blend Ratio"
|
|
hexmask.long.byte 0x394 18.--23. 1. " CP3_229R ,Color Palette 3_229 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x394 10.--15. 1. " CP3_229G ,Color Palette 3_229 Green"
|
|
hexmask.long.byte 0x394 2.--7. 1. " CP3_229B ,Color Palette 3_229 Blue"
|
|
line.long 0x398 "CP3_230R,Color Palette 3 Register 230"
|
|
hexmask.long.byte 0x398 24.--31. 1. " CP3_230A ,Color Palette 3_230 Blend Ratio"
|
|
hexmask.long.byte 0x398 18.--23. 1. " CP3_230R ,Color Palette 3_230 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x398 10.--15. 1. " CP3_230G ,Color Palette 3_230 Green"
|
|
hexmask.long.byte 0x398 2.--7. 1. " CP3_230B ,Color Palette 3_230 Blue"
|
|
line.long 0x39C "CP3_231R,Color Palette 3 Register 231"
|
|
hexmask.long.byte 0x39C 24.--31. 1. " CP3_231A ,Color Palette 3_231 Blend Ratio"
|
|
hexmask.long.byte 0x39C 18.--23. 1. " CP3_231R ,Color Palette 3_231 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x39C 10.--15. 1. " CP3_231G ,Color Palette 3_231 Green"
|
|
hexmask.long.byte 0x39C 2.--7. 1. " CP3_231B ,Color Palette 3_231 Blue"
|
|
line.long 0x3A0 "CP3_232R,Color Palette 3 Register 232"
|
|
hexmask.long.byte 0x3A0 24.--31. 1. " CP3_232A ,Color Palette 3_232 Blend Ratio"
|
|
hexmask.long.byte 0x3A0 18.--23. 1. " CP3_232R ,Color Palette 3_232 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A0 10.--15. 1. " CP3_232G ,Color Palette 3_232 Green"
|
|
hexmask.long.byte 0x3A0 2.--7. 1. " CP3_232B ,Color Palette 3_232 Blue"
|
|
line.long 0x3A4 "CP3_233R,Color Palette 3 Register 233"
|
|
hexmask.long.byte 0x3A4 24.--31. 1. " CP3_233A ,Color Palette 3_233 Blend Ratio"
|
|
hexmask.long.byte 0x3A4 18.--23. 1. " CP3_233R ,Color Palette 3_233 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A4 10.--15. 1. " CP3_233G ,Color Palette 3_233 Green"
|
|
hexmask.long.byte 0x3A4 2.--7. 1. " CP3_233B ,Color Palette 3_233 Blue"
|
|
line.long 0x3A8 "CP3_234R,Color Palette 3 Register 234"
|
|
hexmask.long.byte 0x3A8 24.--31. 1. " CP3_234A ,Color Palette 3_234 Blend Ratio"
|
|
hexmask.long.byte 0x3A8 18.--23. 1. " CP3_234R ,Color Palette 3_234 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3A8 10.--15. 1. " CP3_234G ,Color Palette 3_234 Green"
|
|
hexmask.long.byte 0x3A8 2.--7. 1. " CP3_234B ,Color Palette 3_234 Blue"
|
|
line.long 0x3AC "CP3_235R,Color Palette 3 Register 235"
|
|
hexmask.long.byte 0x3AC 24.--31. 1. " CP3_235A ,Color Palette 3_235 Blend Ratio"
|
|
hexmask.long.byte 0x3AC 18.--23. 1. " CP3_235R ,Color Palette 3_235 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3AC 10.--15. 1. " CP3_235G ,Color Palette 3_235 Green"
|
|
hexmask.long.byte 0x3AC 2.--7. 1. " CP3_235B ,Color Palette 3_235 Blue"
|
|
line.long 0x3B0 "CP3_236R,Color Palette 3 Register 236"
|
|
hexmask.long.byte 0x3B0 24.--31. 1. " CP3_236A ,Color Palette 3_236 Blend Ratio"
|
|
hexmask.long.byte 0x3B0 18.--23. 1. " CP3_236R ,Color Palette 3_236 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B0 10.--15. 1. " CP3_236G ,Color Palette 3_236 Green"
|
|
hexmask.long.byte 0x3B0 2.--7. 1. " CP3_236B ,Color Palette 3_236 Blue"
|
|
line.long 0x3B4 "CP3_237R,Color Palette 3 Register 237"
|
|
hexmask.long.byte 0x3B4 24.--31. 1. " CP3_237A ,Color Palette 3_237 Blend Ratio"
|
|
hexmask.long.byte 0x3B4 18.--23. 1. " CP3_237R ,Color Palette 3_237 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B4 10.--15. 1. " CP3_237G ,Color Palette 3_237 Green"
|
|
hexmask.long.byte 0x3B4 2.--7. 1. " CP3_237B ,Color Palette 3_237 Blue"
|
|
line.long 0x3B8 "CP3_238R,Color Palette 3 Register 238"
|
|
hexmask.long.byte 0x3B8 24.--31. 1. " CP3_238A ,Color Palette 3_238 Blend Ratio"
|
|
hexmask.long.byte 0x3B8 18.--23. 1. " CP3_238R ,Color Palette 3_238 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3B8 10.--15. 1. " CP3_238G ,Color Palette 3_238 Green"
|
|
hexmask.long.byte 0x3B8 2.--7. 1. " CP3_238B ,Color Palette 3_238 Blue"
|
|
line.long 0x3BC "CP3_239R,Color Palette 3 Register 239"
|
|
hexmask.long.byte 0x3BC 24.--31. 1. " CP3_239A ,Color Palette 3_239 Blend Ratio"
|
|
hexmask.long.byte 0x3BC 18.--23. 1. " CP3_239R ,Color Palette 3_239 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3BC 10.--15. 1. " CP3_239G ,Color Palette 3_239 Green"
|
|
hexmask.long.byte 0x3BC 2.--7. 1. " CP3_239B ,Color Palette 3_239 Blue"
|
|
line.long 0x3C0 "CP3_240R,Color Palette 3 Register 240"
|
|
hexmask.long.byte 0x3C0 24.--31. 1. " CP3_240A ,Color Palette 3_240 Blend Ratio"
|
|
hexmask.long.byte 0x3C0 18.--23. 1. " CP3_240R ,Color Palette 3_240 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C0 10.--15. 1. " CP3_240G ,Color Palette 3_240 Green"
|
|
hexmask.long.byte 0x3C0 2.--7. 1. " CP3_240B ,Color Palette 3_240 Blue"
|
|
line.long 0x3C4 "CP3_241R,Color Palette 3 Register 241"
|
|
hexmask.long.byte 0x3C4 24.--31. 1. " CP3_241A ,Color Palette 3_241 Blend Ratio"
|
|
hexmask.long.byte 0x3C4 18.--23. 1. " CP3_241R ,Color Palette 3_241 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C4 10.--15. 1. " CP3_241G ,Color Palette 3_241 Green"
|
|
hexmask.long.byte 0x3C4 2.--7. 1. " CP3_241B ,Color Palette 3_241 Blue"
|
|
line.long 0x3C8 "CP3_242R,Color Palette 3 Register 242"
|
|
hexmask.long.byte 0x3C8 24.--31. 1. " CP3_242A ,Color Palette 3_242 Blend Ratio"
|
|
hexmask.long.byte 0x3C8 18.--23. 1. " CP3_242R ,Color Palette 3_242 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3C8 10.--15. 1. " CP3_242G ,Color Palette 3_242 Green"
|
|
hexmask.long.byte 0x3C8 2.--7. 1. " CP3_242B ,Color Palette 3_242 Blue"
|
|
line.long 0x3CC "CP3_243R,Color Palette 3 Register 243"
|
|
hexmask.long.byte 0x3CC 24.--31. 1. " CP3_243A ,Color Palette 3_243 Blend Ratio"
|
|
hexmask.long.byte 0x3CC 18.--23. 1. " CP3_243R ,Color Palette 3_243 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3CC 10.--15. 1. " CP3_243G ,Color Palette 3_243 Green"
|
|
hexmask.long.byte 0x3CC 2.--7. 1. " CP3_243B ,Color Palette 3_243 Blue"
|
|
line.long 0x3D0 "CP3_244R,Color Palette 3 Register 244"
|
|
hexmask.long.byte 0x3D0 24.--31. 1. " CP3_244A ,Color Palette 3_244 Blend Ratio"
|
|
hexmask.long.byte 0x3D0 18.--23. 1. " CP3_244R ,Color Palette 3_244 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D0 10.--15. 1. " CP3_244G ,Color Palette 3_244 Green"
|
|
hexmask.long.byte 0x3D0 2.--7. 1. " CP3_244B ,Color Palette 3_244 Blue"
|
|
line.long 0x3D4 "CP3_245R,Color Palette 3 Register 245"
|
|
hexmask.long.byte 0x3D4 24.--31. 1. " CP3_245A ,Color Palette 3_245 Blend Ratio"
|
|
hexmask.long.byte 0x3D4 18.--23. 1. " CP3_245R ,Color Palette 3_245 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D4 10.--15. 1. " CP3_245G ,Color Palette 3_245 Green"
|
|
hexmask.long.byte 0x3D4 2.--7. 1. " CP3_245B ,Color Palette 3_245 Blue"
|
|
line.long 0x3D8 "CP3_246R,Color Palette 3 Register 246"
|
|
hexmask.long.byte 0x3D8 24.--31. 1. " CP3_246A ,Color Palette 3_246 Blend Ratio"
|
|
hexmask.long.byte 0x3D8 18.--23. 1. " CP3_246R ,Color Palette 3_246 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3D8 10.--15. 1. " CP3_246G ,Color Palette 3_246 Green"
|
|
hexmask.long.byte 0x3D8 2.--7. 1. " CP3_246B ,Color Palette 3_246 Blue"
|
|
line.long 0x3DC "CP3_247R,Color Palette 3 Register 247"
|
|
hexmask.long.byte 0x3DC 24.--31. 1. " CP3_247A ,Color Palette 3_247 Blend Ratio"
|
|
hexmask.long.byte 0x3DC 18.--23. 1. " CP3_247R ,Color Palette 3_247 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3DC 10.--15. 1. " CP3_247G ,Color Palette 3_247 Green"
|
|
hexmask.long.byte 0x3DC 2.--7. 1. " CP3_247B ,Color Palette 3_247 Blue"
|
|
line.long 0x3E0 "CP3_248R,Color Palette 3 Register 248"
|
|
hexmask.long.byte 0x3E0 24.--31. 1. " CP3_248A ,Color Palette 3_248 Blend Ratio"
|
|
hexmask.long.byte 0x3E0 18.--23. 1. " CP3_248R ,Color Palette 3_248 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E0 10.--15. 1. " CP3_248G ,Color Palette 3_248 Green"
|
|
hexmask.long.byte 0x3E0 2.--7. 1. " CP3_248B ,Color Palette 3_248 Blue"
|
|
line.long 0x3E4 "CP3_249R,Color Palette 3 Register 249"
|
|
hexmask.long.byte 0x3E4 24.--31. 1. " CP3_249A ,Color Palette 3_249 Blend Ratio"
|
|
hexmask.long.byte 0x3E4 18.--23. 1. " CP3_249R ,Color Palette 3_249 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E4 10.--15. 1. " CP3_249G ,Color Palette 3_249 Green"
|
|
hexmask.long.byte 0x3E4 2.--7. 1. " CP3_249B ,Color Palette 3_249 Blue"
|
|
line.long 0x3E8 "CP3_250R,Color Palette 3 Register 250"
|
|
hexmask.long.byte 0x3E8 24.--31. 1. " CP3_250A ,Color Palette 3_250 Blend Ratio"
|
|
hexmask.long.byte 0x3E8 18.--23. 1. " CP3_250R ,Color Palette 3_250 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3E8 10.--15. 1. " CP3_250G ,Color Palette 3_250 Green"
|
|
hexmask.long.byte 0x3E8 2.--7. 1. " CP3_250B ,Color Palette 3_250 Blue"
|
|
line.long 0x3EC "CP3_251R,Color Palette 3 Register 251"
|
|
hexmask.long.byte 0x3EC 24.--31. 1. " CP3_251A ,Color Palette 3_251 Blend Ratio"
|
|
hexmask.long.byte 0x3EC 18.--23. 1. " CP3_251R ,Color Palette 3_251 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3EC 10.--15. 1. " CP3_251G ,Color Palette 3_251 Green"
|
|
hexmask.long.byte 0x3EC 2.--7. 1. " CP3_251B ,Color Palette 3_251 Blue"
|
|
line.long 0x3F0 "CP3_252R,Color Palette 3 Register 252"
|
|
hexmask.long.byte 0x3F0 24.--31. 1. " CP3_252A ,Color Palette 3_252 Blend Ratio"
|
|
hexmask.long.byte 0x3F0 18.--23. 1. " CP3_252R ,Color Palette 3_252 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F0 10.--15. 1. " CP3_252G ,Color Palette 3_252 Green"
|
|
hexmask.long.byte 0x3F0 2.--7. 1. " CP3_252B ,Color Palette 3_252 Blue"
|
|
line.long 0x3F4 "CP3_253R,Color Palette 3 Register 253"
|
|
hexmask.long.byte 0x3F4 24.--31. 1. " CP3_253A ,Color Palette 3_253 Blend Ratio"
|
|
hexmask.long.byte 0x3F4 18.--23. 1. " CP3_253R ,Color Palette 3_253 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F4 10.--15. 1. " CP3_253G ,Color Palette 3_253 Green"
|
|
hexmask.long.byte 0x3F4 2.--7. 1. " CP3_253B ,Color Palette 3_253 Blue"
|
|
line.long 0x3F8 "CP3_254R,Color Palette 3 Register 254"
|
|
hexmask.long.byte 0x3F8 24.--31. 1. " CP3_254A ,Color Palette 3_254 Blend Ratio"
|
|
hexmask.long.byte 0x3F8 18.--23. 1. " CP3_254R ,Color Palette 3_254 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3F8 10.--15. 1. " CP3_254G ,Color Palette 3_254 Green"
|
|
hexmask.long.byte 0x3F8 2.--7. 1. " CP3_254B ,Color Palette 3_254 Blue"
|
|
line.long 0x3FC "CP3_255R,Color Palette 3 Register 255"
|
|
hexmask.long.byte 0x3FC 24.--31. 1. " CP3_255A ,Color Palette 3_255 Blend Ratio"
|
|
hexmask.long.byte 0x3FC 18.--23. 1. " CP3_255R ,Color Palette 3_255 Red"
|
|
textline " "
|
|
hexmask.long.byte 0x3FC 10.--15. 1. " CP3_255G ,Color Palette 3_255 Green"
|
|
hexmask.long.byte 0x3FC 2.--7. 1. " CP3_255B ,Color Palette 3_255 Blue"
|
|
tree.end
|
|
width 9.
|
|
tree "External Synchronization Control Registers"
|
|
tree "Channel 1"
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0X01)
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "ESCR,External Synchronization Control Register"
|
|
bitfld.long 0x00 25. " DCKOINV ,DCLKOUT Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20. " DCLKSEL ,DCLKIN Select" "DCLKIN,CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DCLKDIS ,DCLKOUT Disable" "No,Yes"
|
|
bitfld.long 0x00 8.--9. " SYNCSEL ,SYNC Select" "Not synchronized,Not synchronized,EXVSYNC synchronized,EXHSYNC synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " FRQSEL ,Dot Clock Frequency Ratio Selection" "Not performed,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
else
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "ESCR,External Synchronization Control Register"
|
|
bitfld.long 0x00 25. " DCKOINV ,DCLKOUT Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20. " DCLKSEL ,DCLKIN Select" "DCLKIN,CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DCLKDIS ,DCLKOUT Disable" "No,Yes"
|
|
bitfld.long 0x00 8.--9. " SYNCSEL ,SYNC Select" "Not synchronized,Not synchronized,EXVSYNC synchronized,EXHSYNC synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " FRQSEL ,Dot Clock Frequency Ratio Selection" "Not performed,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
group.long 0x10004++0x03
|
|
line.long 0x00 "OTAR,Output Signal Timing Adjustment Register"
|
|
bitfld.long 0x00 28.--30. " DEA ,DE Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 24.--26. " CLAMPA ,CLAMP Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " DRGBA ,Digital RGB Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 8.--10. " CDEA ,CDE Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DISPA ,DISP Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 0.--2. " SYNCA ,SYNC Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
tree.end
|
|
tree "Channel 2"
|
|
if (((per.l(ad:0xFFF80000+0x20))&0x01)==0x01)
|
|
group.long 0x31000++0x03
|
|
line.long 0x00 "ESCR2,External Synchronization Control Register"
|
|
bitfld.long 0x00 25. " DCKOINV ,DCLKOUT Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20. " DCLKSEL ,DCLKIN Select" "DCLKIN,CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DCLKDIS ,DCLKOUT Disable" "No,Yes"
|
|
bitfld.long 0x00 8.--9. " SYNCSEL ,SYNC Select" "Not synchronized,Not synchronized,EXVSYNC synchronized,EXHSYNC synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0.--5. " FRQSEL ,Dot Clock Frequency Ratio Selection" "Not performed,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64"
|
|
else
|
|
group.long 0x31000++0x03
|
|
line.long 0x00 "ESCR2,External Synchronization Control Register"
|
|
bitfld.long 0x00 25. " DCKOINV ,DCLKOUT Invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 20. " DCLKSEL ,DCLKIN Select" "DCLKIN,CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DCLKDIS ,DCLKOUT Disable" "No,Yes"
|
|
bitfld.long 0x00 8.--9. " SYNCSEL ,SYNC Select" "Not synchronized,Not synchronized,EXVSYNC synchronized,EXHSYNC synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " FRQSEL ,Dot Clock Frequency Ratio Selection" "Not performed,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32"
|
|
endif
|
|
group.long 0x31004++0x03
|
|
line.long 0x00 "OTAR2,Output Signal Timing Adjustment Register"
|
|
bitfld.long 0x00 28.--30. " DEA ,DE Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 24.--26. " CLAMPA ,CLAMP Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " DRGBA ,Digital RGB Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 8.--10. " CDEA ,CDE Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DISPA ,DISP Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
bitfld.long 0x00 0.--2. " SYNCA ,SYNC Output Timing Adjustment" "No adjustment,Rising/delayed 1 cycle,Rising/delayed 2 cycles,Rising/delayed 3 cycles,Falling/preceded 0.5 cycle,Falling/delayed 0.5 cycle,Falling/delayed 1.5 cycles,Falling/delayed 2.5 cycles"
|
|
tree.end
|
|
tree.end
|
|
tree "Dual Display Output Control Registers"
|
|
group.long 0x11000++0xb
|
|
line.long 0x00 "DORCR,Display Unit Output Route Control Register"
|
|
bitfld.long 0x00 30. " PG2T ,Pin Generate 2 Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x00 28. " DK2S ,Dot Clock Select 2" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " PG2D ,Pin Generate 2 Input Data Select" "Superposition processor 1,Superposition processor 2,Fixed to 0,DOOR"
|
|
bitfld.long 0x00 21. " DR1D ,Display Output Route 1 Data Select" "Pin controller 1,Pin controller 1 at rising edge/Pin controller 2 at falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " PG1D ,Pin Generate 1 Input Data Select" "Superposition processor 1,Superposition processor 2,Fixed to 0,DOOR"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RGPV ,R-GP2 V Blank Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x00 0. " DPRS ,Display Priority Register Select" "DPPR,DS1PR/DS2PR"
|
|
line.long 0x04 "DPTSR,Display Unit Plane Timing Select Register"
|
|
bitfld.long 0x04 23. " P8DK ,Plane 8 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 22. " P7DK ,Plane 7 Dot Clock Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P6DK ,Plane 6 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 20. " P5DK ,Plane 5 Dot Clock Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 19. " P4DK ,Plane 4 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 18. " P3DK ,Plane 3 Dot Clock Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 17. " P2DK ,Plane 2 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 16. " P1DK ,Plane 1 Dot Clock Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 7. " P8TS ,Plane 8 Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 6. " P7TS ,Plane 7 Timing Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P6TS ,Plane 6 Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 4. " P5TS ,Plane 5 Timing Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P4TS ,Plane 4 Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 2. " P3TS ,Plane 3 Timing Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x04 1. " P2TS ,Plane 2 Timing Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x04 0. " P1TS ,Plane 1 Timing Select" "Generator 1,Generator 2"
|
|
line.long 0x08 "DAPTSR,Display Unit Alpha Plane Timing Select Register"
|
|
bitfld.long 0x08 17. " AP2DK ,Alpha Plane 2 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x08 16. " AP1DK ,Alpha Plane 1 Dot Clock Select" "Generator 1,Generator 2"
|
|
textline " "
|
|
bitfld.long 0x08 1. " AP2TS ,Alpha Plane 2 Dot Clock Select" "Generator 1,Generator 2"
|
|
bitfld.long 0x08 0. " AP1TS ,Alpha Plane 1 Dot Clock Select" "Generator 1,Generator 2"
|
|
group.long 0x11020++0x07
|
|
line.long 0x00 "DS1PR,Display Superimpose 1 Priority Register"
|
|
bitfld.long 0x00 28.--31. " S1S8 ,Display Superimposition 1 Priority 8 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x00 24.--27. " S1S7 ,Display Superimposition 1 Priority 7 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " S1S6 ,Display Superimposition 1 Priority 6 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x00 16.--19. " S1S5 ,Display Superimposition 1 Priority 5 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " S1S4 ,Display Superimposition 1 Priority 4 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x00 8.--11. " S1S3 ,Display Superimposition 1 Priority 3 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " S1S2 ,Display Superimposition 1 Priority 2 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x00 0.--3. " S1S1 ,Display Superimposition 1 Priority 1 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
line.long 0x04 "DS2PR,Display Superimpose 2 Priority Register"
|
|
bitfld.long 0x04 28.--31. " S2S8 ,Display Superimposition 2 Priority 8 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x04 24.--27. " S2S7 ,Display Superimposition 2 Priority 7 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x04 20.--23. " S2S6 ,Display Superimposition 2 Priority 6 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x04 16.--19. " S2S5 ,Display Superimposition 2 Priority 5 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " S2S4 ,Display Superimposition 2 Priority 4 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x04 8.--11. " S2S3 ,Display Superimposition 2 Priority 3 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " S2S2 ,Display Superimposition 2 Priority 2 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
bitfld.long 0x04 0.--3. " S12S1 ,Display Superimposition 2 Priority 1 Select" "Not used,Plane 1,Plane 2,Plane 3,Plane 4,Plane 5,Plane 6,Plane 7,Plane 8,?..."
|
|
tree.end
|
|
width 7.
|
|
tree "YC-RGB Conversion Coefficient Registers"
|
|
tree "YC-RGB Conversion Before Superpositioning"
|
|
group.long 0x11080++0x1f
|
|
line.long 0x00 "YNCR,Y Normalization Coefficient Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " YNC2 ,Y Normalization Coefficient 2"
|
|
hexmask.long.word 0x00 0.--11. 1. " YNC1 ,Y Normalization Coefficient 1"
|
|
line.long 0x04 "YNOR,Y Normalization Offset Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " YNO2 ,Y Normalization Offset 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " YNO1 ,Y Normalization Offset 1"
|
|
line.long 0x08 "CRNOR,Cr Normalization Offset Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CRNO2 ,Cr Normalization Offset 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CRNO1 ,Cr Normalization Offset 1"
|
|
line.long 0x0c "CBNOR,Cb Normalization Offset Register"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " CBNO2 ,Cb Normalization Offset 2"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " CBNO1 ,Cb Normalization Offset 1"
|
|
line.long 0x10 "RCRCR,Red Cr Coefficient Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " RCRC2 ,Red Cr Coefficient 2"
|
|
hexmask.long.word 0x10 0.--11. 1. " RCRC1 ,Red Cr Coefficient 1"
|
|
line.long 0x14 "GCRCR,Green Cr Coefficient Register"
|
|
hexmask.long.word 0x14 16.--27. 1. " GCRC2 ,Green Cr Coefficient 2"
|
|
hexmask.long.word 0x14 0.--11. 1. " GCRC1 ,Green Cr Coefficient 1"
|
|
line.long 0x18 "GCBCR,Green Cb Coefficient Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " GCBC2 ,Green Cb Coefficient 2"
|
|
hexmask.long.word 0x18 0.--11. 1. " GCBC1 ,Green Cb Coefficient 1"
|
|
line.long 0x1c "BCRCR,Blue Cr Coefficient Register"
|
|
hexmask.long.word 0x1c 16.--27. 1. " BCRC2 ,Blue Cr Coefficient 2"
|
|
hexmask.long.word 0x1c 0.--11. 1. " BCRC1 ,Blue Cr Coefficient 1"
|
|
tree.end
|
|
tree "YC-RGB Conversion After Superpositioning"
|
|
group.long 0x14080++0x1f
|
|
line.long 0x00 "YNCR,Y Normalization Coefficient Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " YNC2 ,Y Normalization Coefficient 2"
|
|
hexmask.long.word 0x00 0.--11. 1. " YNC1 ,Y Normalization Coefficient 1"
|
|
line.long 0x04 "YNOR,Y Normalization Offset Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " YNO2 ,Y Normalization Offset 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " YNO1 ,Y Normalization Offset 1"
|
|
line.long 0x08 "CRNOR,Cr Normalization Offset Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CRNO2 ,Cr Normalization Offset 2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CRNO1 ,Cr Normalization Offset 1"
|
|
line.long 0x0c "CBNOR,Cb Normalization Offset Register"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " CBNO2 ,Cb Normalization Offset 2"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " CBNO1 ,Cb Normalization Offset 1"
|
|
line.long 0x10 "RCRCR,Red Cr Coefficient Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " RCRC2 ,Red Cr Coefficient 2"
|
|
hexmask.long.word 0x10 0.--11. 1. " RCRC1 ,Red Cr Coefficient 1"
|
|
line.long 0x14 "GCRCR,Green Cr Coefficient Register"
|
|
hexmask.long.word 0x14 16.--27. 1. " GCRC2 ,Green Cr Coefficient 2"
|
|
hexmask.long.word 0x14 0.--11. 1. " GCRC1 ,Green Cr Coefficient 1"
|
|
line.long 0x18 "GCBCR,Green Cb Coefficient Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " GCBC2 ,Green Cb Coefficient 2"
|
|
hexmask.long.word 0x18 0.--11. 1. " GCBC1 ,Green Cb Coefficient 1"
|
|
line.long 0x1c "BCRCR,Blue Cr Coefficient Register"
|
|
hexmask.long.word 0x1c 16.--27. 1. " BCRC2 ,Blue Cr Coefficient 2"
|
|
hexmask.long.word 0x1c 0.--11. 1. " BCRC1 ,Blue Cr Coefficient 1"
|
|
tree.end
|
|
tree.end
|
|
width 9.
|
|
tree "RGB-YC Conversion Coefficient Registers"
|
|
group.long 0x14000++0x2f
|
|
line.long 0x0 "YCLRP,Y Calculation R Coefficient Register"
|
|
bitfld.long 0x0 12. " YCLRP ,Y Calculation R Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word 0x0 0.--11. 1. ",Y Calculation R Coefficient"
|
|
line.long (0x0+0x04) "YCLGP,Y Calculation G Coefficient Register"
|
|
bitfld.long (0x0+0x04) 12. " YCLGP ,Y Calculation G Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x0+0x04) 0.--11. 1. ",Y Calculation G Coefficient"
|
|
line.long (0x0+0x08) "YCLBP,Y Calculation B Coefficient Register"
|
|
bitfld.long (0x0+0x08) 12. " YCLBP ,Y Calculation B Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x0+0x08) 0.--11. 1. ",Y Calculation B Coefficient"
|
|
line.long (0x0+0x0c) "YCLAP,Y Calculation Addition Constant Register"
|
|
hexmask.long.byte (0x0+0x0c) 0.--7. 1. " YCLAP ,Y Calculation Addition Constant"
|
|
line.long 0x10 "CBCLRP,Cb Calculation R Coefficient Register"
|
|
bitfld.long 0x10 12. " CBCLRP ,Cb Calculation R Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word 0x10 0.--11. 1. ",Cb Calculation R Coefficient"
|
|
line.long (0x10+0x04) "CBCLGP,Cb Calculation G Coefficient Register"
|
|
bitfld.long (0x10+0x04) 12. " CBCLGP ,Cb Calculation G Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x10+0x04) 0.--11. 1. ",Cb Calculation G Coefficient"
|
|
line.long (0x10+0x08) "CBCLBP,Cb Calculation B Coefficient Register"
|
|
bitfld.long (0x10+0x08) 12. " CBCLBP ,Cb Calculation B Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x10+0x08) 0.--11. 1. ",Cb Calculation B Coefficient"
|
|
line.long (0x10+0x0c) "CBCLAP,Cb Calculation Addition Constant Register"
|
|
hexmask.long.byte (0x10+0x0c) 0.--7. 1. " CBCLAP ,Cb Calculation Addition Constant"
|
|
line.long 0x20 "CRCLRP,Cr Calculation R Coefficient Register"
|
|
bitfld.long 0x20 12. " CRCLRP ,Cr Calculation R Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word 0x20 0.--11. 1. ",Cr Calculation R Coefficient"
|
|
line.long (0x20+0x04) "CRCLGP,Cr Calculation G Coefficient Register"
|
|
bitfld.long (0x20+0x04) 12. " CRCLGP ,Cr Calculation G Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x20+0x04) 0.--11. 1. ",Cr Calculation G Coefficient"
|
|
line.long (0x20+0x08) "CRCLBP,Cr Calculation B Coefficient Register"
|
|
bitfld.long (0x20+0x08) 12. " CRCLBP ,Cr Calculation B Coefficient Sign Bit" "+,-"
|
|
hexmask.long.word (0x20+0x08) 0.--11. 1. ",Cr Calculation B Coefficient"
|
|
line.long (0x20+0x0c) "CRCLAP,Cr Calculation Addition Constant Register"
|
|
hexmask.long.byte (0x20+0x0c) 0.--7. 1. " CRCLAP ,Cr Calculation Addition Constant"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "VIN (Video Input Module)"
|
|
tree "Channel 0"
|
|
base ad:0xFFC50000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "V0MC,Video 0 Main Control Register"
|
|
bitfld.long 0x00 31. " FAST ,High-speed video clock support mode" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("R8A774*")||cpuis("R7S7210*"))
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,No clipping"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,<=0 clipped to 1"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7790X"||cpu()=="R8A77420"
|
|
bitfld.long 0x00 25. " RIS ,RGB interface select" "Rising edge,Both edges"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7792X"
|
|
bitfld.long 0x00 23. " OMI ,Output data mask to IMR" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " OMM ,Output data mask to memory" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " FOC ,Field order control" "Odd,Even"
|
|
bitfld.long 0x00 20. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " YCAL ,YCbCr-422i Input data alignment" "Y upper/CbCr lower,Y lower/CbCr upper"
|
|
textline " "
|
|
sif cpuis("R7S7210*")
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601/BT.709 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601/BT.709 10/12-bit YCbCr-422,?,BT.601/BT.709/BT.1358 16/20/24-bit YCbCr-422,BT.601/BT.709 24-bit RGB-888,BT.601/BT.709 18-bit RGB-666"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601 10/12-bit YCbCr-422,,BT.601/BT.1358 16-bit YCbCr-422,BT.601 24-bit RGB-888,BT.601 18-bit RGB-666/12-bit RGB-888"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " DC ,Dithering mode control" "Dithering with cumulative addition,Ordered dithering,?..."
|
|
bitfld.long 0x00 12.--13. " EXINF ,Extension interface select" ",8-bit,10-bit,12-bit"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VUP ,VIN register update control" "Immediately,On valid data"
|
|
bitfld.long 0x00 6. " EN ,Endian type" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EC ,Error correction control" "No correction,Correction"
|
|
bitfld.long 0x00 3.--4. " IM ,Interlace mode" "Odd-field,Odd/even-field,Even-field,Full interlace"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BPS ,Color space conversion bypass mode" "Converted,Not converted"
|
|
bitfld.long 0x00 0. " ME ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "V0MS,Video 0 Module Status Register"
|
|
bitfld.long 0x00 3.--4. " FBS ,Frame buffer status" "1,2,3,No valid buffer"
|
|
bitfld.long 0x00 2. " FS ,Field status" "Odd field,Even field"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AV ,Active video status" "Not active,Active"
|
|
bitfld.long 0x00 0. " CA ,Video capture active status" "Inactive,Active"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "V0FC,Video 0 Frame Capture Register"
|
|
bitfld.long 0x00 1. " CC ,Continuous frame capture mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SC ,Single frame capture mode" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "V0SLPRC,Start Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPRC ,Start Line Pre-clip"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "V0ELPRC,End Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPRC ,End Line Pre-clip"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "V0SPPRC,Start Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPRC ,Start Pixel Pre-clip"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "V0EPPRC,End Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPRC ,End Pixel Pre-clip"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "V0SLPOC,Start Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPOC ,Start Line Post-clip"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "V0ELPOC,End Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPOC ,End Line Post-clip"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "V0SPPOC,Start Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPOC ,Start Pixel Post-clip"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "V0EPPOC,End Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPOC ,End Pixel Post-clip"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "V0IS,Video 0 Image Stride Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " IS ,Image stride"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "V0MB1,Video 0 Memory Base 1 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB1 ,Memory base address 1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "V0MB2,Video 0 Memory Base 2 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB2 ,Memory base address 2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "V0MB3,Video 0 Memory Base 3 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB3 ,Memory base address 3"
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "V0LC,Video 0 Line Count Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " LC ,Line count"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "V0IE,Video 0 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " FIE2 ,Field interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VFE ,VSYNC falling edge detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VRE , VSYNC rising edge detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIE ,Field interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CEE ,Correction error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Scanline interrupt Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EFE ,End of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FOE ,FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "V0INTS,Video 0 Interrupt Status Register"
|
|
bitfld.long 0x04 31. " FIS2 ,Field interrupt status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " VFS ,VSYNC falling edge detect interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VRS ,VSYNC rising edge detect interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " FIS ,Field interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CES ,Correction error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " SIS ,Scanline interrupt error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EFS ,End of frame interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " FOS ,FIFO overflow interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "V0SI,Video 0 Scanline Interrupt"
|
|
hexmask.long.word 0x08 0.--11. 1. " SI ,Scanline interrupt setting"
|
|
sif (cpu()!="RCARM2")&&(cpu()!="R8A77470")
|
|
sif cpuis("R8A774*")
|
|
if (((per.l(ad:0xFFC50000+0x4C))&0x100)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V0MTC,Video 0 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,16Byte,32Byte,,,,,,,,,,,,,240Byte"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V0MTC,Video 0 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,32Byte,64Byte,,,,,,256Byte,,,,,,,480Byte"
|
|
endif
|
|
elif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V0MTC,Video 0 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TUNIT ,Transaction unit setting" "16Byte,?"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst Size Setting" "#,,,,,,,,8 beat access,,,,,,,"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V0MTC,Video 0 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "V0YS,Video 0 Y Scale Register"
|
|
bitfld.long 0x00 12.--15. " MANTISSAY ,Mantissa of scaling ratio in the Y direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " FRACTIONY ,Fraction of scaling ratio in the Y direction"
|
|
line.long 0x04 "V0XS,Video 0 X Scale Register"
|
|
bitfld.long 0x04 12.--15. " MANTISSAX ,Mantissa of scaling ratio in the X direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " FRACTIONX ,Fraction of scaling ratio in the X direction"
|
|
line.long 0x08 "V0DMR,Video 0 Data Mode Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
hexmask.long.byte 0x08 24.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x08 25.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 16. " EVA ,Even field address offset" "Base address,Base address + memory width"
|
|
bitfld.long 0x08 12.--14. " YMODE ,YC data transfer mode" "Y and CbCr,Y 8-bit,Y 10->16-bit and CbCr,Y 10->16-bit,Y 12->16-bit and CbCr,Y 12->16-bit,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 11. " YC_THR ,YC data through mode" "YMODE[2:0] bits,10-bit/12-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " EXRGB ,Extension RGB conversion mode" "Not extended,Extended"
|
|
bitfld.long 0x08 4. " BPSM ,Output data byte swap mode" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ABIT ,Alpha bit" "0,1"
|
|
bitfld.long 0x08 0.--1. " DTMD ,Data conversion mode" "Not converted,RGB -> ARGB,YC separated,?..."
|
|
line.long 0x0C "V0DMR2,Video 0 Data Mode Register 2"
|
|
sif !cpuis("R7S72104*")||!cpuis("R7S72106*")
|
|
bitfld.long 0x0C 31. " FPS ,Field signal polarity select" "Odd/Even field,Even/Odd field"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " VPS ,Vsync signal polarity select" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " HPS ,Hsync signal polarity select" "Active low,Active high"
|
|
bitfld.long 0x0C 28. " CES ,Clock enable signal polarity select" "Active high,Active low"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 27. " DES ,Data extension select" "Expanded,Padded"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 23. " CHS ,Clock enable Hsync select" "VIn_CLKEN,Vin_HSYNC"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 22. " YDS ,YCbCr422 8-bit data input pin select" "VIn_B[7:0] pins,VIn_G[7:0] pins"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 17. " FTEV ,VSYNC field toggle mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " FTEH ,HSYNC field toggle counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--15. " VLV ,VSYNC field toggle mode transition period" "Every VSYNC,1 signal,2 signals,3 signals,4 signals,5 signals,6 signals,7 signals,8 signals,9 signals,10 signals,11 signals,12 signals,13 signals,14 signals,15 signals"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--11. 1. " HLV ,HSYNC filed toggle count value"
|
|
line.long 0x10 "V0UVAOF,Video 0 Address Offset Register"
|
|
hexmask.long 0x10 7.--31. 0x80 " UVAOF ,UV data address offset"
|
|
sif cpuis("R8A77420")
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V0CSCC1,Video 0 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V0CSCC2,Video 0 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V0CSCC3,Video 0 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
else
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V0CSCC1,Video 0 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V0CSCC2,Video 0 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V0CSCC3,Video 0 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
endif
|
|
width 9.
|
|
tree "Coefficient Set Registers"
|
|
sif !cpuis("R8A77440")
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V0C1A,Video 0 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C1B,Video 0 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C1C,Video 0 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V0C2A,Video 0 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C2B,Video 0 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C2C,Video 0 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V0C3A,Video 0 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C3B,Video 0 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C3C,Video 0 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V0C4A,Video 0 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C4B,Video 0 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C4C,Video 0 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V0C5A,Video 0 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C5B,Video 0 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C5C,Video 0 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V0C6A,Video 0 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C6B,Video 0 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C6C,Video 0 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V0C7A,Video 0 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C7B,Video 0 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C7C,Video 0 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V0C8A,Video 0 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C8B,Video 0 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C8C,Video 0 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
else
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V0C1A,Video 0 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C1B,Video 0 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C1C,Video 0 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V0C2A,Video 0 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C2B,Video 0 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C2C,Video 0 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V0C3A,Video 0 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C3B,Video 0 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C3C,Video 0 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V0C4A,Video 0 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C4B,Video 0 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C4C,Video 0 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V0C5A,Video 0 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C5B,Video 0 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C5C,Video 0 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V0C6A,Video 0 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C6B,Video 0 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C6C,Video 0 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V0C7A,Video 0 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C7B,Video 0 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C7C,Video 0 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V0C8A,Video 0 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V0C8B,Video 0 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V0C8C,Video 0 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
width 13.
|
|
sif (cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
sif !cpuis("R8A77440")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V0LUTP,Video 0 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V0LUTD,Video 0 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V0LUTP,Video 0 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V0LUTD,Video 0 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
endif
|
|
group.long 0x228++0x23
|
|
line.long 0x00 "V0YCCR1,Video 0 RGB->YC Calculation Setting Register 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " YCLRP ,R multiplication coefficient for YC calculation"
|
|
line.long 0x04 "V0YCCR2,Video 0 RGB->YC Calculation Setting Register 2"
|
|
hexmask.long.word 0x04 16.--28. 1. " YCLBP ,B multiplication coefficient for YC calculation"
|
|
hexmask.long.word 0x04 0.--12. 1. " YCLGP ,G multiplication coefficient for YC calculation"
|
|
line.long 0x08 "V0YCCR3,Video 0 RGB->YC Calculation Setting Register 3"
|
|
bitfld.long 0x08 31. " YEXPEN ,YC calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " YCLSFT ,YC calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " YCLHEN ,YC calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " YCLCEN ,YC calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--11. 1. " YCLAP ,YC calculation data normalized additional value"
|
|
line.long 0x0C "V0CBCCR1,Video 0 RGB->Cb Calculation Setting Register 1"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CBCLRP ,R multiplication coefficient for Cb calculation"
|
|
line.long 0x10 "V0CBCCR2,Video 0 RGB->Cb Calculation Setting Register 2"
|
|
hexmask.long.word 0x10 16.--28. 1. " CBCLBP ,B multiplication coefficient for CBC calculation"
|
|
hexmask.long.word 0x10 0.--12. 1. " CBCLGP ,G multiplication coefficient for CBC calculation"
|
|
line.long 0x14 "V0CBCCR3,Video 0 RGB->Cb Calculation Setting Register 3"
|
|
bitfld.long 0x14 31. " CBEXPEN ,Cb calculation Sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24.--28. " CBCLSFT ,Cb calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 23. " CBCLHEN ,Cb calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " CBCLCEN ,Cb calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--11. 1. " CBCLAP ,Cb calculation data normalized additional value"
|
|
line.long 0x18 "V0CRCCR1,Video 0 RGB->Cr Calculation Setting Register 1"
|
|
hexmask.long.word 0x18 0.--12. 1. " CRCLRP ,R multiplication coefficient for Cr calculation"
|
|
line.long 0x1C "V0CRCCR2,Video 0 RGB->Cr Calculation Setting Register 2"
|
|
hexmask.long.word 0x1C 16.--28. 1. " CRCLBP ,B multiplication coefficient for CRC calculation"
|
|
hexmask.long.word 0x1C 0.--12. 1. " CRCLGP ,G multiplication coefficient for CRC calculation"
|
|
line.long 0x20 "V0CRCCR3,Video 0 RGB->Cr Calculation Setting Register 3"
|
|
bitfld.long 0x20 31. " CRCEXPEN ,Cr calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 24.--28. " CRCLSFT ,Cr calculation shift Down Volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 23. " CRCLHEN ,Cr calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " CRCLCEN ,Cr calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CRCLAP ,Cr calculation data normalized additional value"
|
|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V0LUTP,Video 0 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V0LUTD,Video 0 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
group.long 0x228++0x23
|
|
line.long 0x00 "V0YCCR1,Video 0 RGB->YC Calculation Setting Register 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " YCLRP ,R multiplication coefficient for YC calculation"
|
|
line.long 0x04 "V0YCCR2,Video 0 RGB->YC Calculation Setting Register 2"
|
|
hexmask.long.word 0x04 16.--28. 1. " YCLBP ,B multiplication coefficient for YC calculation"
|
|
hexmask.long.word 0x04 0.--12. 1. " YCLGP ,G multiplication coefficient for YC calculation"
|
|
line.long 0x08 "V0YCCR3,Video 0 RGB->YC Calculation Setting Register 3"
|
|
bitfld.long 0x08 31. " YEXPEN ,YC calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " YCLSFT ,YC calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " YCLHEN ,YC calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " YCLCEN ,YC calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--11. 1. " YCLAP ,YC calculation data normalized additional value"
|
|
line.long 0x0C "V0CBCCR1,Video 0 RGB->Cb Calculation Setting Register 1"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CBCLRP ,R multiplication coefficient for Cb calculation"
|
|
line.long 0x10 "V0CBCCR2,Video 0 RGB->Cb Calculation Setting Register 2"
|
|
hexmask.long.word 0x10 16.--28. 1. " CBCLBP ,B multiplication coefficient for CBC calculation"
|
|
hexmask.long.word 0x10 0.--12. 1. " CBCLGP ,G multiplication coefficient for CBC calculation"
|
|
line.long 0x14 "V0CBCCR3,Video 0 RGB->Cb Calculation Setting Register 3"
|
|
bitfld.long 0x14 31. " CBEXPEN ,Cb calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24.--28. " CBCLSFT ,Cb calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 23. " CBCLHEN ,Cb calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " CBCLCEN ,Cb calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--11. 1. " CBCLAP ,Cb calculation data normalized additional value"
|
|
line.long 0x18 "V0CRCCR1,Video 0 RGB->Cr Calculation Setting Register 1"
|
|
hexmask.long.word 0x18 0.--12. 1. " CRCLRP ,R multiplication coefficient for Cr calculation"
|
|
line.long 0x1C "V0CRCCR2,Video 0 RGB->Cr Calculation Setting Register 2"
|
|
hexmask.long.word 0x1C 16.--28. 1. " CRCLBP ,B multiplication coefficient for CRC calculation"
|
|
hexmask.long.word 0x1C 0.--12. 1. " CRCLGP ,G multiplication coefficient for CRC calculation"
|
|
line.long 0x20 "V0CRCCR3,Video 0 RGB->Cr Calculation Setting Register 3"
|
|
bitfld.long 0x20 31. " CRCEXPEN ,Cr calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 24.--28. " CRCLSFT ,Cr calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 23. " CRCLHEN ,Cr calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " CRCLCEN ,Cr calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CRCLAP ,Cr calculation data normalized additional value"
|
|
endif
|
|
group.long 0x300++0x0F
|
|
line.long 0x00 "V0CSCE1,Video 0 YC->RGB Calculation Setting Extension Register 1"
|
|
hexmask.long.word 0x00 0.--13. 1. " YMUL2 ,Y multiplication coefficient 2 for RGB calculation"
|
|
line.long 0x04 "V0CSCE2,Video 0 YC->RGB Calculation Setting Extension Register 2"
|
|
hexmask.long.word 0x04 16.--27. 1. " YSUB2 ,Y subtraction coefficient 2 for RGB calculation"
|
|
hexmask.long.word 0x04 0.--11. 1. " CSUB2 ,CbCr Subtraction coefficient 2 for RGB calculation"
|
|
line.long 0x08 "V0CSCE3,Video 0 YC->RGB Calculation Setting Extension Register 3"
|
|
hexmask.long.word 0x08 16.--29. 1. " RCRMUL2 ,YCr multiplication coefficient 2 for R calculation"
|
|
hexmask.long.word 0x08 0.--13. 1. " GCRMUL2 ,Cr multiplication coefficient 2 for G calculation"
|
|
line.long 0x0C "V0CSCE4,Video 0 YC->RGB Calculation Setting Extension Register 4"
|
|
hexmask.long.word 0x0C 16.--29. 1. " GCBMUL2 ,Cb multiplication coefficient 2 for G calculation"
|
|
hexmask.long.word 0x0C 0.--13. 1. " BCBMUL2 ,Cb multiplication coefficient 2 for B calculation"
|
|
sif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "V0SRCSEL,Video 0 Input Source Selection Register"
|
|
bitfld.long 0x00 0. " SEL ,Input data selection" "LVTTL,MIPI CSI-2 output signal"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFC51000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "V1MC,Video 1 Main Control Register"
|
|
bitfld.long 0x00 31. " FAST ,High-speed video clock support mode" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("R8A774*")||cpuis("R7S7210*"))
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,No clipping"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,<=0 clipped to 1"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7790X"||cpu()=="R8A77420"
|
|
bitfld.long 0x00 25. " RIS ,RGB interface select" "Rising edge,Both edges"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7792X"
|
|
bitfld.long 0x00 23. " OMI ,Output data mask to IMR" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " OMM ,Output data mask to memory" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " FOC ,Field order control" "Odd,Even"
|
|
bitfld.long 0x00 20. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " YCAL ,YCbCr-422i Input data alignment" "Y upper/CbCr lower,Y lower/CbCr upper"
|
|
textline " "
|
|
sif cpuis("R7S7210*")
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601/BT.709 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601/BT.709 10/12-bit YCbCr-422,?,BT.601/BT.709/BT.1358 16/20/24-bit YCbCr-422,BT.601/BT.709 24-bit RGB-888,BT.601/BT.709 18-bit RGB-666"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601 10/12-bit YCbCr-422,,BT.601/BT.1358 16-bit YCbCr-422,BT.601 24-bit RGB-888,BT.601 18-bit RGB-666/12-bit RGB-888"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " DC ,Dithering mode control" "Dithering with cumulative addition,Ordered dithering,?..."
|
|
bitfld.long 0x00 12.--13. " EXINF ,Extension interface select" ",8-bit,10-bit,12-bit"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VUP ,VIN register update control" "Immediately,On valid data"
|
|
bitfld.long 0x00 6. " EN ,Endian type" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EC ,Error correction control" "No correction,Correction"
|
|
bitfld.long 0x00 3.--4. " IM ,Interlace mode" "Odd-field,Odd/even-field,Even-field,Full interlace"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BPS ,Color space conversion bypass mode" "Converted,Not converted"
|
|
bitfld.long 0x00 0. " ME ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "V1MS,Video 1 Module Status Register"
|
|
bitfld.long 0x00 3.--4. " FBS ,Frame buffer status" "1,2,3,No valid buffer"
|
|
bitfld.long 0x00 2. " FS ,Field status" "Odd field,Even field"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AV ,Active video status" "Not active,Active"
|
|
bitfld.long 0x00 0. " CA ,Video capture active status" "Inactive,Active"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "V1FC,Video 1 Frame Capture Register"
|
|
bitfld.long 0x00 1. " CC ,Continuous frame capture mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SC ,Single frame capture mode" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "V1SLPRC,Start Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPRC ,Start Line Pre-clip"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "V1ELPRC,End Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPRC ,End Line Pre-clip"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "V1SPPRC,Start Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPRC ,Start Pixel Pre-clip"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "V1EPPRC,End Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPRC ,End Pixel Pre-clip"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "V1SLPOC,Start Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPOC ,Start Line Post-clip"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "V1ELPOC,End Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPOC ,End Line Post-clip"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "V1SPPOC,Start Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPOC ,Start Pixel Post-clip"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "V1EPPOC,End Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPOC ,End Pixel Post-clip"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "V1IS,Video 1 Image Stride Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " IS ,Image stride"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "V1MB1,Video 1 Memory Base 1 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB1 ,Memory base address 1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "V1MB2,Video 1 Memory Base 2 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB2 ,Memory base address 2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "V1MB3,Video 1 Memory Base 3 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB3 ,Memory base address 3"
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "V1LC,Video 1 Line Count Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " LC ,Line count"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "V1IE,Video 1 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " FIE2 ,Field interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VFE ,VSYNC falling edge detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VRE , VSYNC rising edge detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIE ,Field interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CEE ,Correction error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Scanline interrupt Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EFE ,End of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FOE ,FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "V1INTS,Video 1 Interrupt Status Register"
|
|
bitfld.long 0x04 31. " FIS2 ,Field interrupt status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " VFS ,VSYNC falling edge detect interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VRS ,VSYNC rising edge detect interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " FIS ,Field interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CES ,Correction error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " SIS ,Scanline interrupt error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EFS ,End of frame interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " FOS ,FIFO overflow interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "V1SI,Video 1 Scanline Interrupt"
|
|
hexmask.long.word 0x08 0.--11. 1. " SI ,Scanline interrupt setting"
|
|
sif (cpu()!="RCARM2")&&(cpu()!="R8A77470")
|
|
sif cpuis("R8A774*")
|
|
if (((per.l(ad:0xFFC51000+0x4C))&0x100)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V1MTC,Video 1 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,16Byte,32Byte,,,,,,,,,,,,,240Byte"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V1MTC,Video 1 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,32Byte,64Byte,,,,,,256Byte,,,,,,,480Byte"
|
|
endif
|
|
elif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V1MTC,Video 1 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TUNIT ,Transaction unit setting" "16Byte,?"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst Size Setting" "#,,,,,,,,8 beat access,,,,,,,"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V1MTC,Video 1 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "V1YS,Video 1 Y Scale Register"
|
|
bitfld.long 0x00 12.--15. " MANTISSAY ,Mantissa of scaling ratio in the Y direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " FRACTIONY ,Fraction of scaling ratio in the Y direction"
|
|
line.long 0x04 "V1XS,Video 1 X Scale Register"
|
|
bitfld.long 0x04 12.--15. " MANTISSAX ,Mantissa of scaling ratio in the X direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " FRACTIONX ,Fraction of scaling ratio in the X direction"
|
|
line.long 0x08 "V1DMR,Video 1 Data Mode Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
hexmask.long.byte 0x08 24.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x08 25.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 16. " EVA ,Even field address offset" "Base address,Base address + memory width"
|
|
bitfld.long 0x08 12.--14. " YMODE ,YC data transfer mode" "Y and CbCr,Y 8-bit,Y 10->16-bit and CbCr,Y 10->16-bit,Y 12->16-bit and CbCr,Y 12->16-bit,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 11. " YC_THR ,YC data through mode" "YMODE[2:0] bits,10-bit/12-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " EXRGB ,Extension RGB conversion mode" "Not extended,Extended"
|
|
bitfld.long 0x08 4. " BPSM ,Output data byte swap mode" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ABIT ,Alpha bit" "0,1"
|
|
bitfld.long 0x08 0.--1. " DTMD ,Data conversion mode" "Not converted,RGB -> ARGB,YC separated,?..."
|
|
line.long 0x0C "V1DMR2,Video 1 Data Mode Register 2"
|
|
sif !cpuis("R7S72104*")||!cpuis("R7S72106*")
|
|
bitfld.long 0x0C 31. " FPS ,Field signal polarity select" "Odd/Even field,Even/Odd field"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " VPS ,Vsync signal polarity select" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " HPS ,Hsync signal polarity select" "Active low,Active high"
|
|
bitfld.long 0x0C 28. " CES ,Clock enable signal polarity select" "Active high,Active low"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 27. " DES ,Data extension select" "Expanded,Padded"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 23. " CHS ,Clock enable Hsync select" "VIn_CLKEN,Vin_HSYNC"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 22. " YDS ,YCbCr422 8-bit data input pin select" "VIn_B[7:0] pins,VIn_G[7:0] pins"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 17. " FTEV ,VSYNC field toggle mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " FTEH ,HSYNC field toggle counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--15. " VLV ,VSYNC field toggle mode transition period" "Every VSYNC,1 signal,2 signals,3 signals,4 signals,5 signals,6 signals,7 signals,8 signals,9 signals,10 signals,11 signals,12 signals,13 signals,14 signals,15 signals"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--11. 1. " HLV ,HSYNC filed toggle count value"
|
|
line.long 0x10 "V1UVAOF,Video 1 Address Offset Register"
|
|
hexmask.long 0x10 7.--31. 0x80 " UVAOF ,UV data address offset"
|
|
sif cpuis("R8A77420")
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V1CSCC1,Video 1 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V1CSCC2,Video 1 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V1CSCC3,Video 1 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
else
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V1CSCC1,Video 1 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V1CSCC2,Video 1 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V1CSCC3,Video 1 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
endif
|
|
width 9.
|
|
tree "Coefficient Set Registers"
|
|
sif !cpuis("R8A77440")
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V1C1A,Video 1 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C1B,Video 1 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C1C,Video 1 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V1C2A,Video 1 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C2B,Video 1 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C2C,Video 1 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V1C3A,Video 1 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C3B,Video 1 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C3C,Video 1 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V1C4A,Video 1 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C4B,Video 1 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C4C,Video 1 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V1C5A,Video 1 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C5B,Video 1 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C5C,Video 1 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V1C6A,Video 1 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C6B,Video 1 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C6C,Video 1 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V1C7A,Video 1 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C7B,Video 1 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C7C,Video 1 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V1C8A,Video 1 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C8B,Video 1 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C8C,Video 1 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
else
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V1C1A,Video 1 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C1B,Video 1 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C1C,Video 1 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V1C2A,Video 1 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C2B,Video 1 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C2C,Video 1 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V1C3A,Video 1 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C3B,Video 1 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C3C,Video 1 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V1C4A,Video 1 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C4B,Video 1 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C4C,Video 1 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V1C5A,Video 1 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C5B,Video 1 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C5C,Video 1 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V1C6A,Video 1 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C6B,Video 1 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C6C,Video 1 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V1C7A,Video 1 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C7B,Video 1 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C7C,Video 1 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V1C8A,Video 1 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V1C8B,Video 1 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V1C8C,Video 1 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
width 13.
|
|
sif (cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
sif !cpuis("R8A77440")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V1LUTP,Video 1 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V1LUTD,Video 1 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V1LUTP,Video 1 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V1LUTD,Video 1 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
endif
|
|
group.long 0x228++0x23
|
|
line.long 0x00 "V1YCCR1,Video 1 RGB->YC Calculation Setting Register 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " YCLRP ,R multiplication coefficient for YC calculation"
|
|
line.long 0x04 "V1YCCR2,Video 1 RGB->YC Calculation Setting Register 2"
|
|
hexmask.long.word 0x04 16.--28. 1. " YCLBP ,B multiplication coefficient for YC calculation"
|
|
hexmask.long.word 0x04 0.--12. 1. " YCLGP ,G multiplication coefficient for YC calculation"
|
|
line.long 0x08 "V1YCCR3,Video 1 RGB->YC Calculation Setting Register 3"
|
|
bitfld.long 0x08 31. " YEXPEN ,YC calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " YCLSFT ,YC calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " YCLHEN ,YC calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " YCLCEN ,YC calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--11. 1. " YCLAP ,YC calculation data normalized additional value"
|
|
line.long 0x0C "V1CBCCR1,Video 1 RGB->Cb Calculation Setting Register 1"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CBCLRP ,R multiplication coefficient for Cb calculation"
|
|
line.long 0x10 "V1CBCCR2,Video 1 RGB->Cb Calculation Setting Register 2"
|
|
hexmask.long.word 0x10 16.--28. 1. " CBCLBP ,B multiplication coefficient for CBC calculation"
|
|
hexmask.long.word 0x10 0.--12. 1. " CBCLGP ,G multiplication coefficient for CBC calculation"
|
|
line.long 0x14 "V1CBCCR3,Video 1 RGB->Cb Calculation Setting Register 3"
|
|
bitfld.long 0x14 31. " CBEXPEN ,Cb calculation Sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24.--28. " CBCLSFT ,Cb calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 23. " CBCLHEN ,Cb calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " CBCLCEN ,Cb calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--11. 1. " CBCLAP ,Cb calculation data normalized additional value"
|
|
line.long 0x18 "V1CRCCR1,Video 1 RGB->Cr Calculation Setting Register 1"
|
|
hexmask.long.word 0x18 0.--12. 1. " CRCLRP ,R multiplication coefficient for Cr calculation"
|
|
line.long 0x1C "V1CRCCR2,Video 1 RGB->Cr Calculation Setting Register 2"
|
|
hexmask.long.word 0x1C 16.--28. 1. " CRCLBP ,B multiplication coefficient for CRC calculation"
|
|
hexmask.long.word 0x1C 0.--12. 1. " CRCLGP ,G multiplication coefficient for CRC calculation"
|
|
line.long 0x20 "V1CRCCR3,Video 1 RGB->Cr Calculation Setting Register 3"
|
|
bitfld.long 0x20 31. " CRCEXPEN ,Cr calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 24.--28. " CRCLSFT ,Cr calculation shift Down Volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 23. " CRCLHEN ,Cr calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " CRCLCEN ,Cr calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CRCLAP ,Cr calculation data normalized additional value"
|
|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V1LUTP,Video 1 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V1LUTD,Video 1 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
group.long 0x228++0x23
|
|
line.long 0x00 "V1YCCR1,Video 1 RGB->YC Calculation Setting Register 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " YCLRP ,R multiplication coefficient for YC calculation"
|
|
line.long 0x04 "V1YCCR2,Video 1 RGB->YC Calculation Setting Register 2"
|
|
hexmask.long.word 0x04 16.--28. 1. " YCLBP ,B multiplication coefficient for YC calculation"
|
|
hexmask.long.word 0x04 0.--12. 1. " YCLGP ,G multiplication coefficient for YC calculation"
|
|
line.long 0x08 "V1YCCR3,Video 1 RGB->YC Calculation Setting Register 3"
|
|
bitfld.long 0x08 31. " YEXPEN ,YC calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " YCLSFT ,YC calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " YCLHEN ,YC calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " YCLCEN ,YC calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--11. 1. " YCLAP ,YC calculation data normalized additional value"
|
|
line.long 0x0C "V1CBCCR1,Video 1 RGB->Cb Calculation Setting Register 1"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CBCLRP ,R multiplication coefficient for Cb calculation"
|
|
line.long 0x10 "V1CBCCR2,Video 1 RGB->Cb Calculation Setting Register 2"
|
|
hexmask.long.word 0x10 16.--28. 1. " CBCLBP ,B multiplication coefficient for CBC calculation"
|
|
hexmask.long.word 0x10 0.--12. 1. " CBCLGP ,G multiplication coefficient for CBC calculation"
|
|
line.long 0x14 "V1CBCCR3,Video 1 RGB->Cb Calculation Setting Register 3"
|
|
bitfld.long 0x14 31. " CBEXPEN ,Cb calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24.--28. " CBCLSFT ,Cb calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 23. " CBCLHEN ,Cb calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " CBCLCEN ,Cb calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--11. 1. " CBCLAP ,Cb calculation data normalized additional value"
|
|
line.long 0x18 "V1CRCCR1,Video 1 RGB->Cr Calculation Setting Register 1"
|
|
hexmask.long.word 0x18 0.--12. 1. " CRCLRP ,R multiplication coefficient for Cr calculation"
|
|
line.long 0x1C "V1CRCCR2,Video 1 RGB->Cr Calculation Setting Register 2"
|
|
hexmask.long.word 0x1C 16.--28. 1. " CRCLBP ,B multiplication coefficient for CRC calculation"
|
|
hexmask.long.word 0x1C 0.--12. 1. " CRCLGP ,G multiplication coefficient for CRC calculation"
|
|
line.long 0x20 "V1CRCCR3,Video 1 RGB->Cr Calculation Setting Register 3"
|
|
bitfld.long 0x20 31. " CRCEXPEN ,Cr calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 24.--28. " CRCLSFT ,Cr calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 23. " CRCLHEN ,Cr calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " CRCLCEN ,Cr calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CRCLAP ,Cr calculation data normalized additional value"
|
|
endif
|
|
group.long 0x300++0x0F
|
|
line.long 0x00 "V1CSCE1,Video 1 YC->RGB Calculation Setting Extension Register 1"
|
|
hexmask.long.word 0x00 0.--13. 1. " YMUL2 ,Y multiplication coefficient 2 for RGB calculation"
|
|
line.long 0x04 "V1CSCE2,Video 1 YC->RGB Calculation Setting Extension Register 2"
|
|
hexmask.long.word 0x04 16.--27. 1. " YSUB2 ,Y subtraction coefficient 2 for RGB calculation"
|
|
hexmask.long.word 0x04 0.--11. 1. " CSUB2 ,CbCr Subtraction coefficient 2 for RGB calculation"
|
|
line.long 0x08 "V1CSCE3,Video 1 YC->RGB Calculation Setting Extension Register 3"
|
|
hexmask.long.word 0x08 16.--29. 1. " RCRMUL2 ,YCr multiplication coefficient 2 for R calculation"
|
|
hexmask.long.word 0x08 0.--13. 1. " GCRMUL2 ,Cr multiplication coefficient 2 for G calculation"
|
|
line.long 0x0C "V1CSCE4,Video 1 YC->RGB Calculation Setting Extension Register 4"
|
|
hexmask.long.word 0x0C 16.--29. 1. " GCBMUL2 ,Cb multiplication coefficient 2 for G calculation"
|
|
hexmask.long.word 0x0C 0.--13. 1. " BCBMUL2 ,Cb multiplication coefficient 2 for B calculation"
|
|
sif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "V1SRCSEL,Video 1 Input Source Selection Register"
|
|
bitfld.long 0x00 0. " SEL ,Input data selection" "LVTTL,MIPI CSI-2 output signal"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFC52000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "V2MC,Video 2 Main Control Register"
|
|
bitfld.long 0x00 31. " FAST ,High-speed video clock support mode" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("R8A774*")||cpuis("R7S7210*"))
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,No clipping"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,<=0 clipped to 1"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7790X"||cpu()=="R8A77420"
|
|
bitfld.long 0x00 25. " RIS ,RGB interface select" "Rising edge,Both edges"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7792X"
|
|
bitfld.long 0x00 23. " OMI ,Output data mask to IMR" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " OMM ,Output data mask to memory" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " FOC ,Field order control" "Odd,Even"
|
|
bitfld.long 0x00 20. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " YCAL ,YCbCr-422i Input data alignment" "Y upper/CbCr lower,Y lower/CbCr upper"
|
|
textline " "
|
|
sif cpuis("R7S7210*")
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601/BT.709 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601/BT.709 10/12-bit YCbCr-422,?,BT.601/BT.709/BT.1358 16/20/24-bit YCbCr-422,BT.601/BT.709 24-bit RGB-888,BT.601/BT.709 18-bit RGB-666"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601 10/12-bit YCbCr-422,,BT.601/BT.1358 16-bit YCbCr-422,BT.601 24-bit RGB-888,BT.601 18-bit RGB-666/12-bit RGB-888"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " DC ,Dithering mode control" "Dithering with cumulative addition,Ordered dithering,?..."
|
|
bitfld.long 0x00 12.--13. " EXINF ,Extension interface select" ",8-bit,10-bit,12-bit"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VUP ,VIN register update control" "Immediately,On valid data"
|
|
bitfld.long 0x00 6. " EN ,Endian type" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EC ,Error correction control" "No correction,Correction"
|
|
bitfld.long 0x00 3.--4. " IM ,Interlace mode" "Odd-field,Odd/even-field,Even-field,Full interlace"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BPS ,Color space conversion bypass mode" "Converted,Not converted"
|
|
bitfld.long 0x00 0. " ME ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "V2MS,Video 2 Module Status Register"
|
|
bitfld.long 0x00 3.--4. " FBS ,Frame buffer status" "1,2,3,No valid buffer"
|
|
bitfld.long 0x00 2. " FS ,Field status" "Odd field,Even field"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AV ,Active video status" "Not active,Active"
|
|
bitfld.long 0x00 0. " CA ,Video capture active status" "Inactive,Active"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "V2FC,Video 2 Frame Capture Register"
|
|
bitfld.long 0x00 1. " CC ,Continuous frame capture mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SC ,Single frame capture mode" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "V2SLPRC,Start Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPRC ,Start Line Pre-clip"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "V2ELPRC,End Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPRC ,End Line Pre-clip"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "V2SPPRC,Start Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPRC ,Start Pixel Pre-clip"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "V2EPPRC,End Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPRC ,End Pixel Pre-clip"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "V2SLPOC,Start Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPOC ,Start Line Post-clip"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "V2ELPOC,End Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPOC ,End Line Post-clip"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "V2SPPOC,Start Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPOC ,Start Pixel Post-clip"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "V2EPPOC,End Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPOC ,End Pixel Post-clip"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "V2IS,Video 2 Image Stride Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " IS ,Image stride"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "V2MB1,Video 2 Memory Base 1 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB1 ,Memory base address 1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "V2MB2,Video 2 Memory Base 2 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB2 ,Memory base address 2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "V2MB3,Video 2 Memory Base 3 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB3 ,Memory base address 3"
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "V2LC,Video 2 Line Count Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " LC ,Line count"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "V2IE,Video 2 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " FIE2 ,Field interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VFE ,VSYNC falling edge detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VRE , VSYNC rising edge detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIE ,Field interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CEE ,Correction error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Scanline interrupt Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EFE ,End of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FOE ,FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "V2INTS,Video 2 Interrupt Status Register"
|
|
bitfld.long 0x04 31. " FIS2 ,Field interrupt status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " VFS ,VSYNC falling edge detect interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VRS ,VSYNC rising edge detect interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " FIS ,Field interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CES ,Correction error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " SIS ,Scanline interrupt error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EFS ,End of frame interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " FOS ,FIFO overflow interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "V2SI,Video 2 Scanline Interrupt"
|
|
hexmask.long.word 0x08 0.--11. 1. " SI ,Scanline interrupt setting"
|
|
sif (cpu()!="RCARM2")&&(cpu()!="R8A77470")
|
|
sif cpuis("R8A774*")
|
|
if (((per.l(ad:0xFFC52000+0x4C))&0x100)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V2MTC,Video 2 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,16Byte,32Byte,,,,,,,,,,,,,240Byte"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V2MTC,Video 2 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,32Byte,64Byte,,,,,,256Byte,,,,,,,480Byte"
|
|
endif
|
|
elif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V2MTC,Video 2 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TUNIT ,Transaction unit setting" "16Byte,?"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst Size Setting" "#,,,,,,,,8 beat access,,,,,,,"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V2MTC,Video 2 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "V2YS,Video 2 Y Scale Register"
|
|
bitfld.long 0x00 12.--15. " MANTISSAY ,Mantissa of scaling ratio in the Y direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " FRACTIONY ,Fraction of scaling ratio in the Y direction"
|
|
line.long 0x04 "V2XS,Video 2 X Scale Register"
|
|
bitfld.long 0x04 12.--15. " MANTISSAX ,Mantissa of scaling ratio in the X direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " FRACTIONX ,Fraction of scaling ratio in the X direction"
|
|
line.long 0x08 "V2DMR,Video 2 Data Mode Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
hexmask.long.byte 0x08 24.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x08 25.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 16. " EVA ,Even field address offset" "Base address,Base address + memory width"
|
|
bitfld.long 0x08 12.--14. " YMODE ,YC data transfer mode" "Y and CbCr,Y 8-bit,Y 10->16-bit and CbCr,Y 10->16-bit,Y 12->16-bit and CbCr,Y 12->16-bit,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 11. " YC_THR ,YC data through mode" "YMODE[2:0] bits,10-bit/12-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " EXRGB ,Extension RGB conversion mode" "Not extended,Extended"
|
|
bitfld.long 0x08 4. " BPSM ,Output data byte swap mode" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ABIT ,Alpha bit" "0,1"
|
|
bitfld.long 0x08 0.--1. " DTMD ,Data conversion mode" "Not converted,RGB -> ARGB,YC separated,?..."
|
|
line.long 0x0C "V2DMR2,Video 2 Data Mode Register 2"
|
|
sif !cpuis("R7S72104*")||!cpuis("R7S72106*")
|
|
bitfld.long 0x0C 31. " FPS ,Field signal polarity select" "Odd/Even field,Even/Odd field"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " VPS ,Vsync signal polarity select" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " HPS ,Hsync signal polarity select" "Active low,Active high"
|
|
bitfld.long 0x0C 28. " CES ,Clock enable signal polarity select" "Active high,Active low"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 27. " DES ,Data extension select" "Expanded,Padded"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 23. " CHS ,Clock enable Hsync select" "VIn_CLKEN,Vin_HSYNC"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 22. " YDS ,YCbCr422 8-bit data input pin select" "VIn_B[7:0] pins,VIn_G[7:0] pins"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 17. " FTEV ,VSYNC field toggle mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " FTEH ,HSYNC field toggle counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--15. " VLV ,VSYNC field toggle mode transition period" "Every VSYNC,1 signal,2 signals,3 signals,4 signals,5 signals,6 signals,7 signals,8 signals,9 signals,10 signals,11 signals,12 signals,13 signals,14 signals,15 signals"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--11. 1. " HLV ,HSYNC filed toggle count value"
|
|
line.long 0x10 "V2UVAOF,Video 2 Address Offset Register"
|
|
hexmask.long 0x10 7.--31. 0x80 " UVAOF ,UV data address offset"
|
|
sif cpuis("R8A77420")
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V2CSCC1,Video 2 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V2CSCC2,Video 2 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V2CSCC3,Video 2 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
else
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V2CSCC1,Video 2 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V2CSCC2,Video 2 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V2CSCC3,Video 2 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
endif
|
|
width 9.
|
|
tree "Coefficient Set Registers"
|
|
sif !cpuis("R8A77440")
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V2C1A,Video 2 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C1B,Video 2 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C1C,Video 2 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V2C2A,Video 2 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C2B,Video 2 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C2C,Video 2 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V2C3A,Video 2 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C3B,Video 2 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C3C,Video 2 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V2C4A,Video 2 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C4B,Video 2 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C4C,Video 2 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V2C5A,Video 2 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C5B,Video 2 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C5C,Video 2 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V2C6A,Video 2 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C6B,Video 2 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C6C,Video 2 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V2C7A,Video 2 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C7B,Video 2 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C7C,Video 2 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V2C8A,Video 2 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C8B,Video 2 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C8C,Video 2 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
else
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V2C1A,Video 2 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C1B,Video 2 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C1C,Video 2 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V2C2A,Video 2 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C2B,Video 2 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C2C,Video 2 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V2C3A,Video 2 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C3B,Video 2 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C3C,Video 2 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V2C4A,Video 2 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C4B,Video 2 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C4C,Video 2 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V2C5A,Video 2 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C5B,Video 2 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C5C,Video 2 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V2C6A,Video 2 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C6B,Video 2 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C6C,Video 2 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V2C7A,Video 2 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V2C7B,Video 2 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V2C7C,Video 2 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
width 13.
|
|
sif (cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
sif !cpuis("R8A77440")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V2LUTP,Video 2 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V2LUTD,Video 2 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
else
|
|
endif
|
|
else
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V2LUTP,Video 2 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V2LUTD,Video 2 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
group.long 0x228++0x23
|
|
line.long 0x00 "V2YCCR1,Video 2 RGB->YC Calculation Setting Register 1"
|
|
hexmask.long.word 0x00 0.--12. 1. " YCLRP ,R multiplication coefficient for YC calculation"
|
|
line.long 0x04 "V2YCCR2,Video 2 RGB->YC Calculation Setting Register 2"
|
|
hexmask.long.word 0x04 16.--28. 1. " YCLBP ,B multiplication coefficient for YC calculation"
|
|
hexmask.long.word 0x04 0.--12. 1. " YCLGP ,G multiplication coefficient for YC calculation"
|
|
line.long 0x08 "V2YCCR3,Video 2 RGB->YC Calculation Setting Register 3"
|
|
bitfld.long 0x08 31. " YEXPEN ,YC calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " YCLSFT ,YC calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x08 23. " YCLHEN ,YC calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " YCLCEN ,YC calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--11. 1. " YCLAP ,YC calculation data normalized additional value"
|
|
line.long 0x0C "V2CBCCR1,Video 2 RGB->Cb Calculation Setting Register 1"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CBCLRP ,R multiplication coefficient for Cb calculation"
|
|
line.long 0x10 "V2CBCCR2,Video 2 RGB->Cb Calculation Setting Register 2"
|
|
hexmask.long.word 0x10 16.--28. 1. " CBCLBP ,B multiplication coefficient for CBC calculation"
|
|
hexmask.long.word 0x10 0.--12. 1. " CBCLGP ,G multiplication coefficient for CBC calculation"
|
|
line.long 0x14 "V2CBCCR3,Video 2 RGB->Cb Calculation Setting Register 3"
|
|
bitfld.long 0x14 31. " CBEXPEN ,Cb calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24.--28. " CBCLSFT ,Cb calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x14 23. " CBCLHEN ,Cb calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " CBCLCEN ,Cb calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--11. 1. " CBCLAP ,Cb calculation data normalized additional value"
|
|
line.long 0x18 "V2CRCCR1,Video 2 RGB->Cr Calculation Setting Register 1"
|
|
hexmask.long.word 0x18 0.--12. 1. " CRCLRP ,R multiplication coefficient for Cr calculation"
|
|
line.long 0x1C "V2CRCCR2,Video 2 RGB->Cr Calculation Setting Register 2"
|
|
hexmask.long.word 0x1C 16.--28. 1. " CRCLBP ,B multiplication coefficient for CRC calculation"
|
|
hexmask.long.word 0x1C 0.--12. 1. " CRCLGP ,G multiplication coefficient for CRC calculation"
|
|
line.long 0x20 "V2CRCCR3,Video 2 RGB->Cr Calculation Setting Register 3"
|
|
bitfld.long 0x20 31. " CRCEXPEN ,Cr calculation sign extension enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 24.--28. " CRCLSFT ,Cr calculation shift down volume" "0,1,2,3,4,5,6,7,8,10,11,12,13,14,15,?..."
|
|
textline " "
|
|
bitfld.long 0x20 23. " CRCLHEN ,Cr calculation shift down result round-off enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " CRCLCEN ,Cr calculation data clip enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--11. 1. " CRCLAP ,Cr calculation data normalized additional value"
|
|
endif
|
|
sif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "V2SRCSEL,Video 2 Input Source Selection Register"
|
|
bitfld.long 0x00 0. " SEL ,Input data selection" "LVTTL,MIPI CSI-2 output signal"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFC53000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "V3MC,Video 3 Main Control Register"
|
|
bitfld.long 0x00 31. " FAST ,High-speed video clock support mode" "Not supported,Supported"
|
|
textline " "
|
|
sif (cpuis("R8A774*")||cpuis("R7S7210*"))
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,No clipping"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 28.--29. " CLP ,Pixel data clipping" "No clipping,<16 clipped to 16/>=240 clipped to 240,No clipping,<=0 clipped to 1"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7790X"||cpu()=="R8A77420"
|
|
bitfld.long 0x00 25. " RIS ,RGB interface select" "Rising edge,Both edges"
|
|
textline " "
|
|
endif
|
|
sif cpu()=="R8A7792X"
|
|
bitfld.long 0x00 23. " OMI ,Output data mask to IMR" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " OMM ,Output data mask to memory" "Enabled,Disabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " FOC ,Field order control" "Odd,Even"
|
|
bitfld.long 0x00 20. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " YCAL ,YCbCr-422i Input data alignment" "Y upper/CbCr lower,Y lower/CbCr upper"
|
|
textline " "
|
|
sif cpuis("R7S7210*")
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601/BT.709 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601/BT.709 10/12-bit YCbCr-422,?,BT.601/BT.709/BT.1358 16/20/24-bit YCbCr-422,BT.601/BT.709 24-bit RGB-888,BT.601/BT.709 18-bit RGB-666"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16.--18. " INF ,Input interface format" "BT.656 8-bit YCbCr-422,BT.601 8-bit YCbCr-422,BT.656 10/12-bit YCbCr-422,BT.601 10/12-bit YCbCr-422,,BT.601/BT.1358 16-bit YCbCr-422,BT.601 24-bit RGB-888,BT.601 18-bit RGB-666/12-bit RGB-888"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 14.--15. " DC ,Dithering mode control" "Dithering with cumulative addition,Ordered dithering,?..."
|
|
bitfld.long 0x00 12.--13. " EXINF ,Extension interface select" ",8-bit,10-bit,12-bit"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VUP ,VIN register update control" "Immediately,On valid data"
|
|
bitfld.long 0x00 6. " EN ,Endian type" "Little,Big"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EC ,Error correction control" "No correction,Correction"
|
|
bitfld.long 0x00 3.--4. " IM ,Interlace mode" "Odd-field,Odd/even-field,Even-field,Full interlace"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BPS ,Color space conversion bypass mode" "Converted,Not converted"
|
|
bitfld.long 0x00 0. " ME ,Module enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "V3MS,Video 3 Module Status Register"
|
|
bitfld.long 0x00 3.--4. " FBS ,Frame buffer status" "1,2,3,No valid buffer"
|
|
bitfld.long 0x00 2. " FS ,Field status" "Odd field,Even field"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AV ,Active video status" "Not active,Active"
|
|
bitfld.long 0x00 0. " CA ,Video capture active status" "Inactive,Active"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "V3FC,Video 3 Frame Capture Register"
|
|
bitfld.long 0x00 1. " CC ,Continuous frame capture mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SC ,Single frame capture mode" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "V3SLPRC,Start Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPRC ,Start Line Pre-clip"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "V3ELPRC,End Line Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPRC ,End Line Pre-clip"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "V3SPPRC,Start Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPRC ,Start Pixel Pre-clip"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "V3EPPRC,End Pixel Pre-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPRC ,End Pixel Pre-clip"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "V3SLPOC,Start Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SLPOC ,Start Line Post-clip"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "V3ELPOC,End Line Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " ELPOC ,End Line Post-clip"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "V3SPPOC,Start Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " SPPOC ,Start Pixel Post-clip"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "V3EPPOC,End Pixel Post-Clip Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPPOC ,End Pixel Post-clip"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "V3IS,Video 3 Image Stride Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " IS ,Image stride"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "V3MB1,Video 3 Memory Base 1 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB1 ,Memory base address 1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "V3MB2,Video 3 Memory Base 2 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB2 ,Memory base address 2"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "V3MB3,Video 3 Memory Base 3 Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " MB3 ,Memory base address 3"
|
|
rgroup.long 0x3c++0x03
|
|
line.long 0x00 "V3LC,Video 3 Line Count Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " LC ,Line count"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "V3IE,Video 3 Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " FIE2 ,Field interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VFE ,VSYNC falling edge detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VRE , VSYNC rising edge detect interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIE ,Field interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CEE ,Correction error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SIE ,Scanline interrupt Error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EFE ,End of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FOE ,FIFO overflow interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "V3INTS,Video 3 Interrupt Status Register"
|
|
bitfld.long 0x04 31. " FIS2 ,Field interrupt status 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " VFS ,VSYNC falling edge detect interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 16. " VRS ,VSYNC rising edge detect interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " FIS ,Field interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CES ,Correction error interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " SIS ,Scanline interrupt error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " EFS ,End of frame interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " FOS ,FIFO overflow interrupt status" "No interrupt,Interrupt"
|
|
line.long 0x08 "V3SI,Video 3 Scanline Interrupt"
|
|
hexmask.long.word 0x08 0.--11. 1. " SI ,Scanline interrupt setting"
|
|
sif (cpu()!="RCARM2")&&(cpu()!="R8A77470")
|
|
sif cpuis("R8A774*")
|
|
if (((per.l(ad:0xFFC53000+0x4C))&0x100)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V3MTC,Video 3 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,16Byte,32Byte,,,,,,,,,,,,,240Byte"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V3MTC,Video 3 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SIZE ,Transaction size unit setting" "16Byte,32Byte"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst size setting" "No transfer,32Byte,64Byte,,,,,,256Byte,,,,,,,480Byte"
|
|
endif
|
|
elif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V3MTC,Video 3 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TUNIT ,Transaction unit setting" "16Byte,?"
|
|
bitfld.long 0x00 0.--3. " BSIZE ,Burst Size Setting" "#,,,,,,,,8 beat access,,,,,,,"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "V3MTC,Video 3 Memory Transfer Control Register"
|
|
bitfld.long 0x00 24.--27. " PRIH ,Priority high level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PRIL ,Priority low level value setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x50++0x13
|
|
line.long 0x00 "V3YS,Video 3 Y Scale Register"
|
|
bitfld.long 0x00 12.--15. " MANTISSAY ,Mantissa of scaling ratio in the Y direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " FRACTIONY ,Fraction of scaling ratio in the Y direction"
|
|
line.long 0x04 "V3XS,Video 3 X Scale Register"
|
|
bitfld.long 0x04 12.--15. " MANTISSAX ,Mantissa of scaling ratio in the X direction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x04 0.--11. 1. " FRACTIONX ,Fraction of scaling ratio in the X direction"
|
|
line.long 0x08 "V3DMR,Video 3 Data Mode Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
hexmask.long.byte 0x08 24.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
else
|
|
hexmask.long.byte 0x08 25.--31. 1. " A8BIT ,Alpha 8- alpha value for the ARGB8888 format output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 16. " EVA ,Even field address offset" "Base address,Base address + memory width"
|
|
bitfld.long 0x08 12.--14. " YMODE ,YC data transfer mode" "Y and CbCr,Y 8-bit,Y 10->16-bit and CbCr,Y 10->16-bit,Y 12->16-bit and CbCr,Y 12->16-bit,?..."
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 11. " YC_THR ,YC data through mode" "YMODE[2:0] bits,10-bit/12-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 8. " EXRGB ,Extension RGB conversion mode" "Not extended,Extended"
|
|
bitfld.long 0x08 4. " BPSM ,Output data byte swap mode" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ABIT ,Alpha bit" "0,1"
|
|
bitfld.long 0x08 0.--1. " DTMD ,Data conversion mode" "Not converted,RGB -> ARGB,YC separated,?..."
|
|
line.long 0x0C "V3DMR2,Video 3 Data Mode Register 2"
|
|
sif !cpuis("R7S72104*")||!cpuis("R7S72106*")
|
|
bitfld.long 0x0C 31. " FPS ,Field signal polarity select" "Odd/Even field,Even/Odd field"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 30. " VPS ,Vsync signal polarity select" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " HPS ,Hsync signal polarity select" "Active low,Active high"
|
|
bitfld.long 0x0C 28. " CES ,Clock enable signal polarity select" "Active high,Active low"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 27. " DES ,Data extension select" "Expanded,Padded"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 23. " CHS ,Clock enable Hsync select" "VIn_CLKEN,Vin_HSYNC"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
bitfld.long 0x0C 22. " YDS ,YCbCr422 8-bit data input pin select" "VIn_B[7:0] pins,VIn_G[7:0] pins"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 17. " FTEV ,VSYNC field toggle mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " FTEH ,HSYNC field toggle counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--15. " VLV ,VSYNC field toggle mode transition period" "Every VSYNC,1 signal,2 signals,3 signals,4 signals,5 signals,6 signals,7 signals,8 signals,9 signals,10 signals,11 signals,12 signals,13 signals,14 signals,15 signals"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--11. 1. " HLV ,HSYNC filed toggle count value"
|
|
line.long 0x10 "V3UVAOF,Video 3 Address Offset Register"
|
|
hexmask.long 0x10 7.--31. 0x80 " UVAOF ,UV data address offset"
|
|
sif cpuis("R8A77420")
|
|
else
|
|
group.long 0x64++0x0B
|
|
line.long 0x00 "V3CSCC1,Video 3 Color Space Change Coefficient 1 Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " YMUL ,Y data multiplication coefficient"
|
|
hexmask.long.byte 0x00 8.--15. 1. " YSUB ,Y data subtraction coefficient"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CSUB ,CbCr data subtraction coefficient"
|
|
line.long 0x04 "V3CSCC2,Video 3 Color Space Change Coefficient 2 Register"
|
|
hexmask.long.word 0x04 16.--25. 1. " RCRMUL ,Cr multiplication coefficient for R data calculation"
|
|
hexmask.long.word 0x04 0.--9. 1. " GCRMUL ,Cr multiplication coefficient for G data calculation"
|
|
line.long 0x08 "V3CSCC3,Video 3 Color Space Change Coefficient 3 Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " GCBMUL ,Cb multiplication coefficient for G data calculation"
|
|
hexmask.long.word 0x08 0.--9. 1. " BCBMUL ,Cb multiplication coefficient for B data calculation"
|
|
endif
|
|
width 9.
|
|
tree "Coefficient Set Registers"
|
|
sif !cpuis("R8A77440")
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V3C1A,Video 3 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C1B,Video 3 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C1C,Video 3 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V3C2A,Video 3 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C2B,Video 3 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C2C,Video 3 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V3C3A,Video 3 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C3B,Video 3 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C3C,Video 3 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V3C4A,Video 3 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C4B,Video 3 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C4C,Video 3 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V3C5A,Video 3 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C5B,Video 3 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C5C,Video 3 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V3C6A,Video 3 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C6B,Video 3 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C6C,Video 3 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V3C7A,Video 3 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C7B,Video 3 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C7C,Video 3 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 8"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "V3C8A,Video 3 Coefficient Set C8A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C8B,Video 3 Coefficient Set C8B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C8C,Video 3 Coefficient Set C8C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
else
|
|
tree "Coefficient 1"
|
|
group.long 0x80++0x0B
|
|
line.long 0x00 "V3C1A,Video 3 Coefficient Set C1A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C1B,Video 3 Coefficient Set C1B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C1C,Video 3 Coefficient Set C1C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 2"
|
|
group.long 0x90++0x0B
|
|
line.long 0x00 "V3C2A,Video 3 Coefficient Set C2A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C2B,Video 3 Coefficient Set C2B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C2C,Video 3 Coefficient Set C2C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 3"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "V3C3A,Video 3 Coefficient Set C3A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C3B,Video 3 Coefficient Set C3B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C3C,Video 3 Coefficient Set C3C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 4"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "V3C4A,Video 3 Coefficient Set C4A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C4B,Video 3 Coefficient Set C4B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C4C,Video 3 Coefficient Set C4C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 5"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "V3C5A,Video 3 Coefficient Set C5A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C5B,Video 3 Coefficient Set C5B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C5C,Video 3 Coefficient Set C5C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 6"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "V3C6A,Video 3 Coefficient Set C6A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C6B,Video 3 Coefficient Set C6B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C6C,Video 3 Coefficient Set C6C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
tree "Coefficient 7"
|
|
group.long 0xE0++0x0B
|
|
line.long 0x00 "V3C7A,Video 3 Coefficient Set C7A Register"
|
|
hexmask.long.word 0x00 20.--29. 1. " L1 ,L1 coefficient"
|
|
hexmask.long.word 0x00 10.--19. 1. " L2 ,L2 coefficient"
|
|
hexmask.long.word 0x00 0.--9. 1. " L3 ,L3 coefficient"
|
|
line.long 0x04 "V3C7B,Video 3 Coefficient Set C7B Register"
|
|
hexmask.long.word 0x04 20.--29. 1. " R1 ,R1 coefficient"
|
|
hexmask.long.word 0x04 10.--19. 1. " R2 ,R2 coefficient"
|
|
hexmask.long.word 0x04 0.--9. 1. " R3 ,R3 coefficient"
|
|
line.long 0x08 "V3C7C,Video 3 Coefficient Set C7C Register"
|
|
hexmask.long.word 0x08 20.--29. 1. " R4 ,R4 coefficient"
|
|
hexmask.long.word 0x08 10.--19. 1. " L4 ,L4 coefficient"
|
|
hexmask.long.word 0x08 0.--9. 1. " M ,M coefficient"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
width 13.
|
|
sif (cpu()=="R8A7792X")||cpuis("R8A774*")||cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
sif !cpuis("R8A77440")
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "V3LUTP,Video 3 Lookup Table Pointer"
|
|
hexmask.long.word 0x00 20.--29. 1. " LTYPR ,Lookup table Y pointer"
|
|
hexmask.long.word 0x00 10.--19. 1. " LTCBPR ,Lookup table Cb pointer"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " LTCRPR ,Lookup table Cr pointer"
|
|
line.long 0x04 "V3LUTD,Video 3 Lookup Table Data Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LTYDT ,Lookup table Y data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " LTCBDT ,Lookup table Cb data"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " LTCRDT ,Lookup table Cr data"
|
|
else
|
|
endif
|
|
else
|
|
endif
|
|
sif cpuis("R7S72104*")||cpuis("R7S72106*")
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "V3SRCSEL,Video 3 Input Source Selection Register"
|
|
bitfld.long 0x00 0. " SEL ,Input data selection" "LVTTL,MIPI CSI-2 output signal"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "IMR-X (Distortion Correction Engine)"
|
|
tree "Channel 0"
|
|
base ad:0xFFEE0000
|
|
width 9.
|
|
tree "Control Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Rendering Start" "Not started,Started"
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 2. " INT ,INT Instruction Decode" "Not decoded,Decoded"
|
|
bitfld.long 0x00 1. " IER ,Illegal Instruction Decode" "Not decoded,Decoded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRA ,Trap- rendering operation completed" "Not started/Not completed,Completed"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SRCR,Status Clear Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFOCLR ,Line Memory Frame Overflow Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LMOCLR ,Line Memory Mesh Overflow Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " INTCLR ,INT Instruction Decode Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " IERCLR ,Illegal Instruction Decode Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRACLR ,Rendering Operation Completed Flag Clear" "No effect,Clear"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ICR,Interrupt Control Register"
|
|
bitfld.long 0x00 2. " INTENB ,INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IERENB ,IER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRAENB ,TRA Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IMR,Interrupt Mask Enable"
|
|
bitfld.long 0x04 2. " INM ,INT Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " IEM ,IER Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRAM ,TA Interrupt Mask" "Not masked,Masked"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "DLSP,DL Stack Pointer Register"
|
|
endif
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DLPR,DL Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EDLR,Executed DL Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDL ,Executed DL status"
|
|
endif
|
|
tree.end
|
|
tree "Memory Control Registers"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DLSAR,DL Start Address Register"
|
|
hexmask.long 0x00 3.--31. 0x8 " DLSA ,DL Start Address"
|
|
line.long 0x04 "DSAR,Destination Start Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " DSA ,Destination Start Address"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SSAR,Source Start Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " SSAR ,SRC Area Start Address"
|
|
group.long 0x3c++0x07
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " DSTR ,Memory width of the DST area"
|
|
line.long 0x04 "SSTR,Source Stride Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " SSTR ,Memory width of the SRC area"
|
|
tree.end
|
|
tree "Rendering Control Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CMRCR,Rendering Mode Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CFS_set/clr ,Color Format Select" "YUV,RGB"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " YCM_set/clr ,YC Mode" "Y,UV"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " UVS_set/clr ,UV Select" "YUV422,YUV420"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SY10_set/clr ,Luminance processing precision in the source side" "8-bbp,10-bbp"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DY10_set/clr ,Luminance processing precision in the destination side" "8-bbp,10-bbp"
|
|
sif (cpu()=="RCARH2")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RGBS_set/clr ,RGB Select" "ARGB1555,RGB565"
|
|
else
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RGBS_set/clr ,RGB Select" "RGB565,Separate Y/UV"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRIMR,Triangle Mode Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TCM_set/clr ,Triangle Clockwise Mode" "Counter clockwise,Clockwise"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DUDVM_set/clr ,Relative Source Specification Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DXDYM_set/clr ,Relative Destination Specification Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AUTOSG_set/clr ,Automatic Source Coordinate Generation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AUTODG_set/clr ,Automatic Destination Coordinate Generation Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " BFE_set/clr ,Bilinear Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TME_set/clr ,Texture Mapping Enable" "Disabled,Enabled"
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "TRICR,Triangle Color Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TCOL ,Triangle Drawing Color"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "UVDPOR,Source and Destination Coordinate Decimal Point Register"
|
|
bitfld.long 0x00 0.--2. " UVDPO ,Source Coordinate Decimal Point" "0,1,2,3,4,5,?..."
|
|
line.long 0x04 "SUSR,Width Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " SUW ,Source width - 2"
|
|
hexmask.long.word 0x04 0.--10. 1. " SYVWRW ,Source width - 1"
|
|
line.long 0x08 "SVSR,Source Height Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " SVSR ,Height (vertical size) of the source"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
else
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
endif
|
|
sif (cpu()=="RCARH2")
|
|
hexmask.long.word 0x0c 0.--10. 1. " YMAX ,Y Clip MAX"
|
|
else
|
|
hexmask.long.word 0x0c 0.--9. 1. " YMAX ,Y Clip MAX"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
else
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "LINEMR,Line mode register"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EOLS_set/clr ,Line End Drawing Mode" "No last vertex,Last vertex"
|
|
tree.end
|
|
sif (cpu()!="RCARH2")&&(cpu()!="R8A7792X")
|
|
tree "Bud Access Control Register"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "MACR1,Memory Access Control Register 1"
|
|
bitfld.long 0x00 31. " QWSWPI ,Selects the endian of 64-bit units of 128 bits in the instruction fetch field (DL)" "Big,Little"
|
|
bitfld.long 0x00 30. " QWSWPIC ,Selects the endian of 64-bit units of 128 bits for pixels" "Big,Little"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMAM ,Extended Memory Address Mode" "29-bit address,32-bit address"
|
|
bitfld.long 0x00 9. " LWSWAP ,Selects the endian of a 64-bit unit in the instruction fetch field (DL)" "Big,Little"
|
|
line.long 0x04 "MACR2,Memory Access Control Register 2"
|
|
bitfld.long 0x04 15. " EDSWP ,Selects the endian of a 64-bit unit for pixels" "Big,Little"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Rendering Correction Registers"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "YLMINR,Minimum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMIN ,Minimum luminance value when luminance correction is applied"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "UBMINR,Minimum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMIN ,Minimum U value when hue correction is applied"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "VRMINR,Minimum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMIN ,Minimum V value when hue correction is applied"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "YLMAXR,Maximum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMAX ,Maximum luminance value when luminance correction is applied"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "UBMAXR,Maximum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMAX ,Maximum U value when hue correction is applied"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "VRMAXR,Maximum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMAX ,Maximum V value when hue correction is applied"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CPDPOR,Correction Decimal Point Register"
|
|
bitfld.long 0x00 8.--10. " YLDPO ,Number of bits after the decimal point for the value specified as the luminance correction scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " UBDPO ,Number of bits after the decimal point for the value specified as the hue correction U value scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " VRDPO ,Number of bits after the decimal point for the value specified as the hue correction V value scale value" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "YLCPR,Luminance Correction Parameter Y Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LSCAL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOFST ,Offset parameter"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "UBCPR,Hue Correction Parameter U Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " UBSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " UBOFS ,Offset parameter"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "VRCPR,Hue Correction Parameter V Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VRSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VROFS ,Offset parameter"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Lookup Table Data Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "LUTDR,Lookup Table Data Register"
|
|
button "LUT" "d (x+0x1000)--(x+0x1FFC) /long"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFEF0000
|
|
width 9.
|
|
tree "Control Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Rendering Start" "Not started,Started"
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 2. " INT ,INT Instruction Decode" "Not decoded,Decoded"
|
|
bitfld.long 0x00 1. " IER ,Illegal Instruction Decode" "Not decoded,Decoded"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRA ,Trap- rendering operation completed" "Not started/Not completed,Completed"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SRCR,Status Clear Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFOCLR ,Line Memory Frame Overflow Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LMOCLR ,Line Memory Mesh Overflow Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " INTCLR ,INT Instruction Decode Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " IERCLR ,Illegal Instruction Decode Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRACLR ,Rendering Operation Completed Flag Clear" "No effect,Clear"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ICR,Interrupt Control Register"
|
|
bitfld.long 0x00 2. " INTENB ,INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IERENB ,IER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRAENB ,TRA Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IMR,Interrupt Mask Enable"
|
|
bitfld.long 0x04 2. " INM ,INT Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " IEM ,IER Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRAM ,TA Interrupt Mask" "Not masked,Masked"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "DLSP,DL Stack Pointer Register"
|
|
endif
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DLPR,DL Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EDLR,Executed DL Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDL ,Executed DL status"
|
|
endif
|
|
tree.end
|
|
tree "Memory Control Registers"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DLSAR,DL Start Address Register"
|
|
hexmask.long 0x00 3.--31. 0x8 " DLSA ,DL Start Address"
|
|
line.long 0x04 "DSAR,Destination Start Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " DSA ,Destination Start Address"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SSAR,Source Start Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " SSAR ,SRC Area Start Address"
|
|
group.long 0x3c++0x07
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " DSTR ,Memory width of the DST area"
|
|
line.long 0x04 "SSTR,Source Stride Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " SSTR ,Memory width of the SRC area"
|
|
tree.end
|
|
tree "Rendering Control Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CMRCR,Rendering Mode Register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CFS_set/clr ,Color Format Select" "YUV,RGB"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " YCM_set/clr ,YC Mode" "Y,UV"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " UVS_set/clr ,UV Select" "YUV422,YUV420"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SY10_set/clr ,Luminance processing precision in the source side" "8-bbp,10-bbp"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DY10_set/clr ,Luminance processing precision in the destination side" "8-bbp,10-bbp"
|
|
sif (cpu()=="RCARH2")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RGBS_set/clr ,RGB Select" "ARGB1555,RGB565"
|
|
else
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " RGBS_set/clr ,RGB Select" "RGB565,Separate Y/UV"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRIMR,Triangle Mode Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TCM_set/clr ,Triangle Clockwise Mode" "Counter clockwise,Clockwise"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DUDVM_set/clr ,Relative Source Specification Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DXDYM_set/clr ,Relative Destination Specification Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AUTOSG_set/clr ,Automatic Source Coordinate Generation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AUTODG_set/clr ,Automatic Destination Coordinate Generation Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " BFE_set/clr ,Bilinear Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TME_set/clr ,Texture Mapping Enable" "Disabled,Enabled"
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "TRICR,Triangle Color Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TCOL ,Triangle Drawing Color"
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "UVDPOR,Source and Destination Coordinate Decimal Point Register"
|
|
bitfld.long 0x00 0.--2. " UVDPO ,Source Coordinate Decimal Point" "0,1,2,3,4,5,?..."
|
|
line.long 0x04 "SUSR,Width Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " SUW ,Source width - 2"
|
|
hexmask.long.word 0x04 0.--10. 1. " SYVWRW ,Source width - 1"
|
|
line.long 0x08 "SVSR,Source Height Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " SVSR ,Height (vertical size) of the source"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
else
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
endif
|
|
sif (cpu()=="RCARH2")
|
|
hexmask.long.word 0x0c 0.--10. 1. " YMAX ,Y Clip MAX"
|
|
else
|
|
hexmask.long.word 0x0c 0.--9. 1. " YMAX ,Y Clip MAX"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
else
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "LINEMR,Line mode register"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " EOLS_set/clr ,Line End Drawing Mode" "No last vertex,Last vertex"
|
|
tree.end
|
|
sif (cpu()!="RCARH2")&&(cpu()!="R8A7792X")
|
|
tree "Bud Access Control Register"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "MACR1,Memory Access Control Register 1"
|
|
bitfld.long 0x00 31. " QWSWPI ,Selects the endian of 64-bit units of 128 bits in the instruction fetch field (DL)" "Big,Little"
|
|
bitfld.long 0x00 30. " QWSWPIC ,Selects the endian of 64-bit units of 128 bits for pixels" "Big,Little"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMAM ,Extended Memory Address Mode" "29-bit address,32-bit address"
|
|
bitfld.long 0x00 9. " LWSWAP ,Selects the endian of a 64-bit unit in the instruction fetch field (DL)" "Big,Little"
|
|
line.long 0x04 "MACR2,Memory Access Control Register 2"
|
|
bitfld.long 0x04 15. " EDSWP ,Selects the endian of a 64-bit unit for pixels" "Big,Little"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Rendering Correction Registers"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "YLMINR,Minimum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMIN ,Minimum luminance value when luminance correction is applied"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "UBMINR,Minimum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMIN ,Minimum U value when hue correction is applied"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "VRMINR,Minimum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMIN ,Minimum V value when hue correction is applied"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "YLMAXR,Maximum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMAX ,Maximum luminance value when luminance correction is applied"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "UBMAXR,Maximum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMAX ,Maximum U value when hue correction is applied"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "VRMAXR,Maximum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMAX ,Maximum V value when hue correction is applied"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CPDPOR,Correction Decimal Point Register"
|
|
bitfld.long 0x00 8.--10. " YLDPO ,Number of bits after the decimal point for the value specified as the luminance correction scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " UBDPO ,Number of bits after the decimal point for the value specified as the hue correction U value scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " VRDPO ,Number of bits after the decimal point for the value specified as the hue correction V value scale value" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "YLCPR,Luminance Correction Parameter Y Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LSCAL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOFST ,Offset parameter"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "UBCPR,Hue Correction Parameter U Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " UBSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " UBOFS ,Offset parameter"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "VRCPR,Hue Correction Parameter V Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VRSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VROFS ,Offset parameter"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Lookup Table Data Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "LUTDR,Lookup Table Data Register"
|
|
button "LUT" "d (x+0x1000)--(x+0x1FFC) /long"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "IMR-LSX (Distortion Correction Engine)"
|
|
tree "Channel 0"
|
|
base ad:0xFFEC0000
|
|
width 9.
|
|
tree "Control Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " SFE ,Separate Field Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARS ,Auto Rendering Start" "No,Yes"
|
|
bitfld.long 0x00 0. " RS ,Rendering Start" "Not started,Started"
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFO ,Line Memory Frame Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 8. " LMO ,Line Memory Mesh Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.long 0x00 7. " SFS ,Separate Field" "Even,Odd"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 5. " REN ,Drawing-in-Progress Flag" "Not in progress,In progress"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSA ,Destination Start Address" "DSAR,DSAR2"
|
|
bitfld.long 0x00 2. " INT ,INT Instruction Decode" "Not decoded,Decoded"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IER ,Illegal Instruction Decode" "Not decoded,Decoded"
|
|
bitfld.long 0x00 0. " TRA ,Trap - rendering operation completed" "Not started/Not completed,Completed"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SRCR,Status Clear Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFOCLR ,Line Memory Frame Overflow Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LMOCLR ,Line Memory Mesh Overflow Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " INTCLR ,INT Instruction Decode Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " IERCLR ,Illegal Instruction Decode Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRACLR ,Rendering Operation Completed Flag Clear" "No effect,Clear"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ICR,Interrupt Control Register"
|
|
bitfld.long 0x00 2. " INTENB ,INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IERENB ,IER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRAENB ,TRA Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IMR,Interrupt Mask Enable"
|
|
bitfld.long 0x04 2. " INM ,INT Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " IEM ,IER Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRAM ,TA Interrupt Mask" "Not masked,Masked"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "DLSP,DL Stack Pointer Register"
|
|
endif
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DLPR,DL Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EDLR,Executed DL Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDL ,Executed DL status"
|
|
endif
|
|
tree.end
|
|
tree "Memory Control Registers"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DLSAR,DL Start Address Register"
|
|
hexmask.long 0x00 3.--31. 0x8 " DLSA ,DL Start Address"
|
|
line.long 0x04 "DSAR,Destination Start Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " DSA ,Destination Start Address"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SSAR,Source Start Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " SSAR ,SRC Area Start Address"
|
|
group.long 0x3c++0x07
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DSTR ,Memory width of the DST area"
|
|
line.long 0x04 "SSTR,Source Stride Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " SSTR ,Memory width of the SRC area"
|
|
else
|
|
group.long 0x3c++0x03
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " DST ,Memory width of the DST area"
|
|
endif
|
|
group.long 0x48++0x0b
|
|
line.long 0x00 "DSAR2,Destination Start Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " DSA2 ,Destination Start Address 2"
|
|
line.long 0x04 "DLSAR2,DL Start Address Register 2"
|
|
hexmask.long 0x04 3.--31. 0x8 " DLSA2 ,DL Start Address"
|
|
line.long 0x08 "DSOR,Destination Start Offset Address Register"
|
|
hexmask.long 0x08 5.--31. 0x20 " DSOFSTA ,Destination Start Offset Address"
|
|
tree.end
|
|
tree "Rendering Control Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CMRCR,Rendering Mode Register"
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " CLSM_set/clr ,Hue Correction Scale Parameter Register Specification Mode" "DL,UBCPR/VRCPR"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CLOM_set/clr ,Hue Correction Offset Parameter Register Specification Mode" "DL,UBCPR/VRCPR"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " LUSM_set/clr ,Luminance Correction Scale Parameter Register Specification Mode" "DL,YLCPR"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " LUOM_set/clr ,Luminance Correction Offset Parameter Register Specification Mode" "DL,YLCPR"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CP16E_set/clr ,Copy 16-bit Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " YCM_set/clr ,YC Mode" "Y,UV"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " SY12_set/clr ,Luminance Processing of Source Data Precision" "8-bpp/10-bpp,12-bpp"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SY10_set/clr ,Luminance Processing of Source Data Precision" "8-bpp/12-bpp,10-bpp"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " YOM_set/clr ,CbCr Data Output Mode" "Y and CbCr data,Y data"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " Y12_set/clr ,Sets the precision of Y data when it is output" "8-bpp,12-bpp"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " Y10_set/clr ,Sets the precision of Y data when it is output" "8-bpp,10-bpp"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " YISM_set/clr ,Selects the output format for YUV data" "Interleave YUV,Separate Y/UV"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 5.--6. 0x04 5.--6. 0x08 5.--6. " SUV ,Color Difference Processing of Source Data Precision" "8-bpp,10-bpp,12-bpp,?..."
|
|
setclrfld.long 0x00 3.--4. 0x04 3.--4. 0x08 3.--4. " DUV ,Color Difference of Output Data Precision" "8-bpp,10-bpp,12-bpp,?..."
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CLCE ,Hue Correction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " LUCE ,Luminance Correction Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXTM ,Texture Data Read Memory" "Line,External"
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CMRCR2,Rendering Mode Register 2"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRIMR,Triangle Mode Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TCM_set/clr ,Triangle Clockwise Mode" "Counter clockwise,Clockwise"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DUDVM_set/clr ,Relative Source Specification Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DXDYM_set/clr ,Relative Destination Specification Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AUTOSG_set/clr ,Automatic Source Coordinate Generation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AUTODG_set/clr ,Automatic Destination Coordinate Generation Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " BFE_set/clr ,Bilinear Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TME_set/clr ,Texture Mapping Enable" "Disabled,Enabled"
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "TRICR,Triangle Color Register"
|
|
bitfld.long 0x00 31. " YCFORM ,For interleave output changes the order of Y and U/V" "Not changed,Changed"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 26.--27. " TCY3 ,When Y is to be output in 12 bpp specifies bits 11 and 10 of color Y for single-color drawing" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--25. " TCY2 ,When Y is to be output in 10 bits specifies the upper 2 bits of color Y for monochrome drawing" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCV ,Specifies color V for monochrome drawing with the TRI instruction"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TCU ,Specifies color U for monochrome drawing with the TRI instruction"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCY ,Specifies color Y for monochrome drawing with the TRI instruction"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRICR2,Triangle Color Register 2 "
|
|
bitfld.long 0x00 26.--27. " TCV12 ,When V is to be output in 12 bpp specifies bits 11 and 10 of color V for single-color drawing" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. " TCV10 ,When U is to be output in 12 bpp specifies bits 11 and 10 of color U for single-color drawing"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TCU12 ,When U is to be output in 12 bpp specifies bits 11 and 10 of color U for single-color drawing" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--9. 1. " TCU10 ,When U is to be output in 10/12 bpp specifies bits 9 to 0 of color U for single-color drawing"
|
|
endif
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "UVDPOR,Source and Destination Coordinate Decimal Point Register"
|
|
bitfld.long 0x00 8. " DDP ,Destination coordinates described in the DL and the registers related to the setting of destination coordinates" "Integer,Fixed-point"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " UVDPO ,Source Coordinate Decimal Point" "0,1,2,3,4,5,?..."
|
|
line.long 0x04 "SUSR,Width Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " SUW ,Source width - 2"
|
|
hexmask.long.word 0x04 0.--10. 1. " SVW ,Source width - 1"
|
|
line.long 0x08 "SVSR,Source Height Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " SVS ,Height (vertical size) of the source"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
sif (cpu()=="R8A7792X")
|
|
hexmask.long.word 0x0C 0.--12. 1. " YMAX ,Y Clip MAX"
|
|
endif
|
|
else
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
endif
|
|
hexmask.long.word 0x0c 0.--11. 1. " YMAX ,Y Clip MAX"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
else
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="RCARH2")&&(cpu()!="R8A7792X")
|
|
tree "Bud Access Control Register"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "MACR1,Memory Access Control Register 1"
|
|
bitfld.long 0x00 31. " QWSWPI ,Selects the endian of 64-bit units of 128 bits in the instruction fetch field (DL)" "Big,Little"
|
|
bitfld.long 0x00 30. " QWSWPIC ,Selects the endian of 64-bit units of 128 bits for pixels" "Big,Little"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMAM ,Extended Memory Address Mode" "29-bit address,32-bit address"
|
|
bitfld.long 0x00 9. " LWSWAP ,Selects the endian of a 64-bit unit in the instruction fetch field (DL)" "Big,Little"
|
|
line.long 0x04 "MACR2,Memory Access Control Register 2"
|
|
bitfld.long 0x04 15. " EDSWP ,Selects the endian of a 64-bit unit for pixels" "Big,Little"
|
|
tree.end
|
|
endif
|
|
tree "Line Memory Control Registers"
|
|
group.long 0xA00++0x0b
|
|
line.long 0x00 "LSPR,Start Line Set Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " LSPR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction"
|
|
line.long 0x04 "LEPR,End Line Set Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " LEPR ,Number of the line beyond which the IMR-LSX does not leave the drawing waiting state after the execution of the SYNCW instruction"
|
|
line.long 0x08 "LMSR,Mesh Sizer Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 0.--2. " LMSR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction" ",,2,3,?..."
|
|
else
|
|
bitfld.long 0x08 0.--2. " LMSR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction" ",,2,3,4,?..."
|
|
endif
|
|
group.long 0xA20++0x0b
|
|
line.long 0x00 "LMCR,Line Memory Control Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 14. " VIM ,Video Input Mode" "VIN,iVDP1C"
|
|
bitfld.long 0x00 13. " JPE ,JPEG Image Format Select" "H.264,JPEG"
|
|
bitfld.long 0x00 12. " ROSEL ,Capture Source iVDP1C Module Select" "Input 0,Input 1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 8.--9. " DATSEL ,Capture-Source Module Select" "VIN0,VIN1,VIN2,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " DATSEL ,Capture-Source Module Select" "VIN0,VIN1,VIN2,VIN3"
|
|
endif
|
|
line.long 0x04 "LMSPPCR,Line Memory Pre-Clip Start Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " SPPC ,Pre-Clipping Start Point"
|
|
line.long 0x08 "LMEPPCR,Line Memory Pre-Clip End Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " EPPC ,Pre-Clipping End Point"
|
|
tree.end
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Rendering Correction Registers"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "YLMINR,Minimum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMIN ,Minimum luminance value when luminance correction is applied"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "UBMINR,Minimum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMIN ,Minimum U value when hue correction is applied"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "VRMINR,Minimum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMIN ,Minimum V value when hue correction is applied"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "YLMAXR,Maximum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMAX ,Maximum luminance value when luminance correction is applied"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "UBMAXR,Maximum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMAX ,Maximum U value when hue correction is applied"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "VRMAXR,Maximum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMAX ,Maximum V value when hue correction is applied"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CPDPOR,Correction Decimal Point Register"
|
|
bitfld.long 0x00 8.--10. " YLDPO ,Number of bits after the decimal point for the value specified as the luminance correction scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " UBDPO ,Number of bits after the decimal point for the value specified as the hue correction U value scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " VRDPO ,Number of bits after the decimal point for the value specified as the hue correction V value scale value" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "YLCPR,Luminance Correction Parameter Y Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LSCAL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOFST ,Offset parameter"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "UBCPR,Hue Correction Parameter U Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " UBSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " UBOFS ,Offset parameter"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "VRCPR,Hue Correction Parameter V Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VRSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VROFS ,Offset parameter"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Lookup Table Data Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "LUTDR,Lookup Table Data Register"
|
|
button "LUT" "d (lsx+0x1000)--(lsx+0x1FFC) /long"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFED0000
|
|
width 9.
|
|
tree "Control Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software Reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " SFE ,Separate Field Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARS ,Auto Rendering Start" "No,Yes"
|
|
bitfld.long 0x00 0. " RS ,Rendering Start" "Not started,Started"
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFO ,Line Memory Frame Overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 8. " LMO ,Line Memory Mesh Overflow" "No overflow,Overflow"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.long 0x00 7. " SFS ,Separate Field" "Even,Odd"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 5. " REN ,Drawing-in-Progress Flag" "Not in progress,In progress"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " DSA ,Destination Start Address" "DSAR,DSAR2"
|
|
bitfld.long 0x00 2. " INT ,INT Instruction Decode" "Not decoded,Decoded"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IER ,Illegal Instruction Decode" "Not decoded,Decoded"
|
|
bitfld.long 0x00 0. " TRA ,Trap - rendering operation completed" "Not started/Not completed,Completed"
|
|
wgroup.long 0x10++0x03
|
|
line.long 0x00 "SRCR,Status Clear Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 9. " LFOCLR ,Line Memory Frame Overflow Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " LMOCLR ,Line Memory Mesh Overflow Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " INTCLR ,INT Instruction Decode Flag Clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " IERCLR ,Illegal Instruction Decode Flag Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRACLR ,Rendering Operation Completed Flag Clear" "No effect,Clear"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ICR,Interrupt Control Register"
|
|
bitfld.long 0x00 2. " INTENB ,INT Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IERENB ,IER Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRAENB ,TRA Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x04 "IMR,Interrupt Mask Enable"
|
|
bitfld.long 0x04 2. " INM ,INT Interrupt Mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " IEM ,IER Interrupt Mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRAM ,TA Interrupt Mask" "Not masked,Masked"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x00 "DLSP,DL Stack Pointer Register"
|
|
endif
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DLPR,DL Status Register"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "EDLR,Executed DL Status Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " EDL ,Executed DL status"
|
|
endif
|
|
tree.end
|
|
tree "Memory Control Registers"
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DLSAR,DL Start Address Register"
|
|
hexmask.long 0x00 3.--31. 0x8 " DLSA ,DL Start Address"
|
|
line.long 0x04 "DSAR,Destination Start Address Register"
|
|
hexmask.long 0x04 5.--31. 0x20 " DSA ,Destination Start Address"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SSAR,Source Start Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " SSAR ,SRC Area Start Address"
|
|
group.long 0x3c++0x07
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DSTR ,Memory width of the DST area"
|
|
line.long 0x04 "SSTR,Source Stride Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " SSTR ,Memory width of the SRC area"
|
|
else
|
|
group.long 0x3c++0x03
|
|
line.long 0x00 "DSTR,Destination Stride Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " DST ,Memory width of the DST area"
|
|
endif
|
|
group.long 0x48++0x0b
|
|
line.long 0x00 "DSAR2,Destination Start Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " DSA2 ,Destination Start Address 2"
|
|
line.long 0x04 "DLSAR2,DL Start Address Register 2"
|
|
hexmask.long 0x04 3.--31. 0x8 " DLSA2 ,DL Start Address"
|
|
line.long 0x08 "DSOR,Destination Start Offset Address Register"
|
|
hexmask.long 0x08 5.--31. 0x20 " DSOFSTA ,Destination Start Offset Address"
|
|
tree.end
|
|
tree "Rendering Control Register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CMRCR,Rendering Mode Register"
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " CLSM_set/clr ,Hue Correction Scale Parameter Register Specification Mode" "DL,UBCPR/VRCPR"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " CLOM_set/clr ,Hue Correction Offset Parameter Register Specification Mode" "DL,UBCPR/VRCPR"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " LUSM_set/clr ,Luminance Correction Scale Parameter Register Specification Mode" "DL,YLCPR"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " LUOM_set/clr ,Luminance Correction Offset Parameter Register Specification Mode" "DL,YLCPR"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " CP16E_set/clr ,Copy 16-bit Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " YCM_set/clr ,YC Mode" "Y,UV"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " SY12_set/clr ,Luminance Processing of Source Data Precision" "8-bpp/10-bpp,12-bpp"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " SY10_set/clr ,Luminance Processing of Source Data Precision" "8-bpp/12-bpp,10-bpp"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " YOM_set/clr ,CbCr Data Output Mode" "Y and CbCr data,Y data"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " Y12_set/clr ,Sets the precision of Y data when it is output" "8-bpp,12-bpp"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " Y10_set/clr ,Sets the precision of Y data when it is output" "8-bpp,10-bpp"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " YISM_set/clr ,Selects the output format for YUV data" "Interleave YUV,Separate Y/UV"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
setclrfld.long 0x00 5.--6. 0x04 5.--6. 0x08 5.--6. " SUV ,Color Difference Processing of Source Data Precision" "8-bpp,10-bpp,12-bpp,?..."
|
|
setclrfld.long 0x00 3.--4. 0x04 3.--4. 0x08 3.--4. " DUV ,Color Difference of Output Data Precision" "8-bpp,10-bpp,12-bpp,?..."
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CLCE ,Hue Correction Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " LUCE ,Luminance Correction Enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXTM ,Texture Data Read Memory" "Line,External"
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CMRCR2,Rendering Mode Register 2"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " LUTE ,Lookup table enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRIMR,Triangle Mode Register"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " TCM_set/clr ,Triangle Clockwise Mode" "Counter clockwise,Clockwise"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DUDVM_set/clr ,Relative Source Specification Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DXDYM_set/clr ,Relative Destination Specification Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AUTOSG_set/clr ,Automatic Source Coordinate Generation Mode" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AUTODG_set/clr ,Automatic Destination Coordinate Generation Mode" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " BFE_set/clr ,Bilinear Filter Enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TME_set/clr ,Texture Mapping Enable" "Disabled,Enabled"
|
|
group.long 0x6c++0x03
|
|
line.long 0x00 "TRICR,Triangle Color Register"
|
|
bitfld.long 0x00 31. " YCFORM ,For interleave output changes the order of Y and U/V" "Not changed,Changed"
|
|
textline " "
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 26.--27. " TCY3 ,When Y is to be output in 12 bpp specifies bits 11 and 10 of color Y for single-color drawing" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--25. " TCY2 ,When Y is to be output in 10 bits specifies the upper 2 bits of color Y for monochrome drawing" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " TCV ,Specifies color V for monochrome drawing with the TRI instruction"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TCU ,Specifies color U for monochrome drawing with the TRI instruction"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TCY ,Specifies color Y for monochrome drawing with the TRI instruction"
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TRICR2,Triangle Color Register 2 "
|
|
bitfld.long 0x00 26.--27. " TCV12 ,When V is to be output in 12 bpp specifies bits 11 and 10 of color V for single-color drawing" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--25. 1. " TCV10 ,When U is to be output in 12 bpp specifies bits 11 and 10 of color U for single-color drawing"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TCU12 ,When U is to be output in 12 bpp specifies bits 11 and 10 of color U for single-color drawing" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--9. 1. " TCU10 ,When U is to be output in 10/12 bpp specifies bits 9 to 0 of color U for single-color drawing"
|
|
endif
|
|
group.long 0x70++0x0B
|
|
line.long 0x00 "UVDPOR,Source and Destination Coordinate Decimal Point Register"
|
|
bitfld.long 0x00 8. " DDP ,Destination coordinates described in the DL and the registers related to the setting of destination coordinates" "Integer,Fixed-point"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " UVDPO ,Source Coordinate Decimal Point" "0,1,2,3,4,5,?..."
|
|
line.long 0x04 "SUSR,Width Register"
|
|
hexmask.long.word 0x04 16.--26. 1. " SUW ,Source width - 2"
|
|
hexmask.long.word 0x04 0.--10. 1. " SVW ,Source width - 1"
|
|
line.long 0x08 "SVSR,Source Height Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " SVS ,Height (vertical size) of the source"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--12. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--12. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--12. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
sif (cpu()=="R8A7792X")
|
|
hexmask.long.word 0x0C 0.--12. 1. " YMAX ,Y Clip MAX"
|
|
endif
|
|
else
|
|
group.long 0x80++0x1f
|
|
line.long 0x00 "XMINR,MIN Clipping X Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " XMIN ,X Clip MIN"
|
|
line.long 0x04 "YMINR,MIN Clipping Y Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " YMIN ,Y Clip MIN"
|
|
line.long 0x08 "XMAXR,MAX Clipping X Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " XMAX ,X Clip MAX"
|
|
line.long 0x0c "YMAXR,MAX Clipping Y Register"
|
|
endif
|
|
hexmask.long.word 0x0c 0.--11. 1. " YMAX ,Y Clip MAX"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--12. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--12. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--12. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
else
|
|
line.long 0x10 "AMXSR,Mesh Generation X Size Register"
|
|
hexmask.long.word 0x10 0.--10. 1. " AMXS ,Automatic Mesh X Size"
|
|
line.long 0x14 "AMYSR,Mesh Generation Y Size Register"
|
|
hexmask.long.word 0x14 0.--10. 1. " AMYS ,Automatic Mesh Y Size"
|
|
line.long 0x18 "AMXOR,Mesh Generation X Start Register"
|
|
hexmask.long.word 0x18 0.--10. 1. " AMXO ,Automatic Mesh X Origin"
|
|
line.long 0x1c "AMYOR,Mesh Generation Y Start Register"
|
|
hexmask.long.word 0x1c 0.--10. 1. " AMYO ,Automatic Mesh Y Origin"
|
|
endif
|
|
tree.end
|
|
sif (cpu()!="RCARH2")&&(cpu()!="R8A7792X")
|
|
tree "Bud Access Control Register"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "MACR1,Memory Access Control Register 1"
|
|
bitfld.long 0x00 31. " QWSWPI ,Selects the endian of 64-bit units of 128 bits in the instruction fetch field (DL)" "Big,Little"
|
|
bitfld.long 0x00 30. " QWSWPIC ,Selects the endian of 64-bit units of 128 bits for pixels" "Big,Little"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EMAM ,Extended Memory Address Mode" "29-bit address,32-bit address"
|
|
bitfld.long 0x00 9. " LWSWAP ,Selects the endian of a 64-bit unit in the instruction fetch field (DL)" "Big,Little"
|
|
line.long 0x04 "MACR2,Memory Access Control Register 2"
|
|
bitfld.long 0x04 15. " EDSWP ,Selects the endian of a 64-bit unit for pixels" "Big,Little"
|
|
tree.end
|
|
endif
|
|
tree "Line Memory Control Registers"
|
|
group.long 0xA00++0x0b
|
|
line.long 0x00 "LSPR,Start Line Set Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " LSPR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction"
|
|
line.long 0x04 "LEPR,End Line Set Register"
|
|
hexmask.long.word 0x04 0.--9. 1. " LEPR ,Number of the line beyond which the IMR-LSX does not leave the drawing waiting state after the execution of the SYNCW instruction"
|
|
line.long 0x08 "LMSR,Mesh Sizer Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x08 0.--2. " LMSR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction" ",,2,3,?..."
|
|
else
|
|
bitfld.long 0x08 0.--2. " LMSR ,Number of lines required to leave the drawing waiting state after the execution of the SYNCW instruction" ",,2,3,4,?..."
|
|
endif
|
|
group.long 0xA20++0x0b
|
|
line.long 0x00 "LMCR,Line Memory Control Register"
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 14. " VIM ,Video Input Mode" "VIN,iVDP1C"
|
|
bitfld.long 0x00 13. " JPE ,JPEG Image Format Select" "H.264,JPEG"
|
|
bitfld.long 0x00 12. " ROSEL ,Capture Source iVDP1C Module Select" "Input 0,Input 1"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
bitfld.long 0x00 8.--9. " DATSEL ,Capture-Source Module Select" "VIN0,VIN1,VIN2,?..."
|
|
else
|
|
bitfld.long 0x00 8.--9. " DATSEL ,Capture-Source Module Select" "VIN0,VIN1,VIN2,VIN3"
|
|
endif
|
|
line.long 0x04 "LMSPPCR,Line Memory Pre-Clip Start Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " SPPC ,Pre-Clipping Start Point"
|
|
line.long 0x08 "LMEPPCR,Line Memory Pre-Clip End Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " EPPC ,Pre-Clipping End Point"
|
|
tree.end
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Rendering Correction Registers"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "YLMINR,Minimum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMIN ,Minimum luminance value when luminance correction is applied"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "UBMINR,Minimum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMIN ,Minimum U value when hue correction is applied"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "VRMINR,Minimum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMIN ,Minimum V value when hue correction is applied"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "YLMAXR,Maximum Luminance Correction Y Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " YLMAX ,Maximum luminance value when luminance correction is applied"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "UBMAXR,Maximum Hue Correction U Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " UBMAX ,Maximum U value when hue correction is applied"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "VRMAXR,Maximum Hue Correction V Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " VRMAX ,Maximum V value when hue correction is applied"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CPDPOR,Correction Decimal Point Register"
|
|
bitfld.long 0x00 8.--10. " YLDPO ,Number of bits after the decimal point for the value specified as the luminance correction scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " UBDPO ,Number of bits after the decimal point for the value specified as the hue correction U value scale value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " VRDPO ,Number of bits after the decimal point for the value specified as the hue correction V value scale value" "0,1,2,3,4,5,6,7"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "YLCPR,Luminance Correction Parameter Y Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LSCAL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LOFST ,Offset parameter"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "UBCPR,Hue Correction Parameter U Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " UBSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " UBOFS ,Offset parameter"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "VRCPR,Hue Correction Parameter V Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VRSCL ,Scale parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VROFS ,Offset parameter"
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
tree "Lookup Table Data Registers"
|
|
group.long 0x1000++0x3
|
|
line.long 0x00 "LUTDR,Lookup Table Data Register"
|
|
button "LUT" "d (lsx+0x1000)--(lsx+0x1FFC) /long"
|
|
tree.end
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "SRU (Sound Routing Unit)"
|
|
base ad:0xFFD90000
|
|
width 19.
|
|
if (((per.l(ad:0xFFD90000+0xb0))&0x10000)==0x10000)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SRC_ROUTE_SELECT0,SRC Route Select 0 Register"
|
|
bitfld.long 0x00 30.--31. " SRC8 ,SRC route 8 select" "Not routed,HPBIF8->SRC8->SSI8,SSI8->SRC8->HPBIF8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " SRC7 ,SRC route 7 select" "Not routed,HPBIF7->SRC7->SSI7,SSI7->SRC7->HPBIF7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " SRC6 ,SRC route 6 select" "Not routed,HPBIF6->SRC6->SSI6,SSI6->SRC6->HPBIF6,STREAM_mimlcp5->SRC6->HPBIF6,SSI6->SRC6->STREAM_mimlcp6,STREAM_mimlcp6->SRC6->SSI6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " SRC5 ,SRC route 5 select" "Not routed,HPBIF5->SRC5->SSI5,SSI5->SRC5->HPBIF5,STREAM_mimlcp5->SRC5->HPBIF5,SSI5->SRC5->STREAM_mimlcp5,SSI5->SRC5->STREAM_mimlcp5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SRC4 ,SRC route 4 select" "Not routed,HPBIF4->SRC4->SSI4,SSI4->SRC4->HPBIF4,HPBIF4->SRC4->STREAM_mimlcp4,STREAM_mimlcp4->SRC4->HPBIF4,SSI4->SRC4->STREAM_mimlcp4,STREAM_mimlcp4->SRC4->SSI4,HPBIF4->SRC4->CTU1->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " SRC3 ,SRC route 3 select" "Not routed,HPBIF3->SRC3->SSI3,SSI3->SRC3->HPBIF3,HPBIF3->SRC3->STREAM_mimlcp3,STREAM_mimlcp3->SRC3->HPBIF3,SSI3->SRC3->STREAM_mimlcp3,STREAM_mimlcp3->SRC3->SSI3,HPBIF3->SRC3->CTU0->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SRC2 ,SRC route 2 select" "Not routed,HPBIF2->SRC2->SSI2,SSI2->SRC2->HPBIF2,,,HPBIF2->SRC2->STREAM_mimlcp2,,SSI2->SRC2->STREAM_mimlcp2,STREAM_mimlcp2->SRC2->SSI2,,,HPBIF2->SRC2->CTU3->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,SSI2->SRC2->CTU3->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SRC1 ,SRC route 1 select" "Not routed,HPBIF1->SRC1->SSI1,SSI1->SRC1->HPBIF1,,,HPBIF1->SRC1->STREAM_mimlcp1,STREAM_mimlcp1->SRC1->SSI1,SSI1->SRC1->STREAM_mimlcp1,STREAM_mimlcp1->SRC1->SSI1,,,HPBIF1->SRC1->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,SSI1->SRC1->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,SSI5->SRC1->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,STREAM_mimlcp1->SRC1->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_milcp4,?..."
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|
textline " "
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|
bitfld.long 0x00 0.--3. " SRC0 ,SRC route 0 select" "Not routed,HPBIF0->SRC0->SSI0,SSI0->SRC0->HPBIFO,HPBIF0->SRC0->SSI0/SSI1/SSI2/SSI9,SSI0/SSI1/SSI2/SSI9->SRC0->HPBIF0,HPBIF0->SRC0->STREAM_mimlcp0,STREAM_mimlcp0->SRC0->HPBIF0,SSI0->SRC0->STREAM_mimlcp0,STREAM_mimlcp0->SRC0->SSI0,SSI0/SSI1/SSI2/SSI9->SRC0->STREAM_mimlcp0,STREAM_mimlcp0->SRC0->SSI0/SSI1/SSI2/SSI9,HPBIF0->SRC0->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,SSI0->SRC0->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,SSI0/SSI1/SSI2/SSI9->SRC0->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,STREAM_mimlcp0->SRC0->CTU2->SSI3/SSI4/STREAM_mimlcp3/STREAM_mimlcp4,?..."
|
|
line.long 0x04 "SRC_ROUTE_SELECT1,SRC Route Select 1 Register"
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|
bitfld.long 0x04 0.--2. " SRC9 ,SRC route 9 select" "Not routed,HPBIF->SRC9->SSI9,SSI9->SRC9->HPBIF9,HPBIF9->SRC9->STREAM_mimlcp8,STREAM_mimclp8->SRC9->HPBIF9,SSI9->SRC9->STREAM_mimclp8,STREAM_mimclp8->SRC9-SSI9,?..."
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|
else
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|
group.long 0x00++0x07
|
|
line.long 0x00 "SRC_ROUTE_SELECT0,SRC Route Select 0 Register"
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|
bitfld.long 0x00 30.--31. " SRC8 ,SRC route 8 select" "Not routed,HPBIF8->SRC8->SSI8,SSI8->SRC8->HPBIF8,?..."
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|
textline " "
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|
bitfld.long 0x00 28.--29. " SRC7 ,SRC route 7 select" "Not routed,HPBIF7->SRC7->SSI7,SSI7->SRC7->HPBIF7,?..."
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|
textline " "
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|
bitfld.long 0x00 24.--26. " SRC6 ,SRC route 6 select" "Not routed,HPBIF6->SRC6->SSI6,SSI6->SRC6->HPBIF6,STREAM_mlp6->SRC6->HPBIF6,SSI6->SRC6->STREAM_mlp6,STREAM_mlp6->SRC6->SSI6,?..."
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|
textline " "
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|
bitfld.long 0x00 20.--22. " SRC5 ,SRC route 5 select" "Not routed,HPBIF5->SRC5->SSI5,SSI5->SRC5->HPBIF5,STREAM_mlp5->SRC5->HPBIF5,SSI5->SRC5->STREAM_mlp5,SSI5->SRC5->STREAM_mlp5,?..."
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|
textline " "
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bitfld.long 0x00 16.--18. " SRC4 ,SRC route 4 select" "Not routed,HPBIF4->SRC4->SSI4,SSI4->SRC4->HPBIF4,HPBIF4->SRC4->STREAM_MLP4,STREAM_mlp4->SRC4->HPBIF4,SSI4->SRC4->STREAM_mlp4,STREAM_mlp4->SRC4->SSI4,HPBIF4->SRC4->CTU1->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4"
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|
textline " "
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bitfld.long 0x00 12.--14. " SRC3 ,SRC route 3 select" "Not routed,HPBIF3->SRC3->SSI3,SSI3->SRC3->HPBIF3,HPBIF3->SRC3->STREAM_mlp3,STREAM_mlp3->SRC3->HPBIF3,SSI3->SRC3->STREAM_mlp3,STREAM_mlp3->SRC3->SSI3,HPBIF3->SRC3->CTU0->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4"
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|
textline " "
|
|
bitfld.long 0x00 8.--11. " SRC2 ,SRC route 2 select" "Not routed,HPBIF2->SRC2->SSI2,SSI2->SRC2->HPBIF2,,,HPBIF2->SRC2->STREAM_mlp2,,SSI2->SRC2->STREAM_mlp2,STREAM_mlp2->SRC2->SSI2,,,HPBIF2->SRC2->CTU3->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,SSI2->SRC2->CTU3->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,?..."
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|
textline " "
|
|
bitfld.long 0x00 4.--7. " SRC1 ,SRC route 1 select" "Not routed,HPBIF1->SRC1->SSI1,SSI1->SRC1->HPBIF1,,,HPBIF1->SRC1->STREAM_mlp1,STREAM_mlp1->SRC1->SSI1,SSI1->SRC1->STREAM_mlp1,STREAM_mlp1->SRC1->SSI1,,,HPBIF1->SRC1->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,SSI1->SRC1->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,SSI5->SRC1->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,STREAM_mlp1->SRC1->CTU2->SSI3/SSI4/STREAM_milcp4/STREAM_mlp3/STREAM_mlp4,?..."
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|
textline " "
|
|
bitfld.long 0x00 0.--3. " SRC0 ,SRC route 0 select" "Not routed,HPBIF0->SRC0->SSI0,SSI0->SRC0->HPBIFO,HPBIF0->SRC0->SSI0/SSI1/SSI2/SSI9,SSI0/SSI1/SSI2/SSI9->SRC0->HPBIF0,HPBIF0->SRC0->STREAM_mlp0,STREAM_mlp0->SRC0->HPBIF0,SSI0->SRC0->STREAM_mlp0,STREAM_mlp0->SRC0->SSI0,SSI0/SSI1/SSI2/SSI9->SRC0->STREAM_mlp0,STREAM_mlp0->SRC0->SSI0/SSI1/SSI2/SSI9,HPBIF0->SRC0->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,SSI0->SRC0->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,SSI0/SSI1/SSI2/SSI9->SRC0->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,STREAM_mlp0->SRC0->CTU2->SSI3/SSI4/STREAM_mlp3/STREAM_mlp4,?..."
|
|
line.long 0x04 "SRC_ROUTE_SELECT1,SRC Route Select 1 Register"
|
|
bitfld.long 0x04 0.--2. " SRC9 ,SRC route 9 select" "Not routed,HPBIF->SRC9->SSI9,SSI9->SRC9->HPBIF9,HPBIF9->SRC9->STREAM_mlp7,STREAM_mlp7->SRC9->HPBIF9,SSI9->SRC9->STREAM_mlp7,STREAM_mlp7->SRC9-SSI9,?..."
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD_ROUTE_SELECT,CMD Route Select Register"
|
|
bitfld.long 0x00 20.--22. " CMD1_CASE ,Selects the route in CMD1" "CTU0 to CTU3->MIX->DVC,CTU0->DVC,CTU1->DVC,CTU2->DVC,CTU3->DVC,?..."
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|
bitfld.long 0x00 16.--18. " CMD0_CASE ,Selects the route in CMD0" "CTU0 to CTU3->MIX->DVC,CTU0->DVC,CTU1->DVC,CTU2->DVC,CTU3->DVC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " CMD_OUT_ROUTE1 ,Selects the output route from CMD1" "Not routed,CMD1->SSI4,CMD1->STREAM_mimlcp4,?..."
|
|
bitfld.long 0x00 8.--10. " CMD_OUT_ROUTE0 ,Selects the output route from CMD0" "Not routed,CMD0->SSI3,CMD0->STREAM_mimlcp3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " CMD_IN_ROUTE1 ,Selects the input route to CMD1" "SRC0,SRC1"
|
|
bitfld.long 0x00 0. " CMD_IN_ROUTE0 ,Selects the input route to CMD0" "SRC0,SRC1"
|
|
if (((per.l(ad:0xFFD90000+0xb0))&0x10000)==0x10000)
|
|
group.long 0x0c++0x13
|
|
line.long 0x00 "SRC_TIMING_SELECT0,SRC Timing Select 0 Register"
|
|
bitfld.long 0x00 24.--28. " HPBIF3_TMG ,Selects the timing signal for HPBIF3" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
|
bitfld.long 0x00 16.--20. " HPBIF2_TMG ,Selects the timing signal for HPBIF2" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " HPBIF1_TMG ,Selects the timing signal for HPBIF1" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
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bitfld.long 0x00 0.--4. " HPBIF0_TMG ,Selects the timing signal for HPBIF0" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
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line.long 0x04 "SRC_TIMING_SELECT1,SRC Timing Select 1 Register"
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|
bitfld.long 0x04 24.--28. " HPBIF7_TMG ,Selects the timing signal for HPBIF7" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
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bitfld.long 0x04 16.--20. " HPBIF6_TMG ,Selects the timing signal for HPBIF6" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " HPBIF5_TMG ,Selects the timing signal for HPBIF1" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
|
bitfld.long 0x04 0.--4. " HPBIF4_TMG ,Selects the timing signal for HPBIF4" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
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line.long 0x08 "SRC_TIMING_SELECT2,SRC Timing Select 2 Register"
|
|
bitfld.long 0x08 0.--4. " HPBIF8_TMG ,Selects the timing signal for HPBIF4" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
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line.long 0x0c "SRC_TIMING_SELECT3,SRC Timing Select 3 Register"
|
|
bitfld.long 0x0c 16.--18. " SRCOUT4_TMG ,Selects the timing signal for output from SRC4" "SSI3,SSI4,STREAM_mimlcp3,STREAM_mimlcp4,?..."
|
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bitfld.long 0x0c 12.--14. " SRCOUT3_TMG ,Selects the timing signal for output from SRC3" "SSI3,SSI4,STREAM_mimlcp3,STREAM_mimlcp4,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " SRCOUT2_TMG ,Selects the timing signal for output from SRC2" "SSI3,SSI4,STREAM_mimlcp3,STREAM_mimlcp4,?..."
|
|
bitfld.long 0x0c 4.--6. " SRCOUT1_TMG ,Selects the timing signal for output from SRC1" "SSI3,SSI4,STREAM_mimlcp3,STREAM_mimlcp4,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 0.--2. " SRCOUT0_TMG ,Selects the timing signal for output from SRC0" "SSI3,SSI4,STREAM_mimlcp3,STREAM_mimlcp4,?..."
|
|
line.long 0x10 "SRC_TIMING_SELECT4,SRC Timing Select 4 Register"
|
|
bitfld.long 0x10 0.--4. " HPBIF9_TMG ,Selects the timing signal for HPBIF9" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mimlcp0,STREAM_mimlcp1,STREAM_mimlcp2,STREAM_mimlcp3,STREAM_mimlcp4,STREAM_mimlcp5,STREAM_mimlcp6,SSI9,STREAM_mimlcp8,?..."
|
|
else
|
|
group.long 0x0c++0x13
|
|
line.long 0x00 "SRC_TIMING_SELECT0,SRC Timing Select 0 Register"
|
|
bitfld.long 0x00 24.--28. " HPBIF3_TMG ,Selects the timing signal for HPBIF3" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
bitfld.long 0x00 16.--20. " HPBIF2_TMG ,Selects the timing signal for HPBIF2" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " HPBIF1_TMG ,Selects the timing signal for HPBIF1" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
bitfld.long 0x00 0.--4. " HPBIF0_TMG ,Selects the timing signal for HPBIF0" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
line.long 0x04 "SRC_TIMING_SELECT1,SRC Timing Select 1 Register"
|
|
bitfld.long 0x04 24.--28. " HPBIF7_TMG ,Selects the timing signal for HPBIF7" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
bitfld.long 0x04 16.--20. " HPBIF6_TMG ,Selects the timing signal for HPBIF6" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--12. " HPBIF5_TMG ,Selects the timing signal for HPBIF5" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
bitfld.long 0x04 0.--4. " HPBIF4_TMG ,Selects the timing signal for HPBIF4" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
line.long 0x08 "SRC_TIMING_SELECT2,SRC Timing Select 2 Register"
|
|
bitfld.long 0x08 0.--4. " HPBIF8_TMG ,Selects the timing signal for HPBIF8" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
line.long 0x0c "SRC_TIMING_SELECT3,SRC Timing Select 3 Register"
|
|
bitfld.long 0x0c 16.--18. " SRCOUT4_TMG ,Selects the timing signal for output from SRC4" "SSI3,SSI4,STREAM_mlp3,STREAM_mlp4,?..."
|
|
bitfld.long 0x0c 12.--14. " SRCOUT3_TMG ,Selects the timing signal for output from SRC3" "SSI3,SSI4,STREAM_mlp3,STREAM_mlp4,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--10. " SRCOUT2_TMG ,Selects the timing signal for output from SRC2" "SSI3,SSI4,STREAM_mlp3,STREAM_mlp4,?..."
|
|
bitfld.long 0x0c 4.--6. " SRCOUT1_TMG ,Selects the timing signal for output from SRC1" "SSI3,SSI4,STREAM_mlp3,STREAM_mlp4,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 0.--2. " SRCOUT0_TMG ,Selects the timing signal for output from SRC0" "SSI3,SSI4,STREAM_mlp3,STREAM_mlp4,?..."
|
|
line.long 0x10 "SRC_TIMING_SELECT4,SRC Timing Select 24 Register"
|
|
bitfld.long 0x10 0.--4. " HPBIF9_TMG ,Selects the timing signal for HPBIF9" "ADG,SSI0,SSI1,SSI2,SSI3,SSI4,SSI5,SSI6,SSI7,STREAM_mlp0,STREAM_mlp1,STREAM_mlp2,STREAM_mlp3,STREAM_mlp4,STREAM_mlp5,STREAM_mlp6,SSI9,STREAM_mlp7,?..."
|
|
endif
|
|
tree "HPBIF Mode Registers"
|
|
width 15.
|
|
group.long 0x20++0x27
|
|
line.long 0x0 "HPBIF_MODE0,HPBIF Mode 0 Register"
|
|
bitfld.long 0x0 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
|
|
bitfld.long 0x0 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
|
|
bitfld.long 0x0 0. " DMA ,Selects the access type for HPBIF0" ",DMA"
|
|
line.long 0x4 "HPBIF_MODE1,HPBIF Mode 1 Register"
|
|
bitfld.long 0x4 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
|
|
bitfld.long 0x4 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
|
|
bitfld.long 0x4 0. " DMA ,Selects the access type for HPBIF1" ",DMA"
|
|
line.long 0x8 "HPBIF_MODE2,HPBIF Mode 2 Register"
|
|
bitfld.long 0x8 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
|
|
bitfld.long 0x8 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
|
|
bitfld.long 0x8 0. " DMA ,Selects the access type for HPBIF2" ",DMA"
|
|
line.long 0xC "HPBIF_MODE3,HPBIF Mode 3 Register"
|
|
bitfld.long 0xC 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0xC 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xC 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0xC 0. " DMA ,Selects the access type for HPBIF3" ",DMA"
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line.long 0x10 "HPBIF_MODE4,HPBIF Mode 4 Register"
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bitfld.long 0x10 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x10 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x10 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x10 0. " DMA ,Selects the access type for HPBIF4" ",DMA"
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line.long 0x14 "HPBIF_MODE5,HPBIF Mode 5 Register"
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bitfld.long 0x14 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x14 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x14 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x14 0. " DMA ,Selects the access type for HPBIF5" ",DMA"
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line.long 0x18 "HPBIF_MODE6,HPBIF Mode 6 Register"
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bitfld.long 0x18 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x18 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x18 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x18 0. " DMA ,Selects the access type for HPBIF6" ",DMA"
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line.long 0x1C "HPBIF_MODE7,HPBIF Mode 7 Register"
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bitfld.long 0x1C 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x1C 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x1C 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x1C 0. " DMA ,Selects the access type for HPBIF7" ",DMA"
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line.long 0x20 "HPBIF_MODE8,HPBIF Mode 8 Register"
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bitfld.long 0x20 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x20 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x20 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x20 0. " DMA ,Selects the access type for HPBIF8" ",DMA"
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line.long 0x24 "HPBIF_MODE9,HPBIF Mode 9 Register"
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bitfld.long 0x24 20. " SFT_DIR ,Selects the bit-shift direction for valid bit position adjustment in the HPBIFn input and output data" "Left,Right"
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bitfld.long 0x24 16.--19. " SFT_NUM ,Selects the bit-shift count for valid bit position adjustment [bit]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x24 8. " WORD_SWAP ,Swaps thw word order" "Not swapped,Swapped"
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bitfld.long 0x24 0. " DMA ,Selects the access type for HPBIF9" ",DMA"
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tree.end
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width 19.
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tree "SRC Mode Registers"
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textline " "
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group.long 0x50++0x4f
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line.long 0x0 "SRC_ROUTE0_MODE0,SRC Route 0 Mode 0 Register"
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bitfld.long 0x0 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
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bitfld.long 0x0 0. " SRC ,Selects whether to use SRC0" "Not used,Used"
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line.long (0x0+0x04) "SRC_ROUTE0_MODE1,SRC Route 0 Mode 0 Register"
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bitfld.long (0x0+0x04) 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x0+0x04) 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x0+0x04) 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x0+0x04) 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x0+0x04) 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x0+0x04) 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x0+0x04) 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x0+0x04) 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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line.long 0x8 "SRC_ROUTE1_MODE0,SRC Route 1 Mode 0 Register"
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bitfld.long 0x8 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
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|
bitfld.long 0x8 0. " SRC ,Selects whether to use SRC1" "Not used,Used"
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line.long (0x8+0x04) "SRC_ROUTE1_MODE1,SRC Route 1 Mode 0 Register"
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bitfld.long (0x8+0x04) 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x8+0x04) 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x8+0x04) 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x8+0x04) 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x8+0x04) 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x8+0x04) 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x8+0x04) 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x8+0x04) 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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line.long 0x10 "SRC_ROUTE2_MODE0,SRC Route 2 Mode 0 Register"
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bitfld.long 0x10 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
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|
bitfld.long 0x10 0. " SRC ,Selects whether to use SRC2" "Not used,Used"
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|
line.long (0x10+0x04) "SRC_ROUTE2_MODE1,SRC Route 2 Mode 0 Register"
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bitfld.long (0x10+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
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bitfld.long (0x10+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
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line.long 0x18 "SRC_ROUTE3_MODE0,SRC Route 3 Mode 0 Register"
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bitfld.long 0x18 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
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|
bitfld.long 0x18 0. " SRC ,Selects whether to use SRC3" "Not used,Used"
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|
line.long (0x18+0x04) "SRC_ROUTE3_MODE1,SRC Route 3 Mode 0 Register"
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bitfld.long (0x18+0x04) 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x18+0x04) 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x18+0x04) 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x18+0x04) 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x18+0x04) 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x18+0x04) 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x18+0x04) 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x18+0x04) 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
line.long 0x20 "SRC_ROUTE4_MODE0,SRC Route 4 Mode 0 Register"
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|
bitfld.long 0x20 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
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|
bitfld.long 0x20 0. " SRC ,Selects whether to use SRC4" "Not used,Used"
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|
line.long (0x20+0x04) "SRC_ROUTE4_MODE1,SRC Route 4 Mode 0 Register"
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|
bitfld.long (0x20+0x04) 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x20+0x04) 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
textline " "
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bitfld.long (0x20+0x04) 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x20+0x04) 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x20+0x04) 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x20+0x04) 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long (0x20+0x04) 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long (0x20+0x04) 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
line.long 0x28 "SRC_ROUTE5_MODE0,SRC Route 5 Mode 0 Register"
|
|
bitfld.long 0x28 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
|
|
bitfld.long 0x28 0. " SRC ,Selects whether to use SRC5" "Not used,Used"
|
|
line.long (0x28+0x04) "SRC_ROUTE5_MODE1,SRC Route 5 Mode 0 Register"
|
|
bitfld.long (0x28+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
|
|
bitfld.long (0x28+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
|
|
line.long 0x30 "SRC_ROUTE6_MODE0,SRC Route 6 Mode 0 Register"
|
|
bitfld.long 0x30 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
|
|
bitfld.long 0x30 0. " SRC ,Selects whether to use SRC6" "Not used,Used"
|
|
line.long (0x30+0x04) "SRC_ROUTE6_MODE1,SRC Route 6 Mode 0 Register"
|
|
bitfld.long (0x30+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
|
|
bitfld.long (0x30+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
|
|
line.long 0x38 "SRC_ROUTE7_MODE0,SRC Route 7 Mode 0 Register"
|
|
bitfld.long 0x38 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
|
|
bitfld.long 0x38 0. " SRC ,Selects whether to use SRC7" "Not used,Used"
|
|
line.long (0x38+0x04) "SRC_ROUTE7_MODE1,SRC Route 7 Mode 0 Register"
|
|
bitfld.long (0x38+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
|
|
bitfld.long (0x38+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
|
|
line.long 0x40 "SRC_ROUTE8_MODE0,SRC Route 8 Mode 0 Register"
|
|
bitfld.long 0x40 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
|
|
bitfld.long 0x40 0. " SRC ,Selects whether to use SRC8" "Not used,Used"
|
|
line.long (0x40+0x04) "SRC_ROUTE8_MODE1,SRC Route 8 Mode 0 Register"
|
|
bitfld.long (0x40+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
|
|
bitfld.long (0x40+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
|
|
line.long 0x48 "SRC_ROUTE9_MODE0,SRC Route 9 Mode 0 Register"
|
|
bitfld.long 0x48 16. " UF_DATA ,Selects how to treat data when an underflow occurs in the SRC input buffer" "Before underflow data output,Output all 0s"
|
|
bitfld.long 0x48 0. " SRC ,Selects whether to use SRC9" "Not used,Used"
|
|
line.long (0x48+0x04) "SRC_ROUTE9_MODE1,SRC Route 9 Mode 0 Register"
|
|
bitfld.long (0x48+0x04) 4. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1"
|
|
bitfld.long (0x48+0x04) 0. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1"
|
|
tree.end
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textline " "
|
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width 19.
|
|
group.long 0xa0++0x07
|
|
line.long 0x0 "CMD_ROUTE0_MODE,CMD Route 0 Mode Register"
|
|
bitfld.long 0x0 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
|
|
bitfld.long 0x0 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x0 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
bitfld.long 0x0 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x0 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
bitfld.long 0x0 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x0 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
bitfld.long 0x0 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
line.long 0x4 "CMD_ROUTE1_MODE,CMD Route 1 Mode Register"
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|
bitfld.long 0x4 28.--30. " PLACE7 ,Stream data order [input-side data to be output to place 7 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long 0x4 24.--26. " PLACE6 ,Stream data order [input-side data to be output to place 6 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x4 20.--22. " PLACE5 ,Stream data order [input-side data to be output to place 5 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
bitfld.long 0x4 16.--18. " PLACE4 ,Stream data order [input-side data to be output to place 4 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x4 12.--14. " PLACE3 ,Stream data order [input-side data to be output to place 3 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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bitfld.long 0x4 8.--10. " PLACE2 ,Stream data order [input-side data to be output to place 2 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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textline " "
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bitfld.long 0x4 4.--6. " PLACE1 ,Stream data order [input-side data to be output to place 1 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
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|
bitfld.long 0x4 0.--2. " PLACE0 ,Stream data order [input-side data to be output to place 0 on the output side]" "Place 0,Place 1,Place 2,Place 3,Place 4,Place 5,Place 6,Place 7"
|
|
group.long 0xb0++0x03
|
|
line.long 0x00 "MOST_ROUTE_MODE,Most Route Mode Register"
|
|
bitfld.long 0x00 16. " MLB_MODE ,Selects whether to use the STREAM_mimlcp or STREAM_mlp route" "MLP,MIMLCP"
|
|
group.long 0xc0++0x03
|
|
line.long 0x00 "SRC_ROUTE_CONTROL,DRC Route Control Register"
|
|
bitfld.long 0x00 17. " START41 ,Controls the start and stop of data transfer through cmd_out_route1" "Stopped,Started"
|
|
bitfld.long 0x00 16. " START20 ,Controls the start and stop of data transfer through cmd_out_route0" "Stopped,Started"
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|
textline " "
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bitfld.long 0x00 9. " START9 ,Controls the start and stop of data transfer through src_route9" "Stopped,Started"
|
|
bitfld.long 0x00 8. " START8 ,Controls the start and stop of data transfer through src_route8" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x00 7. " START7 ,Controls the start and stop of data transfer through src_route7" "Stopped,Started"
|
|
bitfld.long 0x00 6. " START6 ,Controls the start and stop of data transfer through src_route6" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x00 5. " START5 ,Controls the start and stop of data transfer through src_route5" "Stopped,Started"
|
|
bitfld.long 0x00 4. " START4 ,Controls the start and stop of data transfer through src_route4" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x00 3. " START3 ,Controls the start and stop of data transfer through src_route3" "Stopped,Started"
|
|
bitfld.long 0x00 2. " START2 ,Controls the start and stop of data transfer through src_route2" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " START1 ,Controls the start and stop of data transfer through src_route1" "Stopped,Started"
|
|
bitfld.long 0x00 0. " START0 ,Controls the start and stop of data transfer through src_route0" "Stopped,Started"
|
|
group.long 0xd0++0x0b
|
|
line.long 0x00 "SSI_MODE0,SSI Mode Register 0"
|
|
bitfld.long 0x00 25. " IND_WORD_SWAP9 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
bitfld.long 0x00 24. " IND_WORD_SWAP8 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IND_WORD_SWAP7 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
bitfld.long 0x00 22. " IND_WORD_SWAP6 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 21. " IND_WORD_SWAP5 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
bitfld.long 0x00 20. " IND_WORD_SWAP4 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IND_WORD_SWAP3 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
bitfld.long 0x00 18. " IND_WORD_SWAP2 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " IND_WORD_SWAP1 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
bitfld.long 0x00 16. " IND_WORD_SWAP0 ,Swaps the word order for access to SSITDR or SSIRDR" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IND9 ,Independent SSI 9 transfer" "Not performed,Performed"
|
|
bitfld.long 0x00 8. " IND8 ,Independent SSI 8 transfer" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IND7 ,Independent SSI 7 transfer" "Not performed,Performed"
|
|
bitfld.long 0x00 6. " IND6 ,Independent SSI 6 transfer" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " IND5 ,Independent SSI 5 transfer" "Not performed,Performed"
|
|
bitfld.long 0x00 4. " IND4 ,Independent SSI 4 transfer" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IND3 ,Independent SSI 3 transfer" "Not performed,Performed"
|
|
bitfld.long 0x00 2. " IND2 ,Independent SSI 2 transfer" "Not performed,Performed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IND1 ,Independent SSI 1 transfer" "Not performed,Performed"
|
|
bitfld.long 0x00 0. " IND0 ,Independent SSI 0 transfer" "Not performed,Performed"
|
|
line.long 0x04 "SSI_MODE1,SSI Mode Register 1"
|
|
bitfld.long 0x04 20. " SSI34_SYNC ,Synchronize SSI# and SSI4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x04 16.--17. " SSI4_PIN ,Selects the connections of the SSI_SCK4 and SSI_WS4 pins" "Independent,SSI3 shared/both slaves,SSI3 shared/SSI3 master/SSI4 slave,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4. " SSI012_3MOD ,Selects whether to use three modules (SSI0, SSI1, and SSI2) together as six channels" "No,Yes"
|
|
bitfld.long 0x04 2.--3. " SSI2_PIN ,Selects the connections of the SSI_SCK2 and SSI_WS2 pins" "Independent,SSI0 shared/both slaves,SSI0 shared/SSI0 master/SSI2 slave,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SSI1_PIN ,Selects the connections of the SSI_SCK1 and SSI_WS1 pins" "Independent,SSI0 shared/both slaves,SSI0 shared/SSI0 master/SSI1 slave,?..."
|
|
line.long 0x08 "SSI_MODE2,SSI Mode Register 2"
|
|
bitfld.long 0x08 4. " SSI129_4MOD ,Selects whether to use four modules (SSI0, SSI1, SSI2, and SSI9) together as eight channels" "No,Yes"
|
|
bitfld.long 0x08 0.--2. " SSI9_PIN ,Selects the connections of the SSI_SCK1 and SSI_WS1 pins" "Independent,SSI0 shared/both slaves,SSI0 shared/SSI0 master/SSI9 slave,,,SSI3 shared/both slaves,SSI3 shared/SSI3 master/SSI9 slave,?..."
|
|
if (((per.l(ad:0xFFD90000+0xd8))&0x10)==0x00)
|
|
group.long 0xdc++0x03
|
|
line.long 0x00 "SSI_CONTROL,SSI Control Register"
|
|
bitfld.long 0x00 4. " SSI34 ,Starts or stops data transfer through SSI3 and SSI4 at the same time" "Stopped,Started"
|
|
bitfld.long 0x00 0. " SSI0129 ,Starts or stops data transfer through SSI0, SSI1,and SSI2 at the same time" "Stopped,Started"
|
|
else
|
|
group.long 0xdc++0x03
|
|
line.long 0x00 "SSI_CONTROL,SSI Control Register"
|
|
bitfld.long 0x00 4. " SSI34 ,Starts or stops data transfer through SSI3 and SSI4 at the same time" "Stopped,Started"
|
|
bitfld.long 0x00 0. " SSI0129 ,Starts or stops data transfer through SSI0, SSI1, SSI2 and SSI9 at the same time" "Stopped,Started"
|
|
endif
|
|
rgroup.long 0xe0++0x03
|
|
line.long 0x00 "HPBIF_STATUS,HPBIF Status Register"
|
|
bitfld.long 0x00 28. " WR_NOT_FULL9 ,Transmission buffer to be written by HPBIF9 is not full" "Full,Not full"
|
|
bitfld.long 0x00 24. " WR_NOT_FULL8 ,Transmission buffer to be written by HPBIF8 is not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WR_NOT_FULL7 ,Transmission buffer to be written by HPBIF7 is not full" "Full,Not full"
|
|
bitfld.long 0x00 22. " WR_NOT_FULL6 ,Transmission buffer to be written by HPBIF6 is not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WR_NOT_FULL5 ,Transmission buffer to be written by HPBIF5 is not full" "Full,Not full"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4 ,Transmission buffer to be written by HPBIF4 is not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WR_NOT_FULL3 ,Transmission buffer to be written by HPBIF3 is not full" "Full,Not full"
|
|
bitfld.long 0x00 18. " WR_NOT_FULL2 ,Transmission buffer to be written by HPBIF2 is not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WR_NOT_FULL1 ,Transmission buffer to be written by HPBIF1 is not full" "Full,Not full"
|
|
bitfld.long 0x00 16. " WR_NOT_FULL0 ,Transmission buffer to be written by HPBIF0 is not full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RD_NOT_EMPTY9 ,Transmission buffer to be read by HPBIF9 not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 8. " RD_NOT_EMPTY8 ,Transmission buffer to be read by HPBIF8 not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RD_NOT_EMPTY7 ,Transmission buffer to be read by HPBIF7 not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 6. " RD_NOT_EMPTY6 ,Transmission buffer to be read by HPBIF6 not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RD_NOT_EMPTY5 ,Transmission buffer to be read by HPBIF5 not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " RD_NOT_EMPTY4 ,Transmission buffer to be read by HPBIF4 not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RD_NOT_EMPTY3 ,Transmission buffer to be read by HPBIF3 not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " RD_NOT_EMPTY2 ,Transmission buffer to be read by HPBIF2 not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RD_NOT_EMPTY1 ,Transmission buffer to be read by HPBIF1 not empty" "Empty,Not empty"
|
|
bitfld.long 0x00 0. " RD_NOT_EMPTY0 ,Transmission buffer to be read by HPBIF0 not empty" "Empty,Not empty"
|
|
group.long 0xe4++0x0b
|
|
line.long 0x00 "HPBIF_INT_ENABLE,HPBIF Interrupt Enable Register"
|
|
bitfld.long 0x00 28. " WR_NOT_FULL9_IE ,Transmission buffer to be written by HPBIF9 is not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " WR_NOT_FULL8_IE ,Transmission buffer to be written by HPBIF8 is not full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WR_NOT_FULL7_IE ,Transmission buffer to be written by HPBIF7 is not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WR_NOT_FULL6_IE ,Transmission buffer to be written by HPBIF6 is not full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WR_NOT_FULL5_IE ,Transmission buffer to be written by HPBIF5 is not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4_IE ,Transmission buffer to be written by HPBIF4 is not full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " WR_NOT_FULL3_IE ,Transmission buffer to be written by HPBIF3 is not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " WR_NOT_FULL2_IE ,Transmission buffer to be written by HPBIF2 is not full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WR_NOT_FULL1_IE ,Transmission buffer to be written by HPBIF1 is not full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WR_NOT_FULL0_IE ,Transmission buffer to be written by HPBIF0 is not full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RD_NOT_EMPTY9_IE ,Transmission buffer to be read by HPBIF9 not empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RD_NOT_EMPTY8_IE ,Transmission buffer to be read by HPBIF8 not empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RD_NOT_EMPTY7_IE ,Transmission buffer to be read by HPBIF7 not empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RD_NOT_EMPTY6_IE ,Transmission buffer to be read by HPBIF6 not empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RD_NOT_EMPTY5_IE ,Transmission buffer to be read by HPBIF5 not empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RD_NOT_EMPTY4_IE ,Transmission buffer to be read by HPBIF4 not empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RD_NOT_EMPTY3_IE ,Transmission buffer to be read by HPBIF3 not empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RD_NOT_EMPTY2_IE ,Transmission buffer to be read by HPBIF2 not empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RD_NOT_EMPTY1_IE ,Transmission buffer to be read by HPBIF1 not empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RD_NOT_EMPTY0_IE ,Transmission buffer to be read by HPBIF0 not empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYSTEM_STATUS0,SYSTEM Status Register 0"
|
|
eventfld.long 0x04 28. " OF9 ,Src_route9 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 26. " OF41 ,Cmd_route1 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 25. " OF30 ,Cmd_route0 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 24. " OF8 ,Src_route8 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 23. " OF7 ,Src_route7 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 22. " OF6 ,Src_route6 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 21. " OF5 ,Src_route5 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 20. " OF4 ,Src_route4 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 19. " OF3 ,Src_route3 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 18. " OF2 ,Src_route2 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 17. " OF1 ,Src_route1 output buffer overflow" "No overflow,Overflow"
|
|
eventfld.long 0x04 16. " OF0 ,Src_route0 output buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 12. " UF9 ,Src_route9 input buffer underflow" "No uderflow,Underflow"
|
|
eventfld.long 0x04 8. " UF8 ,Src_route8 input buffer underflow" "No uderflow,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 7. " UF7 ,Src_route7 input buffer underflow" "No uderflow,Underflow"
|
|
eventfld.long 0x04 6. " UF6 ,Src_route6 input buffer underflow" "No uderflow,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 5. " UF5 ,Src_route5 input buffer underflow" "No uderflow,Underflow"
|
|
eventfld.long 0x04 4. " UF4 ,Src_route4 input buffer underflow" "No uderflow,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 3. " UF3 ,Src_route3 input buffer underflow" "No uderflow,Underflow"
|
|
eventfld.long 0x04 2. " UF2 ,Src_route2 input buffer underflow" "No uderflow,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 1. " UF1 ,Src_route1 input buffer underflow" "No uderflow,Underflow"
|
|
eventfld.long 0x04 0. " UF0 ,Src_route0 input buffer underflow" "No uderflow,Underflow"
|
|
line.long 0x08 "SYSTEM_INT_ENABLE0,System Interupt Enable Register 0"
|
|
eventfld.long 0x08 28. " OF9_IE ,Src_route9 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 26. " OF41_IE ,Cmd_route1 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 25. " OF30_IE ,Cmd_route0 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 24. " OF8_IE ,Src_route8 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 23. " OF7_IE ,Src_route7 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 22. " OF6_IE ,Src_route6 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 21. " OF5_IE ,Src_route5 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 20. " OF4_IE ,Src_route4 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 19. " OF3_IE ,Src_route3 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 18. " OF2_IE ,Src_route2 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 17. " OF1_IE ,Src_route1 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 16. " OF0_IE ,Src_route0 output buffer overflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 12. " UF9_IE ,Src_route12 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 8. " UF8_IE ,Src_route8 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 7. " UF7_IE ,Src_route7 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 6. " UF6_IE ,Src_route6 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 5. " UF5_IE ,Src_route5 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 4. " UF4_IE ,Src_route4 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 3. " UF3_IE ,Src_route3 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 2. " UF2_IE ,Src_route2 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x08 1. " UF1_IE ,Src_route1 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
eventfld.long 0x08 0. " UF0_IE ,Src_route0 input buffer underflow interupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
tree "SRC Registers (Sampling Rate Converter)"
|
|
tree "SRC 0"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "SRC0_SWRSR,SRC0 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC0_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x200+0x14)++0x03
|
|
line.long 0x00 "SRC0_ADNIR,SRC0 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x200+0x1c)++0x0f
|
|
line.long 0x00 "SRC0_IFSCR,SRC0 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC0_IFSVR,SRC0 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC0_SRCCR ,SRC0 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC0_MNFSR,SRC0 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x200+0x24))&0x1000)==0x1000)
|
|
group.long (0x200+0x2c)++0x03
|
|
line.long 0x00 "SRC0_BFSSR,SRC0 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x200+0x2c)++0x03
|
|
hide.long 0x00 "SRC0_BFSSR,SRC0 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 1"
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "SRC1_SWRSR,SRC1 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC1_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x240+0x14)++0x03
|
|
line.long 0x00 "SRC1_ADNIR,SRC1 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x240+0x1c)++0x0f
|
|
line.long 0x00 "SRC1_IFSCR,SRC1 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC1_IFSVR,SRC1 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC1_SRCCR ,SRC1 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC1_MNFSR,SRC1 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x240+0x24))&0x1000)==0x1000)
|
|
group.long (0x240+0x2c)++0x03
|
|
line.long 0x00 "SRC1_BFSSR,SRC1 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x240+0x2c)++0x03
|
|
hide.long 0x00 "SRC1_BFSSR,SRC1 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 2"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "SRC2_SWRSR,SRC2 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC2_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x280+0x14)++0x03
|
|
line.long 0x00 "SRC2_ADNIR,SRC2 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x280+0x1c)++0x0f
|
|
line.long 0x00 "SRC2_IFSCR,SRC2 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC2_IFSVR,SRC2 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC2_SRCCR ,SRC2 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC2_MNFSR,SRC2 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x280+0x24))&0x1000)==0x1000)
|
|
group.long (0x280+0x2c)++0x03
|
|
line.long 0x00 "SRC2_BFSSR,SRC2 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x280+0x2c)++0x03
|
|
hide.long 0x00 "SRC2_BFSSR,SRC2 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 3"
|
|
group.long 0x2C0++0x07
|
|
line.long 0x00 "SRC3_SWRSR,SRC3 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC3_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x2C0+0x14)++0x03
|
|
line.long 0x00 "SRC3_ADNIR,SRC3 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x2C0+0x1c)++0x0f
|
|
line.long 0x00 "SRC3_IFSCR,SRC3 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC3_IFSVR,SRC3 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC3_SRCCR ,SRC3 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC3_MNFSR,SRC3 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x2C0+0x24))&0x1000)==0x1000)
|
|
group.long (0x2C0+0x2c)++0x03
|
|
line.long 0x00 "SRC3_BFSSR,SRC3 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x2C0+0x2c)++0x03
|
|
hide.long 0x00 "SRC3_BFSSR,SRC3 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 4"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "SRC4_SWRSR,SRC4 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC4_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x300+0x14)++0x03
|
|
line.long 0x00 "SRC4_ADNIR,SRC4 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x300+0x1c)++0x0f
|
|
line.long 0x00 "SRC4_IFSCR,SRC4 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC4_IFSVR,SRC4 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC4_SRCCR ,SRC4 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC4_MNFSR,SRC4 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x300+0x24))&0x1000)==0x1000)
|
|
group.long (0x300+0x2c)++0x03
|
|
line.long 0x00 "SRC4_BFSSR,SRC4 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x300+0x2c)++0x03
|
|
hide.long 0x00 "SRC4_BFSSR,SRC4 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 5"
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "SRC5_SWRSR,SRC5 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC5_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x340+0x14)++0x03
|
|
line.long 0x00 "SRC5_ADNIR,SRC5 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x340+0x1c)++0x0f
|
|
line.long 0x00 "SRC5_IFSCR,SRC5 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC5_IFSVR,SRC5 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC5_SRCCR ,SRC5 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC5_MNFSR,SRC5 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x340+0x24))&0x1000)==0x1000)
|
|
group.long (0x340+0x2c)++0x03
|
|
line.long 0x00 "SRC5_BFSSR,SRC5 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x340+0x2c)++0x03
|
|
hide.long 0x00 "SRC5_BFSSR,SRC5 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 6"
|
|
group.long 0x380++0x07
|
|
line.long 0x00 "SRC6_SWRSR,SRC6 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC6_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x380+0x14)++0x03
|
|
line.long 0x00 "SRC6_ADNIR,SRC6 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x380+0x1c)++0x0f
|
|
line.long 0x00 "SRC6_IFSCR,SRC6 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC6_IFSVR,SRC6 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC6_SRCCR ,SRC6 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC6_MNFSR,SRC6 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x380+0x24))&0x1000)==0x1000)
|
|
group.long (0x380+0x2c)++0x03
|
|
line.long 0x00 "SRC6_BFSSR,SRC6 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x380+0x2c)++0x03
|
|
hide.long 0x00 "SRC6_BFSSR,SRC6 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 7"
|
|
group.long 0x3C0++0x07
|
|
line.long 0x00 "SRC7_SWRSR,SRC7 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC7_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x3C0+0x14)++0x03
|
|
line.long 0x00 "SRC7_ADNIR,SRC7 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x3C0+0x1c)++0x0f
|
|
line.long 0x00 "SRC7_IFSCR,SRC7 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC7_IFSVR,SRC7 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC7_SRCCR ,SRC7 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC7_MNFSR,SRC7 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x3C0+0x24))&0x1000)==0x1000)
|
|
group.long (0x3C0+0x2c)++0x03
|
|
line.long 0x00 "SRC7_BFSSR,SRC7 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x3C0+0x2c)++0x03
|
|
hide.long 0x00 "SRC7_BFSSR,SRC7 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 8"
|
|
group.long 0x400++0x07
|
|
line.long 0x00 "SRC8_SWRSR,SRC8 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC8_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x400+0x14)++0x03
|
|
line.long 0x00 "SRC8_ADNIR,SRC8 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x400+0x1c)++0x0f
|
|
line.long 0x00 "SRC8_IFSCR,SRC8 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC8_IFSVR,SRC8 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC8_SRCCR ,SRC8 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC8_MNFSR,SRC8 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x400+0x24))&0x1000)==0x1000)
|
|
group.long (0x400+0x2c)++0x03
|
|
line.long 0x00 "SRC8_BFSSR,SRC8 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x400+0x2c)++0x03
|
|
hide.long 0x00 "SRC8_BFSSR,SRC8 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree "SRC 9"
|
|
group.long 0x440++0x07
|
|
line.long 0x00 "SRC9_SWRSR,SRC9 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "SRC9_SRCIR,SRCm SRC Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
group.long (0x440+0x14)++0x03
|
|
line.long 0x00 "SRC9_ADNIR,SRC9 Audio Information Register"
|
|
bitfld.long 0x00 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x440+0x1c)++0x0f
|
|
line.long 0x00 "SRC9_IFSCR,SRC9 IFS Control Register"
|
|
bitfld.long 0x00 0. " INTIFSEN ,INTIFS Value Mode" "Disabled,Enabled"
|
|
line.long 0x04 "SRC9_IFSVR,SRC9 IFS Value Setting Register"
|
|
hexmask.long 0x04 0.--27. 1. " INTIFS ,Initial Value of FSI"
|
|
line.long 0x08 "SRC9_SRCCR ,SRC9 SRC Control Register"
|
|
bitfld.long 0x08 12. " BUFMD ,Low Delay Control by Buffer Size" "Normal,Low delay"
|
|
line.long 0x0c "SRC9_MNFSR,SRC9 Minimum FS Setting Register"
|
|
hexmask.long 0x0c 0.--27. 1. " MINFS ,Minimum FS"
|
|
if (((per.l(ad:0xFFD90000+0x440+0x24))&0x1000)==0x1000)
|
|
group.long (0x440+0x2c)++0x03
|
|
line.long 0x00 "SRC9_BFSSR,SRC9 Buffer Size Setting Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " BUFDATA ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUFIJEC ,Set the buffer size ratio when BUFMD bit of SRCCR register is 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hgroup.long (0x440+0x2c)++0x03
|
|
hide.long 0x00 "SRC9_BFSSR,SRC9 Buffer Size Setting Register"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "CTU Registers (Channel Count Conversion Unit)"
|
|
tree "CTU00"
|
|
group.long 0x500++0xb
|
|
line.long 0x00 "CTU00_SWRSR,CTU00 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT00_CTUIR,CTU00 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU00_ADINR,CTU00 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x500+0x10)++0x03
|
|
line.long 0x00 "CTU00_CPMDR,CTU00 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
group.long (0x500+0x14)++0x03
|
|
line.long 0x00 "CTU00_SCMDR,CTU00 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
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|
tree "Scale Value Registers"
|
|
group.long (0x500+0x18)++0x7f
|
|
line.long 0x00 "CTU00_SV00R,CTU00 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
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|
line.long 0x04 "CTU00_SV01R,CTU00 Scale Value e01 Register"
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|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
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|
line.long 0x08 "CTU00_SV02R,CTU00 Scale Value e02 Register"
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|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU00_SV03R,CTU00 Scale Value e03 Register"
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|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU00_SV04R,CTU00 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
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|
line.long 0x14 "CTU00_SV05R,CTU00 Scale Value e05 Register"
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|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
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|
line.long 0x18 "CTU00_SV06R,CTU00 Scale Value e06 Register"
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|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
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|
line.long 0x1c "CTU00_SV07R,CTU00 Scale Value e07 Register"
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|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
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|
line.long 0x20 "CTU00_SV10R,CTU00 Scale Value e10 Register"
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|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
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|
line.long 0x24 "CTU00_SV11R,CTU00 Scale Value e11 Register"
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|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU00_SV12R,CTU00 Scale Value e12 Register"
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|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
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|
line.long 0x2c "CTU00_SV13R,CTU00 Scale Value e13 Register"
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|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
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|
line.long 0x30 "CTU00_SV14R,CTU00 Scale Value e14 Register"
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|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
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|
line.long 0x34 "CTU00_SV15R,CTU00 Scale Value e15 Register"
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|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
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|
line.long 0x38 "CTU00_SV16R,CTU00 Scale Value e16 Register"
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|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU00_SV17R,CTU00 Scale Value e17 Register"
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|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
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|
line.long 0x40 "CTU00_SV20R,CTU00 Scale Value e20 Register"
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|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
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|
line.long 0x44 "CTU00_SV21R,CTU00 Scale Value e21 Register"
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|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU00_SV22R,CTU00 Scale Value e22 Register"
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|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
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|
line.long 0x4c "CTU00_SV23R,CTU00 Scale Value e23 Register"
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|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
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|
line.long 0x50 "CTU00_SV24R,CTU00 Scale Value e24 Register"
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|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
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|
line.long 0x54 "CTU00_SV25R,CTU00 Scale Value e25 Register"
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|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
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|
line.long 0x58 "CTU00_SV26R,CTU00 Scale Value e26 Register"
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|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU00_SV27R,CTU00 Scale Value e27 Register"
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|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU00_SV30R,CTU00 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU00_SV31R,CTU00 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU00_SV32R,CTU00 Scale Value e32 Register"
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|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
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|
line.long 0x6c "CTU00_SV33R,CTU00 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
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|
line.long 0x70 "CTU00_SV34R,CTU00 Scale Value e34 Register"
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|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU00_SV35R,CTU00 Scale Value e35 Register"
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|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU00_SV36R,CTU00 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU00_SV37R,CTU00 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU01"
|
|
group.long 0x600++0xb
|
|
line.long 0x00 "CTU01_SWRSR,CTU01 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT01_CTUIR,CTU01 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU01_ADINR,CTU01 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x600+0x10)++0x03
|
|
line.long 0x00 "CTU01_CPMDR,CTU01 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
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|
group.long (0x600+0x14)++0x03
|
|
line.long 0x00 "CTU01_SCMDR,CTU01 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0x600+0x18)++0x7f
|
|
line.long 0x00 "CTU01_SV00R,CTU01 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU01_SV01R,CTU01 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU01_SV02R,CTU01 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU01_SV03R,CTU01 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU01_SV04R,CTU01 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU01_SV05R,CTU01 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU01_SV06R,CTU01 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU01_SV07R,CTU01 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU01_SV10R,CTU01 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU01_SV11R,CTU01 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU01_SV12R,CTU01 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU01_SV13R,CTU01 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU01_SV14R,CTU01 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU01_SV15R,CTU01 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU01_SV16R,CTU01 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU01_SV17R,CTU01 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU01_SV20R,CTU01 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU01_SV21R,CTU01 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU01_SV22R,CTU01 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU01_SV23R,CTU01 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU01_SV24R,CTU01 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU01_SV25R,CTU01 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU01_SV26R,CTU01 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU01_SV27R,CTU01 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU01_SV30R,CTU01 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU01_SV31R,CTU01 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU01_SV32R,CTU01 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU01_SV33R,CTU01 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU01_SV34R,CTU01 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU01_SV35R,CTU01 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU01_SV36R,CTU01 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU01_SV37R,CTU01 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU02"
|
|
group.long 0x700++0xb
|
|
line.long 0x00 "CTU02_SWRSR,CTU02 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT02_CTUIR,CTU02 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU02_ADINR,CTU02 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x700+0x10)++0x03
|
|
line.long 0x00 "CTU02_CPMDR,CTU02 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0x700+0x14)++0x03
|
|
line.long 0x00 "CTU02_SCMDR,CTU02 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0x700+0x18)++0x7f
|
|
line.long 0x00 "CTU02_SV00R,CTU02 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU02_SV01R,CTU02 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU02_SV02R,CTU02 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU02_SV03R,CTU02 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU02_SV04R,CTU02 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU02_SV05R,CTU02 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU02_SV06R,CTU02 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU02_SV07R,CTU02 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU02_SV10R,CTU02 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU02_SV11R,CTU02 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU02_SV12R,CTU02 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU02_SV13R,CTU02 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU02_SV14R,CTU02 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU02_SV15R,CTU02 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU02_SV16R,CTU02 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU02_SV17R,CTU02 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU02_SV20R,CTU02 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU02_SV21R,CTU02 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU02_SV22R,CTU02 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU02_SV23R,CTU02 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU02_SV24R,CTU02 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU02_SV25R,CTU02 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU02_SV26R,CTU02 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU02_SV27R,CTU02 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU02_SV30R,CTU02 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU02_SV31R,CTU02 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU02_SV32R,CTU02 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU02_SV33R,CTU02 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU02_SV34R,CTU02 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU02_SV35R,CTU02 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU02_SV36R,CTU02 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU02_SV37R,CTU02 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU03"
|
|
group.long 0x800++0xb
|
|
line.long 0x00 "CTU03_SWRSR,CTU03 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT03_CTUIR,CTU03 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU03_ADINR,CTU03 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x800+0x10)++0x03
|
|
line.long 0x00 "CTU03_CPMDR,CTU03 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0x800+0x14)++0x03
|
|
line.long 0x00 "CTU03_SCMDR,CTU03 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0x800+0x18)++0x7f
|
|
line.long 0x00 "CTU03_SV00R,CTU03 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU03_SV01R,CTU03 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU03_SV02R,CTU03 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU03_SV03R,CTU03 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU03_SV04R,CTU03 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU03_SV05R,CTU03 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU03_SV06R,CTU03 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU03_SV07R,CTU03 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU03_SV10R,CTU03 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU03_SV11R,CTU03 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU03_SV12R,CTU03 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU03_SV13R,CTU03 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU03_SV14R,CTU03 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU03_SV15R,CTU03 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU03_SV16R,CTU03 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU03_SV17R,CTU03 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU03_SV20R,CTU03 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU03_SV21R,CTU03 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU03_SV22R,CTU03 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU03_SV23R,CTU03 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU03_SV24R,CTU03 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU03_SV25R,CTU03 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU03_SV26R,CTU03 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU03_SV27R,CTU03 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU03_SV30R,CTU03 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU03_SV31R,CTU03 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU03_SV32R,CTU03 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU03_SV33R,CTU03 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU03_SV34R,CTU03 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU03_SV35R,CTU03 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU03_SV36R,CTU03 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU03_SV37R,CTU03 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU10"
|
|
group.long 0x900++0xb
|
|
line.long 0x00 "CTU10_SWRSR,CTU10 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT10_CTUIR,CTU10 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU10_ADINR,CTU10 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0x900+0x10)++0x03
|
|
line.long 0x00 "CTU10_CPMDR,CTU10 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0x900+0x14)++0x03
|
|
line.long 0x00 "CTU10_SCMDR,CTU10 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0x900+0x18)++0x7f
|
|
line.long 0x00 "CTU10_SV00R,CTU10 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU10_SV01R,CTU10 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU10_SV02R,CTU10 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU10_SV03R,CTU10 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU10_SV04R,CTU10 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU10_SV05R,CTU10 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU10_SV06R,CTU10 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU10_SV07R,CTU10 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU10_SV10R,CTU10 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU10_SV11R,CTU10 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU10_SV12R,CTU10 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU10_SV13R,CTU10 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU10_SV14R,CTU10 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU10_SV15R,CTU10 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU10_SV16R,CTU10 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU10_SV17R,CTU10 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU10_SV20R,CTU10 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU10_SV21R,CTU10 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU10_SV22R,CTU10 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU10_SV23R,CTU10 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU10_SV24R,CTU10 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU10_SV25R,CTU10 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU10_SV26R,CTU10 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU10_SV27R,CTU10 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU10_SV30R,CTU10 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU10_SV31R,CTU10 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU10_SV32R,CTU10 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU10_SV33R,CTU10 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU10_SV34R,CTU10 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU10_SV35R,CTU10 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU10_SV36R,CTU10 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU10_SV37R,CTU10 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU11"
|
|
group.long 0xA00++0xb
|
|
line.long 0x00 "CTU11_SWRSR,CTU11 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT11_CTUIR,CTU11 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU11_ADINR,CTU11 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xA00+0x10)++0x03
|
|
line.long 0x00 "CTU11_CPMDR,CTU11 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0xA00+0x14)++0x03
|
|
line.long 0x00 "CTU11_SCMDR,CTU11 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0xA00+0x18)++0x7f
|
|
line.long 0x00 "CTU11_SV00R,CTU11 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU11_SV01R,CTU11 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU11_SV02R,CTU11 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU11_SV03R,CTU11 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU11_SV04R,CTU11 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU11_SV05R,CTU11 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU11_SV06R,CTU11 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU11_SV07R,CTU11 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU11_SV10R,CTU11 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU11_SV11R,CTU11 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU11_SV12R,CTU11 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU11_SV13R,CTU11 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU11_SV14R,CTU11 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU11_SV15R,CTU11 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU11_SV16R,CTU11 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU11_SV17R,CTU11 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU11_SV20R,CTU11 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU11_SV21R,CTU11 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU11_SV22R,CTU11 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU11_SV23R,CTU11 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU11_SV24R,CTU11 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU11_SV25R,CTU11 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU11_SV26R,CTU11 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU11_SV27R,CTU11 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU11_SV30R,CTU11 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU11_SV31R,CTU11 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU11_SV32R,CTU11 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU11_SV33R,CTU11 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU11_SV34R,CTU11 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU11_SV35R,CTU11 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU11_SV36R,CTU11 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU11_SV37R,CTU11 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU12"
|
|
group.long 0xB00++0xb
|
|
line.long 0x00 "CTU12_SWRSR,CTU12 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT12_CTUIR,CTU12 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU12_ADINR,CTU12 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xB00+0x10)++0x03
|
|
line.long 0x00 "CTU12_CPMDR,CTU12 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0xB00+0x14)++0x03
|
|
line.long 0x00 "CTU12_SCMDR,CTU12 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0xB00+0x18)++0x7f
|
|
line.long 0x00 "CTU12_SV00R,CTU12 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU12_SV01R,CTU12 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU12_SV02R,CTU12 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU12_SV03R,CTU12 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU12_SV04R,CTU12 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU12_SV05R,CTU12 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU12_SV06R,CTU12 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU12_SV07R,CTU12 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU12_SV10R,CTU12 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU12_SV11R,CTU12 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU12_SV12R,CTU12 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU12_SV13R,CTU12 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU12_SV14R,CTU12 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU12_SV15R,CTU12 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU12_SV16R,CTU12 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU12_SV17R,CTU12 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU12_SV20R,CTU12 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU12_SV21R,CTU12 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU12_SV22R,CTU12 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU12_SV23R,CTU12 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU12_SV24R,CTU12 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU12_SV25R,CTU12 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU12_SV26R,CTU12 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU12_SV27R,CTU12 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU12_SV30R,CTU12 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU12_SV31R,CTU12 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU12_SV32R,CTU12 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU12_SV33R,CTU12 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU12_SV34R,CTU12 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU12_SV35R,CTU12 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU12_SV36R,CTU12 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU12_SV37R,CTU12 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree "CTU13"
|
|
group.long 0xC00++0xb
|
|
line.long 0x00 "CTU13_SWRSR,CTU13 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "CUT13_CTUIR,CTU13 CTU Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Processing,Initialization"
|
|
line.long 0x08 "CTU13_ADINR,CTU13 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xC00+0x10)++0x03
|
|
line.long 0x00 "CTU13_CPMDR,CTU13 CTU Pass Mode Register"
|
|
bitfld.long 0x00 28.--31. " SELOT7 ,Select output data for channel 7" "Channel 7,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 24.--27. " SELOT6 ,Select output data for channel 6" "Channel 6,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " SELOT5 ,Select output data for channel 5" "Channel 5,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 16.--19. " SELOT4 ,Select output data for channel 4" "Channel 4,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SELOT3 ,Select output data for channel 3" "Channel 3,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 8.--11. " SELOT2 ,Select output data for channel 2" "Channel 2,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SELOT1 ,Select output data for channel 1" "Channel 1,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
bitfld.long 0x00 0.--3. " SELOT0 ,Select output data for channel 0" "Channel 0,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Matrix row 0,Matrix row 1,Matrix row 2,Matrix row 3,?..."
|
|
group.long (0xC00+0x14)++0x03
|
|
line.long 0x00 "CTU13_SCMDR,CTU13 Scale Mode Register"
|
|
bitfld.long 0x00 0.--2. " SCMD ,The number of rows calculated by matrix" "No operation,Row 0,Row0/1,Row 0/1/2,Row 0/1/2/3,?..."
|
|
tree "Scale Value Registers"
|
|
group.long (0xC00+0x18)++0x7f
|
|
line.long 0x00 "CTU13_SV00R,CTU13 Scale Value e00 Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " SVE00 ,Scale Value e00 for Input Channel 0 of Matrix Row 0"
|
|
line.long 0x04 "CTU13_SV01R,CTU13 Scale Value e01 Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " SVE01 ,Scale Value e01 for Input Channel 1 of Matrix Row 0"
|
|
line.long 0x08 "CTU13_SV02R,CTU13 Scale Value e02 Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " SVE02 ,Scale Value e02 for Input Channel 2 of Matrix Row 0"
|
|
line.long 0x0c "CTU13_SV03R,CTU13 Scale Value e03 Register"
|
|
hexmask.long.tbyte 0xc 0.--23. 1. " SVE03 ,Scale Value e03 for Input Channel 3 of Matrix Row 0"
|
|
line.long 0x10 "CTU13_SV04R,CTU13 Scale Value e04 Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SVE04 ,Scale Value e04 for Input Channel 4 of Matrix Row 0"
|
|
line.long 0x14 "CTU13_SV05R,CTU13 Scale Value e05 Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " SVE05 ,Scale Value e05 for Input Channel 5 of Matrix Row 0"
|
|
line.long 0x18 "CTU13_SV06R,CTU13 Scale Value e06 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " SVE06 ,Scale Value e06 for Input Channel 6 of Matrix Row 0"
|
|
line.long 0x1c "CTU13_SV07R,CTU13 Scale Value e07 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " SVE07 ,Scale Value e07 for Input Channel 7 of Matrix Row 0"
|
|
line.long 0x20 "CTU13_SV10R,CTU13 Scale Value e10 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " SVE10 ,Scale Value e10 for Input Channel 0 of Matrix Row 1"
|
|
line.long 0x24 "CTU13_SV11R,CTU13 Scale Value e11 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " SVE11 ,Scale Value e11 for Input Channel 1 of Matrix Row 1"
|
|
line.long 0x28 "CTU13_SV12R,CTU13 Scale Value e12 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " SVE12 ,Scale Value e12 for Input Channel 2 of Matrix Row 1"
|
|
line.long 0x2c "CTU13_SV13R,CTU13 Scale Value e13 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " SVE13 ,Scale Value e13 for Input Channel 3 of Matrix Row 1"
|
|
line.long 0x30 "CTU13_SV14R,CTU13 Scale Value e14 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " SVE14 ,Scale Value e14 for Input Channel 4 of Matrix Row 1"
|
|
line.long 0x34 "CTU13_SV15R,CTU13 Scale Value e15 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " SVE15 ,Scale Value e15 for Input Channel 5 of Matrix Row 1"
|
|
line.long 0x38 "CTU13_SV16R,CTU13 Scale Value e16 Register"
|
|
hexmask.long.tbyte 0x38 0.--23. 1. " SVE16 ,Scale Value e16 for Input Channel 6 of Matrix Row 1"
|
|
line.long 0x3c "CTU13_SV17R,CTU13 Scale Value e17 Register"
|
|
hexmask.long.tbyte 0x3c 0.--23. 1. " SVE17 ,Scale Value e17 for Input Channel 7 of Matrix Row 1"
|
|
line.long 0x40 "CTU13_SV20R,CTU13 Scale Value e20 Register"
|
|
hexmask.long.tbyte 0x40 0.--23. 1. " SVE20 ,Scale Value e20 for Input Channel 0 of Matrix Row 2"
|
|
line.long 0x44 "CTU13_SV21R,CTU13 Scale Value e21 Register"
|
|
hexmask.long.tbyte 0x44 0.--23. 1. " SVE21 ,Scale Value e21 for Input Channel 1 of Matrix Row 2"
|
|
line.long 0x48 "CTU13_SV22R,CTU13 Scale Value e22 Register"
|
|
hexmask.long.tbyte 0x48 0.--23. 1. " SVE22 ,Scale Value e22 for Input Channel 2 of Matrix Row 2"
|
|
line.long 0x4c "CTU13_SV23R,CTU13 Scale Value e23 Register"
|
|
hexmask.long.tbyte 0x4c 0.--23. 1. " SVE23 ,Scale Value e23 for Input Channel 3 of Matrix Row 2"
|
|
line.long 0x50 "CTU13_SV24R,CTU13 Scale Value e24 Register"
|
|
hexmask.long.tbyte 0x50 0.--23. 1. " SVE24 ,Scale Value e24 for Input Channel 4 of Matrix Row 2"
|
|
line.long 0x54 "CTU13_SV25R,CTU13 Scale Value e25 Register"
|
|
hexmask.long.tbyte 0x54 0.--23. 1. " SVE25 ,Scale Value e25 for Input Channel 5 of Matrix Row 2"
|
|
line.long 0x58 "CTU13_SV26R,CTU13 Scale Value e26 Register"
|
|
hexmask.long.tbyte 0x58 0.--23. 1. " SVE26 ,Scale Value e26 for Input Channel 6 of Matrix Row 2"
|
|
line.long 0x5c "CTU13_SV27R,CTU13 Scale Value e27 Register"
|
|
hexmask.long.tbyte 0x5c 0.--23. 1. " SVE27 ,Scale Value e27 for Input Channel 7 of Matrix Row 2"
|
|
line.long 0x60 "CTU13_SV30R,CTU13 Scale Value e30 Register"
|
|
hexmask.long.tbyte 0x60 0.--23. 1. " SVE30 ,Scale Value e30 for Input Channel 0 of Matrix Row 3"
|
|
line.long 0x64 "CTU13_SV31R,CTU13 Scale Value e31 Register"
|
|
hexmask.long.tbyte 0x64 0.--23. 1. " SVE31 ,Scale Value e31 for Input Channel 1 of Matrix Row 3"
|
|
line.long 0x68 "CTU13_SV32R,CTU13 Scale Value e32 Register"
|
|
hexmask.long.tbyte 0x68 0.--23. 1. " SVE32 ,Scale Value e32 for Input Channel 2 of Matrix Row 3"
|
|
line.long 0x6c "CTU13_SV33R,CTU13 Scale Value e33 Register"
|
|
hexmask.long.tbyte 0x6c 0.--23. 1. " SVE33 ,Scale Value e33 for Input Channel 3 of Matrix Row 3"
|
|
line.long 0x70 "CTU13_SV34R,CTU13 Scale Value e34 Register"
|
|
hexmask.long.tbyte 0x70 0.--23. 1. " SVE34 ,Scale Value e34 for Input Channel 4 of Matrix Row 3"
|
|
line.long 0x74 "CTU13_SV35R,CTU13 Scale Value e35 Register"
|
|
hexmask.long.tbyte 0x74 0.--23. 1. " SVE35 ,Scale Value e35 for Input Channel 5 of Matrix Row 3"
|
|
line.long 0x78 "CTU13_SV36R,CTU13 Scale Value e36 Register"
|
|
hexmask.long.tbyte 0x78 0.--23. 1. " SVE36 ,Scale Value e36 for Input Channel 6 of Matrix Row 3"
|
|
line.long 0x7c "CTU13_SV37R,CTU13 Scale Value e37 Register"
|
|
hexmask.long.tbyte 0x7c 0.--23. 1. " SVE37 ,Scale Value e37 for Input Channel 7 of Matrix Row 3"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "MIX Registers"
|
|
tree "MIX0"
|
|
group.long 0xD00++0x0b
|
|
line.long 0x00 "MIX0_SWRSR,MIX0 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "MIX0_MIXIR,MIX0 Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Procesing,Initialization"
|
|
line.long 0x08 "MIX0_ADINR,MIX0 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xD00+0x10)++0x1b
|
|
line.long 0x00 "MIX0_MIXMR,MIX0 MIX Mode Register"
|
|
bitfld.long 0x00 0. " MIXMODE ,MIX Mode" "Volume step,Volume ramp"
|
|
line.long 0x04 "MIX0_MVPDR,MIX0 MIX Volume Period Register"
|
|
bitfld.long 0x04 8.--11. " MXPDUP ,MIX Period for Volume Up [/1 sample]" "128 dB,64 dB,32 dB,16 dB,8 dB,4 dB,2 dB,1 dB,0.5 dB,0.25 dB,0.125 dB,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " MXPDDW ,MIX Period for Volume Down [/1 sample]" "-128 dB,-64 dB,-32 dB,-16 dB,-8 dB,-4 dB,-2 dB,-1 dB,-0.5 dB,-0.25 dB,-0.125 dB,-,?..."
|
|
line.long 0x08 "MIX0_MDBAR,MIX0 MIX Decibel A Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " MXDBA ,dB of System A"
|
|
line.long 0x0c "MIX0_MDBBR,MIX0 MIX Decibel B Register"
|
|
hexmask.long.word 0x0c 0.--9. 1. " MXDBB ,dB of System B"
|
|
line.long 0x10 "MIX0_MDBCR,MIX0 MIX Decibel C Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " MXDBC ,dB of System C"
|
|
line.long 0x14 "MIX0_MDBDR,MIX0 MIX Decibel D Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " MXDBD ,dB of System D"
|
|
line.long 0x18 "MIX0_MDBER,MIX0 MIX Decibel Enable Register"
|
|
bitfld.long 0x18 0. " MIXDVEN ,MIX dB Enable" "Disabled,Enabled"
|
|
rgroup.long (0xD00+0x2c)++0x03
|
|
line.long 0x00 "MIX0_MIXSR,MIX0 MIX Status Register"
|
|
bitfld.long 0x00 0.--1. " MRPSTS ,MIX Volume Ramp Status" "Stable,Down,Up,?..."
|
|
tree.end
|
|
tree "MIX1"
|
|
group.long 0xD40++0x0b
|
|
line.long 0x00 "MIX1_SWRSR,MIX1 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "MIX1_MIXIR,MIX1 Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Procesing,Initialization"
|
|
line.long 0x08 "MIX1_ADINR,MIX1 Audio Information Register"
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xD40+0x10)++0x1b
|
|
line.long 0x00 "MIX1_MIXMR,MIX1 MIX Mode Register"
|
|
bitfld.long 0x00 0. " MIXMODE ,MIX Mode" "Volume step,Volume ramp"
|
|
line.long 0x04 "MIX1_MVPDR,MIX1 MIX Volume Period Register"
|
|
bitfld.long 0x04 8.--11. " MXPDUP ,MIX Period for Volume Up [/1 sample]" "128 dB,64 dB,32 dB,16 dB,8 dB,4 dB,2 dB,1 dB,0.5 dB,0.25 dB,0.125 dB,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " MXPDDW ,MIX Period for Volume Down [/1 sample]" "-128 dB,-64 dB,-32 dB,-16 dB,-8 dB,-4 dB,-2 dB,-1 dB,-0.5 dB,-0.25 dB,-0.125 dB,-,?..."
|
|
line.long 0x08 "MIX1_MDBAR,MIX1 MIX Decibel A Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " MXDBA ,dB of System A"
|
|
line.long 0x0c "MIX1_MDBBR,MIX1 MIX Decibel B Register"
|
|
hexmask.long.word 0x0c 0.--9. 1. " MXDBB ,dB of System B"
|
|
line.long 0x10 "MIX1_MDBCR,MIX1 MIX Decibel C Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " MXDBC ,dB of System C"
|
|
line.long 0x14 "MIX1_MDBDR,MIX1 MIX Decibel D Register"
|
|
hexmask.long.word 0x14 0.--9. 1. " MXDBD ,dB of System D"
|
|
line.long 0x18 "MIX1_MDBER,MIX1 MIX Decibel Enable Register"
|
|
bitfld.long 0x18 0. " MIXDVEN ,MIX dB Enable" "Disabled,Enabled"
|
|
rgroup.long (0xD40+0x2c)++0x03
|
|
line.long 0x00 "MIX1_MIXSR,MIX1 MIX Status Register"
|
|
bitfld.long 0x00 0.--1. " MRPSTS ,MIX Volume Ramp Status" "Stable,Down,Up,?..."
|
|
tree.end
|
|
tree.end
|
|
tree "DVC Registers"
|
|
tree "DVC0"
|
|
group.long 0xE00++0x0B
|
|
line.long 0x00 "DVC0_SWRSR,DVC0 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "DVC0_DVCIR,DVC0 Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Procesing,Initialization"
|
|
line.long 0x08 "DVC0_ADINR,DVC0 Audio Information Register"
|
|
bitfld.long 0x08 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xE00+0x10)++0x3b
|
|
line.long 0x00 "DVC0_DVUCR,DVC0 DVU Control Register"
|
|
bitfld.long 0x00 8. " VVMD ,Select Digital Volume Value Mode" "Not used,Used"
|
|
bitfld.long 0x00 4. " VRMD ,Select Volume Ramp Mode" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZCMD ,Select Zero Cross Mute Mode" "Not used,Used"
|
|
line.long 0x04 "DVC0_ZCMCR,DVC0 Zero Cross Mute Control Register"
|
|
bitfld.long 0x04 7. " ZCEN7 ,Zero Cross Mute Enable for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ZCEN6 ,Zero Cross Mute Enable for Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ZCEN5 ,Zero Cross Mute Enable for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ZCEN4 ,Zero Cross Mute Enable for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ZCEN3 ,Zero Cross Mute Enable for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ZCEN2 ,Zero Cross Mute Enable for Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ZCEN1 ,Zero Cross Mute Enable for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ZCEN0 ,Zero Cross Mute Enable for Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "DVC0_VRCTR,DVC0 Volume Ramp Control Register"
|
|
bitfld.long 0x08 7. " VREN7 ,Volume Ramp Enable for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " VREN6 ,Volume Ramp Enable for Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " VREN5 ,Volume Ramp Enable for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " VREN4 ,Volume Ramp Enable for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " VREN3 ,Volume Ramp Enable for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " VREN2 ,Volume Ramp Enable for Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " VREN1 ,Volume Ramp Enable for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " VREN0 ,Volume Ramp Enable for Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "DVC0_VRPDR,DVC0 Volume Ramp Period Register"
|
|
bitfld.long 0x0c 8.--12. " VRPDUP ,Volume Ramp Period for Volume Up [sample]" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288,1048576,2097152,4194304,8388608,?..."
|
|
bitfld.long 0x0c 0.--4. " VRPDDW ,Volume Ramp Period for Volume Down [sample]" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288,1048576,2097152,4194304,8388608,?..."
|
|
line.long 0x10 "DVC0_VRDBR,DVC0 Volume Ramp Decibel Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " VRDB ,dB of Volume Ramp"
|
|
line.long 0x14 "DVC0_VRWTR,DVC0 Volume Ramp Wait Time Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " VRWT ,Volume Ramp Wait Time"
|
|
line.long 0x18 "DVC0_VOL0R,DVC0 Volume Value Setting 0 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " VOLVAL0 ,Digital Volume Value for Channel 0"
|
|
line.long 0x1c "DVC0_VOL1R,DVC0 Volume Value Setting 1 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " VOLVAL1 ,Digital Volume Value for Channel 1"
|
|
line.long 0x20 "DVC0_VOL2R,DVC0 Volume Value Setting 2 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " VOLVAL2 ,Digital Volume Value for Channel 2"
|
|
line.long 0x24 "DVC0_VOL3R,DVC0 Volume Value Setting 3 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " VOLVAL3 ,Digital Volume Value for Channel 3"
|
|
line.long 0x28 "DVC0_VOL4R,DVC0 Volume Value Setting 4 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " VOLVAL4 ,Digital Volume Value for Channel 4"
|
|
line.long 0x2c "DVC0_VOL5R,DVC0 Volume Value Setting 5 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " VOLVAL5 ,Digital Volume Value for Channel 5"
|
|
line.long 0x30 "DVC0_VOL6R,DVC0 Volume Value Setting 6 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " VOLVAL6 ,Digital Volume Value for Channel 6"
|
|
line.long 0x34 "DVC0_VOL7R,DVC0 Volume Value Setting 7 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " VOLVAL7 ,Digital Volume Value for Channel 7"
|
|
line.long 0x38 "DVC0_DVUER,DVC0 DVU Enable Register"
|
|
bitfld.long 0x38 0. " DVCEN ,DVC Register Setting Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "DVC1"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "DVC1_SWRSR,DVC1 Software Reset Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software Reset" "Reset,No reset"
|
|
line.long 0x04 "DVC1_DVCIR,DVC1 Initialization Register"
|
|
bitfld.long 0x04 0. " INIT ,Initialization of Processing" "Procesing,Initialization"
|
|
line.long 0x08 "DVC1_ADINR,DVC1 Audio Information Register"
|
|
bitfld.long 0x08 16.--20. " OTBL ,Bit Length of Output Audio Data" "24 bits,,22 bits,,20 bits,,18 bits,,16 bits,,,,,,,,8 bits,?..."
|
|
bitfld.long 0x08 0.--3. " CHNUM ,Channel Number" "0 (None),1,2,,4,,6,,8,?..."
|
|
group.long (0xF00+0x10)++0x3b
|
|
line.long 0x00 "DVC1_DVUCR,DVC1 DVU Control Register"
|
|
bitfld.long 0x00 8. " VVMD ,Select Digital Volume Value Mode" "Not used,Used"
|
|
bitfld.long 0x00 4. " VRMD ,Select Volume Ramp Mode" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ZCMD ,Select Zero Cross Mute Mode" "Not used,Used"
|
|
line.long 0x04 "DVC1_ZCMCR,DVC1 Zero Cross Mute Control Register"
|
|
bitfld.long 0x04 7. " ZCEN7 ,Zero Cross Mute Enable for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " ZCEN6 ,Zero Cross Mute Enable for Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ZCEN5 ,Zero Cross Mute Enable for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " ZCEN4 ,Zero Cross Mute Enable for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ZCEN3 ,Zero Cross Mute Enable for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ZCEN2 ,Zero Cross Mute Enable for Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ZCEN1 ,Zero Cross Mute Enable for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ZCEN0 ,Zero Cross Mute Enable for Channel 0" "Disabled,Enabled"
|
|
line.long 0x08 "DVC1_VRCTR,DVC1 Volume Ramp Control Register"
|
|
bitfld.long 0x08 7. " VREN7 ,Volume Ramp Enable for Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " VREN6 ,Volume Ramp Enable for Channel 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " VREN5 ,Volume Ramp Enable for Channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " VREN4 ,Volume Ramp Enable for Channel 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " VREN3 ,Volume Ramp Enable for Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " VREN2 ,Volume Ramp Enable for Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " VREN1 ,Volume Ramp Enable for Channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " VREN0 ,Volume Ramp Enable for Channel 0" "Disabled,Enabled"
|
|
line.long 0x0c "DVC1_VRPDR,DVC1 Volume Ramp Period Register"
|
|
bitfld.long 0x0c 8.--12. " VRPDUP ,Volume Ramp Period for Volume Up [sample]" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288,1048576,2097152,4194304,8388608,?..."
|
|
bitfld.long 0x0c 0.--4. " VRPDDW ,Volume Ramp Period for Volume Down [sample]" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072,262144,524288,1048576,2097152,4194304,8388608,?..."
|
|
line.long 0x10 "DVC1_VRDBR,DVC1 Volume Ramp Decibel Register"
|
|
hexmask.long.word 0x10 0.--9. 1. " VRDB ,dB of Volume Ramp"
|
|
line.long 0x14 "DVC1_VRWTR,DVC1 Volume Ramp Wait Time Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " VRWT ,Volume Ramp Wait Time"
|
|
line.long 0x18 "DVC1_VOL0R,DVC1 Volume Value Setting 0 Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " VOLVAL0 ,Digital Volume Value for Channel 0"
|
|
line.long 0x1c "DVC1_VOL1R,DVC1 Volume Value Setting 1 Register"
|
|
hexmask.long.tbyte 0x1c 0.--23. 1. " VOLVAL1 ,Digital Volume Value for Channel 1"
|
|
line.long 0x20 "DVC1_VOL2R,DVC1 Volume Value Setting 2 Register"
|
|
hexmask.long.tbyte 0x20 0.--23. 1. " VOLVAL2 ,Digital Volume Value for Channel 2"
|
|
line.long 0x24 "DVC1_VOL3R,DVC1 Volume Value Setting 3 Register"
|
|
hexmask.long.tbyte 0x24 0.--23. 1. " VOLVAL3 ,Digital Volume Value for Channel 3"
|
|
line.long 0x28 "DVC1_VOL4R,DVC1 Volume Value Setting 4 Register"
|
|
hexmask.long.tbyte 0x28 0.--23. 1. " VOLVAL4 ,Digital Volume Value for Channel 4"
|
|
line.long 0x2c "DVC1_VOL5R,DVC1 Volume Value Setting 5 Register"
|
|
hexmask.long.tbyte 0x2c 0.--23. 1. " VOLVAL5 ,Digital Volume Value for Channel 5"
|
|
line.long 0x30 "DVC1_VOL6R,DVC1 Volume Value Setting 6 Register"
|
|
hexmask.long.tbyte 0x30 0.--23. 1. " VOLVAL6 ,Digital Volume Value for Channel 6"
|
|
line.long 0x34 "DVC1_VOL7R,DVC1 Volume Value Setting 7 Register"
|
|
hexmask.long.tbyte 0x34 0.--23. 1. " VOLVAL7 ,Digital Volume Value for Channel 7"
|
|
line.long 0x38 "DVC1_DVUER,DVC1 DVU Enable Register"
|
|
bitfld.long 0x38 0. " DVCEN ,DVC Register Setting Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "HPBIF Data Storing Registers"
|
|
group.long 0x10000++0x03
|
|
line.long 0x00 "HPBIF0,HPBIF0 Data Storing Registers"
|
|
group.long 0x11000++0x03
|
|
line.long 0x00 "HPBIF1,HPBIF1 Data Storing Registers"
|
|
group.long 0x12000++0x03
|
|
line.long 0x00 "HPBIF2,HPBIF2 Data Storing Registers"
|
|
group.long 0x13000++0x03
|
|
line.long 0x00 "HPBIF3,HPBIF3 Data Storing Registers"
|
|
group.long 0x14000++0x03
|
|
line.long 0x00 "HPBIF4,HPBIF4 Data Storing Registers"
|
|
group.long 0x15000++0x03
|
|
line.long 0x00 "HPBIF5,HPBIF5 Data Storing Registers"
|
|
group.long 0x16000++0x03
|
|
line.long 0x00 "HPBIF6,HPBIF6 Data Storing Registers"
|
|
group.long 0x17000++0x03
|
|
line.long 0x00 "HPBIF7,HPBIF7 Data Storing Registers"
|
|
group.long 0x18000++0x03
|
|
line.long 0x00 "HPBIF8,HPBIF8 Data Storing Registers"
|
|
group.long 0x19000++0x03
|
|
line.long 0x00 "HPBIF9,HPBIF9 Data Storing Registers"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "SSI (Serial Sound Interface)"
|
|
tree "Channel 0"
|
|
base ad:0xFFD91000
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91000+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91000+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91000+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91000+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91000))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91000))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR0,Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91000))&0x02)==0x00)&&(((per.l(ad:0xFFD91000+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR0,Status Register 0"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91000))&0x02)==0x02)&&(((per.l(ad:0xFFD91000+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR0,Status Register 0"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91000))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR0,Status Register 0"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR0,Status Register 0"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR0,Transmit Data Register 0"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR0,Receive Data Register 0"
|
|
if (((per.l(ad:0xFFD91000+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91000))&0xc000)==0xc000)||(((per.l(ad:0xFFD91000))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91000))&0xc000)==0xc000))||(((per.l(ad:0xFFD91000))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91000+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91000+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91000))&0xc000)==0xc000))||(((per.l(ad:0xFFD91000))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR0,WS Mode Register 0"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR0,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR0,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE0,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFD91040
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91040+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91040+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91040+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91040+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91040))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91040))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR1,Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91040))&0x02)==0x00)&&(((per.l(ad:0xFFD91040+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR1,Status Register 1"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91040))&0x02)==0x02)&&(((per.l(ad:0xFFD91040+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR1,Status Register 1"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91040))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR1,Status Register 1"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR1,Status Register 1"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR1,Transmit Data Register 1"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR1,Receive Data Register 1"
|
|
if (((per.l(ad:0xFFD91040+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91040))&0xc000)==0xc000)||(((per.l(ad:0xFFD91040))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91040))&0xc000)==0xc000))||(((per.l(ad:0xFFD91040))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91040+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91040+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91040))&0xc000)==0xc000))||(((per.l(ad:0xFFD91040))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR1,WS Mode Register 1"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR1,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR1,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE1,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFD91080
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91080+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91080+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91080+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91080+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91080))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91080))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR2,Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91080))&0x02)==0x00)&&(((per.l(ad:0xFFD91080+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR2,Status Register 2"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91080))&0x02)==0x02)&&(((per.l(ad:0xFFD91080+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR2,Status Register 2"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91080))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR2,Status Register 2"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR2,Status Register 2"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR2,Transmit Data Register 2"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR2,Receive Data Register 2"
|
|
if (((per.l(ad:0xFFD91080+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91080))&0xc000)==0xc000)||(((per.l(ad:0xFFD91080))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91080))&0xc000)==0xc000))||(((per.l(ad:0xFFD91080))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91080+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91080+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91080))&0xc000)==0xc000))||(((per.l(ad:0xFFD91080))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR2,WS Mode Register 2"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR2,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR2,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE2,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFD910C0
|
|
width 15.
|
|
if (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD910C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD910C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD910C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD910C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD910C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD910C0))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR3,Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD910C0))&0x02)==0x00)&&(((per.l(ad:0xFFD910C0+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR3,Status Register 3"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD910C0))&0x02)==0x02)&&(((per.l(ad:0xFFD910C0+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR3,Status Register 3"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD910C0))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR3,Status Register 3"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR3,Status Register 3"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR3,Transmit Data Register 3"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR3,Receive Data Register 3"
|
|
if (((per.l(ad:0xFFD910C0+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD910C0))&0xc000)==0xc000)||(((per.l(ad:0xFFD910C0))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD910C0))&0xc000)==0xc000))||(((per.l(ad:0xFFD910C0))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD910C0+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD910C0+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD910C0))&0xc000)==0xc000))||(((per.l(ad:0xFFD910C0))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR3,WS Mode Register 3"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR3,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR3,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE3,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xFFD91100
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91100+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91100+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91100+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91100+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91100))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91100))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR4,Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91100))&0x02)==0x00)&&(((per.l(ad:0xFFD91100+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR4,Status Register 4"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91100))&0x02)==0x02)&&(((per.l(ad:0xFFD91100+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR4,Status Register 4"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91100))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR4,Status Register 4"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR4,Status Register 4"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR4,Transmit Data Register 4"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR4,Receive Data Register 4"
|
|
if (((per.l(ad:0xFFD91100+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91100))&0xc000)==0xc000)||(((per.l(ad:0xFFD91100))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91100))&0xc000)==0xc000))||(((per.l(ad:0xFFD91100))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91100+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91100+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91100))&0xc000)==0xc000))||(((per.l(ad:0xFFD91100))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR4,WS Mode Register 4"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR4,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR4,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE4,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xFFD91140
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91140+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91140+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91140+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91140+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91140))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91140))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR5,Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91140))&0x02)==0x00)&&(((per.l(ad:0xFFD91140+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR5,Status Register 5"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91140))&0x02)==0x02)&&(((per.l(ad:0xFFD91140+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR5,Status Register 5"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91140))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR5,Status Register 5"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR5,Status Register 5"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR5,Transmit Data Register 5"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR5,Receive Data Register 5"
|
|
if (((per.l(ad:0xFFD91140+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91140))&0xc000)==0xc000)||(((per.l(ad:0xFFD91140))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91140))&0xc000)==0xc000))||(((per.l(ad:0xFFD91140))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91140+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91140+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91140))&0xc000)==0xc000))||(((per.l(ad:0xFFD91140))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR5,WS Mode Register 5"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR5,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR5,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0xFFD91180
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91180+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91180+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91180+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91180+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91180))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91180))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR6,Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91180))&0x02)==0x00)&&(((per.l(ad:0xFFD91180+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR6,Status Register 6"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91180))&0x02)==0x02)&&(((per.l(ad:0xFFD91180+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR6,Status Register 6"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91180))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR6,Status Register 6"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR6,Status Register 6"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR6,Transmit Data Register 6"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR6,Receive Data Register 6"
|
|
if (((per.l(ad:0xFFD91180+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91180))&0xc000)==0xc000)||(((per.l(ad:0xFFD91180))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91180))&0xc000)==0xc000))||(((per.l(ad:0xFFD91180))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91180+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91180+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91180))&0xc000)==0xc000))||(((per.l(ad:0xFFD91180))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR6,WS Mode Register 6"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR6,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR6,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 7"
|
|
base ad:0xFFD911C0
|
|
width 15.
|
|
if (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD911C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD911C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD911C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD911C0+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD911C0))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD911C0))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR7,Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD911C0))&0x02)==0x00)&&(((per.l(ad:0xFFD911C0+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR7,Status Register 7"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD911C0))&0x02)==0x02)&&(((per.l(ad:0xFFD911C0+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR7,Status Register 7"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD911C0))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR7,Status Register 7"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR7,Status Register 7"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR7,Transmit Data Register 7"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR7,Receive Data Register 7"
|
|
if (((per.l(ad:0xFFD911C0+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD911C0))&0xc000)==0xc000)||(((per.l(ad:0xFFD911C0))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD911C0))&0xc000)==0xc000))||(((per.l(ad:0xFFD911C0))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD911C0+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD911C0+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD911C0))&0xc000)==0xc000))||(((per.l(ad:0xFFD911C0))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR7,WS Mode Register 7"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR7,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR7,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 8"
|
|
base ad:0xFFD91200
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91200+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91200+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91200+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91200+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91200))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91200))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR8,Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91200))&0x02)==0x00)&&(((per.l(ad:0xFFD91200+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR8,Status Register 8"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91200))&0x02)==0x02)&&(((per.l(ad:0xFFD91200+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR8,Status Register 8"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91200))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR8,Status Register 8"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR8,Status Register 8"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR8,Transmit Data Register 8"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR8,Receive Data Register 8"
|
|
if (((per.l(ad:0xFFD91200+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91200))&0xc000)==0xc000)||(((per.l(ad:0xFFD91200))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91200))&0xc000)==0xc000))||(((per.l(ad:0xFFD91200))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91200+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91200+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91200))&0xc000)==0xc000))||(((per.l(ad:0xFFD91200))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR8,WS Mode Register 8"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR8,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR8,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 9"
|
|
base ad:0xFFD91240
|
|
width 15.
|
|
if (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" "OV_CLK/1,OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpuis("R8A7792X"))||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00100)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,2,3,4"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (First/Second channel)" "Low/High,High/Low"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00001)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,?..."
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x1f1003)==0x00101)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 31. " FORCE ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" ",4,6,8"
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,18,20,22,24,32,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "8,16,24,32,48,64,128,256"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (system word 1/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,Padding bits"
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,Right"
|
|
textline " "
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91240+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x103)==0x00003)&&(((per.l(ad:0xFFD91240+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91240+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x0000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x103)==0x103)&&(((per.l(ad:0xFFD91240+0x20))&0x1f0000)>0x00000)&&(((per.l(ad:0xFFD91240))&0x8004)==0x8000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " CHNL ,Channels in each system word" "1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " DWL ,Data Word Length (bit)" "8,16,?..."
|
|
bitfld.long 0x00 16.--18. " SWL ,System Word Length (bit)" "16,32,48,64,96,128,256,512"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SPDP ,Serial Padding Polarity" "Low,High"
|
|
bitfld.long 0x00 10. " SDTA ,Serial Data Alignment" "Serial data,?..."
|
|
textline " "
|
|
bitfld.long 0x00 09. " PDTA ,Parallel Data Alignment" "Left,?..."
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" "1 cycle,No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFD91240))&0x8004)==0x0004)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04.--06. " CKDV ,Serial Oversampling Clock Division Ratio" ",OV_CLK/2,OV_CLK/4,OV_CLK/8,OV_CLK/16,OV_CLK/6,OV_CLK/12,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8A7792X"))&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SSICR9,Control Register 9"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 29. " FIEN ,Frequency Switching Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " DMEN ,DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " UIEN ,Underflow Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIEN ,Overflow Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " IIEN ,Idle Mode Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIEN ,Data Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SCKD ,Serial Bit Clock Direction" "Input/Slave mode,Output/Master mode"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SWSD ,Serial Word Selection Signal Direction" "Input/Slave mode,Output/Master mode"
|
|
bitfld.long 0x00 13. " SCKP ,Serial Clock Polarity" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SWSP ,Serial Word Selection Signal polarity (WIDTH bits in the WS mode register/otherwise)" "High/Low,Low/High"
|
|
bitfld.long 0x00 08. " DEL ,Serial Data Delay" ",No delay"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 07. " BREN ,Burst Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " MUEN ,Mute Enable" "Not muted,Muted"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 02. " CPEN ,Compressed Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 01. " TRMD ,Transmit/Receive Mode Select" "Receive,Transmit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 00. " EN ,SSI Module Enable" "Disabled,Enabled"
|
|
endif
|
|
if ((((per.l(ad:0xFFD91240))&0x02)==0x00)&&(((per.l(ad:0xFFD91240+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR9,Status Register 9"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif ((((per.l(ad:0xFFD91240))&0x02)==0x02)&&(((per.l(ad:0xFFD91240+0x20))&0x101)==0x000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR9,Status Register 9"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 02.--03. " CHNO ,Channel Number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SWNO ,System Word Number" "0,1"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
elif (((per.l(ad:0xFFD91240))&0x02)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR9,Status Register 9"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "No unread data,Unread data"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SSISR9,Status Register 9"
|
|
bitfld.long 0x00 28. " DMRQ ,DMA Request Status Flag" "No data requested,Data requested"
|
|
bitfld.long 0x00 27. " UIRQ ,Underflow Error Interrupt Status Flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OIRQ ,Overflow Error Interrupt Status Register" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " IIRQ ,Idle Mode Interrupt Status Flag" "Not idle,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 24. " DIRQ ,Data Interrupt Status Flag" "Buffer full,Buffer empty"
|
|
bitfld.long 0x00 00. " IDST ,Idle Mode Status Flag" "Not completed,Completed"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SSITDR9,Transmit Data Register 9"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "SSIRDR9,Receive Data Register 9"
|
|
if (((per.l(ad:0xFFD91240+0x20))&0x3)==0x1)&&((((per.l(ad:0xFFD91240))&0xc000)==0xc000)||(((per.l(ad:0xFFD91240))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x3)==0x3)&&(((((per.l(ad:0xFFD91240))&0xc000)==0xc000))||(((per.l(ad:0xFFD91240))&0x8000)==0x0000))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x3)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" "TDM format,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif (((per.l(ad:0xFFD91240+0x20))&0x3)==0x3)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
elif ((((per.l(ad:0xFFD91240+0x20))&0x1)==0x0)&&(((((per.l(ad:0xFFD91240))&0xc000)==0xc000))||(((per.l(ad:0xFFD91240))&0x8000)==0x0000)))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
bitfld.long 0x00 8. " CONT ,WS Continue Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SSIWSR9,WS Mode Register 9"
|
|
bitfld.long 0x00 16.--20. " WIDTH ,SYNC Pulse Width Change" ",1 cycle of SCK,2 cycles of SCK,3 cycles of SCK,4 cycles of SCK,5 cycles of SCK,6 cycles of SCK,7 cycles of SCK,8 cycles of SCK,9 cycles of SCK,10 cycles of SCK,11 cycles of SCK,12 cycles of SCK,13 cycles of SCK,14 cycles of SCK,15 cycles of SCK,16 cycles of SCK,17 cycles of SCK,18 cycles of SCK,19 cycles of SCK,20 cycles of SCK,21 cycles of SCK,22 cycles of SCK,23 cycles of SCK,24 cycles of SCK,25 cycles of SCK,26 cycles of SCK,27 cycles of SCK,28 cycles of SCK,29 cycles of SCK,30 cycles of SCK,31 cycles of SCK"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MONO ,TDM Format/Monaural Format" "TDM,Monaural"
|
|
bitfld.long 0x00 0. " WS_MODE ,WS Mode" "Stereo/multi-channel/compressed,TDM/monaural"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||cpuis("R8A7792X")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "SSIFMR9,FS Mode Register"
|
|
bitfld.long 0x00 16.--21. " DTCT ,Frequency Switching Detection Range Set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4.--5. " CTDV ,Bus Clock Division Ratio" ",,,Bclkf/8"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FSEN ,Frequency Switching Detection Function Enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x00 "SSIFSR9,FS Status Register"
|
|
bitfld.long 0x00 15. " FCST ,WS Stopped Status Flag" "Not stopped,Stopped"
|
|
bitfld.long 0x00 14. " DTST ,Frequency Switching Detection Status Flag" "Not detected,Detected"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FCNT ,Frequency Count Monitor"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SSICRE9,Control Register Extend"
|
|
bitfld.long 0x00 0. " CHNL2 ,Extension bit of SSICR.CHNL[1:0]" "Default value,TDM = 16 words"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "ADG (Audio Clock Generator)"
|
|
base ad:0xFFFE0000
|
|
width 16.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "BRRA,BRGA Baud Rate Set Register"
|
|
bitfld.long 0x00 8.--9. " CKS ,Clock Source Select for Baud Rate Generator A" "ACLK_A,ACLK_A/4,ACLK_A/16,ACLK_A/64"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BRRA ,Dividing Factor Set"
|
|
line.long 0x04 "BRRB,BRGB Baud Rate Set Register"
|
|
bitfld.long 0x04 8.--9. " CKS ,Clock Source Select for Baud Rate Generator B" "ACLK_B,ACLK_B/4,ACLK_B/16,ACLK_B/64"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BRRB ,Dividing Factor Set"
|
|
line.long 0x08 "SSICKR,Clock Select Register"
|
|
bitfld.long 0x08 31. " SSICKR_31 ,Selects the clock output to the external pin AUDIO_CLKOUT" "BRGA output,BRGB output"
|
|
textline " "
|
|
bitfld.long 0x08 20.--22. " SSICKR_[22:20] ,Selects the clock input to the BRGA" "AUDIO_CLKA,AUDIO_CLKB,Clks1,Clks1,AUDIO_CLKC,Fixed at 0,Fixed at 0,Fixed at 0"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " SSICKR_[18:16] ,Selects the clock input to the BRGB" "AUDIO_CLKA,AUDIO_CLKB,Clks1,Clks1,AUDIO_CLKC,Fixed at 0,Fixed at 0,Fixed at 0"
|
|
line.long 0x0c "AUDIO_CLK_SEL0,Audio Clock Select Register 0"
|
|
bitfld.long 0x0c 30.--31. " DIVSEL_SSI3 ,SSI3 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x0c 28.--29. " DIVSEL_SSI3 ,SSI3 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x0c 24.--26. " DIVCLK_SEL_SSI3 ,SSI3 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 22.--23. " DIVSEL_SSI2 ,SSI2 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x0c 20.--21. " DIVSEL_SSI2 ,SSI2 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x0c 16.--18. " DIVCLK_SEL_SSI2 ,SSI2 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 14.--15. " DIVSEL_SSI1 ,SSI1 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x0c 12.--13. " DIVSEL_SSI1 ,SSI1 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x0c 8.--10. " DIVCLK_SEL_SSI1 ,SSI1 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 6.--7. " DIVSEL_SSI0 ,SSI0 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x0c 4.--5. " DIVSEL_SSI0 ,SSI0 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x0c 0.--2. " DIVCLK_SEL_SSI0 ,SSI0 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
line.long 0x10 "AUDIO_CLK_SEL1,Audio Clock Select Register 1"
|
|
bitfld.long 0x10 30.--31. " DIVSEL_SSI7 ,SSI7 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x10 28.--29. " DIVSEL_SSI7 ,SSI7 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x10 24.--26. " DIVCLK_SEL_SSI7 ,SSI7 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x10 22.--23. " DIVSEL_SSI6 ,SSI6 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x10 20.--21. " DIVSEL_SSI6 ,SSI6 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x10 16.--18. " DIVCLK_SEL_SSI6 ,SSI6 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x10 14.--15. " DIVSEL_SSI5 ,SSI5 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x10 12.--13. " DIVSEL_SSI5 ,SSI5 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x10 8.--10. " DIVCLK_SEL_SSI5 ,SSI5 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x10 6.--7. " DIVSEL_SSI4 ,SSI4 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x10 4.--5. " DIVSEL_SSI4 ,SSI4 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x10 0.--2. " DIVCLK_SEL_SSI4 ,SSI4 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
line.long 0x14 "AUDIO_CLK_SEL2,Audio Clock Select Register 2"
|
|
bitfld.long 0x14 14.--15. " DIVSEL_SSI9 ,SSI9 Frequency Divider Select" "Not divided,/2,/4,/8"
|
|
bitfld.long 0x14 12.--13. " DIVSEL_SSI9 ,SSI9 Clock Select" "DIVCLK,BRGA output,BRGB output,?..."
|
|
bitfld.long 0x14 8.--10. " DIVCLK_SEL_SSI9 ,SSI9 Clock Select" "Fixed at 0,AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,MLBCLK/MLPCLK,?..."
|
|
line.long 0x18 "AUDIO_CLK_SEL3,Audio Clock Select Register 3"
|
|
bitfld.long 0x18 28.--30. " DIV_HPBIF3 ,HPBIF3 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x18 24.--26. " AUDIO_SEL_HPBIF3 ,HPBIF3 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x18 20.--22. " DIV_HPBIF2 ,HPBIF2 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x18 16.--18. " AUDIO_SEL_HPBIF2 ,HPBIF2 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x18 12.--14. " DIV_HPBIF1 ,HPBIF1 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x18 8.--10. " AUDIO_SEL_HPBIF1 ,HPBIF1 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x18 4.--6. " DIV_HPBIF0 ,HPBIF0 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x18 0.--2. " AUDIO_SEL_HPBIF0 ,HPBIF0 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
line.long 0x1c "AUDIO_CLK_SEL4,Audio Clock Select Register 4"
|
|
bitfld.long 0x1c 28.--30. " DIV_HPBIF7 ,HPBIF7 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x1c 24.--26. " AUDIO_SEL_HPBIF7 ,HPBIF7 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x1c 20.--22. " DIV_HPBIF6 ,HPBIF6 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x1c 16.--18. " AUDIO_SEL_HPBIF6 ,HPBIF6 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x1c 12.--14. " DIV_HPBIF5 ,HPBIF5 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x1c 8.--10. " AUDIO_SEL_HPBIF5 ,HPBIF5 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x1c 4.--6. " DIV_HPBIF4 ,HPBIF4 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x1c 0.--2. " AUDIO_SEL_HPBIF4 ,HPBIF4 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
line.long 0x20 "AUDIO_CLK_SEL5,Audio Clock Select Register 5"
|
|
bitfld.long 0x20 12.--14. " DIV_HPBIF9 ,HPBIF9 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x20 8.--10. " AUDIO_SEL_HPBIF9 ,HPBIF9 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
textline " "
|
|
bitfld.long 0x20 4.--6. " DIV_HPBIF8 ,HPBIF8 Frequency Divider Select" "/128,/256,/512,/1024,/2048,MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz"
|
|
bitfld.long 0x20 0.--2. " AUDIO_SEL_HPBIF8 ,HPBIF8 Clock Select" "AUDIO_CLKA,AUDIO_CLKB,AUDIO_CLKC,,BRGA,BRGB,?..."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "AUDIO_CLK_SEL_7,Audio Clock Select Register 7"
|
|
bitfld.long 0x00 28.--29. " DIV_MLBCLK7 ,STREAM_MIMLCP7 or STREAM_MLP7 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
bitfld.long 0x00 24.--25. " DIV_MLBCLK6 ,STREAM_MIMLCP6 or STREAM_MLP6 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " DIV_MLBCLK5 ,STREAM_MIMLCP5 or STREAM_MLP5 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
bitfld.long 0x00 16.--17. " DIV_MLBCLK4 ,STREAM_MIMLCP4 or STREAM_MLP4 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DIV_MLBCLK3 ,STREAM_MIMLCP3 or STREAM_MLP3 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
bitfld.long 0x00 8.--9. " DIV_MLBCLK2 ,STREAM_MIMLCP2 or STREAM_MLP2 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DIV_MLBCLK1 ,STREAM_MIMLCP1 or STREAM_MLP1 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
bitfld.long 0x00 0.--1. " DIV_MLBCLK0 ,STREAM_MIMLCP0 or STREAM_MLP0 Frequency Divider Select" "MLBCLK or MLPCLK 48kHz,MLBCLK or MLPCLK 96kHz,MLBCLK or MLPCLK 192kHz,?..."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MLBP_DIV_EN,MLBCLK or MLPCLK Frequency Division Register"
|
|
bitfld.long 0x00 0. " MLBP_DIV_EN ,Enables frequency division for MLBCLK or MLPCLK" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "SPU2F (Sound Processing Unit 2)"
|
|
base ad:0xFD8FE010
|
|
width 14.
|
|
group.long 0x00++0x27
|
|
line.long 0x0 "P0BASE,SPU Cache Memory (DSP0-PRAM) Base Address Register"
|
|
hexmask.long 0x0 5.--31. 0x20 " P0BASE ,Base address of the DSP0-PRAM data located in the main memory in bytes"
|
|
line.long (0x0+0x04) "X0BASE,SPU Cache Memory (DSP0-XRAM) Base Address Register"
|
|
hexmask.long (0x0+0x04) 5.--31. 0x20 " X0BASE ,Base address of the DSP0-XRAM data located in the main memory in bytes"
|
|
line.long (0x0+0x08) "Y0BASE,SPU Cache Memory (DSP0-YRAM) Base Address Register"
|
|
hexmask.long (0x0+0x08) 5.--31. 0x20 " Y0BASE ,Base address of the DSP0-YRAM data located in the main memory in bytes"
|
|
line.long 0xC "P1BASE,SPU Cache Memory (DSP1-PRAM) Base Address Register"
|
|
hexmask.long 0xC 5.--31. 0x20 " P1BASE ,Base address of the DSP1-PRAM data located in the main memory in bytes"
|
|
line.long (0xC+0x04) "X1BASE,SPU Cache Memory (DSP1-XRAM) Base Address Register"
|
|
hexmask.long (0xC+0x04) 5.--31. 0x20 " X0BASE ,Base address of the DSP1-XRAM data located in the main memory in bytes"
|
|
line.long (0xC+0x08) "Y1BASE,SPU Cache Memory (DSP1-YRAM) Base Address Register"
|
|
hexmask.long (0xC+0x08) 5.--31. 0x20 " Y1BASE ,Base address of the DSP1-YRAM data located in the main memory in bytes"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "LDST_SIZE,SPU cache memory load/store size register"
|
|
bitfld.long 0x00 4.--5. " ST_SIZE ,Usage of DSP0 and DSP1" "Simultaneously,,,Not simultaneously"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LD_SIZE ,Usage of DSP0 and DSP1" "Simultaneously,,,Not simultaneously"
|
|
group.long 0x1c14++0x3
|
|
line.long 0x00 "SPUSRST,SPU Software Reset Register"
|
|
bitfld.long 0x00 7. " BUF3SRST ,DMABUF3 Software Reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BUF2SRST ,DMABUF2 Software Reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BUF1SRST ,DMABUF1 Software Reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " BUF0SRST ,DMABUF0 Software Reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPUSRST ,SPU2 Software Reset" "Reset,No reset"
|
|
group.long 0x1cf0++0x07
|
|
line.long 0x00 "DSPRST_0,DSP Full Reset Register_0"
|
|
bitfld.long 0x00 0. " DSPRST ,DSP0 Reset" "No reset,Reset"
|
|
line.long 0x04 "DSPCORERST_0,DSP Core Reset Register_0"
|
|
bitfld.long 0x04 0. " DSPCORERST ,DSP0 Core Reset" "No reset,Reset"
|
|
group.long 0x1eb0++0x07
|
|
line.long 0x00 "ASID_DSP_0,DSP ASID Control Register_0"
|
|
bitfld.long 0x00 0.--3. " ASID_DSP ,ASID Control bits for the DSP" "0,?..."
|
|
line.long 0x04 "ASID_CPU_0,CPU ASID Control Register_0"
|
|
bitfld.long 0x04 0.--3. " ASID_CPU ,ASID Control bits for the CPU" "0,?..."
|
|
group.long 0x101cf0++0x07
|
|
line.long 0x00 "DSPRST_1,DSP Full Reset Register_1"
|
|
bitfld.long 0x00 0. " DSPRST ,DSP1 Reset" "No reset,Reset"
|
|
line.long 0x04 "DSPCORERST_1,DSP Core Reset Register_1"
|
|
bitfld.long 0x04 0. " DSPCORERST ,DSP1 Core Reset" "No reset,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "Ether (Ethernet MAC Controller)"
|
|
base ad:0xFDE00200
|
|
width 7.
|
|
group.long 0x00++0x03 "HDMAC Register Configuration"
|
|
line.long 0x00 "CXR0,HDMAC Operating Mode Setting Register"
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x00 6. " DE ,DMA data endian conversion" "Not performed,Performed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--5. " DL ,Transmit/Receive descriptor length" "16 bytes,32 bytes,64 bytes,?..."
|
|
bitfld.long 0x00 0. " SWR ,HDMAC/feLic software reset" "No reset,Reset"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CXR1,Transmit Activation Register"
|
|
bitfld.long 0x00 0. " TRNS ,Transmit activation" "No effect,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CXR2,Receive Activation Register"
|
|
bitfld.long 0x00 0. " R ,Receive ready" "Not ready,Ready"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CXR3,Transmit Descriptor Start Address Setting Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CXR4,Receive Descriptor Start Address Setting Register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CXR5,Status Register"
|
|
eventfld.long 0x00 30. " TWB ,Write-back to the transmit descriptor performed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " TABT ,Transmit abort detect" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " RABT ,Receive abort detect" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 24. " RFRMER ,Receive frame count overflow occurrence" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " BER ,Indicates that a DMA error is input" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif cpuis("R8A774*")
|
|
rbitfld.long 0x00 22. " MINT ,M port interrupt occurrence" "No interrupt,Interrupt"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 22. " MINT ,M port interrupt occurrence" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 21. " FTC ,Frame transmit completion" "No interrupt,Interrupt"
|
|
textline " "
|
|
sif !cpuis("R8A774*")
|
|
eventfld.long 0x00 20. " TDE ,Transmit descriptor depletion" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x00 19. " TFE ,Transmit FIFO underflow error occurrence" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 18. " FRC ,Frame receive completion" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " RDE ,Receive descriptor depletion" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " RFE ,Receive FIFO overflow error occurrence" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " TINT8 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " TINT7 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " TINT6 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " TINT5 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " TINT4 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " TINT3 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " TINT2 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " TINT1 ,Transmit port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " RINT8 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " RINT7 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " RINT6 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " RINT5 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RINT4 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " RINT3 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " RINT2 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RINT1 ,Receive port interrupt" "No interrupt,Interrupt"
|
|
sif cpuis("R8A774*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CXR6,Interrupt Mask Setting Register"
|
|
bitfld.long 0x00 30. " TWB ,TWB interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " BINT ,BINT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " AINT ,AINT interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " LKON ,LKON interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TABT ,TABT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " RABT ,RABT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RFRMER ,RFRMER interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " BER ,BER interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MINT ,MINT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FTC ,FTC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDE ,TDE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TFE ,TFE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FRC ,FRC interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDE ,RDE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFE ,RFE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TINT8 ,TINT8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TINT7 ,TINT7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TINT6 ,TINT6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TINT5 ,TINT5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TINT4 ,TINT4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TINT3 ,TINT3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TINT2 ,TINT2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TINT1 ,TINT1 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RINT8 ,RINT8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RINT7 , RINT7 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RINT6 ,RINT6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RINT5 ,RINT5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RINT4 ,RINT4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RINT3 ,RINT3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RINT2 ,RINT2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RINT1 ,RINT1 interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CXR6,Interrupt Enable Setting Register"
|
|
bitfld.long 0x00 30. " TWB ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TABT ,Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " RABT ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RFRMER ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " BER ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MINT ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " FTC ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDE ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TFE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " FRC ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDE ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RFE ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TINT8 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TINT7 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TINT6 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TINT5 ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TINT4 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TINT3 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TINT2 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TINT1 ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RINT8 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RINT7 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RINT6 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RINT5 ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RINT4 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RINT3 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RINT2 ,Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RINT1 ,Interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CXR7,Error Mask Setting Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(CPUIS("R8A774*"))
|
|
bitfld.long 0x00 7. " RINT8 ,Receive descriptor error flag (RFE) mask" "Not masked,Masked"
|
|
else
|
|
bitfld.long 0x00 15. " TINT8 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 14. " TINT7 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 13. " TINT6 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 12. " TINT5 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TINT4 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 10. " TINT3 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 9. " TINT2 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 8. " TINT1 ,Transmit descriptor error flag (TFE) mask" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RINT8 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 6. " RINT7 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " RINT6 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " RINT5 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RINT4 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 2. " RINT3 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 1. " RINT2 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
bitfld.long 0x00 0. " RINT1 ,Receive descriptor error flag (RFE) mask" "Not allowed,Allowed"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CXR8,Discarded Frame Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MIS ,Discarded frame counter"
|
|
if (((per.l(ad:0xFDE00200+0x08))&0x01)==0x01)
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CXR9,Transmit FIFO Threshold Setting Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FO ,Transmit FIFO threshold"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CXR9,Transmit FIFO Threshold Setting Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " FO ,Transmit FIFO threshold"
|
|
endif
|
|
sif cpuis("R8A774*")
|
|
if (((per.l(ad:0xFDE00200+0x08))&0x01)==0x01)&&(((per.l(ad:0xFDE00200+0x10))&0x01)==0x01)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
bitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
bitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
elif (((per.l(ad:0xFDE00200+0x08))&0x01)==0x01)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
rbitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
bitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
elif (((per.l(ad:0xFDE00200+0x10))&0x01)==0x01)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
bitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
rbitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
bitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
bitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFDE00200+0x08))&0x01)==0x01)&&(((per.l(ad:0xFDE00200+0x10))&0x01)==0x01)
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
bitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
bitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CXR10,External FIFO Depth Setting Register"
|
|
bitfld.long 0x00 8.--12. " TA ,Transmit FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
bitfld.long 0x00 0.--4. " RA ,Receive FIFO depth" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0xFDE00200+0x10))&0x1)==0x01)
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CXR11,Receive Activation Reset Method Setting Register"
|
|
bitfld.long 0x00 0. " RR ,Receive ready reset" "Cleared,Reset"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CXR11,Receive Activation Reset Method Setting Register"
|
|
bitfld.long 0x00 0. " RR ,Receive ready reset" "Cleared,Reset"
|
|
endif
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CXR13,Transmit FIFO Underflow Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TFUF ,Transmit FIFO underflow counter"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CXR14,Receive FIFO Overflow Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RFOF ,Receive FIFO overflow counter"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||CPUIS("R8A774*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CXR15,RMII Mode Register"
|
|
bitfld.long 0x00 0. " RMII ,RMII mode specification" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CXR16,Receive FIFO Busy Transmit Threshold Setting Register"
|
|
bitfld.long 0x00 16.--18. " RFF ,Busy transmit threshold based on the number of receive frames" "2 frames,4 frames,6 frames,8 frames,10 frames,12 frames,14 frames,16 frames"
|
|
bitfld.long 0x00 0.--2. " RFD ,Busy transmit threshold based on the amount of data in the receive FIFO" "224 (256-32),480 (512-32),736 (768-32),992 (1024-32),1248(1280-32),1504(1536-32),1760 (1792-32),?..."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CXR18,Transmit Interrupt Mode Setting Register"
|
|
bitfld.long 0x00 4. " TIM ,Transmit interrupt mode" "Each time a frame transmitted,Write-back to the descriptor completed"
|
|
bitfld.long 0x00 0. " TIS ,Interrupt mode enable" "Disabled,Enabled"
|
|
group.long 0x100++0x03 "feLic Register Configuration"
|
|
line.long 0x00 "CXR20,feLic Operating Mode Setting Register"
|
|
bitfld.long 0x00 20. " TPC ,PAUSE frame transmission" "Enabled,Disabled"
|
|
bitfld.long 0x00 19. " ZPF ,PAUSE frame enable with TIME = 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PFR ,PAUSE frame receive mode" "Not transferred,Transferred"
|
|
bitfld.long 0x00 17. " RXF ,Operating mode for reception flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TXF ,Operating mode for transmission flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " CER ,CRC error frame receive mode" "Normal,CRC not error"
|
|
bitfld.long 0x00 9. " MPM ,Magic packet detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RPE ,Reception enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TPE ,Transmission enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ILB ,FELIC loopback mode" "Normal,Loopback"
|
|
bitfld.long 0x00 2. " OLB ,10-Base T or 100-Base TX transfer setting" "10-base T,100-base TX"
|
|
bitfld.long 0x00 1. " DPM ,Duplex mode" "Half-duplex,Full-duplex"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PRM ,Promiscuous mode" "Normal,Enters promiscuous"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CXR2A,Long Frame Length Check Value Setting Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " FLUL ,Frame length upper limit"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CXR21,Status Register"
|
|
eventfld.long 0x00 4. " PRO ,PAUSE frame retransmit retry over" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " LNK ,LINK signal change interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MPR ,Magic packet receive interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " FCD ,Illegal carrier detection interrupt" "No interrupt,Interrupt"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CXR22,Interrupt Mask Setting Register"
|
|
bitfld.long 0x00 4. " PROE ,PAUSE frame retransmit retry over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LKNE ,LINK signal change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MPRE ,Magic packet receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FCDE ,Illegal carrier detection interrupt enable" "Disabled,Enabled"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CXR23,MII Control Register"
|
|
sif cpuis("R8A774*")
|
|
rbitfld.long 0x00 3. " MDI ,MII management data in" "Not read,Read"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3. " MDI ,MII management data in" "Not read,Read"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " MDO ,MII management data out" "Not written,Written"
|
|
bitfld.long 0x00 1. " MMD ,MII management mode" "Read,Written"
|
|
bitfld.long 0x00 0. " MDC ,MII management clock" "Disabled,Enabled"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CXR2B,PHY Status Register"
|
|
bitfld.long 0x00 0. " LINK ,PHY output LINK signal monitoring status" "Disabled,Enabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CXR30,Random Number Generating Counter Upper Limit Setting Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " RDM ,Upper limit of the counter used for the random number generator"
|
|
group.long 0x150++0x07
|
|
line.long 0x00 "CXR70,IPG Counter Setting Register"
|
|
bitfld.long 0x00 0.--4. " IPG ,IPG value in 40 ns units" "400 ns,400 ns,400 ns,400 ns,400 ns,400 ns,400 ns,440 ns,480 ns,520 ns,560 ns,600 ns,640 ns,680 ns,720 ns,760 ns,800 ns,840 ns,880 ns,920 ns,960 ns,1000 ns,1040 ns,1080 ns,1120 ns,1160 ns,1200 ns,1240 ns,1280 ns,1320 ns,1360 ns,1440 ns"
|
|
line.long 0x04 "CXR71,Automatic PAUSE Parameter Setting Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " APAUSE ,TIME parameter value of an automatic PAUSE frame"
|
|
wgroup.long 0x158++0x03
|
|
line.long 0x00 "CXR72,Manual PAUSE Parameter Setting Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MPAUSE ,TIME parameter value of an manual PAUSE frame"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CXR80,Receive PAUSE Frame Counter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RPAUSE ,Received PAUSE frame counter"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CXR81,PAUSE Frame Retransmit Count Setting Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXPAUSE ,Upper limit of PAUSE frame retransmission"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "CXR82,PAUSE Frame Register Retransmit Counter Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A774*")
|
|
hexmask.long.word 0x00 0.--15. 1. " TXP ,PAUSE frame retransmit counter"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " RPAUS ,Received PAUSE frame counter"
|
|
endif
|
|
if (((per.l(ad:0xFDE00200+0x100))&0x60)==0x60)
|
|
rgroup.long 0x1c0++0x03
|
|
line.long 0x00 "CXR24,MAC Address High Register"
|
|
rgroup.long 0x1c8++0x03
|
|
line.long 0x00 "CXR25,MAC Address Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MACL ,MAC address Lower 16 Bits"
|
|
else
|
|
group.long 0x1c0++0x03
|
|
line.long 0x00 "CXR24,MAC Address High Register"
|
|
group.long 0x1c8++0x03
|
|
line.long 0x00 "CXR25,MAC Address Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MACL ,MAC address lower 16 Bits"
|
|
endif
|
|
group.long 0x1d0++0x0f
|
|
line.long 0x00 "CXR40,TINT1 Count Register"
|
|
line.long 0x04 "CXR41,TINT2 Count Register"
|
|
line.long 0x08 "CXR42,TINT3 Count Register"
|
|
line.long 0x0c "CXR43,TINT4 Count Register"
|
|
group.long 0x1e4++0x017
|
|
line.long 0x00 "CXR50,RINT1 Count Register"
|
|
line.long 0x04 "CXR51,RINT2 Count Register"
|
|
line.long 0x08 "CXR52,RINT3 Count Register"
|
|
line.long 0x0c "CXR53,RINT4 Count Register"
|
|
line.long 0x10 "CXR54,RINT5 Count Register"
|
|
line.long 0x14 "CXR55,RINT8 Count Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CAN (Controller Area Network)"
|
|
tree "Channel 0"
|
|
base ad:0xFFFD0000
|
|
width 12.
|
|
group.word 0x840++0x01
|
|
line.word 0x00 "C0CTLR,CAN0 Control Register"
|
|
bitfld.word 0x00 13. " RBOC ,Forcible Return From Bus-OFF" "No effect,Force return"
|
|
textline " "
|
|
bitfld.word 0x00 11.--12. " BOM ,Bus-Off Recovery Mode" "Normal,Halt at Bus-off entry,Halt at Bus-off end,Halt by Program request"
|
|
textline " "
|
|
bitfld.word 0x00 10. " SLPM ,CAN Sleep Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CANM ,CAN Operating Mode Select" "Operation,Reset,Halt,Force reset"
|
|
bitfld.word 0x00 6.--7. " TSPS ,Time Stamp Prescaler Select" "1,2,4,8"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TSRC ,Time Stamp Counter Reset Command" "No effect,Reset"
|
|
bitfld.word 0x00 4. " TPM ,Transmission Priority Mode Select" "ID,Mailbox"
|
|
bitfld.word 0x00 3. " MLM ,Message Lost Mode Select" "Overwrite,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " IDFM ,ID Format Mode Select" "Standard,Extended,Mixed,?..."
|
|
bitfld.word 0x00 0. " MBM ,CAN Mailbox Mode Select" "Normal,FIFO"
|
|
group.byte 0x847++0x00
|
|
line.byte 0x00 "C0CLKR,CAN0 Clock Select Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")
|
|
bitfld.byte 0x00 0.--1. " CCLKS ,CAN Clock Source Select" "Peripheral 1,Peripheral 2,,External"
|
|
else
|
|
bitfld.byte 0x00 0. " CCLKS ,CAN Clock Source Select" "Peripheral,Main"
|
|
endif
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "C0BCR,CAN0 Bit Configuration Register"
|
|
bitfld.long 0x00 28.--31. " TSEG1 ,Time Segment 1 Control Bits" ",,,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq,9 Tq,10 Tq,11 Tq,12 Tq,13 Tq,14 Tq,15 Tq,16 Tq"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Prescaler Division Ratio"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SJW ,Resynchronization Jump Width Control" "1 Tq,2 Tq,3 Tq,4 Tq"
|
|
bitfld.long 0x00 8.--10. " TSEG2 ,Time Segment 2 Control" ",2 Tq,3 Tq,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq"
|
|
if (((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0)
|
|
group.long 0x430++0x07
|
|
line.long 0x0 "C0MKR0,CAN0 Mask Register 0"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
line.long 0x4 "C0MKR1,CAN0 Mask Register 1"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x0 "C0MKR2,CAN0 Mask Register 2"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x4 "C0MKR3,CAN0 Mask Register 3"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x8 "C0MKR4,CAN0 Mask Register 4"
|
|
bitfld.long 0x8 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x8 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x8 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x8 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x8 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x8 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x8 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x8 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x8 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x8 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x8 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0xC "C0MKR5,CAN0 Mask Register 5"
|
|
bitfld.long 0xC 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0xC 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0xC 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0xC 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0xC 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0xC 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0xC 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0xC 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0xC 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0xC 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0xC 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x10 "C0MKR6,CAN0 Mask Register 6"
|
|
bitfld.long 0x10 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x10 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x10 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x10 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x10 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x10 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x10 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x10 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x10 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x10 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x10 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x14 "C0MKR7,CAN0 Mask Register 7"
|
|
bitfld.long 0x14 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x14 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x14 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x14 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x14 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x14 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x14 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x14 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x14 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x14 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x14 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x18 "C0MKR8,CAN0 Mask Register 8"
|
|
bitfld.long 0x18 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x18 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x18 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x18 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x18 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x18 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x18 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x18 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x18 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x18 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x18 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x1C "C0MKR9,CAN0 Mask Register 9"
|
|
bitfld.long 0x1C 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 18. ",Standard ID Bit 0" "0,1"
|
|
elif ((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2)||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4))
|
|
group.long 0x430++0x07
|
|
line.long 0x0 "C0MKR0,CAN0 Mask Register 0"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x0 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x0 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x0 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x0 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x0 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x0 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x0 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x0 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x0 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x0 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x0 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x0 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x0 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x0 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x0 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x0 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x0 0. ",Extended ID Bit 0" "0,1"
|
|
line.long 0x4 "C0MKR1,CAN0 Mask Register 1"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x4 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x4 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x4 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x4 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x4 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x4 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x4 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x4 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x4 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x4 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x4 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x4 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x4 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x4 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x4 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x4 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x4 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x0 "C0MKR2,CAN0 Mask Register 2"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x0 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x0 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x0 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x0 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x0 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x0 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x0 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x0 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x0 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x0 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x0 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x0 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x0 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x0 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x0 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x0 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x0 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x4 "C0MKR3,CAN0 Mask Register 3"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x4 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x4 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x4 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x4 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x4 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x4 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x4 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x4 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x4 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x4 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x4 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x4 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x4 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x4 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x4 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x4 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x4 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x8 "C0MKR4,CAN0 Mask Register 4"
|
|
bitfld.long 0x8 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x8 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x8 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x8 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x8 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x8 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x8 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x8 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x8 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x8 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x8 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x8 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x8 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x8 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x8 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x8 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x8 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x8 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x8 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x8 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x8 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x8 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x8 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x8 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x8 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x8 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x8 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x8 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0xC "C0MKR5,CAN0 Mask Register 5"
|
|
bitfld.long 0xC 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0xC 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0xC 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0xC 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0xC 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0xC 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0xC 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0xC 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0xC 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0xC 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0xC 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0xC 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0xC 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0xC 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0xC 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0xC 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0xC 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0xC 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0xC 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0xC 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0xC 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0xC 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0xC 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0xC 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0xC 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0xC 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0xC 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0xC 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x10 "C0MKR6,CAN0 Mask Register 6"
|
|
bitfld.long 0x10 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x10 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x10 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x10 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x10 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x10 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x10 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x10 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x10 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x10 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x10 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x10 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x10 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x10 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x10 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x10 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x10 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x10 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x10 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x10 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x10 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x10 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x10 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x10 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x10 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x10 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x10 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x10 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x14 "C0MKR7,CAN0 Mask Register 7"
|
|
bitfld.long 0x14 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x14 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x14 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x14 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x14 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x14 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x14 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x14 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x14 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x14 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x14 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x14 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x14 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x14 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x14 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x14 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x14 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x14 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x14 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x14 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x14 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x14 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x14 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x14 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x14 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x14 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x14 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x14 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x18 "C0MKR8,CAN0 Mask Register 8"
|
|
bitfld.long 0x18 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x18 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x18 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x18 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x18 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x18 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x18 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x18 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x18 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x18 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x18 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x18 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x18 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x18 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x18 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x18 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x18 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x18 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x18 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x18 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x18 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x18 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x18 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x18 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x18 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x18 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x18 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x18 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x1C "C0MKR9,CAN0 Mask Register 9"
|
|
bitfld.long 0x1C 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x1C 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x1C 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x1C 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x1C 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x1C 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x1C 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x1C 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 0. ",Extended ID Bit 0" "0,1"
|
|
else
|
|
hgroup.long 0x430++0x07
|
|
hide.long 0x0 "C0MKR0,CAN0 Mask Register 0"
|
|
hide.long 0x4 "C0MKR1,CAN0 Mask Register 1"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x0 "C0MKR2,CAN0 Mask Register 2"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x4 "C0MKR3,CAN0 Mask Register 3"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x8 "C0MKR4,CAN0 Mask Register 4"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0xC "C0MKR5,CAN0 Mask Register 5"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x10 "C0MKR6,CAN0 Mask Register 6"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x14 "C0MKR7,CAN0 Mask Register 7"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x18 "C0MKR8,CAN0 Mask Register 8"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x1C "C0MKR9,CAN0 Mask Register 9"
|
|
endif
|
|
if ((((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x420))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2)))
|
|
group.long 0x420++0x03
|
|
line.long 0x0 "C0FIDCR0,CAN0 FIFO Received ID Compare Register 0"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
elif ((((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x420))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0)))
|
|
group.long 0x420++0x03
|
|
line.long 0x0 "C0FIDCR0,CAN0 FIFO Received ID Compare Register 0"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x0 "C0FIDCR0,CAN0 FIFO Received ID Compare Register 0"
|
|
endif
|
|
if ((((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x424))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2)))
|
|
group.long 0x424++0x03
|
|
line.long 0x0 "C0FIDCR1,CAN0 FIFO Received ID Compare Register 1"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
elif ((((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x424))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0)))
|
|
group.long 0x424++0x03
|
|
line.long 0x0 "C0FIDCR1,CAN0 FIFO Received ID Compare Register 1"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x0 "C0FIDCR1,CAN0 FIFO Received ID Compare Register 1"
|
|
endif
|
|
group.long 0x428++0x03
|
|
line.long 0x0 "C0MKIVLR1,CAN0 Mask Invalid Register 1"
|
|
bitfld.long 0x00 31. " MBMV63 ,Mask valid for mailbox 63" "Valid,Invalid"
|
|
bitfld.long 0x00 30. " MBMV62 ,Mask valid for mailbox 62" "Valid,Invalid"
|
|
bitfld.long 0x00 29. " MBMV61 ,Mask valid for mailbox 61" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MBMV60 ,Mask valid for mailbox 60" "Valid,Invalid"
|
|
bitfld.long 0x00 27. " MBMV59 ,Mask valid for mailbox 59" "Valid,Invalid"
|
|
bitfld.long 0x00 26. " MBMV58 ,Mask valid for mailbox 58" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MBMV57 ,Mask valid for mailbox 57" "Valid,Invalid"
|
|
bitfld.long 0x00 24. " MBMV56 ,Mask valid for mailbox 56" "Valid,Invalid"
|
|
bitfld.long 0x00 23. " MBMV55 ,Mask valid for mailbox 55" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MBMV54 ,Mask valid for mailbox 54" "Valid,Invalid"
|
|
bitfld.long 0x00 21. " MBMV53 ,Mask valid for mailbox 53" "Valid,Invalid"
|
|
bitfld.long 0x00 20. " MBMV52 ,Mask valid for mailbox 52" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MBMV51 ,Mask valid for mailbox 51" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " MBMV50 ,Mask valid for mailbox 50" "Valid,Invalid"
|
|
bitfld.long 0x00 17. " MBMV49 ,Mask valid for mailbox 49" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MBMV48 ,Mask valid for mailbox 48" "Valid,Invalid"
|
|
bitfld.long 0x00 15. " MBMV47 ,Mask valid for mailbox 47" "Valid,Invalid"
|
|
bitfld.long 0x00 14. " MBMV46 ,Mask valid for mailbox 46" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MBMV45 ,Mask valid for mailbox 45" "Valid,Invalid"
|
|
bitfld.long 0x00 12. " MBMV44 ,Mask valid for mailbox 44" "Valid,Invalid"
|
|
bitfld.long 0x00 11. " MBMV43 ,Mask valid for mailbox 43" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBMV42 ,Mask valid for mailbox 42" "Valid,Invalid"
|
|
bitfld.long 0x00 9. " MBMV41 ,Mask valid for mailbox 41" "Valid,Invalid"
|
|
bitfld.long 0x00 8. " MBMV40 ,Mask valid for mailbox 40" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MBMV39 ,Mask valid for mailbox 39" "Valid,Invalid"
|
|
bitfld.long 0x00 6. " MBMV38 ,Mask valid for mailbox 38" "Valid,Invalid"
|
|
bitfld.long 0x00 5. " MBMV37 ,Mask valid for mailbox 37" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MBMV36 ,Mask valid for mailbox 36" "Valid,Invalid"
|
|
bitfld.long 0x00 3. " MBMV35 ,Mask valid for mailbox 35" "Valid,Invalid"
|
|
bitfld.long 0x00 2. " MBMV34 ,Mask valid for mailbox 34" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MBMV33 ,Mask valid for mailbox 33" "Valid,Invalid"
|
|
bitfld.long 0x00 0. " MBMV32 ,Mask valid for mailbox 32" "Valid,Invalid"
|
|
group.long 0x438++0x03
|
|
line.long 0x0 "C0MKIVLR0,CAN0 Mask Invalid Register 0"
|
|
bitfld.long 0x00 31. " MBMV31 ,Mask valid for mailbox 31" "Valid,Invalid"
|
|
bitfld.long 0x00 30. " MBMV30 ,Mask valid for mailbox 30" "Valid,Invalid"
|
|
bitfld.long 0x00 29. " MBMV29 ,Mask valid for mailbox 29" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MBMV28 ,Mask valid for mailbox 28" "Valid,Invalid"
|
|
bitfld.long 0x00 27. " MBMV27 ,Mask valid for mailbox 27" "Valid,Invalid"
|
|
bitfld.long 0x00 26. " MBMV26 ,Mask valid for mailbox 26" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MBMV25 ,Mask valid for mailbox 25" "Valid,Invalid"
|
|
bitfld.long 0x00 24. " MBMV24 ,Mask valid for mailbox 24" "Valid,Invalid"
|
|
bitfld.long 0x00 23. " MBMV23 ,Mask valid for mailbox 23" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MBMV22 ,Mask valid for mailbox 22" "Valid,Invalid"
|
|
bitfld.long 0x00 21. " MBMV21 ,Mask valid for mailbox 21" "Valid,Invalid"
|
|
bitfld.long 0x00 20. " MBMV20 ,Mask valid for mailbox 20" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MBMV19 ,Mask valid for mailbox 19" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " MBMV18 ,Mask valid for mailbox 18" "Valid,Invalid"
|
|
bitfld.long 0x00 17. " MBMV17 ,Mask valid for mailbox 17" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MBMV16 ,Mask valid for mailbox 16" "Valid,Invalid"
|
|
bitfld.long 0x00 15. " MBMV15 ,Mask valid for mailbox 15" "Valid,Invalid"
|
|
bitfld.long 0x00 14. " MBMV14 ,Mask valid for mailbox 14" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MBMV13 ,Mask valid for mailbox 13" "Valid,Invalid"
|
|
bitfld.long 0x00 12. " MBMV12 ,Mask valid for mailbox 12" "Valid,Invalid"
|
|
bitfld.long 0x00 11. " MBMV11 ,Mask valid for mailbox 11" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBMV10 ,Mask valid for mailbox 10" "Valid,Invalid"
|
|
bitfld.long 0x00 9. " MBMV9 ,Mask valid for mailbox 9" "Valid,Invalid"
|
|
bitfld.long 0x00 8. " MBMV8 ,Mask valid for mailbox 8" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MBMV7 ,Mask valid for mailbox 7" "Valid,Invalid"
|
|
bitfld.long 0x00 6. " MBMV6 ,Mask valid for mailbox 6" "Valid,Invalid"
|
|
bitfld.long 0x00 5. " MBMV5 ,Mask valid for mailbox 5" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MBMV4 ,Mask valid for mailbox 4" "Valid,Invalid"
|
|
bitfld.long 0x00 3. " MBMV3 ,Mask valid for mailbox 3" "Valid,Invalid"
|
|
bitfld.long 0x00 2. " MBMV2 ,Mask valid for mailbox 2" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MBMV1 ,Mask valid for mailbox 1" "Valid,Invalid"
|
|
bitfld.long 0x00 0. " MBMV0 ,Mask valid for mailbox 0" "Valid,Invalid"
|
|
tree "CAN Mailboxes registers"
|
|
if (((63.==60.)||(63.==61.)||(63.==62.)||(63.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C0MB63_ID,CAN0 Mailbox 63 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "C0MB63_ID,CAN0 Mailbox 63 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "C0MB63_ID,CAN0 Mailbox 63 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C0MB63_ID,CAN0 Mailbox 63 Register"
|
|
endif
|
|
group.word (0x0+0x04)++0x1
|
|
line.word 0x00 "C0MB63_DLC,CAN0 Mailbox 63 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x0+0x06)++0x07
|
|
line.byte 0x00 "C0MB63_D0,CAN0 Mailbox 63 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB63_D1,CAN0 Mailbox 63 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB63_D2,CAN0 Mailbox 63 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB63_D3,CAN0 Mailbox 63 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB63_D4,CAN0 Mailbox 63 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB63_D5,CAN0 Mailbox 63 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB63_D6,CAN0 Mailbox 63 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB63_D7,CAN0 Mailbox 63 Data byte 7 Register"
|
|
group.word (0x0+0x0e)++0x01
|
|
line.word 0x00 "C0MB63_TS,CAN0 Mailbox 63 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((62.==60.)||(62.==61.)||(62.==62.)||(62.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "C0MB62_ID,CAN0 Mailbox 62 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x10))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0MB62_ID,CAN0 Mailbox 62 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x10))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0MB62_ID,CAN0 Mailbox 62 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "C0MB62_ID,CAN0 Mailbox 62 Register"
|
|
endif
|
|
group.word (0x10+0x04)++0x1
|
|
line.word 0x00 "C0MB62_DLC,CAN0 Mailbox 62 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x10+0x06)++0x07
|
|
line.byte 0x00 "C0MB62_D0,CAN0 Mailbox 62 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB62_D1,CAN0 Mailbox 62 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB62_D2,CAN0 Mailbox 62 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB62_D3,CAN0 Mailbox 62 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB62_D4,CAN0 Mailbox 62 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB62_D5,CAN0 Mailbox 62 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB62_D6,CAN0 Mailbox 62 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB62_D7,CAN0 Mailbox 62 Data byte 7 Register"
|
|
group.word (0x10+0x0e)++0x01
|
|
line.word 0x00 "C0MB62_TS,CAN0 Mailbox 62 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((61.==60.)||(61.==61.)||(61.==62.)||(61.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "C0MB61_ID,CAN0 Mailbox 61 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x20))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C0MB61_ID,CAN0 Mailbox 61 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x20))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C0MB61_ID,CAN0 Mailbox 61 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "C0MB61_ID,CAN0 Mailbox 61 Register"
|
|
endif
|
|
group.word (0x20+0x04)++0x1
|
|
line.word 0x00 "C0MB61_DLC,CAN0 Mailbox 61 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x20+0x06)++0x07
|
|
line.byte 0x00 "C0MB61_D0,CAN0 Mailbox 61 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB61_D1,CAN0 Mailbox 61 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB61_D2,CAN0 Mailbox 61 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB61_D3,CAN0 Mailbox 61 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB61_D4,CAN0 Mailbox 61 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB61_D5,CAN0 Mailbox 61 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB61_D6,CAN0 Mailbox 61 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB61_D7,CAN0 Mailbox 61 Data byte 7 Register"
|
|
group.word (0x20+0x0e)++0x01
|
|
line.word 0x00 "C0MB61_TS,CAN0 Mailbox 61 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((60.==60.)||(60.==61.)||(60.==62.)||(60.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "C0MB60_ID,CAN0 Mailbox 60 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x30))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C0MB60_ID,CAN0 Mailbox 60 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x30))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C0MB60_ID,CAN0 Mailbox 60 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "C0MB60_ID,CAN0 Mailbox 60 Register"
|
|
endif
|
|
group.word (0x30+0x04)++0x1
|
|
line.word 0x00 "C0MB60_DLC,CAN0 Mailbox 60 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x30+0x06)++0x07
|
|
line.byte 0x00 "C0MB60_D0,CAN0 Mailbox 60 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB60_D1,CAN0 Mailbox 60 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB60_D2,CAN0 Mailbox 60 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB60_D3,CAN0 Mailbox 60 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB60_D4,CAN0 Mailbox 60 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB60_D5,CAN0 Mailbox 60 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB60_D6,CAN0 Mailbox 60 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB60_D7,CAN0 Mailbox 60 Data byte 7 Register"
|
|
group.word (0x30+0x0e)++0x01
|
|
line.word 0x00 "C0MB60_TS,CAN0 Mailbox 60 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((59.==60.)||(59.==61.)||(59.==62.)||(59.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "C0MB59_ID,CAN0 Mailbox 59 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x40))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C0MB59_ID,CAN0 Mailbox 59 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x40))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C0MB59_ID,CAN0 Mailbox 59 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "C0MB59_ID,CAN0 Mailbox 59 Register"
|
|
endif
|
|
group.word (0x40+0x04)++0x1
|
|
line.word 0x00 "C0MB59_DLC,CAN0 Mailbox 59 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x40+0x06)++0x07
|
|
line.byte 0x00 "C0MB59_D0,CAN0 Mailbox 59 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB59_D1,CAN0 Mailbox 59 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB59_D2,CAN0 Mailbox 59 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB59_D3,CAN0 Mailbox 59 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB59_D4,CAN0 Mailbox 59 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB59_D5,CAN0 Mailbox 59 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB59_D6,CAN0 Mailbox 59 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB59_D7,CAN0 Mailbox 59 Data byte 7 Register"
|
|
group.word (0x40+0x0e)++0x01
|
|
line.word 0x00 "C0MB59_TS,CAN0 Mailbox 59 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((58.==60.)||(58.==61.)||(58.==62.)||(58.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "C0MB58_ID,CAN0 Mailbox 58 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x50))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "C0MB58_ID,CAN0 Mailbox 58 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x50))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "C0MB58_ID,CAN0 Mailbox 58 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "C0MB58_ID,CAN0 Mailbox 58 Register"
|
|
endif
|
|
group.word (0x50+0x04)++0x1
|
|
line.word 0x00 "C0MB58_DLC,CAN0 Mailbox 58 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x50+0x06)++0x07
|
|
line.byte 0x00 "C0MB58_D0,CAN0 Mailbox 58 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB58_D1,CAN0 Mailbox 58 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB58_D2,CAN0 Mailbox 58 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB58_D3,CAN0 Mailbox 58 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB58_D4,CAN0 Mailbox 58 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB58_D5,CAN0 Mailbox 58 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB58_D6,CAN0 Mailbox 58 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB58_D7,CAN0 Mailbox 58 Data byte 7 Register"
|
|
group.word (0x50+0x0e)++0x01
|
|
line.word 0x00 "C0MB58_TS,CAN0 Mailbox 58 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((57.==60.)||(57.==61.)||(57.==62.)||(57.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "C0MB57_ID,CAN0 Mailbox 57 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x60))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C0MB57_ID,CAN0 Mailbox 57 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x60))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C0MB57_ID,CAN0 Mailbox 57 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "C0MB57_ID,CAN0 Mailbox 57 Register"
|
|
endif
|
|
group.word (0x60+0x04)++0x1
|
|
line.word 0x00 "C0MB57_DLC,CAN0 Mailbox 57 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x60+0x06)++0x07
|
|
line.byte 0x00 "C0MB57_D0,CAN0 Mailbox 57 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB57_D1,CAN0 Mailbox 57 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB57_D2,CAN0 Mailbox 57 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB57_D3,CAN0 Mailbox 57 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB57_D4,CAN0 Mailbox 57 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB57_D5,CAN0 Mailbox 57 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB57_D6,CAN0 Mailbox 57 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB57_D7,CAN0 Mailbox 57 Data byte 7 Register"
|
|
group.word (0x60+0x0e)++0x01
|
|
line.word 0x00 "C0MB57_TS,CAN0 Mailbox 57 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((56.==60.)||(56.==61.)||(56.==62.)||(56.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "C0MB56_ID,CAN0 Mailbox 56 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x70))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "C0MB56_ID,CAN0 Mailbox 56 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x70))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "C0MB56_ID,CAN0 Mailbox 56 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "C0MB56_ID,CAN0 Mailbox 56 Register"
|
|
endif
|
|
group.word (0x70+0x04)++0x1
|
|
line.word 0x00 "C0MB56_DLC,CAN0 Mailbox 56 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x70+0x06)++0x07
|
|
line.byte 0x00 "C0MB56_D0,CAN0 Mailbox 56 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB56_D1,CAN0 Mailbox 56 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB56_D2,CAN0 Mailbox 56 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB56_D3,CAN0 Mailbox 56 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB56_D4,CAN0 Mailbox 56 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB56_D5,CAN0 Mailbox 56 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB56_D6,CAN0 Mailbox 56 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB56_D7,CAN0 Mailbox 56 Data byte 7 Register"
|
|
group.word (0x70+0x0e)++0x01
|
|
line.word 0x00 "C0MB56_TS,CAN0 Mailbox 56 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((55.==60.)||(55.==61.)||(55.==62.)||(55.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "C0MB55_ID,CAN0 Mailbox 55 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x80))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "C0MB55_ID,CAN0 Mailbox 55 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x80))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "C0MB55_ID,CAN0 Mailbox 55 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "C0MB55_ID,CAN0 Mailbox 55 Register"
|
|
endif
|
|
group.word (0x80+0x04)++0x1
|
|
line.word 0x00 "C0MB55_DLC,CAN0 Mailbox 55 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x80+0x06)++0x07
|
|
line.byte 0x00 "C0MB55_D0,CAN0 Mailbox 55 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB55_D1,CAN0 Mailbox 55 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB55_D2,CAN0 Mailbox 55 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB55_D3,CAN0 Mailbox 55 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB55_D4,CAN0 Mailbox 55 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB55_D5,CAN0 Mailbox 55 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB55_D6,CAN0 Mailbox 55 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB55_D7,CAN0 Mailbox 55 Data byte 7 Register"
|
|
group.word (0x80+0x0e)++0x01
|
|
line.word 0x00 "C0MB55_TS,CAN0 Mailbox 55 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((54.==60.)||(54.==61.)||(54.==62.)||(54.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "C0MB54_ID,CAN0 Mailbox 54 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x90))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "C0MB54_ID,CAN0 Mailbox 54 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x90))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "C0MB54_ID,CAN0 Mailbox 54 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "C0MB54_ID,CAN0 Mailbox 54 Register"
|
|
endif
|
|
group.word (0x90+0x04)++0x1
|
|
line.word 0x00 "C0MB54_DLC,CAN0 Mailbox 54 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x90+0x06)++0x07
|
|
line.byte 0x00 "C0MB54_D0,CAN0 Mailbox 54 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB54_D1,CAN0 Mailbox 54 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB54_D2,CAN0 Mailbox 54 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB54_D3,CAN0 Mailbox 54 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB54_D4,CAN0 Mailbox 54 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB54_D5,CAN0 Mailbox 54 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB54_D6,CAN0 Mailbox 54 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB54_D7,CAN0 Mailbox 54 Data byte 7 Register"
|
|
group.word (0x90+0x0e)++0x01
|
|
line.word 0x00 "C0MB54_TS,CAN0 Mailbox 54 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((53.==60.)||(53.==61.)||(53.==62.)||(53.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "C0MB53_ID,CAN0 Mailbox 53 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xA0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "C0MB53_ID,CAN0 Mailbox 53 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xA0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "C0MB53_ID,CAN0 Mailbox 53 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "C0MB53_ID,CAN0 Mailbox 53 Register"
|
|
endif
|
|
group.word (0xA0+0x04)++0x1
|
|
line.word 0x00 "C0MB53_DLC,CAN0 Mailbox 53 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xA0+0x06)++0x07
|
|
line.byte 0x00 "C0MB53_D0,CAN0 Mailbox 53 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB53_D1,CAN0 Mailbox 53 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB53_D2,CAN0 Mailbox 53 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB53_D3,CAN0 Mailbox 53 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB53_D4,CAN0 Mailbox 53 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB53_D5,CAN0 Mailbox 53 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB53_D6,CAN0 Mailbox 53 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB53_D7,CAN0 Mailbox 53 Data byte 7 Register"
|
|
group.word (0xA0+0x0e)++0x01
|
|
line.word 0x00 "C0MB53_TS,CAN0 Mailbox 53 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((52.==60.)||(52.==61.)||(52.==62.)||(52.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "C0MB52_ID,CAN0 Mailbox 52 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xB0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "C0MB52_ID,CAN0 Mailbox 52 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xB0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "C0MB52_ID,CAN0 Mailbox 52 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "C0MB52_ID,CAN0 Mailbox 52 Register"
|
|
endif
|
|
group.word (0xB0+0x04)++0x1
|
|
line.word 0x00 "C0MB52_DLC,CAN0 Mailbox 52 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xB0+0x06)++0x07
|
|
line.byte 0x00 "C0MB52_D0,CAN0 Mailbox 52 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB52_D1,CAN0 Mailbox 52 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB52_D2,CAN0 Mailbox 52 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB52_D3,CAN0 Mailbox 52 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB52_D4,CAN0 Mailbox 52 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB52_D5,CAN0 Mailbox 52 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB52_D6,CAN0 Mailbox 52 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB52_D7,CAN0 Mailbox 52 Data byte 7 Register"
|
|
group.word (0xB0+0x0e)++0x01
|
|
line.word 0x00 "C0MB52_TS,CAN0 Mailbox 52 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((51.==60.)||(51.==61.)||(51.==62.)||(51.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "C0MB51_ID,CAN0 Mailbox 51 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xC0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "C0MB51_ID,CAN0 Mailbox 51 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xC0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "C0MB51_ID,CAN0 Mailbox 51 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "C0MB51_ID,CAN0 Mailbox 51 Register"
|
|
endif
|
|
group.word (0xC0+0x04)++0x1
|
|
line.word 0x00 "C0MB51_DLC,CAN0 Mailbox 51 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xC0+0x06)++0x07
|
|
line.byte 0x00 "C0MB51_D0,CAN0 Mailbox 51 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB51_D1,CAN0 Mailbox 51 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB51_D2,CAN0 Mailbox 51 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB51_D3,CAN0 Mailbox 51 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB51_D4,CAN0 Mailbox 51 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB51_D5,CAN0 Mailbox 51 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB51_D6,CAN0 Mailbox 51 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB51_D7,CAN0 Mailbox 51 Data byte 7 Register"
|
|
group.word (0xC0+0x0e)++0x01
|
|
line.word 0x00 "C0MB51_TS,CAN0 Mailbox 51 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((50.==60.)||(50.==61.)||(50.==62.)||(50.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "C0MB50_ID,CAN0 Mailbox 50 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xD0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "C0MB50_ID,CAN0 Mailbox 50 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xD0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "C0MB50_ID,CAN0 Mailbox 50 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "C0MB50_ID,CAN0 Mailbox 50 Register"
|
|
endif
|
|
group.word (0xD0+0x04)++0x1
|
|
line.word 0x00 "C0MB50_DLC,CAN0 Mailbox 50 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xD0+0x06)++0x07
|
|
line.byte 0x00 "C0MB50_D0,CAN0 Mailbox 50 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB50_D1,CAN0 Mailbox 50 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB50_D2,CAN0 Mailbox 50 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB50_D3,CAN0 Mailbox 50 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB50_D4,CAN0 Mailbox 50 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB50_D5,CAN0 Mailbox 50 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB50_D6,CAN0 Mailbox 50 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB50_D7,CAN0 Mailbox 50 Data byte 7 Register"
|
|
group.word (0xD0+0x0e)++0x01
|
|
line.word 0x00 "C0MB50_TS,CAN0 Mailbox 50 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((49.==60.)||(49.==61.)||(49.==62.)||(49.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "C0MB49_ID,CAN0 Mailbox 49 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xE0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "C0MB49_ID,CAN0 Mailbox 49 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xE0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "C0MB49_ID,CAN0 Mailbox 49 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "C0MB49_ID,CAN0 Mailbox 49 Register"
|
|
endif
|
|
group.word (0xE0+0x04)++0x1
|
|
line.word 0x00 "C0MB49_DLC,CAN0 Mailbox 49 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xE0+0x06)++0x07
|
|
line.byte 0x00 "C0MB49_D0,CAN0 Mailbox 49 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB49_D1,CAN0 Mailbox 49 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB49_D2,CAN0 Mailbox 49 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB49_D3,CAN0 Mailbox 49 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB49_D4,CAN0 Mailbox 49 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB49_D5,CAN0 Mailbox 49 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB49_D6,CAN0 Mailbox 49 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB49_D7,CAN0 Mailbox 49 Data byte 7 Register"
|
|
group.word (0xE0+0x0e)++0x01
|
|
line.word 0x00 "C0MB49_TS,CAN0 Mailbox 49 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((48.==60.)||(48.==61.)||(48.==62.)||(48.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "C0MB48_ID,CAN0 Mailbox 48 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xF0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "C0MB48_ID,CAN0 Mailbox 48 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0xF0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "C0MB48_ID,CAN0 Mailbox 48 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "C0MB48_ID,CAN0 Mailbox 48 Register"
|
|
endif
|
|
group.word (0xF0+0x04)++0x1
|
|
line.word 0x00 "C0MB48_DLC,CAN0 Mailbox 48 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xF0+0x06)++0x07
|
|
line.byte 0x00 "C0MB48_D0,CAN0 Mailbox 48 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB48_D1,CAN0 Mailbox 48 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB48_D2,CAN0 Mailbox 48 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB48_D3,CAN0 Mailbox 48 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB48_D4,CAN0 Mailbox 48 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB48_D5,CAN0 Mailbox 48 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB48_D6,CAN0 Mailbox 48 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB48_D7,CAN0 Mailbox 48 Data byte 7 Register"
|
|
group.word (0xF0+0x0e)++0x01
|
|
line.word 0x00 "C0MB48_TS,CAN0 Mailbox 48 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((47.==60.)||(47.==61.)||(47.==62.)||(47.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "C0MB47_ID,CAN0 Mailbox 47 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x100))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0MB47_ID,CAN0 Mailbox 47 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x100))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C0MB47_ID,CAN0 Mailbox 47 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "C0MB47_ID,CAN0 Mailbox 47 Register"
|
|
endif
|
|
group.word (0x100+0x04)++0x1
|
|
line.word 0x00 "C0MB47_DLC,CAN0 Mailbox 47 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x100+0x06)++0x07
|
|
line.byte 0x00 "C0MB47_D0,CAN0 Mailbox 47 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB47_D1,CAN0 Mailbox 47 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB47_D2,CAN0 Mailbox 47 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB47_D3,CAN0 Mailbox 47 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB47_D4,CAN0 Mailbox 47 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB47_D5,CAN0 Mailbox 47 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB47_D6,CAN0 Mailbox 47 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB47_D7,CAN0 Mailbox 47 Data byte 7 Register"
|
|
group.word (0x100+0x0e)++0x01
|
|
line.word 0x00 "C0MB47_TS,CAN0 Mailbox 47 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((46.==60.)||(46.==61.)||(46.==62.)||(46.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "C0MB46_ID,CAN0 Mailbox 46 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x110))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0MB46_ID,CAN0 Mailbox 46 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x110))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C0MB46_ID,CAN0 Mailbox 46 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "C0MB46_ID,CAN0 Mailbox 46 Register"
|
|
endif
|
|
group.word (0x110+0x04)++0x1
|
|
line.word 0x00 "C0MB46_DLC,CAN0 Mailbox 46 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x110+0x06)++0x07
|
|
line.byte 0x00 "C0MB46_D0,CAN0 Mailbox 46 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB46_D1,CAN0 Mailbox 46 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB46_D2,CAN0 Mailbox 46 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB46_D3,CAN0 Mailbox 46 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB46_D4,CAN0 Mailbox 46 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB46_D5,CAN0 Mailbox 46 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB46_D6,CAN0 Mailbox 46 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB46_D7,CAN0 Mailbox 46 Data byte 7 Register"
|
|
group.word (0x110+0x0e)++0x01
|
|
line.word 0x00 "C0MB46_TS,CAN0 Mailbox 46 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((45.==60.)||(45.==61.)||(45.==62.)||(45.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "C0MB45_ID,CAN0 Mailbox 45 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x120))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C0MB45_ID,CAN0 Mailbox 45 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x120))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C0MB45_ID,CAN0 Mailbox 45 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "C0MB45_ID,CAN0 Mailbox 45 Register"
|
|
endif
|
|
group.word (0x120+0x04)++0x1
|
|
line.word 0x00 "C0MB45_DLC,CAN0 Mailbox 45 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x120+0x06)++0x07
|
|
line.byte 0x00 "C0MB45_D0,CAN0 Mailbox 45 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB45_D1,CAN0 Mailbox 45 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB45_D2,CAN0 Mailbox 45 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB45_D3,CAN0 Mailbox 45 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB45_D4,CAN0 Mailbox 45 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB45_D5,CAN0 Mailbox 45 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB45_D6,CAN0 Mailbox 45 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB45_D7,CAN0 Mailbox 45 Data byte 7 Register"
|
|
group.word (0x120+0x0e)++0x01
|
|
line.word 0x00 "C0MB45_TS,CAN0 Mailbox 45 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((44.==60.)||(44.==61.)||(44.==62.)||(44.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "C0MB44_ID,CAN0 Mailbox 44 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x130))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C0MB44_ID,CAN0 Mailbox 44 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x130))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C0MB44_ID,CAN0 Mailbox 44 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "C0MB44_ID,CAN0 Mailbox 44 Register"
|
|
endif
|
|
group.word (0x130+0x04)++0x1
|
|
line.word 0x00 "C0MB44_DLC,CAN0 Mailbox 44 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x130+0x06)++0x07
|
|
line.byte 0x00 "C0MB44_D0,CAN0 Mailbox 44 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB44_D1,CAN0 Mailbox 44 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB44_D2,CAN0 Mailbox 44 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB44_D3,CAN0 Mailbox 44 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB44_D4,CAN0 Mailbox 44 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB44_D5,CAN0 Mailbox 44 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB44_D6,CAN0 Mailbox 44 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB44_D7,CAN0 Mailbox 44 Data byte 7 Register"
|
|
group.word (0x130+0x0e)++0x01
|
|
line.word 0x00 "C0MB44_TS,CAN0 Mailbox 44 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((43.==60.)||(43.==61.)||(43.==62.)||(43.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "C0MB43_ID,CAN0 Mailbox 43 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x140))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "C0MB43_ID,CAN0 Mailbox 43 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x140))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "C0MB43_ID,CAN0 Mailbox 43 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "C0MB43_ID,CAN0 Mailbox 43 Register"
|
|
endif
|
|
group.word (0x140+0x04)++0x1
|
|
line.word 0x00 "C0MB43_DLC,CAN0 Mailbox 43 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x140+0x06)++0x07
|
|
line.byte 0x00 "C0MB43_D0,CAN0 Mailbox 43 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB43_D1,CAN0 Mailbox 43 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB43_D2,CAN0 Mailbox 43 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB43_D3,CAN0 Mailbox 43 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB43_D4,CAN0 Mailbox 43 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB43_D5,CAN0 Mailbox 43 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB43_D6,CAN0 Mailbox 43 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB43_D7,CAN0 Mailbox 43 Data byte 7 Register"
|
|
group.word (0x140+0x0e)++0x01
|
|
line.word 0x00 "C0MB43_TS,CAN0 Mailbox 43 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((42.==60.)||(42.==61.)||(42.==62.)||(42.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "C0MB42_ID,CAN0 Mailbox 42 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x150))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "C0MB42_ID,CAN0 Mailbox 42 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x150))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "C0MB42_ID,CAN0 Mailbox 42 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "C0MB42_ID,CAN0 Mailbox 42 Register"
|
|
endif
|
|
group.word (0x150+0x04)++0x1
|
|
line.word 0x00 "C0MB42_DLC,CAN0 Mailbox 42 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x150+0x06)++0x07
|
|
line.byte 0x00 "C0MB42_D0,CAN0 Mailbox 42 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB42_D1,CAN0 Mailbox 42 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB42_D2,CAN0 Mailbox 42 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB42_D3,CAN0 Mailbox 42 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB42_D4,CAN0 Mailbox 42 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB42_D5,CAN0 Mailbox 42 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB42_D6,CAN0 Mailbox 42 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB42_D7,CAN0 Mailbox 42 Data byte 7 Register"
|
|
group.word (0x150+0x0e)++0x01
|
|
line.word 0x00 "C0MB42_TS,CAN0 Mailbox 42 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((41.==60.)||(41.==61.)||(41.==62.)||(41.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "C0MB41_ID,CAN0 Mailbox 41 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x160))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "C0MB41_ID,CAN0 Mailbox 41 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x160))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "C0MB41_ID,CAN0 Mailbox 41 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "C0MB41_ID,CAN0 Mailbox 41 Register"
|
|
endif
|
|
group.word (0x160+0x04)++0x1
|
|
line.word 0x00 "C0MB41_DLC,CAN0 Mailbox 41 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x160+0x06)++0x07
|
|
line.byte 0x00 "C0MB41_D0,CAN0 Mailbox 41 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB41_D1,CAN0 Mailbox 41 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB41_D2,CAN0 Mailbox 41 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB41_D3,CAN0 Mailbox 41 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB41_D4,CAN0 Mailbox 41 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB41_D5,CAN0 Mailbox 41 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB41_D6,CAN0 Mailbox 41 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB41_D7,CAN0 Mailbox 41 Data byte 7 Register"
|
|
group.word (0x160+0x0e)++0x01
|
|
line.word 0x00 "C0MB41_TS,CAN0 Mailbox 41 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((40.==60.)||(40.==61.)||(40.==62.)||(40.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "C0MB40_ID,CAN0 Mailbox 40 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x170))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "C0MB40_ID,CAN0 Mailbox 40 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x170))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "C0MB40_ID,CAN0 Mailbox 40 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "C0MB40_ID,CAN0 Mailbox 40 Register"
|
|
endif
|
|
group.word (0x170+0x04)++0x1
|
|
line.word 0x00 "C0MB40_DLC,CAN0 Mailbox 40 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x170+0x06)++0x07
|
|
line.byte 0x00 "C0MB40_D0,CAN0 Mailbox 40 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB40_D1,CAN0 Mailbox 40 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB40_D2,CAN0 Mailbox 40 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB40_D3,CAN0 Mailbox 40 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB40_D4,CAN0 Mailbox 40 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB40_D5,CAN0 Mailbox 40 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB40_D6,CAN0 Mailbox 40 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB40_D7,CAN0 Mailbox 40 Data byte 7 Register"
|
|
group.word (0x170+0x0e)++0x01
|
|
line.word 0x00 "C0MB40_TS,CAN0 Mailbox 40 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((39.==60.)||(39.==61.)||(39.==62.)||(39.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "C0MB39_ID,CAN0 Mailbox 39 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x180))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "C0MB39_ID,CAN0 Mailbox 39 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x180))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "C0MB39_ID,CAN0 Mailbox 39 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "C0MB39_ID,CAN0 Mailbox 39 Register"
|
|
endif
|
|
group.word (0x180+0x04)++0x1
|
|
line.word 0x00 "C0MB39_DLC,CAN0 Mailbox 39 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x180+0x06)++0x07
|
|
line.byte 0x00 "C0MB39_D0,CAN0 Mailbox 39 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB39_D1,CAN0 Mailbox 39 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB39_D2,CAN0 Mailbox 39 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB39_D3,CAN0 Mailbox 39 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB39_D4,CAN0 Mailbox 39 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB39_D5,CAN0 Mailbox 39 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB39_D6,CAN0 Mailbox 39 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB39_D7,CAN0 Mailbox 39 Data byte 7 Register"
|
|
group.word (0x180+0x0e)++0x01
|
|
line.word 0x00 "C0MB39_TS,CAN0 Mailbox 39 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((38.==60.)||(38.==61.)||(38.==62.)||(38.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "C0MB38_ID,CAN0 Mailbox 38 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x190))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "C0MB38_ID,CAN0 Mailbox 38 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x190))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "C0MB38_ID,CAN0 Mailbox 38 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "C0MB38_ID,CAN0 Mailbox 38 Register"
|
|
endif
|
|
group.word (0x190+0x04)++0x1
|
|
line.word 0x00 "C0MB38_DLC,CAN0 Mailbox 38 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x190+0x06)++0x07
|
|
line.byte 0x00 "C0MB38_D0,CAN0 Mailbox 38 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB38_D1,CAN0 Mailbox 38 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB38_D2,CAN0 Mailbox 38 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB38_D3,CAN0 Mailbox 38 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB38_D4,CAN0 Mailbox 38 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB38_D5,CAN0 Mailbox 38 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB38_D6,CAN0 Mailbox 38 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB38_D7,CAN0 Mailbox 38 Data byte 7 Register"
|
|
group.word (0x190+0x0e)++0x01
|
|
line.word 0x00 "C0MB38_TS,CAN0 Mailbox 38 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((37.==60.)||(37.==61.)||(37.==62.)||(37.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "C0MB37_ID,CAN0 Mailbox 37 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "C0MB37_ID,CAN0 Mailbox 37 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "C0MB37_ID,CAN0 Mailbox 37 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "C0MB37_ID,CAN0 Mailbox 37 Register"
|
|
endif
|
|
group.word (0x1A0+0x04)++0x1
|
|
line.word 0x00 "C0MB37_DLC,CAN0 Mailbox 37 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1A0+0x06)++0x07
|
|
line.byte 0x00 "C0MB37_D0,CAN0 Mailbox 37 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB37_D1,CAN0 Mailbox 37 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB37_D2,CAN0 Mailbox 37 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB37_D3,CAN0 Mailbox 37 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB37_D4,CAN0 Mailbox 37 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB37_D5,CAN0 Mailbox 37 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB37_D6,CAN0 Mailbox 37 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB37_D7,CAN0 Mailbox 37 Data byte 7 Register"
|
|
group.word (0x1A0+0x0e)++0x01
|
|
line.word 0x00 "C0MB37_TS,CAN0 Mailbox 37 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((36.==60.)||(36.==61.)||(36.==62.)||(36.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "C0MB36_ID,CAN0 Mailbox 36 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "C0MB36_ID,CAN0 Mailbox 36 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "C0MB36_ID,CAN0 Mailbox 36 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "C0MB36_ID,CAN0 Mailbox 36 Register"
|
|
endif
|
|
group.word (0x1B0+0x04)++0x1
|
|
line.word 0x00 "C0MB36_DLC,CAN0 Mailbox 36 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1B0+0x06)++0x07
|
|
line.byte 0x00 "C0MB36_D0,CAN0 Mailbox 36 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB36_D1,CAN0 Mailbox 36 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB36_D2,CAN0 Mailbox 36 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB36_D3,CAN0 Mailbox 36 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB36_D4,CAN0 Mailbox 36 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB36_D5,CAN0 Mailbox 36 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB36_D6,CAN0 Mailbox 36 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB36_D7,CAN0 Mailbox 36 Data byte 7 Register"
|
|
group.word (0x1B0+0x0e)++0x01
|
|
line.word 0x00 "C0MB36_TS,CAN0 Mailbox 36 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((35.==60.)||(35.==61.)||(35.==62.)||(35.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "C0MB35_ID,CAN0 Mailbox 35 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "C0MB35_ID,CAN0 Mailbox 35 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "C0MB35_ID,CAN0 Mailbox 35 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "C0MB35_ID,CAN0 Mailbox 35 Register"
|
|
endif
|
|
group.word (0x1C0+0x04)++0x1
|
|
line.word 0x00 "C0MB35_DLC,CAN0 Mailbox 35 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1C0+0x06)++0x07
|
|
line.byte 0x00 "C0MB35_D0,CAN0 Mailbox 35 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB35_D1,CAN0 Mailbox 35 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB35_D2,CAN0 Mailbox 35 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB35_D3,CAN0 Mailbox 35 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB35_D4,CAN0 Mailbox 35 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB35_D5,CAN0 Mailbox 35 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB35_D6,CAN0 Mailbox 35 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB35_D7,CAN0 Mailbox 35 Data byte 7 Register"
|
|
group.word (0x1C0+0x0e)++0x01
|
|
line.word 0x00 "C0MB35_TS,CAN0 Mailbox 35 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((34.==60.)||(34.==61.)||(34.==62.)||(34.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "C0MB34_ID,CAN0 Mailbox 34 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "C0MB34_ID,CAN0 Mailbox 34 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "C0MB34_ID,CAN0 Mailbox 34 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "C0MB34_ID,CAN0 Mailbox 34 Register"
|
|
endif
|
|
group.word (0x1D0+0x04)++0x1
|
|
line.word 0x00 "C0MB34_DLC,CAN0 Mailbox 34 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1D0+0x06)++0x07
|
|
line.byte 0x00 "C0MB34_D0,CAN0 Mailbox 34 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB34_D1,CAN0 Mailbox 34 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB34_D2,CAN0 Mailbox 34 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB34_D3,CAN0 Mailbox 34 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB34_D4,CAN0 Mailbox 34 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB34_D5,CAN0 Mailbox 34 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB34_D6,CAN0 Mailbox 34 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB34_D7,CAN0 Mailbox 34 Data byte 7 Register"
|
|
group.word (0x1D0+0x0e)++0x01
|
|
line.word 0x00 "C0MB34_TS,CAN0 Mailbox 34 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((33.==60.)||(33.==61.)||(33.==62.)||(33.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "C0MB33_ID,CAN0 Mailbox 33 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "C0MB33_ID,CAN0 Mailbox 33 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "C0MB33_ID,CAN0 Mailbox 33 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "C0MB33_ID,CAN0 Mailbox 33 Register"
|
|
endif
|
|
group.word (0x1E0+0x04)++0x1
|
|
line.word 0x00 "C0MB33_DLC,CAN0 Mailbox 33 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1E0+0x06)++0x07
|
|
line.byte 0x00 "C0MB33_D0,CAN0 Mailbox 33 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB33_D1,CAN0 Mailbox 33 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB33_D2,CAN0 Mailbox 33 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB33_D3,CAN0 Mailbox 33 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB33_D4,CAN0 Mailbox 33 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB33_D5,CAN0 Mailbox 33 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB33_D6,CAN0 Mailbox 33 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB33_D7,CAN0 Mailbox 33 Data byte 7 Register"
|
|
group.word (0x1E0+0x0e)++0x01
|
|
line.word 0x00 "C0MB33_TS,CAN0 Mailbox 33 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((32.==60.)||(32.==61.)||(32.==62.)||(32.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "C0MB32_ID,CAN0 Mailbox 32 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "C0MB32_ID,CAN0 Mailbox 32 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x1F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "C0MB32_ID,CAN0 Mailbox 32 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "C0MB32_ID,CAN0 Mailbox 32 Register"
|
|
endif
|
|
group.word (0x1F0+0x04)++0x1
|
|
line.word 0x00 "C0MB32_DLC,CAN0 Mailbox 32 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1F0+0x06)++0x07
|
|
line.byte 0x00 "C0MB32_D0,CAN0 Mailbox 32 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB32_D1,CAN0 Mailbox 32 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB32_D2,CAN0 Mailbox 32 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB32_D3,CAN0 Mailbox 32 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB32_D4,CAN0 Mailbox 32 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB32_D5,CAN0 Mailbox 32 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB32_D6,CAN0 Mailbox 32 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB32_D7,CAN0 Mailbox 32 Data byte 7 Register"
|
|
group.word (0x1F0+0x0e)++0x01
|
|
line.word 0x00 "C0MB32_TS,CAN0 Mailbox 32 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((31.==60.)||(31.==61.)||(31.==62.)||(31.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "C0MB31_ID,CAN0 Mailbox 31 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x200))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "C0MB31_ID,CAN0 Mailbox 31 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x200))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "C0MB31_ID,CAN0 Mailbox 31 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "C0MB31_ID,CAN0 Mailbox 31 Register"
|
|
endif
|
|
group.word (0x200+0x04)++0x1
|
|
line.word 0x00 "C0MB31_DLC,CAN0 Mailbox 31 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x200+0x06)++0x07
|
|
line.byte 0x00 "C0MB31_D0,CAN0 Mailbox 31 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB31_D1,CAN0 Mailbox 31 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB31_D2,CAN0 Mailbox 31 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB31_D3,CAN0 Mailbox 31 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB31_D4,CAN0 Mailbox 31 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB31_D5,CAN0 Mailbox 31 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB31_D6,CAN0 Mailbox 31 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB31_D7,CAN0 Mailbox 31 Data byte 7 Register"
|
|
group.word (0x200+0x0e)++0x01
|
|
line.word 0x00 "C0MB31_TS,CAN0 Mailbox 31 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((30.==60.)||(30.==61.)||(30.==62.)||(30.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "C0MB30_ID,CAN0 Mailbox 30 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x210))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C0MB30_ID,CAN0 Mailbox 30 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x210))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C0MB30_ID,CAN0 Mailbox 30 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "C0MB30_ID,CAN0 Mailbox 30 Register"
|
|
endif
|
|
group.word (0x210+0x04)++0x1
|
|
line.word 0x00 "C0MB30_DLC,CAN0 Mailbox 30 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x210+0x06)++0x07
|
|
line.byte 0x00 "C0MB30_D0,CAN0 Mailbox 30 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB30_D1,CAN0 Mailbox 30 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB30_D2,CAN0 Mailbox 30 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB30_D3,CAN0 Mailbox 30 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB30_D4,CAN0 Mailbox 30 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB30_D5,CAN0 Mailbox 30 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB30_D6,CAN0 Mailbox 30 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB30_D7,CAN0 Mailbox 30 Data byte 7 Register"
|
|
group.word (0x210+0x0e)++0x01
|
|
line.word 0x00 "C0MB30_TS,CAN0 Mailbox 30 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((29.==60.)||(29.==61.)||(29.==62.)||(29.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "C0MB29_ID,CAN0 Mailbox 29 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x220))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C0MB29_ID,CAN0 Mailbox 29 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x220))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C0MB29_ID,CAN0 Mailbox 29 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "C0MB29_ID,CAN0 Mailbox 29 Register"
|
|
endif
|
|
group.word (0x220+0x04)++0x1
|
|
line.word 0x00 "C0MB29_DLC,CAN0 Mailbox 29 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x220+0x06)++0x07
|
|
line.byte 0x00 "C0MB29_D0,CAN0 Mailbox 29 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB29_D1,CAN0 Mailbox 29 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB29_D2,CAN0 Mailbox 29 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB29_D3,CAN0 Mailbox 29 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB29_D4,CAN0 Mailbox 29 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB29_D5,CAN0 Mailbox 29 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB29_D6,CAN0 Mailbox 29 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB29_D7,CAN0 Mailbox 29 Data byte 7 Register"
|
|
group.word (0x220+0x0e)++0x01
|
|
line.word 0x00 "C0MB29_TS,CAN0 Mailbox 29 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((28.==60.)||(28.==61.)||(28.==62.)||(28.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "C0MB28_ID,CAN0 Mailbox 28 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x230))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "C0MB28_ID,CAN0 Mailbox 28 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x230))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "C0MB28_ID,CAN0 Mailbox 28 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "C0MB28_ID,CAN0 Mailbox 28 Register"
|
|
endif
|
|
group.word (0x230+0x04)++0x1
|
|
line.word 0x00 "C0MB28_DLC,CAN0 Mailbox 28 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x230+0x06)++0x07
|
|
line.byte 0x00 "C0MB28_D0,CAN0 Mailbox 28 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB28_D1,CAN0 Mailbox 28 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB28_D2,CAN0 Mailbox 28 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB28_D3,CAN0 Mailbox 28 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB28_D4,CAN0 Mailbox 28 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB28_D5,CAN0 Mailbox 28 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB28_D6,CAN0 Mailbox 28 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB28_D7,CAN0 Mailbox 28 Data byte 7 Register"
|
|
group.word (0x230+0x0e)++0x01
|
|
line.word 0x00 "C0MB28_TS,CAN0 Mailbox 28 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((27.==60.)||(27.==61.)||(27.==62.)||(27.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "C0MB27_ID,CAN0 Mailbox 27 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x240))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "C0MB27_ID,CAN0 Mailbox 27 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x240))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "C0MB27_ID,CAN0 Mailbox 27 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "C0MB27_ID,CAN0 Mailbox 27 Register"
|
|
endif
|
|
group.word (0x240+0x04)++0x1
|
|
line.word 0x00 "C0MB27_DLC,CAN0 Mailbox 27 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x240+0x06)++0x07
|
|
line.byte 0x00 "C0MB27_D0,CAN0 Mailbox 27 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB27_D1,CAN0 Mailbox 27 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB27_D2,CAN0 Mailbox 27 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB27_D3,CAN0 Mailbox 27 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB27_D4,CAN0 Mailbox 27 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB27_D5,CAN0 Mailbox 27 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB27_D6,CAN0 Mailbox 27 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB27_D7,CAN0 Mailbox 27 Data byte 7 Register"
|
|
group.word (0x240+0x0e)++0x01
|
|
line.word 0x00 "C0MB27_TS,CAN0 Mailbox 27 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((26.==60.)||(26.==61.)||(26.==62.)||(26.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "C0MB26_ID,CAN0 Mailbox 26 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x250))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "C0MB26_ID,CAN0 Mailbox 26 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x250))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "C0MB26_ID,CAN0 Mailbox 26 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "C0MB26_ID,CAN0 Mailbox 26 Register"
|
|
endif
|
|
group.word (0x250+0x04)++0x1
|
|
line.word 0x00 "C0MB26_DLC,CAN0 Mailbox 26 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x250+0x06)++0x07
|
|
line.byte 0x00 "C0MB26_D0,CAN0 Mailbox 26 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB26_D1,CAN0 Mailbox 26 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB26_D2,CAN0 Mailbox 26 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB26_D3,CAN0 Mailbox 26 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB26_D4,CAN0 Mailbox 26 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB26_D5,CAN0 Mailbox 26 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB26_D6,CAN0 Mailbox 26 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB26_D7,CAN0 Mailbox 26 Data byte 7 Register"
|
|
group.word (0x250+0x0e)++0x01
|
|
line.word 0x00 "C0MB26_TS,CAN0 Mailbox 26 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((25.==60.)||(25.==61.)||(25.==62.)||(25.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "C0MB25_ID,CAN0 Mailbox 25 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x260))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "C0MB25_ID,CAN0 Mailbox 25 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x260))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "C0MB25_ID,CAN0 Mailbox 25 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "C0MB25_ID,CAN0 Mailbox 25 Register"
|
|
endif
|
|
group.word (0x260+0x04)++0x1
|
|
line.word 0x00 "C0MB25_DLC,CAN0 Mailbox 25 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x260+0x06)++0x07
|
|
line.byte 0x00 "C0MB25_D0,CAN0 Mailbox 25 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB25_D1,CAN0 Mailbox 25 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB25_D2,CAN0 Mailbox 25 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB25_D3,CAN0 Mailbox 25 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB25_D4,CAN0 Mailbox 25 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB25_D5,CAN0 Mailbox 25 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB25_D6,CAN0 Mailbox 25 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB25_D7,CAN0 Mailbox 25 Data byte 7 Register"
|
|
group.word (0x260+0x0e)++0x01
|
|
line.word 0x00 "C0MB25_TS,CAN0 Mailbox 25 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((24.==60.)||(24.==61.)||(24.==62.)||(24.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "C0MB24_ID,CAN0 Mailbox 24 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x270))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "C0MB24_ID,CAN0 Mailbox 24 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x270))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "C0MB24_ID,CAN0 Mailbox 24 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "C0MB24_ID,CAN0 Mailbox 24 Register"
|
|
endif
|
|
group.word (0x270+0x04)++0x1
|
|
line.word 0x00 "C0MB24_DLC,CAN0 Mailbox 24 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x270+0x06)++0x07
|
|
line.byte 0x00 "C0MB24_D0,CAN0 Mailbox 24 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB24_D1,CAN0 Mailbox 24 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB24_D2,CAN0 Mailbox 24 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB24_D3,CAN0 Mailbox 24 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB24_D4,CAN0 Mailbox 24 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB24_D5,CAN0 Mailbox 24 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB24_D6,CAN0 Mailbox 24 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB24_D7,CAN0 Mailbox 24 Data byte 7 Register"
|
|
group.word (0x270+0x0e)++0x01
|
|
line.word 0x00 "C0MB24_TS,CAN0 Mailbox 24 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((23.==60.)||(23.==61.)||(23.==62.)||(23.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "C0MB23_ID,CAN0 Mailbox 23 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x280))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "C0MB23_ID,CAN0 Mailbox 23 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x280))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "C0MB23_ID,CAN0 Mailbox 23 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "C0MB23_ID,CAN0 Mailbox 23 Register"
|
|
endif
|
|
group.word (0x280+0x04)++0x1
|
|
line.word 0x00 "C0MB23_DLC,CAN0 Mailbox 23 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x280+0x06)++0x07
|
|
line.byte 0x00 "C0MB23_D0,CAN0 Mailbox 23 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB23_D1,CAN0 Mailbox 23 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB23_D2,CAN0 Mailbox 23 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB23_D3,CAN0 Mailbox 23 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB23_D4,CAN0 Mailbox 23 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB23_D5,CAN0 Mailbox 23 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB23_D6,CAN0 Mailbox 23 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB23_D7,CAN0 Mailbox 23 Data byte 7 Register"
|
|
group.word (0x280+0x0e)++0x01
|
|
line.word 0x00 "C0MB23_TS,CAN0 Mailbox 23 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((22.==60.)||(22.==61.)||(22.==62.)||(22.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "C0MB22_ID,CAN0 Mailbox 22 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x290))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "C0MB22_ID,CAN0 Mailbox 22 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x290))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "C0MB22_ID,CAN0 Mailbox 22 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "C0MB22_ID,CAN0 Mailbox 22 Register"
|
|
endif
|
|
group.word (0x290+0x04)++0x1
|
|
line.word 0x00 "C0MB22_DLC,CAN0 Mailbox 22 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x290+0x06)++0x07
|
|
line.byte 0x00 "C0MB22_D0,CAN0 Mailbox 22 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB22_D1,CAN0 Mailbox 22 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB22_D2,CAN0 Mailbox 22 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB22_D3,CAN0 Mailbox 22 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB22_D4,CAN0 Mailbox 22 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB22_D5,CAN0 Mailbox 22 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB22_D6,CAN0 Mailbox 22 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB22_D7,CAN0 Mailbox 22 Data byte 7 Register"
|
|
group.word (0x290+0x0e)++0x01
|
|
line.word 0x00 "C0MB22_TS,CAN0 Mailbox 22 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((21.==60.)||(21.==61.)||(21.==62.)||(21.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "C0MB21_ID,CAN0 Mailbox 21 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "C0MB21_ID,CAN0 Mailbox 21 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "C0MB21_ID,CAN0 Mailbox 21 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "C0MB21_ID,CAN0 Mailbox 21 Register"
|
|
endif
|
|
group.word (0x2A0+0x04)++0x1
|
|
line.word 0x00 "C0MB21_DLC,CAN0 Mailbox 21 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2A0+0x06)++0x07
|
|
line.byte 0x00 "C0MB21_D0,CAN0 Mailbox 21 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB21_D1,CAN0 Mailbox 21 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB21_D2,CAN0 Mailbox 21 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB21_D3,CAN0 Mailbox 21 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB21_D4,CAN0 Mailbox 21 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB21_D5,CAN0 Mailbox 21 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB21_D6,CAN0 Mailbox 21 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB21_D7,CAN0 Mailbox 21 Data byte 7 Register"
|
|
group.word (0x2A0+0x0e)++0x01
|
|
line.word 0x00 "C0MB21_TS,CAN0 Mailbox 21 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((20.==60.)||(20.==61.)||(20.==62.)||(20.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "C0MB20_ID,CAN0 Mailbox 20 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "C0MB20_ID,CAN0 Mailbox 20 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "C0MB20_ID,CAN0 Mailbox 20 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "C0MB20_ID,CAN0 Mailbox 20 Register"
|
|
endif
|
|
group.word (0x2B0+0x04)++0x1
|
|
line.word 0x00 "C0MB20_DLC,CAN0 Mailbox 20 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2B0+0x06)++0x07
|
|
line.byte 0x00 "C0MB20_D0,CAN0 Mailbox 20 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB20_D1,CAN0 Mailbox 20 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB20_D2,CAN0 Mailbox 20 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB20_D3,CAN0 Mailbox 20 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB20_D4,CAN0 Mailbox 20 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB20_D5,CAN0 Mailbox 20 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB20_D6,CAN0 Mailbox 20 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB20_D7,CAN0 Mailbox 20 Data byte 7 Register"
|
|
group.word (0x2B0+0x0e)++0x01
|
|
line.word 0x00 "C0MB20_TS,CAN0 Mailbox 20 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((19.==60.)||(19.==61.)||(19.==62.)||(19.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "C0MB19_ID,CAN0 Mailbox 19 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "C0MB19_ID,CAN0 Mailbox 19 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "C0MB19_ID,CAN0 Mailbox 19 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "C0MB19_ID,CAN0 Mailbox 19 Register"
|
|
endif
|
|
group.word (0x2C0+0x04)++0x1
|
|
line.word 0x00 "C0MB19_DLC,CAN0 Mailbox 19 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2C0+0x06)++0x07
|
|
line.byte 0x00 "C0MB19_D0,CAN0 Mailbox 19 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB19_D1,CAN0 Mailbox 19 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB19_D2,CAN0 Mailbox 19 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB19_D3,CAN0 Mailbox 19 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB19_D4,CAN0 Mailbox 19 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB19_D5,CAN0 Mailbox 19 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB19_D6,CAN0 Mailbox 19 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB19_D7,CAN0 Mailbox 19 Data byte 7 Register"
|
|
group.word (0x2C0+0x0e)++0x01
|
|
line.word 0x00 "C0MB19_TS,CAN0 Mailbox 19 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((18.==60.)||(18.==61.)||(18.==62.)||(18.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "C0MB18_ID,CAN0 Mailbox 18 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "C0MB18_ID,CAN0 Mailbox 18 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "C0MB18_ID,CAN0 Mailbox 18 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "C0MB18_ID,CAN0 Mailbox 18 Register"
|
|
endif
|
|
group.word (0x2D0+0x04)++0x1
|
|
line.word 0x00 "C0MB18_DLC,CAN0 Mailbox 18 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2D0+0x06)++0x07
|
|
line.byte 0x00 "C0MB18_D0,CAN0 Mailbox 18 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB18_D1,CAN0 Mailbox 18 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB18_D2,CAN0 Mailbox 18 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB18_D3,CAN0 Mailbox 18 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB18_D4,CAN0 Mailbox 18 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB18_D5,CAN0 Mailbox 18 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB18_D6,CAN0 Mailbox 18 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB18_D7,CAN0 Mailbox 18 Data byte 7 Register"
|
|
group.word (0x2D0+0x0e)++0x01
|
|
line.word 0x00 "C0MB18_TS,CAN0 Mailbox 18 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((17.==60.)||(17.==61.)||(17.==62.)||(17.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "C0MB17_ID,CAN0 Mailbox 17 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "C0MB17_ID,CAN0 Mailbox 17 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "C0MB17_ID,CAN0 Mailbox 17 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "C0MB17_ID,CAN0 Mailbox 17 Register"
|
|
endif
|
|
group.word (0x2E0+0x04)++0x1
|
|
line.word 0x00 "C0MB17_DLC,CAN0 Mailbox 17 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2E0+0x06)++0x07
|
|
line.byte 0x00 "C0MB17_D0,CAN0 Mailbox 17 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB17_D1,CAN0 Mailbox 17 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB17_D2,CAN0 Mailbox 17 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB17_D3,CAN0 Mailbox 17 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB17_D4,CAN0 Mailbox 17 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB17_D5,CAN0 Mailbox 17 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB17_D6,CAN0 Mailbox 17 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB17_D7,CAN0 Mailbox 17 Data byte 7 Register"
|
|
group.word (0x2E0+0x0e)++0x01
|
|
line.word 0x00 "C0MB17_TS,CAN0 Mailbox 17 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((16.==60.)||(16.==61.)||(16.==62.)||(16.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "C0MB16_ID,CAN0 Mailbox 16 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "C0MB16_ID,CAN0 Mailbox 16 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x2F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "C0MB16_ID,CAN0 Mailbox 16 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "C0MB16_ID,CAN0 Mailbox 16 Register"
|
|
endif
|
|
group.word (0x2F0+0x04)++0x1
|
|
line.word 0x00 "C0MB16_DLC,CAN0 Mailbox 16 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2F0+0x06)++0x07
|
|
line.byte 0x00 "C0MB16_D0,CAN0 Mailbox 16 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB16_D1,CAN0 Mailbox 16 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB16_D2,CAN0 Mailbox 16 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB16_D3,CAN0 Mailbox 16 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB16_D4,CAN0 Mailbox 16 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB16_D5,CAN0 Mailbox 16 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB16_D6,CAN0 Mailbox 16 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB16_D7,CAN0 Mailbox 16 Data byte 7 Register"
|
|
group.word (0x2F0+0x0e)++0x01
|
|
line.word 0x00 "C0MB16_TS,CAN0 Mailbox 16 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((15.==60.)||(15.==61.)||(15.==62.)||(15.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "C0MB15_ID,CAN0 Mailbox 15 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x300))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "C0MB15_ID,CAN0 Mailbox 15 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x300))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "C0MB15_ID,CAN0 Mailbox 15 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "C0MB15_ID,CAN0 Mailbox 15 Register"
|
|
endif
|
|
group.word (0x300+0x04)++0x1
|
|
line.word 0x00 "C0MB15_DLC,CAN0 Mailbox 15 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x300+0x06)++0x07
|
|
line.byte 0x00 "C0MB15_D0,CAN0 Mailbox 15 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB15_D1,CAN0 Mailbox 15 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB15_D2,CAN0 Mailbox 15 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB15_D3,CAN0 Mailbox 15 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB15_D4,CAN0 Mailbox 15 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB15_D5,CAN0 Mailbox 15 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB15_D6,CAN0 Mailbox 15 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB15_D7,CAN0 Mailbox 15 Data byte 7 Register"
|
|
group.word (0x300+0x0e)++0x01
|
|
line.word 0x00 "C0MB15_TS,CAN0 Mailbox 15 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((14.==60.)||(14.==61.)||(14.==62.)||(14.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "C0MB14_ID,CAN0 Mailbox 14 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x310))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "C0MB14_ID,CAN0 Mailbox 14 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x310))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "C0MB14_ID,CAN0 Mailbox 14 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "C0MB14_ID,CAN0 Mailbox 14 Register"
|
|
endif
|
|
group.word (0x310+0x04)++0x1
|
|
line.word 0x00 "C0MB14_DLC,CAN0 Mailbox 14 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x310+0x06)++0x07
|
|
line.byte 0x00 "C0MB14_D0,CAN0 Mailbox 14 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB14_D1,CAN0 Mailbox 14 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB14_D2,CAN0 Mailbox 14 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB14_D3,CAN0 Mailbox 14 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB14_D4,CAN0 Mailbox 14 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB14_D5,CAN0 Mailbox 14 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB14_D6,CAN0 Mailbox 14 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB14_D7,CAN0 Mailbox 14 Data byte 7 Register"
|
|
group.word (0x310+0x0e)++0x01
|
|
line.word 0x00 "C0MB14_TS,CAN0 Mailbox 14 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((13.==60.)||(13.==61.)||(13.==62.)||(13.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "C0MB13_ID,CAN0 Mailbox 13 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x320))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "C0MB13_ID,CAN0 Mailbox 13 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x320))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "C0MB13_ID,CAN0 Mailbox 13 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "C0MB13_ID,CAN0 Mailbox 13 Register"
|
|
endif
|
|
group.word (0x320+0x04)++0x1
|
|
line.word 0x00 "C0MB13_DLC,CAN0 Mailbox 13 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x320+0x06)++0x07
|
|
line.byte 0x00 "C0MB13_D0,CAN0 Mailbox 13 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB13_D1,CAN0 Mailbox 13 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB13_D2,CAN0 Mailbox 13 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB13_D3,CAN0 Mailbox 13 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB13_D4,CAN0 Mailbox 13 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB13_D5,CAN0 Mailbox 13 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB13_D6,CAN0 Mailbox 13 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB13_D7,CAN0 Mailbox 13 Data byte 7 Register"
|
|
group.word (0x320+0x0e)++0x01
|
|
line.word 0x00 "C0MB13_TS,CAN0 Mailbox 13 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((12.==60.)||(12.==61.)||(12.==62.)||(12.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "C0MB12_ID,CAN0 Mailbox 12 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x330))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "C0MB12_ID,CAN0 Mailbox 12 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x330))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "C0MB12_ID,CAN0 Mailbox 12 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "C0MB12_ID,CAN0 Mailbox 12 Register"
|
|
endif
|
|
group.word (0x330+0x04)++0x1
|
|
line.word 0x00 "C0MB12_DLC,CAN0 Mailbox 12 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x330+0x06)++0x07
|
|
line.byte 0x00 "C0MB12_D0,CAN0 Mailbox 12 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB12_D1,CAN0 Mailbox 12 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB12_D2,CAN0 Mailbox 12 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB12_D3,CAN0 Mailbox 12 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB12_D4,CAN0 Mailbox 12 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB12_D5,CAN0 Mailbox 12 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB12_D6,CAN0 Mailbox 12 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB12_D7,CAN0 Mailbox 12 Data byte 7 Register"
|
|
group.word (0x330+0x0e)++0x01
|
|
line.word 0x00 "C0MB12_TS,CAN0 Mailbox 12 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((11.==60.)||(11.==61.)||(11.==62.)||(11.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "C0MB11_ID,CAN0 Mailbox 11 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x340))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "C0MB11_ID,CAN0 Mailbox 11 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x340))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "C0MB11_ID,CAN0 Mailbox 11 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "C0MB11_ID,CAN0 Mailbox 11 Register"
|
|
endif
|
|
group.word (0x340+0x04)++0x1
|
|
line.word 0x00 "C0MB11_DLC,CAN0 Mailbox 11 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x340+0x06)++0x07
|
|
line.byte 0x00 "C0MB11_D0,CAN0 Mailbox 11 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB11_D1,CAN0 Mailbox 11 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB11_D2,CAN0 Mailbox 11 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB11_D3,CAN0 Mailbox 11 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB11_D4,CAN0 Mailbox 11 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB11_D5,CAN0 Mailbox 11 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB11_D6,CAN0 Mailbox 11 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB11_D7,CAN0 Mailbox 11 Data byte 7 Register"
|
|
group.word (0x340+0x0e)++0x01
|
|
line.word 0x00 "C0MB11_TS,CAN0 Mailbox 11 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((10.==60.)||(10.==61.)||(10.==62.)||(10.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "C0MB10_ID,CAN0 Mailbox 10 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x350))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "C0MB10_ID,CAN0 Mailbox 10 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x350))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "C0MB10_ID,CAN0 Mailbox 10 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "C0MB10_ID,CAN0 Mailbox 10 Register"
|
|
endif
|
|
group.word (0x350+0x04)++0x1
|
|
line.word 0x00 "C0MB10_DLC,CAN0 Mailbox 10 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x350+0x06)++0x07
|
|
line.byte 0x00 "C0MB10_D0,CAN0 Mailbox 10 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB10_D1,CAN0 Mailbox 10 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB10_D2,CAN0 Mailbox 10 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB10_D3,CAN0 Mailbox 10 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB10_D4,CAN0 Mailbox 10 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB10_D5,CAN0 Mailbox 10 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB10_D6,CAN0 Mailbox 10 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB10_D7,CAN0 Mailbox 10 Data byte 7 Register"
|
|
group.word (0x350+0x0e)++0x01
|
|
line.word 0x00 "C0MB10_TS,CAN0 Mailbox 10 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((9.==60.)||(9.==61.)||(9.==62.)||(9.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "C0MB9_ID,CAN0 Mailbox 9 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x360))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "C0MB9_ID,CAN0 Mailbox 9 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x360))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "C0MB9_ID,CAN0 Mailbox 9 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "C0MB9_ID,CAN0 Mailbox 9 Register"
|
|
endif
|
|
group.word (0x360+0x04)++0x1
|
|
line.word 0x00 "C0MB9_DLC,CAN0 Mailbox 9 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x360+0x06)++0x07
|
|
line.byte 0x00 "C0MB9_D0,CAN0 Mailbox 9 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB9_D1,CAN0 Mailbox 9 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB9_D2,CAN0 Mailbox 9 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB9_D3,CAN0 Mailbox 9 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB9_D4,CAN0 Mailbox 9 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB9_D5,CAN0 Mailbox 9 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB9_D6,CAN0 Mailbox 9 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB9_D7,CAN0 Mailbox 9 Data byte 7 Register"
|
|
group.word (0x360+0x0e)++0x01
|
|
line.word 0x00 "C0MB9_TS,CAN0 Mailbox 9 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((8.==60.)||(8.==61.)||(8.==62.)||(8.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "C0MB8_ID,CAN0 Mailbox 8 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x370))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "C0MB8_ID,CAN0 Mailbox 8 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x370))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "C0MB8_ID,CAN0 Mailbox 8 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "C0MB8_ID,CAN0 Mailbox 8 Register"
|
|
endif
|
|
group.word (0x370+0x04)++0x1
|
|
line.word 0x00 "C0MB8_DLC,CAN0 Mailbox 8 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x370+0x06)++0x07
|
|
line.byte 0x00 "C0MB8_D0,CAN0 Mailbox 8 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB8_D1,CAN0 Mailbox 8 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB8_D2,CAN0 Mailbox 8 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB8_D3,CAN0 Mailbox 8 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB8_D4,CAN0 Mailbox 8 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB8_D5,CAN0 Mailbox 8 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB8_D6,CAN0 Mailbox 8 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB8_D7,CAN0 Mailbox 8 Data byte 7 Register"
|
|
group.word (0x370+0x0e)++0x01
|
|
line.word 0x00 "C0MB8_TS,CAN0 Mailbox 8 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((7.==60.)||(7.==61.)||(7.==62.)||(7.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "C0MB7_ID,CAN0 Mailbox 7 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x380))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "C0MB7_ID,CAN0 Mailbox 7 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x380))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "C0MB7_ID,CAN0 Mailbox 7 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "C0MB7_ID,CAN0 Mailbox 7 Register"
|
|
endif
|
|
group.word (0x380+0x04)++0x1
|
|
line.word 0x00 "C0MB7_DLC,CAN0 Mailbox 7 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x380+0x06)++0x07
|
|
line.byte 0x00 "C0MB7_D0,CAN0 Mailbox 7 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB7_D1,CAN0 Mailbox 7 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB7_D2,CAN0 Mailbox 7 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB7_D3,CAN0 Mailbox 7 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB7_D4,CAN0 Mailbox 7 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB7_D5,CAN0 Mailbox 7 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB7_D6,CAN0 Mailbox 7 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB7_D7,CAN0 Mailbox 7 Data byte 7 Register"
|
|
group.word (0x380+0x0e)++0x01
|
|
line.word 0x00 "C0MB7_TS,CAN0 Mailbox 7 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((6.==60.)||(6.==61.)||(6.==62.)||(6.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "C0MB6_ID,CAN0 Mailbox 6 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x390))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "C0MB6_ID,CAN0 Mailbox 6 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x390))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "C0MB6_ID,CAN0 Mailbox 6 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "C0MB6_ID,CAN0 Mailbox 6 Register"
|
|
endif
|
|
group.word (0x390+0x04)++0x1
|
|
line.word 0x00 "C0MB6_DLC,CAN0 Mailbox 6 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x390+0x06)++0x07
|
|
line.byte 0x00 "C0MB6_D0,CAN0 Mailbox 6 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB6_D1,CAN0 Mailbox 6 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB6_D2,CAN0 Mailbox 6 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB6_D3,CAN0 Mailbox 6 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB6_D4,CAN0 Mailbox 6 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB6_D5,CAN0 Mailbox 6 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB6_D6,CAN0 Mailbox 6 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB6_D7,CAN0 Mailbox 6 Data byte 7 Register"
|
|
group.word (0x390+0x0e)++0x01
|
|
line.word 0x00 "C0MB6_TS,CAN0 Mailbox 6 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((5.==60.)||(5.==61.)||(5.==62.)||(5.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "C0MB5_ID,CAN0 Mailbox 5 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "C0MB5_ID,CAN0 Mailbox 5 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "C0MB5_ID,CAN0 Mailbox 5 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "C0MB5_ID,CAN0 Mailbox 5 Register"
|
|
endif
|
|
group.word (0x3A0+0x04)++0x1
|
|
line.word 0x00 "C0MB5_DLC,CAN0 Mailbox 5 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3A0+0x06)++0x07
|
|
line.byte 0x00 "C0MB5_D0,CAN0 Mailbox 5 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB5_D1,CAN0 Mailbox 5 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB5_D2,CAN0 Mailbox 5 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB5_D3,CAN0 Mailbox 5 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB5_D4,CAN0 Mailbox 5 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB5_D5,CAN0 Mailbox 5 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB5_D6,CAN0 Mailbox 5 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB5_D7,CAN0 Mailbox 5 Data byte 7 Register"
|
|
group.word (0x3A0+0x0e)++0x01
|
|
line.word 0x00 "C0MB5_TS,CAN0 Mailbox 5 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((4.==60.)||(4.==61.)||(4.==62.)||(4.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "C0MB4_ID,CAN0 Mailbox 4 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "C0MB4_ID,CAN0 Mailbox 4 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "C0MB4_ID,CAN0 Mailbox 4 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "C0MB4_ID,CAN0 Mailbox 4 Register"
|
|
endif
|
|
group.word (0x3B0+0x04)++0x1
|
|
line.word 0x00 "C0MB4_DLC,CAN0 Mailbox 4 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3B0+0x06)++0x07
|
|
line.byte 0x00 "C0MB4_D0,CAN0 Mailbox 4 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB4_D1,CAN0 Mailbox 4 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB4_D2,CAN0 Mailbox 4 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB4_D3,CAN0 Mailbox 4 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB4_D4,CAN0 Mailbox 4 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB4_D5,CAN0 Mailbox 4 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB4_D6,CAN0 Mailbox 4 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB4_D7,CAN0 Mailbox 4 Data byte 7 Register"
|
|
group.word (0x3B0+0x0e)++0x01
|
|
line.word 0x00 "C0MB4_TS,CAN0 Mailbox 4 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((3.==60.)||(3.==61.)||(3.==62.)||(3.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "C0MB3_ID,CAN0 Mailbox 3 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "C0MB3_ID,CAN0 Mailbox 3 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "C0MB3_ID,CAN0 Mailbox 3 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "C0MB3_ID,CAN0 Mailbox 3 Register"
|
|
endif
|
|
group.word (0x3C0+0x04)++0x1
|
|
line.word 0x00 "C0MB3_DLC,CAN0 Mailbox 3 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3C0+0x06)++0x07
|
|
line.byte 0x00 "C0MB3_D0,CAN0 Mailbox 3 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB3_D1,CAN0 Mailbox 3 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB3_D2,CAN0 Mailbox 3 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB3_D3,CAN0 Mailbox 3 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB3_D4,CAN0 Mailbox 3 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB3_D5,CAN0 Mailbox 3 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB3_D6,CAN0 Mailbox 3 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB3_D7,CAN0 Mailbox 3 Data byte 7 Register"
|
|
group.word (0x3C0+0x0e)++0x01
|
|
line.word 0x00 "C0MB3_TS,CAN0 Mailbox 3 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((2.==60.)||(2.==61.)||(2.==62.)||(2.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "C0MB2_ID,CAN0 Mailbox 2 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "C0MB2_ID,CAN0 Mailbox 2 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "C0MB2_ID,CAN0 Mailbox 2 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "C0MB2_ID,CAN0 Mailbox 2 Register"
|
|
endif
|
|
group.word (0x3D0+0x04)++0x1
|
|
line.word 0x00 "C0MB2_DLC,CAN0 Mailbox 2 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3D0+0x06)++0x07
|
|
line.byte 0x00 "C0MB2_D0,CAN0 Mailbox 2 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB2_D1,CAN0 Mailbox 2 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB2_D2,CAN0 Mailbox 2 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB2_D3,CAN0 Mailbox 2 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB2_D4,CAN0 Mailbox 2 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB2_D5,CAN0 Mailbox 2 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB2_D6,CAN0 Mailbox 2 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB2_D7,CAN0 Mailbox 2 Data byte 7 Register"
|
|
group.word (0x3D0+0x0e)++0x01
|
|
line.word 0x00 "C0MB2_TS,CAN0 Mailbox 2 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((1.==60.)||(1.==61.)||(1.==62.)||(1.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "C0MB1_ID,CAN0 Mailbox 1 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "C0MB1_ID,CAN0 Mailbox 1 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "C0MB1_ID,CAN0 Mailbox 1 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "C0MB1_ID,CAN0 Mailbox 1 Register"
|
|
endif
|
|
group.word (0x3E0+0x04)++0x1
|
|
line.word 0x00 "C0MB1_DLC,CAN0 Mailbox 1 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3E0+0x06)++0x07
|
|
line.byte 0x00 "C0MB1_D0,CAN0 Mailbox 1 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB1_D1,CAN0 Mailbox 1 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB1_D2,CAN0 Mailbox 1 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB1_D3,CAN0 Mailbox 1 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB1_D4,CAN0 Mailbox 1 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB1_D5,CAN0 Mailbox 1 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB1_D6,CAN0 Mailbox 1 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB1_D7,CAN0 Mailbox 1 Data byte 7 Register"
|
|
group.word (0x3E0+0x0e)++0x01
|
|
line.word 0x00 "C0MB1_TS,CAN0 Mailbox 1 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((0.==60.)||(0.==61.)||(0.==62.)||(0.==63.))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "C0MB0_ID,CAN0 Mailbox 0 Register"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x0))
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "C0MB0_ID,CAN0 Mailbox 0 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD0000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD0000+0x3F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD0000+0x840))&0x6)==0x2))
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "C0MB0_ID,CAN0 Mailbox 0 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "C0MB0_ID,CAN0 Mailbox 0 Register"
|
|
endif
|
|
group.word (0x3F0+0x04)++0x1
|
|
line.word 0x00 "C0MB0_DLC,CAN0 Mailbox 0 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3F0+0x06)++0x07
|
|
line.byte 0x00 "C0MB0_D0,CAN0 Mailbox 0 Data byte 0 Register"
|
|
line.byte 0x01 "C0MB0_D1,CAN0 Mailbox 0 Data byte 1 Register"
|
|
line.byte 0x02 "C0MB0_D2,CAN0 Mailbox 0 Data byte 2 Register"
|
|
line.byte 0x03 "C0MB0_D3,CAN0 Mailbox 0 Data byte 3 Register"
|
|
line.byte 0x04 "C0MB0_D4,CAN0 Mailbox 0 Data byte 4 Register"
|
|
line.byte 0x05 "C0MB0_D5,CAN0 Mailbox 0 Data byte 5 Register"
|
|
line.byte 0x06 "C0MB0_D6,CAN0 Mailbox 0 Data byte 6 Register"
|
|
line.byte 0x07 "C0MB0_D7,CAN0 Mailbox 0 Data byte 7 Register"
|
|
group.word (0x3F0+0x0e)++0x01
|
|
line.word 0x00 "C0MB0_TS,CAN0 Mailbox 0 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
tree.end
|
|
if (((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.long 0x42c++0x03
|
|
line.long 0x0 "C0MIER1,CAN0 Mailbox Interrupt Enable Register 1"
|
|
bitfld.long 0x00 31. " MB63 ,Mailbox 63 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB62 ,Mailbox 62 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB61 ,Mailbox 61 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB60 ,Mailbox 60 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MB59 ,Mailbox 59 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB58 ,Mailbox 58 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB57 ,Mailbox 57 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB56 ,Mailbox 56 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB55 ,Mailbox 55 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB54 ,Mailbox 54 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB53 ,Mailbox 53 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB52 ,Mailbox 52 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB51 ,Mailbox 51 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB50 ,Mailbox 50 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB49 ,Mailbox 49 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB48 ,Mailbox 48 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB47 ,Mailbox 47 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB46 ,Mailbox 46 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB45 ,Mailbox 45 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB44 ,Mailbox 44 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB43 ,Mailbox 43 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB42 ,Mailbox 42 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB41 ,Mailbox 41 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB40 ,Mailbox 40 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB39 ,Mailbox 39 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB38 ,Mailbox 38 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB37 ,Mailbox 37 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB36 ,Mailbox 36 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB35 ,Mailbox 35 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB34 ,Mailbox 34 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB33 ,Mailbox 33 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB32 ,Mailbox 32 Interrupt enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42c++0x03
|
|
line.long 0x0 "C0MR1,CAN0 Mailbox Interrupt Enable Register 1"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 29. " MB61 ,Receive FIFO Interrupt Generation Timing Control" "Every time,Buffer warning"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB60 ,Receive FIFO Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB57 ,Transmit FIFO Interrupt Generation Timing Control" "Every time,Buffer warning"
|
|
bitfld.long 0x00 24. " MB56 ,Transmit FIFO Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " MB55 ,Mailbox 55 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB54 ,Mailbox 54 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB53 ,Mailbox 53 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB52 ,Mailbox 52 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB51 ,Mailbox 51 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB50 ,Mailbox 50 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB49 ,Mailbox 49 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB48 ,Mailbox 48 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB47 ,Mailbox 47 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB46 ,Mailbox 46 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB45 ,Mailbox 45 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB44 ,Mailbox 44 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB43 ,Mailbox 43 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB42 ,Mailbox 42 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB41 ,Mailbox 41 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB40 ,Mailbox 40 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB39 ,Mailbox 39 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB38 ,Mailbox 38 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB37 ,Mailbox 37 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB36 ,Mailbox 36 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB35 ,Mailbox 35 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB34 ,Mailbox 34 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB33 ,Mailbox 33 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB32 ,Mailbox 32 Interrupt enabled" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x43c++0x03
|
|
line.long 0x0 "C0MIER0,CAN0 Mailbox Interrupt Enable Register 0"
|
|
bitfld.long 0x00 31. " MB31IE ,Mailbox 31 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB30IE ,Mailbox 30 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB29IE ,Mailbox 29 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB28IE ,Mailbox 28 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MB27IE ,Mailbox 27 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB26IE ,Mailbox 26 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB25IE ,Mailbox 25 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB24IE ,Mailbox 24 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB23IE ,Mailbox 23 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB22IE ,Mailbox 22 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB21IE ,Mailbox 21 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20IE ,Mailbox 20 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19IE ,Mailbox 19 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB18IE ,Mailbox 18 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17IE ,Mailbox 17 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB16IE ,Mailbox 16 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB15IE ,Mailbox 15 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14IE ,Mailbox 14 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB13IE ,Mailbox 13 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB12IE ,Mailbox 12 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB11IE ,Mailbox 11 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB10IE ,Mailbox 10 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB9IE ,Mailbox 9 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8IE ,Mailbox 8 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7IE ,Mailbox 7 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB6IE ,Mailbox 6 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5IE ,Mailbox 5 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB4IE ,Mailbox 4 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB3IE ,Mailbox 3 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2IE ,Mailbox 2 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB1IE ,Mailbox 1 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB0IE ,Mailbox 0 Interrupt enabled" "Disabled,Enabled"
|
|
tree "Message Control Registers"
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x0))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL63,CAN0 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x0))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL63,CAN0 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x0))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL63,CAN0 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x0)++0x0
|
|
hide.byte 0x00 "C0MCTL63,CAN0 Message Control Register 63"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x1))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL62,CAN0 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x1))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL62,CAN0 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x1))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL62,CAN0 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x1)++0x0
|
|
hide.byte 0x00 "C0MCTL62,CAN0 Message Control Register 62"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x2))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL61,CAN0 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x2))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL61,CAN0 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x2))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL61,CAN0 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x2)++0x0
|
|
hide.byte 0x00 "C0MCTL61,CAN0 Message Control Register 61"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x3))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL60,CAN0 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x3))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL60,CAN0 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x3))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL60,CAN0 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x3)++0x0
|
|
hide.byte 0x00 "C0MCTL60,CAN0 Message Control Register 60"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x4))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL59,CAN0 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x4))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL59,CAN0 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x4))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL59,CAN0 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x4)++0x0
|
|
hide.byte 0x00 "C0MCTL59,CAN0 Message Control Register 59"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x5))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL58,CAN0 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x5))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL58,CAN0 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x5))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL58,CAN0 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x5)++0x0
|
|
hide.byte 0x00 "C0MCTL58,CAN0 Message Control Register 58"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x6))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL57,CAN0 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x6))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL57,CAN0 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x6))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL57,CAN0 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x6)++0x0
|
|
hide.byte 0x00 "C0MCTL57,CAN0 Message Control Register 57"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x800+0x7))&0xc0)==0x40)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL56,CAN0 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x7))&0xc0)==0x80)&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL56,CAN0 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x800+0x7))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD0000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL56,CAN0 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x7)++0x0
|
|
hide.byte 0x00 "C0MCTL56,CAN0 Message Control Register 56"
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x0))&0xc0)==0x40)
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL55,CAN0 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x0))&0xc0)==0x80)
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL55,CAN0 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C0MCTL55,CAN0 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x1))&0xc0)==0x40)
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL54,CAN0 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x1))&0xc0)==0x80)
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL54,CAN0 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C0MCTL54,CAN0 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x2))&0xc0)==0x40)
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL53,CAN0 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x2))&0xc0)==0x80)
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL53,CAN0 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C0MCTL53,CAN0 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x3))&0xc0)==0x40)
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL52,CAN0 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x3))&0xc0)==0x80)
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL52,CAN0 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C0MCTL52,CAN0 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x4))&0xc0)==0x40)
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL51,CAN0 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x4))&0xc0)==0x80)
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL51,CAN0 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C0MCTL51,CAN0 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x5))&0xc0)==0x40)
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL50,CAN0 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x5))&0xc0)==0x80)
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL50,CAN0 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C0MCTL50,CAN0 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x6))&0xc0)==0x40)
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL49,CAN0 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x6))&0xc0)==0x80)
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL49,CAN0 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C0MCTL49,CAN0 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x7))&0xc0)==0x40)
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL48,CAN0 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x7))&0xc0)==0x80)
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL48,CAN0 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C0MCTL48,CAN0 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x8))&0xc0)==0x40)
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C0MCTL47,CAN0 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x8))&0xc0)==0x80)
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C0MCTL47,CAN0 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C0MCTL47,CAN0 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x9))&0xc0)==0x40)
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C0MCTL46,CAN0 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x9))&0xc0)==0x80)
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C0MCTL46,CAN0 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C0MCTL46,CAN0 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xA))&0xc0)==0x40)
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C0MCTL45,CAN0 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xA))&0xc0)==0x80)
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C0MCTL45,CAN0 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C0MCTL45,CAN0 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xB))&0xc0)==0x40)
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C0MCTL44,CAN0 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xB))&0xc0)==0x80)
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C0MCTL44,CAN0 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C0MCTL44,CAN0 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xC))&0xc0)==0x40)
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C0MCTL43,CAN0 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xC))&0xc0)==0x80)
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C0MCTL43,CAN0 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C0MCTL43,CAN0 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xD))&0xc0)==0x40)
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C0MCTL42,CAN0 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xD))&0xc0)==0x80)
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C0MCTL42,CAN0 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C0MCTL42,CAN0 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xE))&0xc0)==0x40)
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C0MCTL41,CAN0 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xE))&0xc0)==0x80)
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C0MCTL41,CAN0 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C0MCTL41,CAN0 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0xF))&0xc0)==0x40)
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C0MCTL40,CAN0 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0xF))&0xc0)==0x80)
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C0MCTL40,CAN0 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C0MCTL40,CAN0 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x10))&0xc0)==0x40)
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C0MCTL39,CAN0 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x10))&0xc0)==0x80)
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C0MCTL39,CAN0 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C0MCTL39,CAN0 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x11))&0xc0)==0x40)
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C0MCTL38,CAN0 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x11))&0xc0)==0x80)
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C0MCTL38,CAN0 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C0MCTL38,CAN0 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x12))&0xc0)==0x40)
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C0MCTL37,CAN0 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x12))&0xc0)==0x80)
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C0MCTL37,CAN0 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C0MCTL37,CAN0 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x13))&0xc0)==0x40)
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C0MCTL36,CAN0 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x13))&0xc0)==0x80)
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C0MCTL36,CAN0 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C0MCTL36,CAN0 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x14))&0xc0)==0x40)
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C0MCTL35,CAN0 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x14))&0xc0)==0x80)
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C0MCTL35,CAN0 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C0MCTL35,CAN0 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x15))&0xc0)==0x40)
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C0MCTL34,CAN0 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x15))&0xc0)==0x80)
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C0MCTL34,CAN0 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C0MCTL34,CAN0 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x16))&0xc0)==0x40)
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C0MCTL33,CAN0 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x16))&0xc0)==0x80)
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C0MCTL33,CAN0 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C0MCTL33,CAN0 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD0000+0x808+0x17))&0xc0)==0x40)
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C0MCTL32,CAN0 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD0000+0x808+0x17))&0xc0)==0x80)
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C0MCTL32,CAN0 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C0MCTL32,CAN0 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
group.byte 0x820++0x1f
|
|
line.byte 0x0 "C0MCTL31,CAN0 Message Control Register 31"
|
|
bitfld.byte 0x0 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x0 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x0 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1 "C0MCTL30,CAN0 Message Control Register 30"
|
|
bitfld.byte 0x1 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x2 "C0MCTL29,CAN0 Message Control Register 29"
|
|
bitfld.byte 0x2 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x2 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x2 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x2 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x3 "C0MCTL28,CAN0 Message Control Register 28"
|
|
bitfld.byte 0x3 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x3 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x3 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x3 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x4 "C0MCTL27,CAN0 Message Control Register 27"
|
|
bitfld.byte 0x4 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x4 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x4 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x4 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x5 "C0MCTL26,CAN0 Message Control Register 26"
|
|
bitfld.byte 0x5 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x5 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x5 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x5 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x6 "C0MCTL25,CAN0 Message Control Register 25"
|
|
bitfld.byte 0x6 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x6 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x6 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x6 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x7 "C0MCTL24,CAN0 Message Control Register 24"
|
|
bitfld.byte 0x7 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x7 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x7 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x7 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x8 "C0MCTL23,CAN0 Message Control Register 23"
|
|
bitfld.byte 0x8 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x8 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x8 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x8 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x9 "C0MCTL22,CAN0 Message Control Register 22"
|
|
bitfld.byte 0x9 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x9 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x9 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x9 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xA "C0MCTL21,CAN0 Message Control Register 21"
|
|
bitfld.byte 0xA 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xA 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xA 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xA 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xB "C0MCTL20,CAN0 Message Control Register 20"
|
|
bitfld.byte 0xB 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xB 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xB 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xB 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xC "C0MCTL19,CAN0 Message Control Register 19"
|
|
bitfld.byte 0xC 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xC 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xC 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xC 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xD "C0MCTL18,CAN0 Message Control Register 18"
|
|
bitfld.byte 0xD 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xD 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xD 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xD 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xE "C0MCTL17,CAN0 Message Control Register 17"
|
|
bitfld.byte 0xE 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xE 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xE 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xE 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xF "C0MCTL16,CAN0 Message Control Register 16"
|
|
bitfld.byte 0xF 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xF 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xF 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xF 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x10 "C0MCTL15,CAN0 Message Control Register 15"
|
|
bitfld.byte 0x10 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x10 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x10 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x10 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x11 "C0MCTL14,CAN0 Message Control Register 14"
|
|
bitfld.byte 0x11 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x11 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x11 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x11 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x12 "C0MCTL13,CAN0 Message Control Register 13"
|
|
bitfld.byte 0x12 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x12 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x12 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x12 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x13 "C0MCTL12,CAN0 Message Control Register 12"
|
|
bitfld.byte 0x13 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x13 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x13 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x13 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x14 "C0MCTL11,CAN0 Message Control Register 11"
|
|
bitfld.byte 0x14 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x14 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x14 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x14 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x15 "C0MCTL10,CAN0 Message Control Register 10"
|
|
bitfld.byte 0x15 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x15 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x15 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x15 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x16 "C0MCTL9,CAN0 Message Control Register 9"
|
|
bitfld.byte 0x16 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x16 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x16 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x16 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x17 "C0MCTL8,CAN0 Message Control Register 8"
|
|
bitfld.byte 0x17 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x17 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x17 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x17 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x18 "C0MCTL7,CAN0 Message Control Register 7"
|
|
bitfld.byte 0x18 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x18 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x18 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x18 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x19 "C0MCTL6,CAN0 Message Control Register 6"
|
|
bitfld.byte 0x19 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x19 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x19 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x19 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1A "C0MCTL5,CAN0 Message Control Register 5"
|
|
bitfld.byte 0x1A 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1A 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1A 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1A 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1B "C0MCTL4,CAN0 Message Control Register 4"
|
|
bitfld.byte 0x1B 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1B 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1B 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1B 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1C "C0MCTL3,CAN0 Message Control Register 3"
|
|
bitfld.byte 0x1C 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1C 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1C 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1C 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1D "C0MCTL2,CAN0 Message Control Register 2"
|
|
bitfld.byte 0x1D 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1D 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1D 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1D 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1E "C0MCTL1,CAN0 Message Control Register 1"
|
|
bitfld.byte 0x1E 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1E 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1E 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1E 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1F "C0MCTL0,CAN0 Message Control Register 0"
|
|
bitfld.byte 0x1F 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1F 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1F 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1F 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
tree.end
|
|
group.byte 0x848++0x0
|
|
line.byte 0x0 "C0RFCR,CAN0 Receive FIFO Control Register"
|
|
bitfld.byte 0x00 7. " RFEST ,Receive FIFO Empty Status" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RFWST ,Receive FIFO Buffer Warning Status" "Not warning,Warning"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RFFST ,Receive FIFO Full Status" "Not full,Full"
|
|
bitfld.byte 0x00 4. " RFMLF ,Receive FIFO Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--3. " RFUST ,Receive FIFO Unread Message Number Status" "0,1,2,3,4,?..."
|
|
bitfld.byte 0x00 0. " RFE ,Receive FIFO Enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xFFFD0000+0x848))&0x1)==0x00)
|
|
rgroup.byte 0x849++0x0
|
|
line.byte 0x0 "C0RFPCR,CAN0 Receive FIFO Pointer Control Register"
|
|
else
|
|
group.byte 0x849++0x0
|
|
line.byte 0x0 "C0RFPCR,CAN0 Receive FIFO Pointer Control Register"
|
|
endif
|
|
group.byte 0x84a++0x0
|
|
line.byte 0x0 "C0TFCR,CAN0 Transmit FIFO Control Register"
|
|
bitfld.byte 0x00 7. " TFEST ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " TFFST ,Transmit FIFO Full Status" "Not full,Full"
|
|
bitfld.byte 0x00 1.--3. " TFUST ,Transmit FIFO Unsent Message Number Status" "0,1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TFE ,Transmit FIFO Enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xFFFD0000+0x84a))&0x1)==0x00)
|
|
rgroup.byte 0x84b++0x0
|
|
line.byte 0x0 "C0TFPCR,CAN0 Transmit FIFO Pointer Control Register"
|
|
else
|
|
group.byte 0x84b++0x0
|
|
line.byte 0x0 "C0TFPCR,CAN0 Transmit FIFO Pointer Control Register"
|
|
endif
|
|
rgroup.word 0x842++0x01
|
|
line.word 0x0 "C0STR,CAN0 Status Register"
|
|
bitfld.word 0x00 14. " RECST ,Receive Status Flag" "Idle/transmission,Reception"
|
|
textline " "
|
|
bitfld.word 0x00 13. " TRMST ,Transmit Status Flag" "Idle/reception,Transmission/bus-off"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BOST ,Bus-Off Status Flag" "Not bus-off,Bus-off"
|
|
bitfld.word 0x00 11. " EPST ,Error-Passive Status Flag" "Not error-passive,Error-passive"
|
|
bitfld.word 0x00 10. " SLPST ,CAN Sleep Status Flag" "Not CAN sleep,CAN sleep"
|
|
textline " "
|
|
bitfld.word 0x00 9. " HLTST ,CAN Halt Status Flag" "Not CAN halt,CAN halt"
|
|
bitfld.word 0x00 8. " RSTST ,CAN Reset Status Flag" "Not CAN reset,CAN reset"
|
|
bitfld.word 0x00 7. " EST ,Error Status Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TABST ,Transmission Abort Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " FMLST ,FIFO Mailbox Message Lost Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " NMLST ,Normal Mailbox Message Lost Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TFST ,Transmit FIFO Status Flag" "Full,Not full"
|
|
bitfld.word 0x00 2. " RFST ,Receive FIFO Status Flag" "Empty,Not empty"
|
|
bitfld.word 0x00 1. " SDST ,SENTDATA Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " NDST ,NEWDATA Status Flag" "Not occurred,Occurred"
|
|
wgroup.byte 0x851++0x00
|
|
line.byte 0x0 "C0CSSR,CAN0 Channel Search Support Register"
|
|
rgroup.byte 0x852++0x00
|
|
line.byte 0x0 "C0MSSR,CAN0 Mailbox Search Status Register"
|
|
bitfld.byte 0x00 7. " SEST ,Search Result Status" "Found,Not found"
|
|
bitfld.byte 0x00 0.--5. " MBNST ,Search Result Mailbox Number Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x853++0x00
|
|
line.byte 0x0 "C0MSMR,CAN0 Mailbox Search Mode Register"
|
|
bitfld.byte 0x00 0.--1. " MBSM ,Mailbox Search Mode Select" "Receive,Transmit,Message lost,Channel"
|
|
group.word 0x856++0x01
|
|
line.word 0x0 "C0AFSR,CAN0 Acceptance Filter Support Register"
|
|
group.byte 0x84c++0x01
|
|
line.byte 0x0 "C0EIER,CAN0 Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BLIE ,Bus Lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " OLIE ,Overload Frame Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ORIE ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BORIE ,Bus-Off Recovery Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BOEIE ,Bus-Off Entry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EPIE ,Error-Passive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EWIE ,Error-Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "C0EIFR,CAN0 Error Interrupt Factor Judge Register"
|
|
bitfld.byte 0x01 7. " BLIF ,Bus Lock Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " OLIF ,Overload Frame Transmission Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 5. " ORIF ,Receive Overrun Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " BORIF ,Bus-Off Recovery Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 3. " BOEIF ,Bus-Off Entry Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 2. " EPIF ,Error Passive Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " EWIF ,Error Warning Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " BEIF ,Bus Error Detect Flag" "Not detected,Detected"
|
|
rgroup.byte 0x84e++0x01
|
|
line.byte 0x0 "C0RECR,CAN0 Receive Error Count Register"
|
|
line.byte 0x1 "C0TECR,CAN0 Transmit Error Count Register"
|
|
group.byte 0x850++0x00
|
|
line.byte 0x0 "C0ECSR,CAN0 Error Code Store Register"
|
|
bitfld.byte 0x0 7. " EDPM ,Error Display Mode Select" "First detected error,Accumulated error"
|
|
textline " "
|
|
bitfld.byte 0x0 6. " ADEF ,ACK Delimiter Error Flag" "No ACK delimiter,ACK delimiter"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " BE0F ,Bit Error (dominant) Flag" "No error,Error"
|
|
bitfld.byte 0x0 4. " BE1F ,Bit Error (recessive) Flag" "No error,Error"
|
|
bitfld.byte 0x0 3. " CEF ,CRC Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " AEF ,ACK Error Flag" "No error,Error"
|
|
bitfld.byte 0x0 1. " FEF ,Form Error Flag" "No error,Error"
|
|
bitfld.byte 0x0 0. " SEF ,Stuff Error Flag" "No error,Error"
|
|
rgroup.word 0x854++0x01
|
|
line.word 0x0 "C0TSR,CAN0 Time Stamp Register"
|
|
group.byte 0x858++0x00
|
|
line.byte 0x0 "C0TCR,CAN0 Test Control Register"
|
|
bitfld.byte 0x0 1.--2. " TSTM ,CAN Test Mode Select" "Other,Listen-only,External loop back,Internal loop back"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " TSTE ,CAN Test Mode Enable" "Disabled,Enabled"
|
|
group.byte 0x860++0x01
|
|
line.byte 0x0 "C0IER,CAN0 Interrupt Enable Register"
|
|
bitfld.byte 0x0 5. " ERSIE ,Error (ERS) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " RXFIE ,Reception FIFO (RXF) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 3. " TXFIE ,Transmission FIFO (TXF) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " RXM0IE ,Mailbox 0 Successful Reception (RXM0) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " RXM1IE ,Mailbox 1 to 63 Successful Reception (RXM1) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " TXMIE ,Mailbox 32 to 63 Successful Transmission (TXM) Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "C0ISR,CAN0 Interrupt Status Register"
|
|
bitfld.byte 0x01 5. " ERSF ,Error (ERS) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 4. " RXFF ,Reception FIFO (RXF) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 3. " TXFF ,Transmission FIFO (TXF) Interrupt Status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " RXM0F ,Mailbox 0 Successful Reception (RXM0) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 1. " RXM1F ,Mailbox 1 to 63 Successful Reception (RXM1) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " TXMF ,Mailbox 32 to 63 Successful Transmission (TXM) Interrupt Status" "Not detected,Detected"
|
|
group.byte 0x863++0x00
|
|
line.byte 0x0 "C0MBSMR,CAN0 Mailbox Search Mask Register"
|
|
bitfld.byte 0x0 0. " MB0SM ,Mailbox 0 Search Mask" "Not masked,Masked"
|
|
sif cpu()=="R8A7792X"
|
|
group.byte 0x85C++0x00
|
|
line.byte 0x00 "C0PECR,CAN0 Parity Error Control Register"
|
|
bitfld.byte 0x00 7. " PF ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " PIE ,Parity Error Interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PME ,Parity Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " PM ,Parity Mode" "Operation Mode,Halt mode"
|
|
group.word 0x85E++0x01
|
|
line.word 0x00 "C0PEACR,CAN0 Parity Error Address Capture Register"
|
|
hexmask.word 0x00 0.--10. 1. " PA ,Parity Error Captured Address Bits"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFFD1000
|
|
width 12.
|
|
group.word 0x840++0x01
|
|
line.word 0x00 "C1CTLR,CAN1 Control Register"
|
|
bitfld.word 0x00 13. " RBOC ,Forcible Return From Bus-OFF" "No effect,Force return"
|
|
textline " "
|
|
bitfld.word 0x00 11.--12. " BOM ,Bus-Off Recovery Mode" "Normal,Halt at Bus-off entry,Halt at Bus-off end,Halt by Program request"
|
|
textline " "
|
|
bitfld.word 0x00 10. " SLPM ,CAN Sleep Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CANM ,CAN Operating Mode Select" "Operation,Reset,Halt,Force reset"
|
|
bitfld.word 0x00 6.--7. " TSPS ,Time Stamp Prescaler Select" "1,2,4,8"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TSRC ,Time Stamp Counter Reset Command" "No effect,Reset"
|
|
bitfld.word 0x00 4. " TPM ,Transmission Priority Mode Select" "ID,Mailbox"
|
|
bitfld.word 0x00 3. " MLM ,Message Lost Mode Select" "Overwrite,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " IDFM ,ID Format Mode Select" "Standard,Extended,Mixed,?..."
|
|
bitfld.word 0x00 0. " MBM ,CAN Mailbox Mode Select" "Normal,FIFO"
|
|
group.byte 0x847++0x00
|
|
line.byte 0x00 "C1CLKR,CAN1 Clock Select Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A7792X")
|
|
bitfld.byte 0x00 0.--1. " CCLKS ,CAN Clock Source Select" "Peripheral 1,Peripheral 2,,External"
|
|
else
|
|
bitfld.byte 0x00 0. " CCLKS ,CAN Clock Source Select" "Peripheral,Main"
|
|
endif
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "C1BCR,CAN1 Bit Configuration Register"
|
|
bitfld.long 0x00 28.--31. " TSEG1 ,Time Segment 1 Control Bits" ",,,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq,9 Tq,10 Tq,11 Tq,12 Tq,13 Tq,14 Tq,15 Tq,16 Tq"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Prescaler Division Ratio"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SJW ,Resynchronization Jump Width Control" "1 Tq,2 Tq,3 Tq,4 Tq"
|
|
bitfld.long 0x00 8.--10. " TSEG2 ,Time Segment 2 Control" ",2 Tq,3 Tq,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq"
|
|
if (((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0)
|
|
group.long 0x430++0x07
|
|
line.long 0x0 "C1MKR0,CAN1 Mask Register 0"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
line.long 0x4 "C1MKR1,CAN1 Mask Register 1"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x0 "C1MKR2,CAN1 Mask Register 2"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x4 "C1MKR3,CAN1 Mask Register 3"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x8 "C1MKR4,CAN1 Mask Register 4"
|
|
bitfld.long 0x8 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x8 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x8 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x8 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x8 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x8 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x8 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x8 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x8 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x8 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x8 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0xC "C1MKR5,CAN1 Mask Register 5"
|
|
bitfld.long 0xC 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0xC 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0xC 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0xC 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0xC 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0xC 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0xC 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0xC 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0xC 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0xC 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0xC 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x10 "C1MKR6,CAN1 Mask Register 6"
|
|
bitfld.long 0x10 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x10 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x10 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x10 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x10 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x10 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x10 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x10 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x10 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x10 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x10 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x14 "C1MKR7,CAN1 Mask Register 7"
|
|
bitfld.long 0x14 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x14 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x14 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x14 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x14 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x14 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x14 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x14 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x14 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x14 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x14 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x18 "C1MKR8,CAN1 Mask Register 8"
|
|
bitfld.long 0x18 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x18 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x18 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x18 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x18 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x18 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x18 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x18 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x18 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x18 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x18 18. ",Standard ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x1C "C1MKR9,CAN1 Mask Register 9"
|
|
bitfld.long 0x1C 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 18. ",Standard ID Bit 0" "0,1"
|
|
elif ((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2)||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4))
|
|
group.long 0x430++0x07
|
|
line.long 0x0 "C1MKR0,CAN1 Mask Register 0"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x0 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x0 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x0 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x0 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x0 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x0 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x0 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x0 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x0 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x0 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x0 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x0 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x0 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x0 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x0 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x0 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x0 0. ",Extended ID Bit 0" "0,1"
|
|
line.long 0x4 "C1MKR1,CAN1 Mask Register 1"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x4 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x4 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x4 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x4 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x4 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x4 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x4 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x4 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x4 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x4 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x4 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x4 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x4 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x4 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x4 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x4 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x4 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x0 "C1MKR2,CAN1 Mask Register 2"
|
|
bitfld.long 0x0 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x0 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x0 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x0 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x0 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x0 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x0 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x0 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x0 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x0 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x0 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x0 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x0 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x0 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x0 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x0 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x0 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x0 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x0 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x0 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x0 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x0 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x0 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x0 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x0 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x0 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x0 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x0 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x4 "C1MKR3,CAN1 Mask Register 3"
|
|
bitfld.long 0x4 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x4 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x4 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x4 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x4 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x4 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x4 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x4 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x4 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x4 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x4 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x4 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x4 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x4 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x4 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x4 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x4 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x4 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x4 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x4 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x4 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x4 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x4 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x4 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x4 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x4 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x4 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x4 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x8 "C1MKR4,CAN1 Mask Register 4"
|
|
bitfld.long 0x8 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x8 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x8 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x8 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x8 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x8 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x8 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x8 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x8 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x8 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x8 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x8 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x8 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x8 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x8 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x8 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x8 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x8 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x8 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x8 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x8 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x8 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x8 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x8 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x8 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x8 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x8 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x8 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0xC "C1MKR5,CAN1 Mask Register 5"
|
|
bitfld.long 0xC 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0xC 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0xC 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0xC 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0xC 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0xC 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0xC 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0xC 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0xC 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0xC 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0xC 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0xC 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0xC 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0xC 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0xC 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0xC 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0xC 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0xC 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0xC 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0xC 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0xC 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0xC 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0xC 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0xC 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0xC 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0xC 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0xC 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0xC 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x10 "C1MKR6,CAN1 Mask Register 6"
|
|
bitfld.long 0x10 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x10 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x10 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x10 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x10 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x10 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x10 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x10 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x10 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x10 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x10 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x10 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x10 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x10 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x10 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x10 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x10 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x10 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x10 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x10 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x10 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x10 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x10 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x10 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x10 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x10 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x10 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x10 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x14 "C1MKR7,CAN1 Mask Register 7"
|
|
bitfld.long 0x14 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x14 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x14 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x14 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x14 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x14 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x14 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x14 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x14 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x14 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x14 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x14 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x14 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x14 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x14 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x14 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x14 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x14 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x14 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x14 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x14 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x14 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x14 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x14 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x14 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x14 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x14 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x14 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x18 "C1MKR8,CAN1 Mask Register 8"
|
|
bitfld.long 0x18 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x18 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x18 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x18 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x18 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x18 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x18 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x18 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x18 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x18 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x18 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x18 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x18 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x18 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x18 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x18 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x18 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x18 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x18 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x18 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x18 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x18 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x18 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x18 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x18 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x18 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x18 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x18 0. ",Extended ID Bit 0" "0,1"
|
|
group.long 0x400++0x1f
|
|
line.long 0x1C "C1MKR9,CAN1 Mask Register 9"
|
|
bitfld.long 0x1C 28. " SID[10:0] ,Standard ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 27. ",Standard ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 26. ",Standard ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 25. ",Standard ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 24. ",Standard ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 23. ",Standard ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 22. ",Standard ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 21. ",Standard ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 20. ",Standard ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 19. ",Standard ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 18. ",Standard ID Bit 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 17. " EID[17:0] ,Extended ID Bit 17" "0,1"
|
|
bitfld.long 0x1C 16. ",Extended ID Bit 16" "0,1"
|
|
bitfld.long 0x1C 15. ",Extended ID Bit 15" "0,1"
|
|
bitfld.long 0x1C 14. ",Extended ID Bit 14" "0,1"
|
|
bitfld.long 0x1C 13. ",Extended ID Bit 13" "0,1"
|
|
bitfld.long 0x1C 12. ",Extended ID Bit 12" "0,1"
|
|
bitfld.long 0x1C 11. ",Extended ID Bit 11" "0,1"
|
|
bitfld.long 0x1C 10. ",Extended ID Bit 10" "0,1"
|
|
bitfld.long 0x1C 9. ",Extended ID Bit 9" "0,1"
|
|
bitfld.long 0x1C 8. ",Extended ID Bit 8" "0,1"
|
|
bitfld.long 0x1C 7. ",Extended ID Bit 7" "0,1"
|
|
bitfld.long 0x1C 6. ",Extended ID Bit 6" "0,1"
|
|
bitfld.long 0x1C 5. ",Extended ID Bit 5" "0,1"
|
|
bitfld.long 0x1C 4. ",Extended ID Bit 4" "0,1"
|
|
bitfld.long 0x1C 3. ",Extended ID Bit 3" "0,1"
|
|
bitfld.long 0x1C 2. ",Extended ID Bit 2" "0,1"
|
|
bitfld.long 0x1C 1. ",Extended ID Bit 1" "0,1"
|
|
bitfld.long 0x1C 0. ",Extended ID Bit 0" "0,1"
|
|
else
|
|
hgroup.long 0x430++0x07
|
|
hide.long 0x0 "C1MKR0,CAN1 Mask Register 0"
|
|
hide.long 0x4 "C1MKR1,CAN1 Mask Register 1"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x0 "C1MKR2,CAN1 Mask Register 2"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x4 "C1MKR3,CAN1 Mask Register 3"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x8 "C1MKR4,CAN1 Mask Register 4"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0xC "C1MKR5,CAN1 Mask Register 5"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x10 "C1MKR6,CAN1 Mask Register 6"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x14 "C1MKR7,CAN1 Mask Register 7"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x18 "C1MKR8,CAN1 Mask Register 8"
|
|
hgroup.long 0x400++0x1f
|
|
hide.long 0x1C "C1MKR9,CAN1 Mask Register 9"
|
|
endif
|
|
if ((((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x420))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2)))
|
|
group.long 0x420++0x03
|
|
line.long 0x0 "C1FIDCR0,CAN1 FIFO Received ID Compare Register 0"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
elif ((((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x420))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0)))
|
|
group.long 0x420++0x03
|
|
line.long 0x0 "C1FIDCR0,CAN1 FIFO Received ID Compare Register 0"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x0 "C1FIDCR0,CAN1 FIFO Received ID Compare Register 0"
|
|
endif
|
|
if ((((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x424))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2)))
|
|
group.long 0x424++0x03
|
|
line.long 0x0 "C1FIDCR1,CAN1 FIFO Received ID Compare Register 1"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
elif ((((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1)&&(((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x424))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0)))
|
|
group.long 0x424++0x03
|
|
line.long 0x0 "C1FIDCR1,CAN1 FIFO Received ID Compare Register 1"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x0 "C1FIDCR1,CAN1 FIFO Received ID Compare Register 1"
|
|
endif
|
|
group.long 0x428++0x03
|
|
line.long 0x0 "C1MKIVLR1,CAN1 Mask Invalid Register 1"
|
|
bitfld.long 0x00 31. " MBMV63 ,Mask valid for mailbox 63" "Valid,Invalid"
|
|
bitfld.long 0x00 30. " MBMV62 ,Mask valid for mailbox 62" "Valid,Invalid"
|
|
bitfld.long 0x00 29. " MBMV61 ,Mask valid for mailbox 61" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MBMV60 ,Mask valid for mailbox 60" "Valid,Invalid"
|
|
bitfld.long 0x00 27. " MBMV59 ,Mask valid for mailbox 59" "Valid,Invalid"
|
|
bitfld.long 0x00 26. " MBMV58 ,Mask valid for mailbox 58" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MBMV57 ,Mask valid for mailbox 57" "Valid,Invalid"
|
|
bitfld.long 0x00 24. " MBMV56 ,Mask valid for mailbox 56" "Valid,Invalid"
|
|
bitfld.long 0x00 23. " MBMV55 ,Mask valid for mailbox 55" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MBMV54 ,Mask valid for mailbox 54" "Valid,Invalid"
|
|
bitfld.long 0x00 21. " MBMV53 ,Mask valid for mailbox 53" "Valid,Invalid"
|
|
bitfld.long 0x00 20. " MBMV52 ,Mask valid for mailbox 52" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MBMV51 ,Mask valid for mailbox 51" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " MBMV50 ,Mask valid for mailbox 50" "Valid,Invalid"
|
|
bitfld.long 0x00 17. " MBMV49 ,Mask valid for mailbox 49" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MBMV48 ,Mask valid for mailbox 48" "Valid,Invalid"
|
|
bitfld.long 0x00 15. " MBMV47 ,Mask valid for mailbox 47" "Valid,Invalid"
|
|
bitfld.long 0x00 14. " MBMV46 ,Mask valid for mailbox 46" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MBMV45 ,Mask valid for mailbox 45" "Valid,Invalid"
|
|
bitfld.long 0x00 12. " MBMV44 ,Mask valid for mailbox 44" "Valid,Invalid"
|
|
bitfld.long 0x00 11. " MBMV43 ,Mask valid for mailbox 43" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBMV42 ,Mask valid for mailbox 42" "Valid,Invalid"
|
|
bitfld.long 0x00 9. " MBMV41 ,Mask valid for mailbox 41" "Valid,Invalid"
|
|
bitfld.long 0x00 8. " MBMV40 ,Mask valid for mailbox 40" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MBMV39 ,Mask valid for mailbox 39" "Valid,Invalid"
|
|
bitfld.long 0x00 6. " MBMV38 ,Mask valid for mailbox 38" "Valid,Invalid"
|
|
bitfld.long 0x00 5. " MBMV37 ,Mask valid for mailbox 37" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MBMV36 ,Mask valid for mailbox 36" "Valid,Invalid"
|
|
bitfld.long 0x00 3. " MBMV35 ,Mask valid for mailbox 35" "Valid,Invalid"
|
|
bitfld.long 0x00 2. " MBMV34 ,Mask valid for mailbox 34" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MBMV33 ,Mask valid for mailbox 33" "Valid,Invalid"
|
|
bitfld.long 0x00 0. " MBMV32 ,Mask valid for mailbox 32" "Valid,Invalid"
|
|
group.long 0x438++0x03
|
|
line.long 0x0 "C1MKIVLR0,CAN1 Mask Invalid Register 0"
|
|
bitfld.long 0x00 31. " MBMV31 ,Mask valid for mailbox 31" "Valid,Invalid"
|
|
bitfld.long 0x00 30. " MBMV30 ,Mask valid for mailbox 30" "Valid,Invalid"
|
|
bitfld.long 0x00 29. " MBMV29 ,Mask valid for mailbox 29" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MBMV28 ,Mask valid for mailbox 28" "Valid,Invalid"
|
|
bitfld.long 0x00 27. " MBMV27 ,Mask valid for mailbox 27" "Valid,Invalid"
|
|
bitfld.long 0x00 26. " MBMV26 ,Mask valid for mailbox 26" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MBMV25 ,Mask valid for mailbox 25" "Valid,Invalid"
|
|
bitfld.long 0x00 24. " MBMV24 ,Mask valid for mailbox 24" "Valid,Invalid"
|
|
bitfld.long 0x00 23. " MBMV23 ,Mask valid for mailbox 23" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MBMV22 ,Mask valid for mailbox 22" "Valid,Invalid"
|
|
bitfld.long 0x00 21. " MBMV21 ,Mask valid for mailbox 21" "Valid,Invalid"
|
|
bitfld.long 0x00 20. " MBMV20 ,Mask valid for mailbox 20" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MBMV19 ,Mask valid for mailbox 19" "Valid,Invalid"
|
|
bitfld.long 0x00 18. " MBMV18 ,Mask valid for mailbox 18" "Valid,Invalid"
|
|
bitfld.long 0x00 17. " MBMV17 ,Mask valid for mailbox 17" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MBMV16 ,Mask valid for mailbox 16" "Valid,Invalid"
|
|
bitfld.long 0x00 15. " MBMV15 ,Mask valid for mailbox 15" "Valid,Invalid"
|
|
bitfld.long 0x00 14. " MBMV14 ,Mask valid for mailbox 14" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MBMV13 ,Mask valid for mailbox 13" "Valid,Invalid"
|
|
bitfld.long 0x00 12. " MBMV12 ,Mask valid for mailbox 12" "Valid,Invalid"
|
|
bitfld.long 0x00 11. " MBMV11 ,Mask valid for mailbox 11" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MBMV10 ,Mask valid for mailbox 10" "Valid,Invalid"
|
|
bitfld.long 0x00 9. " MBMV9 ,Mask valid for mailbox 9" "Valid,Invalid"
|
|
bitfld.long 0x00 8. " MBMV8 ,Mask valid for mailbox 8" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MBMV7 ,Mask valid for mailbox 7" "Valid,Invalid"
|
|
bitfld.long 0x00 6. " MBMV6 ,Mask valid for mailbox 6" "Valid,Invalid"
|
|
bitfld.long 0x00 5. " MBMV5 ,Mask valid for mailbox 5" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MBMV4 ,Mask valid for mailbox 4" "Valid,Invalid"
|
|
bitfld.long 0x00 3. " MBMV3 ,Mask valid for mailbox 3" "Valid,Invalid"
|
|
bitfld.long 0x00 2. " MBMV2 ,Mask valid for mailbox 2" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MBMV1 ,Mask valid for mailbox 1" "Valid,Invalid"
|
|
bitfld.long 0x00 0. " MBMV0 ,Mask valid for mailbox 0" "Valid,Invalid"
|
|
tree "CAN Mailboxes registers"
|
|
if (((63.==60.)||(63.==61.)||(63.==62.)||(63.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C1MB63_ID,CAN1 Mailbox 63 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "C1MB63_ID,CAN1 Mailbox 63 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "C1MB63_ID,CAN1 Mailbox 63 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "C1MB63_ID,CAN1 Mailbox 63 Register"
|
|
endif
|
|
group.word (0x0+0x04)++0x1
|
|
line.word 0x00 "C1MB63_DLC,CAN1 Mailbox 63 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x0+0x06)++0x07
|
|
line.byte 0x00 "C1MB63_D0,CAN1 Mailbox 63 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB63_D1,CAN1 Mailbox 63 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB63_D2,CAN1 Mailbox 63 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB63_D3,CAN1 Mailbox 63 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB63_D4,CAN1 Mailbox 63 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB63_D5,CAN1 Mailbox 63 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB63_D6,CAN1 Mailbox 63 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB63_D7,CAN1 Mailbox 63 Data byte 7 Register"
|
|
group.word (0x0+0x0e)++0x01
|
|
line.word 0x00 "C1MB63_TS,CAN1 Mailbox 63 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((62.==60.)||(62.==61.)||(62.==62.)||(62.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "C1MB62_ID,CAN1 Mailbox 62 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x10))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C1MB62_ID,CAN1 Mailbox 62 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x10))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C1MB62_ID,CAN1 Mailbox 62 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "C1MB62_ID,CAN1 Mailbox 62 Register"
|
|
endif
|
|
group.word (0x10+0x04)++0x1
|
|
line.word 0x00 "C1MB62_DLC,CAN1 Mailbox 62 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x10+0x06)++0x07
|
|
line.byte 0x00 "C1MB62_D0,CAN1 Mailbox 62 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB62_D1,CAN1 Mailbox 62 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB62_D2,CAN1 Mailbox 62 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB62_D3,CAN1 Mailbox 62 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB62_D4,CAN1 Mailbox 62 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB62_D5,CAN1 Mailbox 62 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB62_D6,CAN1 Mailbox 62 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB62_D7,CAN1 Mailbox 62 Data byte 7 Register"
|
|
group.word (0x10+0x0e)++0x01
|
|
line.word 0x00 "C1MB62_TS,CAN1 Mailbox 62 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((61.==60.)||(61.==61.)||(61.==62.)||(61.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "C1MB61_ID,CAN1 Mailbox 61 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x20))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C1MB61_ID,CAN1 Mailbox 61 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x20))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C1MB61_ID,CAN1 Mailbox 61 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "C1MB61_ID,CAN1 Mailbox 61 Register"
|
|
endif
|
|
group.word (0x20+0x04)++0x1
|
|
line.word 0x00 "C1MB61_DLC,CAN1 Mailbox 61 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x20+0x06)++0x07
|
|
line.byte 0x00 "C1MB61_D0,CAN1 Mailbox 61 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB61_D1,CAN1 Mailbox 61 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB61_D2,CAN1 Mailbox 61 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB61_D3,CAN1 Mailbox 61 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB61_D4,CAN1 Mailbox 61 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB61_D5,CAN1 Mailbox 61 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB61_D6,CAN1 Mailbox 61 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB61_D7,CAN1 Mailbox 61 Data byte 7 Register"
|
|
group.word (0x20+0x0e)++0x01
|
|
line.word 0x00 "C1MB61_TS,CAN1 Mailbox 61 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((60.==60.)||(60.==61.)||(60.==62.)||(60.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "C1MB60_ID,CAN1 Mailbox 60 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x30))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C1MB60_ID,CAN1 Mailbox 60 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x30))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C1MB60_ID,CAN1 Mailbox 60 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "C1MB60_ID,CAN1 Mailbox 60 Register"
|
|
endif
|
|
group.word (0x30+0x04)++0x1
|
|
line.word 0x00 "C1MB60_DLC,CAN1 Mailbox 60 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x30+0x06)++0x07
|
|
line.byte 0x00 "C1MB60_D0,CAN1 Mailbox 60 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB60_D1,CAN1 Mailbox 60 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB60_D2,CAN1 Mailbox 60 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB60_D3,CAN1 Mailbox 60 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB60_D4,CAN1 Mailbox 60 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB60_D5,CAN1 Mailbox 60 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB60_D6,CAN1 Mailbox 60 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB60_D7,CAN1 Mailbox 60 Data byte 7 Register"
|
|
group.word (0x30+0x0e)++0x01
|
|
line.word 0x00 "C1MB60_TS,CAN1 Mailbox 60 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((59.==60.)||(59.==61.)||(59.==62.)||(59.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "C1MB59_ID,CAN1 Mailbox 59 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x40))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C1MB59_ID,CAN1 Mailbox 59 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x40))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C1MB59_ID,CAN1 Mailbox 59 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "C1MB59_ID,CAN1 Mailbox 59 Register"
|
|
endif
|
|
group.word (0x40+0x04)++0x1
|
|
line.word 0x00 "C1MB59_DLC,CAN1 Mailbox 59 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x40+0x06)++0x07
|
|
line.byte 0x00 "C1MB59_D0,CAN1 Mailbox 59 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB59_D1,CAN1 Mailbox 59 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB59_D2,CAN1 Mailbox 59 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB59_D3,CAN1 Mailbox 59 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB59_D4,CAN1 Mailbox 59 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB59_D5,CAN1 Mailbox 59 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB59_D6,CAN1 Mailbox 59 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB59_D7,CAN1 Mailbox 59 Data byte 7 Register"
|
|
group.word (0x40+0x0e)++0x01
|
|
line.word 0x00 "C1MB59_TS,CAN1 Mailbox 59 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((58.==60.)||(58.==61.)||(58.==62.)||(58.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "C1MB58_ID,CAN1 Mailbox 58 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x50))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "C1MB58_ID,CAN1 Mailbox 58 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x50))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "C1MB58_ID,CAN1 Mailbox 58 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "C1MB58_ID,CAN1 Mailbox 58 Register"
|
|
endif
|
|
group.word (0x50+0x04)++0x1
|
|
line.word 0x00 "C1MB58_DLC,CAN1 Mailbox 58 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x50+0x06)++0x07
|
|
line.byte 0x00 "C1MB58_D0,CAN1 Mailbox 58 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB58_D1,CAN1 Mailbox 58 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB58_D2,CAN1 Mailbox 58 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB58_D3,CAN1 Mailbox 58 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB58_D4,CAN1 Mailbox 58 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB58_D5,CAN1 Mailbox 58 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB58_D6,CAN1 Mailbox 58 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB58_D7,CAN1 Mailbox 58 Data byte 7 Register"
|
|
group.word (0x50+0x0e)++0x01
|
|
line.word 0x00 "C1MB58_TS,CAN1 Mailbox 58 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((57.==60.)||(57.==61.)||(57.==62.)||(57.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "C1MB57_ID,CAN1 Mailbox 57 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x60))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C1MB57_ID,CAN1 Mailbox 57 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x60))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "C1MB57_ID,CAN1 Mailbox 57 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "C1MB57_ID,CAN1 Mailbox 57 Register"
|
|
endif
|
|
group.word (0x60+0x04)++0x1
|
|
line.word 0x00 "C1MB57_DLC,CAN1 Mailbox 57 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x60+0x06)++0x07
|
|
line.byte 0x00 "C1MB57_D0,CAN1 Mailbox 57 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB57_D1,CAN1 Mailbox 57 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB57_D2,CAN1 Mailbox 57 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB57_D3,CAN1 Mailbox 57 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB57_D4,CAN1 Mailbox 57 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB57_D5,CAN1 Mailbox 57 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB57_D6,CAN1 Mailbox 57 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB57_D7,CAN1 Mailbox 57 Data byte 7 Register"
|
|
group.word (0x60+0x0e)++0x01
|
|
line.word 0x00 "C1MB57_TS,CAN1 Mailbox 57 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((56.==60.)||(56.==61.)||(56.==62.)||(56.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "C1MB56_ID,CAN1 Mailbox 56 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x70))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "C1MB56_ID,CAN1 Mailbox 56 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x70))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "C1MB56_ID,CAN1 Mailbox 56 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "C1MB56_ID,CAN1 Mailbox 56 Register"
|
|
endif
|
|
group.word (0x70+0x04)++0x1
|
|
line.word 0x00 "C1MB56_DLC,CAN1 Mailbox 56 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x70+0x06)++0x07
|
|
line.byte 0x00 "C1MB56_D0,CAN1 Mailbox 56 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB56_D1,CAN1 Mailbox 56 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB56_D2,CAN1 Mailbox 56 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB56_D3,CAN1 Mailbox 56 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB56_D4,CAN1 Mailbox 56 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB56_D5,CAN1 Mailbox 56 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB56_D6,CAN1 Mailbox 56 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB56_D7,CAN1 Mailbox 56 Data byte 7 Register"
|
|
group.word (0x70+0x0e)++0x01
|
|
line.word 0x00 "C1MB56_TS,CAN1 Mailbox 56 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((55.==60.)||(55.==61.)||(55.==62.)||(55.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "C1MB55_ID,CAN1 Mailbox 55 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x80))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "C1MB55_ID,CAN1 Mailbox 55 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x80))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "C1MB55_ID,CAN1 Mailbox 55 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "C1MB55_ID,CAN1 Mailbox 55 Register"
|
|
endif
|
|
group.word (0x80+0x04)++0x1
|
|
line.word 0x00 "C1MB55_DLC,CAN1 Mailbox 55 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x80+0x06)++0x07
|
|
line.byte 0x00 "C1MB55_D0,CAN1 Mailbox 55 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB55_D1,CAN1 Mailbox 55 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB55_D2,CAN1 Mailbox 55 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB55_D3,CAN1 Mailbox 55 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB55_D4,CAN1 Mailbox 55 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB55_D5,CAN1 Mailbox 55 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB55_D6,CAN1 Mailbox 55 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB55_D7,CAN1 Mailbox 55 Data byte 7 Register"
|
|
group.word (0x80+0x0e)++0x01
|
|
line.word 0x00 "C1MB55_TS,CAN1 Mailbox 55 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((54.==60.)||(54.==61.)||(54.==62.)||(54.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "C1MB54_ID,CAN1 Mailbox 54 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x90))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "C1MB54_ID,CAN1 Mailbox 54 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x90))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "C1MB54_ID,CAN1 Mailbox 54 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "C1MB54_ID,CAN1 Mailbox 54 Register"
|
|
endif
|
|
group.word (0x90+0x04)++0x1
|
|
line.word 0x00 "C1MB54_DLC,CAN1 Mailbox 54 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x90+0x06)++0x07
|
|
line.byte 0x00 "C1MB54_D0,CAN1 Mailbox 54 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB54_D1,CAN1 Mailbox 54 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB54_D2,CAN1 Mailbox 54 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB54_D3,CAN1 Mailbox 54 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB54_D4,CAN1 Mailbox 54 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB54_D5,CAN1 Mailbox 54 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB54_D6,CAN1 Mailbox 54 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB54_D7,CAN1 Mailbox 54 Data byte 7 Register"
|
|
group.word (0x90+0x0e)++0x01
|
|
line.word 0x00 "C1MB54_TS,CAN1 Mailbox 54 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((53.==60.)||(53.==61.)||(53.==62.)||(53.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "C1MB53_ID,CAN1 Mailbox 53 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xA0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "C1MB53_ID,CAN1 Mailbox 53 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xA0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "C1MB53_ID,CAN1 Mailbox 53 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xA0++0x03
|
|
hide.long 0x00 "C1MB53_ID,CAN1 Mailbox 53 Register"
|
|
endif
|
|
group.word (0xA0+0x04)++0x1
|
|
line.word 0x00 "C1MB53_DLC,CAN1 Mailbox 53 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xA0+0x06)++0x07
|
|
line.byte 0x00 "C1MB53_D0,CAN1 Mailbox 53 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB53_D1,CAN1 Mailbox 53 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB53_D2,CAN1 Mailbox 53 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB53_D3,CAN1 Mailbox 53 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB53_D4,CAN1 Mailbox 53 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB53_D5,CAN1 Mailbox 53 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB53_D6,CAN1 Mailbox 53 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB53_D7,CAN1 Mailbox 53 Data byte 7 Register"
|
|
group.word (0xA0+0x0e)++0x01
|
|
line.word 0x00 "C1MB53_TS,CAN1 Mailbox 53 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((52.==60.)||(52.==61.)||(52.==62.)||(52.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "C1MB52_ID,CAN1 Mailbox 52 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xB0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "C1MB52_ID,CAN1 Mailbox 52 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xB0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "C1MB52_ID,CAN1 Mailbox 52 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xB0++0x03
|
|
hide.long 0x00 "C1MB52_ID,CAN1 Mailbox 52 Register"
|
|
endif
|
|
group.word (0xB0+0x04)++0x1
|
|
line.word 0x00 "C1MB52_DLC,CAN1 Mailbox 52 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xB0+0x06)++0x07
|
|
line.byte 0x00 "C1MB52_D0,CAN1 Mailbox 52 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB52_D1,CAN1 Mailbox 52 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB52_D2,CAN1 Mailbox 52 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB52_D3,CAN1 Mailbox 52 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB52_D4,CAN1 Mailbox 52 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB52_D5,CAN1 Mailbox 52 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB52_D6,CAN1 Mailbox 52 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB52_D7,CAN1 Mailbox 52 Data byte 7 Register"
|
|
group.word (0xB0+0x0e)++0x01
|
|
line.word 0x00 "C1MB52_TS,CAN1 Mailbox 52 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((51.==60.)||(51.==61.)||(51.==62.)||(51.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "C1MB51_ID,CAN1 Mailbox 51 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xC0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "C1MB51_ID,CAN1 Mailbox 51 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xC0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "C1MB51_ID,CAN1 Mailbox 51 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xC0++0x03
|
|
hide.long 0x00 "C1MB51_ID,CAN1 Mailbox 51 Register"
|
|
endif
|
|
group.word (0xC0+0x04)++0x1
|
|
line.word 0x00 "C1MB51_DLC,CAN1 Mailbox 51 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xC0+0x06)++0x07
|
|
line.byte 0x00 "C1MB51_D0,CAN1 Mailbox 51 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB51_D1,CAN1 Mailbox 51 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB51_D2,CAN1 Mailbox 51 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB51_D3,CAN1 Mailbox 51 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB51_D4,CAN1 Mailbox 51 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB51_D5,CAN1 Mailbox 51 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB51_D6,CAN1 Mailbox 51 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB51_D7,CAN1 Mailbox 51 Data byte 7 Register"
|
|
group.word (0xC0+0x0e)++0x01
|
|
line.word 0x00 "C1MB51_TS,CAN1 Mailbox 51 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((50.==60.)||(50.==61.)||(50.==62.)||(50.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "C1MB50_ID,CAN1 Mailbox 50 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xD0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "C1MB50_ID,CAN1 Mailbox 50 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xD0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "C1MB50_ID,CAN1 Mailbox 50 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xD0++0x03
|
|
hide.long 0x00 "C1MB50_ID,CAN1 Mailbox 50 Register"
|
|
endif
|
|
group.word (0xD0+0x04)++0x1
|
|
line.word 0x00 "C1MB50_DLC,CAN1 Mailbox 50 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xD0+0x06)++0x07
|
|
line.byte 0x00 "C1MB50_D0,CAN1 Mailbox 50 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB50_D1,CAN1 Mailbox 50 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB50_D2,CAN1 Mailbox 50 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB50_D3,CAN1 Mailbox 50 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB50_D4,CAN1 Mailbox 50 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB50_D5,CAN1 Mailbox 50 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB50_D6,CAN1 Mailbox 50 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB50_D7,CAN1 Mailbox 50 Data byte 7 Register"
|
|
group.word (0xD0+0x0e)++0x01
|
|
line.word 0x00 "C1MB50_TS,CAN1 Mailbox 50 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((49.==60.)||(49.==61.)||(49.==62.)||(49.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "C1MB49_ID,CAN1 Mailbox 49 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xE0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "C1MB49_ID,CAN1 Mailbox 49 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xE0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "C1MB49_ID,CAN1 Mailbox 49 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xE0++0x03
|
|
hide.long 0x00 "C1MB49_ID,CAN1 Mailbox 49 Register"
|
|
endif
|
|
group.word (0xE0+0x04)++0x1
|
|
line.word 0x00 "C1MB49_DLC,CAN1 Mailbox 49 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xE0+0x06)++0x07
|
|
line.byte 0x00 "C1MB49_D0,CAN1 Mailbox 49 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB49_D1,CAN1 Mailbox 49 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB49_D2,CAN1 Mailbox 49 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB49_D3,CAN1 Mailbox 49 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB49_D4,CAN1 Mailbox 49 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB49_D5,CAN1 Mailbox 49 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB49_D6,CAN1 Mailbox 49 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB49_D7,CAN1 Mailbox 49 Data byte 7 Register"
|
|
group.word (0xE0+0x0e)++0x01
|
|
line.word 0x00 "C1MB49_TS,CAN1 Mailbox 49 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((48.==60.)||(48.==61.)||(48.==62.)||(48.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "C1MB48_ID,CAN1 Mailbox 48 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xF0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "C1MB48_ID,CAN1 Mailbox 48 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0xF0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "C1MB48_ID,CAN1 Mailbox 48 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0xF0++0x03
|
|
hide.long 0x00 "C1MB48_ID,CAN1 Mailbox 48 Register"
|
|
endif
|
|
group.word (0xF0+0x04)++0x1
|
|
line.word 0x00 "C1MB48_DLC,CAN1 Mailbox 48 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0xF0+0x06)++0x07
|
|
line.byte 0x00 "C1MB48_D0,CAN1 Mailbox 48 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB48_D1,CAN1 Mailbox 48 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB48_D2,CAN1 Mailbox 48 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB48_D3,CAN1 Mailbox 48 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB48_D4,CAN1 Mailbox 48 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB48_D5,CAN1 Mailbox 48 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB48_D6,CAN1 Mailbox 48 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB48_D7,CAN1 Mailbox 48 Data byte 7 Register"
|
|
group.word (0xF0+0x0e)++0x01
|
|
line.word 0x00 "C1MB48_TS,CAN1 Mailbox 48 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((47.==60.)||(47.==61.)||(47.==62.)||(47.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "C1MB47_ID,CAN1 Mailbox 47 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x100))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C1MB47_ID,CAN1 Mailbox 47 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x100))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "C1MB47_ID,CAN1 Mailbox 47 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x100++0x03
|
|
hide.long 0x00 "C1MB47_ID,CAN1 Mailbox 47 Register"
|
|
endif
|
|
group.word (0x100+0x04)++0x1
|
|
line.word 0x00 "C1MB47_DLC,CAN1 Mailbox 47 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x100+0x06)++0x07
|
|
line.byte 0x00 "C1MB47_D0,CAN1 Mailbox 47 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB47_D1,CAN1 Mailbox 47 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB47_D2,CAN1 Mailbox 47 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB47_D3,CAN1 Mailbox 47 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB47_D4,CAN1 Mailbox 47 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB47_D5,CAN1 Mailbox 47 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB47_D6,CAN1 Mailbox 47 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB47_D7,CAN1 Mailbox 47 Data byte 7 Register"
|
|
group.word (0x100+0x0e)++0x01
|
|
line.word 0x00 "C1MB47_TS,CAN1 Mailbox 47 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((46.==60.)||(46.==61.)||(46.==62.)||(46.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "C1MB46_ID,CAN1 Mailbox 46 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x110))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C1MB46_ID,CAN1 Mailbox 46 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x110))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "C1MB46_ID,CAN1 Mailbox 46 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "C1MB46_ID,CAN1 Mailbox 46 Register"
|
|
endif
|
|
group.word (0x110+0x04)++0x1
|
|
line.word 0x00 "C1MB46_DLC,CAN1 Mailbox 46 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x110+0x06)++0x07
|
|
line.byte 0x00 "C1MB46_D0,CAN1 Mailbox 46 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB46_D1,CAN1 Mailbox 46 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB46_D2,CAN1 Mailbox 46 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB46_D3,CAN1 Mailbox 46 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB46_D4,CAN1 Mailbox 46 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB46_D5,CAN1 Mailbox 46 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB46_D6,CAN1 Mailbox 46 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB46_D7,CAN1 Mailbox 46 Data byte 7 Register"
|
|
group.word (0x110+0x0e)++0x01
|
|
line.word 0x00 "C1MB46_TS,CAN1 Mailbox 46 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((45.==60.)||(45.==61.)||(45.==62.)||(45.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "C1MB45_ID,CAN1 Mailbox 45 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x120))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1MB45_ID,CAN1 Mailbox 45 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x120))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "C1MB45_ID,CAN1 Mailbox 45 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "C1MB45_ID,CAN1 Mailbox 45 Register"
|
|
endif
|
|
group.word (0x120+0x04)++0x1
|
|
line.word 0x00 "C1MB45_DLC,CAN1 Mailbox 45 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x120+0x06)++0x07
|
|
line.byte 0x00 "C1MB45_D0,CAN1 Mailbox 45 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB45_D1,CAN1 Mailbox 45 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB45_D2,CAN1 Mailbox 45 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB45_D3,CAN1 Mailbox 45 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB45_D4,CAN1 Mailbox 45 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB45_D5,CAN1 Mailbox 45 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB45_D6,CAN1 Mailbox 45 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB45_D7,CAN1 Mailbox 45 Data byte 7 Register"
|
|
group.word (0x120+0x0e)++0x01
|
|
line.word 0x00 "C1MB45_TS,CAN1 Mailbox 45 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((44.==60.)||(44.==61.)||(44.==62.)||(44.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "C1MB44_ID,CAN1 Mailbox 44 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x130))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1MB44_ID,CAN1 Mailbox 44 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x130))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "C1MB44_ID,CAN1 Mailbox 44 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "C1MB44_ID,CAN1 Mailbox 44 Register"
|
|
endif
|
|
group.word (0x130+0x04)++0x1
|
|
line.word 0x00 "C1MB44_DLC,CAN1 Mailbox 44 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x130+0x06)++0x07
|
|
line.byte 0x00 "C1MB44_D0,CAN1 Mailbox 44 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB44_D1,CAN1 Mailbox 44 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB44_D2,CAN1 Mailbox 44 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB44_D3,CAN1 Mailbox 44 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB44_D4,CAN1 Mailbox 44 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB44_D5,CAN1 Mailbox 44 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB44_D6,CAN1 Mailbox 44 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB44_D7,CAN1 Mailbox 44 Data byte 7 Register"
|
|
group.word (0x130+0x0e)++0x01
|
|
line.word 0x00 "C1MB44_TS,CAN1 Mailbox 44 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((43.==60.)||(43.==61.)||(43.==62.)||(43.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "C1MB43_ID,CAN1 Mailbox 43 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x140))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "C1MB43_ID,CAN1 Mailbox 43 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x140))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "C1MB43_ID,CAN1 Mailbox 43 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x140++0x03
|
|
hide.long 0x00 "C1MB43_ID,CAN1 Mailbox 43 Register"
|
|
endif
|
|
group.word (0x140+0x04)++0x1
|
|
line.word 0x00 "C1MB43_DLC,CAN1 Mailbox 43 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x140+0x06)++0x07
|
|
line.byte 0x00 "C1MB43_D0,CAN1 Mailbox 43 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB43_D1,CAN1 Mailbox 43 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB43_D2,CAN1 Mailbox 43 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB43_D3,CAN1 Mailbox 43 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB43_D4,CAN1 Mailbox 43 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB43_D5,CAN1 Mailbox 43 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB43_D6,CAN1 Mailbox 43 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB43_D7,CAN1 Mailbox 43 Data byte 7 Register"
|
|
group.word (0x140+0x0e)++0x01
|
|
line.word 0x00 "C1MB43_TS,CAN1 Mailbox 43 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((42.==60.)||(42.==61.)||(42.==62.)||(42.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "C1MB42_ID,CAN1 Mailbox 42 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x150))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "C1MB42_ID,CAN1 Mailbox 42 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x150))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "C1MB42_ID,CAN1 Mailbox 42 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "C1MB42_ID,CAN1 Mailbox 42 Register"
|
|
endif
|
|
group.word (0x150+0x04)++0x1
|
|
line.word 0x00 "C1MB42_DLC,CAN1 Mailbox 42 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x150+0x06)++0x07
|
|
line.byte 0x00 "C1MB42_D0,CAN1 Mailbox 42 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB42_D1,CAN1 Mailbox 42 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB42_D2,CAN1 Mailbox 42 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB42_D3,CAN1 Mailbox 42 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB42_D4,CAN1 Mailbox 42 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB42_D5,CAN1 Mailbox 42 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB42_D6,CAN1 Mailbox 42 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB42_D7,CAN1 Mailbox 42 Data byte 7 Register"
|
|
group.word (0x150+0x0e)++0x01
|
|
line.word 0x00 "C1MB42_TS,CAN1 Mailbox 42 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((41.==60.)||(41.==61.)||(41.==62.)||(41.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "C1MB41_ID,CAN1 Mailbox 41 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x160))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "C1MB41_ID,CAN1 Mailbox 41 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x160))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "C1MB41_ID,CAN1 Mailbox 41 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "C1MB41_ID,CAN1 Mailbox 41 Register"
|
|
endif
|
|
group.word (0x160+0x04)++0x1
|
|
line.word 0x00 "C1MB41_DLC,CAN1 Mailbox 41 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x160+0x06)++0x07
|
|
line.byte 0x00 "C1MB41_D0,CAN1 Mailbox 41 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB41_D1,CAN1 Mailbox 41 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB41_D2,CAN1 Mailbox 41 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB41_D3,CAN1 Mailbox 41 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB41_D4,CAN1 Mailbox 41 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB41_D5,CAN1 Mailbox 41 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB41_D6,CAN1 Mailbox 41 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB41_D7,CAN1 Mailbox 41 Data byte 7 Register"
|
|
group.word (0x160+0x0e)++0x01
|
|
line.word 0x00 "C1MB41_TS,CAN1 Mailbox 41 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((40.==60.)||(40.==61.)||(40.==62.)||(40.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "C1MB40_ID,CAN1 Mailbox 40 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x170))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "C1MB40_ID,CAN1 Mailbox 40 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x170))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "C1MB40_ID,CAN1 Mailbox 40 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "C1MB40_ID,CAN1 Mailbox 40 Register"
|
|
endif
|
|
group.word (0x170+0x04)++0x1
|
|
line.word 0x00 "C1MB40_DLC,CAN1 Mailbox 40 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x170+0x06)++0x07
|
|
line.byte 0x00 "C1MB40_D0,CAN1 Mailbox 40 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB40_D1,CAN1 Mailbox 40 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB40_D2,CAN1 Mailbox 40 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB40_D3,CAN1 Mailbox 40 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB40_D4,CAN1 Mailbox 40 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB40_D5,CAN1 Mailbox 40 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB40_D6,CAN1 Mailbox 40 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB40_D7,CAN1 Mailbox 40 Data byte 7 Register"
|
|
group.word (0x170+0x0e)++0x01
|
|
line.word 0x00 "C1MB40_TS,CAN1 Mailbox 40 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((39.==60.)||(39.==61.)||(39.==62.)||(39.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "C1MB39_ID,CAN1 Mailbox 39 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x180))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "C1MB39_ID,CAN1 Mailbox 39 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x180))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "C1MB39_ID,CAN1 Mailbox 39 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x180++0x03
|
|
hide.long 0x00 "C1MB39_ID,CAN1 Mailbox 39 Register"
|
|
endif
|
|
group.word (0x180+0x04)++0x1
|
|
line.word 0x00 "C1MB39_DLC,CAN1 Mailbox 39 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x180+0x06)++0x07
|
|
line.byte 0x00 "C1MB39_D0,CAN1 Mailbox 39 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB39_D1,CAN1 Mailbox 39 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB39_D2,CAN1 Mailbox 39 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB39_D3,CAN1 Mailbox 39 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB39_D4,CAN1 Mailbox 39 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB39_D5,CAN1 Mailbox 39 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB39_D6,CAN1 Mailbox 39 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB39_D7,CAN1 Mailbox 39 Data byte 7 Register"
|
|
group.word (0x180+0x0e)++0x01
|
|
line.word 0x00 "C1MB39_TS,CAN1 Mailbox 39 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((38.==60.)||(38.==61.)||(38.==62.)||(38.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "C1MB38_ID,CAN1 Mailbox 38 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x190))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "C1MB38_ID,CAN1 Mailbox 38 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x190))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "C1MB38_ID,CAN1 Mailbox 38 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x190++0x03
|
|
hide.long 0x00 "C1MB38_ID,CAN1 Mailbox 38 Register"
|
|
endif
|
|
group.word (0x190+0x04)++0x1
|
|
line.word 0x00 "C1MB38_DLC,CAN1 Mailbox 38 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x190+0x06)++0x07
|
|
line.byte 0x00 "C1MB38_D0,CAN1 Mailbox 38 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB38_D1,CAN1 Mailbox 38 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB38_D2,CAN1 Mailbox 38 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB38_D3,CAN1 Mailbox 38 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB38_D4,CAN1 Mailbox 38 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB38_D5,CAN1 Mailbox 38 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB38_D6,CAN1 Mailbox 38 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB38_D7,CAN1 Mailbox 38 Data byte 7 Register"
|
|
group.word (0x190+0x0e)++0x01
|
|
line.word 0x00 "C1MB38_TS,CAN1 Mailbox 38 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((37.==60.)||(37.==61.)||(37.==62.)||(37.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "C1MB37_ID,CAN1 Mailbox 37 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "C1MB37_ID,CAN1 Mailbox 37 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "C1MB37_ID,CAN1 Mailbox 37 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1A0++0x03
|
|
hide.long 0x00 "C1MB37_ID,CAN1 Mailbox 37 Register"
|
|
endif
|
|
group.word (0x1A0+0x04)++0x1
|
|
line.word 0x00 "C1MB37_DLC,CAN1 Mailbox 37 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1A0+0x06)++0x07
|
|
line.byte 0x00 "C1MB37_D0,CAN1 Mailbox 37 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB37_D1,CAN1 Mailbox 37 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB37_D2,CAN1 Mailbox 37 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB37_D3,CAN1 Mailbox 37 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB37_D4,CAN1 Mailbox 37 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB37_D5,CAN1 Mailbox 37 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB37_D6,CAN1 Mailbox 37 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB37_D7,CAN1 Mailbox 37 Data byte 7 Register"
|
|
group.word (0x1A0+0x0e)++0x01
|
|
line.word 0x00 "C1MB37_TS,CAN1 Mailbox 37 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((36.==60.)||(36.==61.)||(36.==62.)||(36.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "C1MB36_ID,CAN1 Mailbox 36 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "C1MB36_ID,CAN1 Mailbox 36 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "C1MB36_ID,CAN1 Mailbox 36 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "C1MB36_ID,CAN1 Mailbox 36 Register"
|
|
endif
|
|
group.word (0x1B0+0x04)++0x1
|
|
line.word 0x00 "C1MB36_DLC,CAN1 Mailbox 36 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1B0+0x06)++0x07
|
|
line.byte 0x00 "C1MB36_D0,CAN1 Mailbox 36 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB36_D1,CAN1 Mailbox 36 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB36_D2,CAN1 Mailbox 36 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB36_D3,CAN1 Mailbox 36 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB36_D4,CAN1 Mailbox 36 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB36_D5,CAN1 Mailbox 36 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB36_D6,CAN1 Mailbox 36 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB36_D7,CAN1 Mailbox 36 Data byte 7 Register"
|
|
group.word (0x1B0+0x0e)++0x01
|
|
line.word 0x00 "C1MB36_TS,CAN1 Mailbox 36 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((35.==60.)||(35.==61.)||(35.==62.)||(35.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "C1MB35_ID,CAN1 Mailbox 35 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "C1MB35_ID,CAN1 Mailbox 35 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "C1MB35_ID,CAN1 Mailbox 35 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "C1MB35_ID,CAN1 Mailbox 35 Register"
|
|
endif
|
|
group.word (0x1C0+0x04)++0x1
|
|
line.word 0x00 "C1MB35_DLC,CAN1 Mailbox 35 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1C0+0x06)++0x07
|
|
line.byte 0x00 "C1MB35_D0,CAN1 Mailbox 35 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB35_D1,CAN1 Mailbox 35 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB35_D2,CAN1 Mailbox 35 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB35_D3,CAN1 Mailbox 35 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB35_D4,CAN1 Mailbox 35 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB35_D5,CAN1 Mailbox 35 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB35_D6,CAN1 Mailbox 35 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB35_D7,CAN1 Mailbox 35 Data byte 7 Register"
|
|
group.word (0x1C0+0x0e)++0x01
|
|
line.word 0x00 "C1MB35_TS,CAN1 Mailbox 35 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((34.==60.)||(34.==61.)||(34.==62.)||(34.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "C1MB34_ID,CAN1 Mailbox 34 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "C1MB34_ID,CAN1 Mailbox 34 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "C1MB34_ID,CAN1 Mailbox 34 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "C1MB34_ID,CAN1 Mailbox 34 Register"
|
|
endif
|
|
group.word (0x1D0+0x04)++0x1
|
|
line.word 0x00 "C1MB34_DLC,CAN1 Mailbox 34 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1D0+0x06)++0x07
|
|
line.byte 0x00 "C1MB34_D0,CAN1 Mailbox 34 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB34_D1,CAN1 Mailbox 34 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB34_D2,CAN1 Mailbox 34 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB34_D3,CAN1 Mailbox 34 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB34_D4,CAN1 Mailbox 34 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB34_D5,CAN1 Mailbox 34 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB34_D6,CAN1 Mailbox 34 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB34_D7,CAN1 Mailbox 34 Data byte 7 Register"
|
|
group.word (0x1D0+0x0e)++0x01
|
|
line.word 0x00 "C1MB34_TS,CAN1 Mailbox 34 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((33.==60.)||(33.==61.)||(33.==62.)||(33.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "C1MB33_ID,CAN1 Mailbox 33 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "C1MB33_ID,CAN1 Mailbox 33 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "C1MB33_ID,CAN1 Mailbox 33 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1E0++0x03
|
|
hide.long 0x00 "C1MB33_ID,CAN1 Mailbox 33 Register"
|
|
endif
|
|
group.word (0x1E0+0x04)++0x1
|
|
line.word 0x00 "C1MB33_DLC,CAN1 Mailbox 33 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1E0+0x06)++0x07
|
|
line.byte 0x00 "C1MB33_D0,CAN1 Mailbox 33 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB33_D1,CAN1 Mailbox 33 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB33_D2,CAN1 Mailbox 33 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB33_D3,CAN1 Mailbox 33 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB33_D4,CAN1 Mailbox 33 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB33_D5,CAN1 Mailbox 33 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB33_D6,CAN1 Mailbox 33 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB33_D7,CAN1 Mailbox 33 Data byte 7 Register"
|
|
group.word (0x1E0+0x0e)++0x01
|
|
line.word 0x00 "C1MB33_TS,CAN1 Mailbox 33 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((32.==60.)||(32.==61.)||(32.==62.)||(32.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "C1MB32_ID,CAN1 Mailbox 32 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "C1MB32_ID,CAN1 Mailbox 32 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x1F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "C1MB32_ID,CAN1 Mailbox 32 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x1F0++0x03
|
|
hide.long 0x00 "C1MB32_ID,CAN1 Mailbox 32 Register"
|
|
endif
|
|
group.word (0x1F0+0x04)++0x1
|
|
line.word 0x00 "C1MB32_DLC,CAN1 Mailbox 32 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x1F0+0x06)++0x07
|
|
line.byte 0x00 "C1MB32_D0,CAN1 Mailbox 32 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB32_D1,CAN1 Mailbox 32 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB32_D2,CAN1 Mailbox 32 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB32_D3,CAN1 Mailbox 32 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB32_D4,CAN1 Mailbox 32 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB32_D5,CAN1 Mailbox 32 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB32_D6,CAN1 Mailbox 32 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB32_D7,CAN1 Mailbox 32 Data byte 7 Register"
|
|
group.word (0x1F0+0x0e)++0x01
|
|
line.word 0x00 "C1MB32_TS,CAN1 Mailbox 32 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((31.==60.)||(31.==61.)||(31.==62.)||(31.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "C1MB31_ID,CAN1 Mailbox 31 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x200))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "C1MB31_ID,CAN1 Mailbox 31 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x200))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "C1MB31_ID,CAN1 Mailbox 31 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "C1MB31_ID,CAN1 Mailbox 31 Register"
|
|
endif
|
|
group.word (0x200+0x04)++0x1
|
|
line.word 0x00 "C1MB31_DLC,CAN1 Mailbox 31 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x200+0x06)++0x07
|
|
line.byte 0x00 "C1MB31_D0,CAN1 Mailbox 31 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB31_D1,CAN1 Mailbox 31 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB31_D2,CAN1 Mailbox 31 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB31_D3,CAN1 Mailbox 31 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB31_D4,CAN1 Mailbox 31 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB31_D5,CAN1 Mailbox 31 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB31_D6,CAN1 Mailbox 31 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB31_D7,CAN1 Mailbox 31 Data byte 7 Register"
|
|
group.word (0x200+0x0e)++0x01
|
|
line.word 0x00 "C1MB31_TS,CAN1 Mailbox 31 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((30.==60.)||(30.==61.)||(30.==62.)||(30.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "C1MB30_ID,CAN1 Mailbox 30 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x210))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C1MB30_ID,CAN1 Mailbox 30 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x210))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C1MB30_ID,CAN1 Mailbox 30 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "C1MB30_ID,CAN1 Mailbox 30 Register"
|
|
endif
|
|
group.word (0x210+0x04)++0x1
|
|
line.word 0x00 "C1MB30_DLC,CAN1 Mailbox 30 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x210+0x06)++0x07
|
|
line.byte 0x00 "C1MB30_D0,CAN1 Mailbox 30 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB30_D1,CAN1 Mailbox 30 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB30_D2,CAN1 Mailbox 30 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB30_D3,CAN1 Mailbox 30 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB30_D4,CAN1 Mailbox 30 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB30_D5,CAN1 Mailbox 30 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB30_D6,CAN1 Mailbox 30 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB30_D7,CAN1 Mailbox 30 Data byte 7 Register"
|
|
group.word (0x210+0x0e)++0x01
|
|
line.word 0x00 "C1MB30_TS,CAN1 Mailbox 30 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((29.==60.)||(29.==61.)||(29.==62.)||(29.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "C1MB29_ID,CAN1 Mailbox 29 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x220))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C1MB29_ID,CAN1 Mailbox 29 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x220))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C1MB29_ID,CAN1 Mailbox 29 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "C1MB29_ID,CAN1 Mailbox 29 Register"
|
|
endif
|
|
group.word (0x220+0x04)++0x1
|
|
line.word 0x00 "C1MB29_DLC,CAN1 Mailbox 29 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x220+0x06)++0x07
|
|
line.byte 0x00 "C1MB29_D0,CAN1 Mailbox 29 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB29_D1,CAN1 Mailbox 29 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB29_D2,CAN1 Mailbox 29 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB29_D3,CAN1 Mailbox 29 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB29_D4,CAN1 Mailbox 29 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB29_D5,CAN1 Mailbox 29 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB29_D6,CAN1 Mailbox 29 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB29_D7,CAN1 Mailbox 29 Data byte 7 Register"
|
|
group.word (0x220+0x0e)++0x01
|
|
line.word 0x00 "C1MB29_TS,CAN1 Mailbox 29 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((28.==60.)||(28.==61.)||(28.==62.)||(28.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "C1MB28_ID,CAN1 Mailbox 28 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x230))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "C1MB28_ID,CAN1 Mailbox 28 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x230))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "C1MB28_ID,CAN1 Mailbox 28 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "C1MB28_ID,CAN1 Mailbox 28 Register"
|
|
endif
|
|
group.word (0x230+0x04)++0x1
|
|
line.word 0x00 "C1MB28_DLC,CAN1 Mailbox 28 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x230+0x06)++0x07
|
|
line.byte 0x00 "C1MB28_D0,CAN1 Mailbox 28 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB28_D1,CAN1 Mailbox 28 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB28_D2,CAN1 Mailbox 28 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB28_D3,CAN1 Mailbox 28 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB28_D4,CAN1 Mailbox 28 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB28_D5,CAN1 Mailbox 28 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB28_D6,CAN1 Mailbox 28 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB28_D7,CAN1 Mailbox 28 Data byte 7 Register"
|
|
group.word (0x230+0x0e)++0x01
|
|
line.word 0x00 "C1MB28_TS,CAN1 Mailbox 28 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((27.==60.)||(27.==61.)||(27.==62.)||(27.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "C1MB27_ID,CAN1 Mailbox 27 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x240))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "C1MB27_ID,CAN1 Mailbox 27 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x240))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "C1MB27_ID,CAN1 Mailbox 27 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "C1MB27_ID,CAN1 Mailbox 27 Register"
|
|
endif
|
|
group.word (0x240+0x04)++0x1
|
|
line.word 0x00 "C1MB27_DLC,CAN1 Mailbox 27 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x240+0x06)++0x07
|
|
line.byte 0x00 "C1MB27_D0,CAN1 Mailbox 27 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB27_D1,CAN1 Mailbox 27 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB27_D2,CAN1 Mailbox 27 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB27_D3,CAN1 Mailbox 27 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB27_D4,CAN1 Mailbox 27 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB27_D5,CAN1 Mailbox 27 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB27_D6,CAN1 Mailbox 27 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB27_D7,CAN1 Mailbox 27 Data byte 7 Register"
|
|
group.word (0x240+0x0e)++0x01
|
|
line.word 0x00 "C1MB27_TS,CAN1 Mailbox 27 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((26.==60.)||(26.==61.)||(26.==62.)||(26.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "C1MB26_ID,CAN1 Mailbox 26 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x250))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "C1MB26_ID,CAN1 Mailbox 26 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x250))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "C1MB26_ID,CAN1 Mailbox 26 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "C1MB26_ID,CAN1 Mailbox 26 Register"
|
|
endif
|
|
group.word (0x250+0x04)++0x1
|
|
line.word 0x00 "C1MB26_DLC,CAN1 Mailbox 26 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x250+0x06)++0x07
|
|
line.byte 0x00 "C1MB26_D0,CAN1 Mailbox 26 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB26_D1,CAN1 Mailbox 26 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB26_D2,CAN1 Mailbox 26 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB26_D3,CAN1 Mailbox 26 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB26_D4,CAN1 Mailbox 26 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB26_D5,CAN1 Mailbox 26 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB26_D6,CAN1 Mailbox 26 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB26_D7,CAN1 Mailbox 26 Data byte 7 Register"
|
|
group.word (0x250+0x0e)++0x01
|
|
line.word 0x00 "C1MB26_TS,CAN1 Mailbox 26 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((25.==60.)||(25.==61.)||(25.==62.)||(25.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "C1MB25_ID,CAN1 Mailbox 25 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x260))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "C1MB25_ID,CAN1 Mailbox 25 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x260))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "C1MB25_ID,CAN1 Mailbox 25 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "C1MB25_ID,CAN1 Mailbox 25 Register"
|
|
endif
|
|
group.word (0x260+0x04)++0x1
|
|
line.word 0x00 "C1MB25_DLC,CAN1 Mailbox 25 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x260+0x06)++0x07
|
|
line.byte 0x00 "C1MB25_D0,CAN1 Mailbox 25 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB25_D1,CAN1 Mailbox 25 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB25_D2,CAN1 Mailbox 25 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB25_D3,CAN1 Mailbox 25 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB25_D4,CAN1 Mailbox 25 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB25_D5,CAN1 Mailbox 25 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB25_D6,CAN1 Mailbox 25 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB25_D7,CAN1 Mailbox 25 Data byte 7 Register"
|
|
group.word (0x260+0x0e)++0x01
|
|
line.word 0x00 "C1MB25_TS,CAN1 Mailbox 25 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((24.==60.)||(24.==61.)||(24.==62.)||(24.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "C1MB24_ID,CAN1 Mailbox 24 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x270))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "C1MB24_ID,CAN1 Mailbox 24 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x270))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "C1MB24_ID,CAN1 Mailbox 24 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "C1MB24_ID,CAN1 Mailbox 24 Register"
|
|
endif
|
|
group.word (0x270+0x04)++0x1
|
|
line.word 0x00 "C1MB24_DLC,CAN1 Mailbox 24 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x270+0x06)++0x07
|
|
line.byte 0x00 "C1MB24_D0,CAN1 Mailbox 24 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB24_D1,CAN1 Mailbox 24 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB24_D2,CAN1 Mailbox 24 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB24_D3,CAN1 Mailbox 24 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB24_D4,CAN1 Mailbox 24 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB24_D5,CAN1 Mailbox 24 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB24_D6,CAN1 Mailbox 24 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB24_D7,CAN1 Mailbox 24 Data byte 7 Register"
|
|
group.word (0x270+0x0e)++0x01
|
|
line.word 0x00 "C1MB24_TS,CAN1 Mailbox 24 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((23.==60.)||(23.==61.)||(23.==62.)||(23.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "C1MB23_ID,CAN1 Mailbox 23 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x280))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "C1MB23_ID,CAN1 Mailbox 23 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x280))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "C1MB23_ID,CAN1 Mailbox 23 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "C1MB23_ID,CAN1 Mailbox 23 Register"
|
|
endif
|
|
group.word (0x280+0x04)++0x1
|
|
line.word 0x00 "C1MB23_DLC,CAN1 Mailbox 23 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x280+0x06)++0x07
|
|
line.byte 0x00 "C1MB23_D0,CAN1 Mailbox 23 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB23_D1,CAN1 Mailbox 23 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB23_D2,CAN1 Mailbox 23 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB23_D3,CAN1 Mailbox 23 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB23_D4,CAN1 Mailbox 23 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB23_D5,CAN1 Mailbox 23 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB23_D6,CAN1 Mailbox 23 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB23_D7,CAN1 Mailbox 23 Data byte 7 Register"
|
|
group.word (0x280+0x0e)++0x01
|
|
line.word 0x00 "C1MB23_TS,CAN1 Mailbox 23 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((22.==60.)||(22.==61.)||(22.==62.)||(22.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "C1MB22_ID,CAN1 Mailbox 22 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x290))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "C1MB22_ID,CAN1 Mailbox 22 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x290))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "C1MB22_ID,CAN1 Mailbox 22 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "C1MB22_ID,CAN1 Mailbox 22 Register"
|
|
endif
|
|
group.word (0x290+0x04)++0x1
|
|
line.word 0x00 "C1MB22_DLC,CAN1 Mailbox 22 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x290+0x06)++0x07
|
|
line.byte 0x00 "C1MB22_D0,CAN1 Mailbox 22 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB22_D1,CAN1 Mailbox 22 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB22_D2,CAN1 Mailbox 22 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB22_D3,CAN1 Mailbox 22 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB22_D4,CAN1 Mailbox 22 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB22_D5,CAN1 Mailbox 22 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB22_D6,CAN1 Mailbox 22 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB22_D7,CAN1 Mailbox 22 Data byte 7 Register"
|
|
group.word (0x290+0x0e)++0x01
|
|
line.word 0x00 "C1MB22_TS,CAN1 Mailbox 22 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((21.==60.)||(21.==61.)||(21.==62.)||(21.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "C1MB21_ID,CAN1 Mailbox 21 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "C1MB21_ID,CAN1 Mailbox 21 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "C1MB21_ID,CAN1 Mailbox 21 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "C1MB21_ID,CAN1 Mailbox 21 Register"
|
|
endif
|
|
group.word (0x2A0+0x04)++0x1
|
|
line.word 0x00 "C1MB21_DLC,CAN1 Mailbox 21 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2A0+0x06)++0x07
|
|
line.byte 0x00 "C1MB21_D0,CAN1 Mailbox 21 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB21_D1,CAN1 Mailbox 21 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB21_D2,CAN1 Mailbox 21 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB21_D3,CAN1 Mailbox 21 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB21_D4,CAN1 Mailbox 21 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB21_D5,CAN1 Mailbox 21 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB21_D6,CAN1 Mailbox 21 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB21_D7,CAN1 Mailbox 21 Data byte 7 Register"
|
|
group.word (0x2A0+0x0e)++0x01
|
|
line.word 0x00 "C1MB21_TS,CAN1 Mailbox 21 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((20.==60.)||(20.==61.)||(20.==62.)||(20.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "C1MB20_ID,CAN1 Mailbox 20 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "C1MB20_ID,CAN1 Mailbox 20 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "C1MB20_ID,CAN1 Mailbox 20 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "C1MB20_ID,CAN1 Mailbox 20 Register"
|
|
endif
|
|
group.word (0x2B0+0x04)++0x1
|
|
line.word 0x00 "C1MB20_DLC,CAN1 Mailbox 20 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2B0+0x06)++0x07
|
|
line.byte 0x00 "C1MB20_D0,CAN1 Mailbox 20 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB20_D1,CAN1 Mailbox 20 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB20_D2,CAN1 Mailbox 20 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB20_D3,CAN1 Mailbox 20 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB20_D4,CAN1 Mailbox 20 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB20_D5,CAN1 Mailbox 20 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB20_D6,CAN1 Mailbox 20 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB20_D7,CAN1 Mailbox 20 Data byte 7 Register"
|
|
group.word (0x2B0+0x0e)++0x01
|
|
line.word 0x00 "C1MB20_TS,CAN1 Mailbox 20 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((19.==60.)||(19.==61.)||(19.==62.)||(19.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "C1MB19_ID,CAN1 Mailbox 19 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "C1MB19_ID,CAN1 Mailbox 19 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "C1MB19_ID,CAN1 Mailbox 19 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "C1MB19_ID,CAN1 Mailbox 19 Register"
|
|
endif
|
|
group.word (0x2C0+0x04)++0x1
|
|
line.word 0x00 "C1MB19_DLC,CAN1 Mailbox 19 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2C0+0x06)++0x07
|
|
line.byte 0x00 "C1MB19_D0,CAN1 Mailbox 19 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB19_D1,CAN1 Mailbox 19 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB19_D2,CAN1 Mailbox 19 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB19_D3,CAN1 Mailbox 19 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB19_D4,CAN1 Mailbox 19 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB19_D5,CAN1 Mailbox 19 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB19_D6,CAN1 Mailbox 19 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB19_D7,CAN1 Mailbox 19 Data byte 7 Register"
|
|
group.word (0x2C0+0x0e)++0x01
|
|
line.word 0x00 "C1MB19_TS,CAN1 Mailbox 19 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((18.==60.)||(18.==61.)||(18.==62.)||(18.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "C1MB18_ID,CAN1 Mailbox 18 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "C1MB18_ID,CAN1 Mailbox 18 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "C1MB18_ID,CAN1 Mailbox 18 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "C1MB18_ID,CAN1 Mailbox 18 Register"
|
|
endif
|
|
group.word (0x2D0+0x04)++0x1
|
|
line.word 0x00 "C1MB18_DLC,CAN1 Mailbox 18 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2D0+0x06)++0x07
|
|
line.byte 0x00 "C1MB18_D0,CAN1 Mailbox 18 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB18_D1,CAN1 Mailbox 18 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB18_D2,CAN1 Mailbox 18 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB18_D3,CAN1 Mailbox 18 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB18_D4,CAN1 Mailbox 18 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB18_D5,CAN1 Mailbox 18 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB18_D6,CAN1 Mailbox 18 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB18_D7,CAN1 Mailbox 18 Data byte 7 Register"
|
|
group.word (0x2D0+0x0e)++0x01
|
|
line.word 0x00 "C1MB18_TS,CAN1 Mailbox 18 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((17.==60.)||(17.==61.)||(17.==62.)||(17.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "C1MB17_ID,CAN1 Mailbox 17 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "C1MB17_ID,CAN1 Mailbox 17 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "C1MB17_ID,CAN1 Mailbox 17 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "C1MB17_ID,CAN1 Mailbox 17 Register"
|
|
endif
|
|
group.word (0x2E0+0x04)++0x1
|
|
line.word 0x00 "C1MB17_DLC,CAN1 Mailbox 17 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2E0+0x06)++0x07
|
|
line.byte 0x00 "C1MB17_D0,CAN1 Mailbox 17 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB17_D1,CAN1 Mailbox 17 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB17_D2,CAN1 Mailbox 17 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB17_D3,CAN1 Mailbox 17 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB17_D4,CAN1 Mailbox 17 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB17_D5,CAN1 Mailbox 17 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB17_D6,CAN1 Mailbox 17 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB17_D7,CAN1 Mailbox 17 Data byte 7 Register"
|
|
group.word (0x2E0+0x0e)++0x01
|
|
line.word 0x00 "C1MB17_TS,CAN1 Mailbox 17 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((16.==60.)||(16.==61.)||(16.==62.)||(16.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "C1MB16_ID,CAN1 Mailbox 16 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "C1MB16_ID,CAN1 Mailbox 16 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x2F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "C1MB16_ID,CAN1 Mailbox 16 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "C1MB16_ID,CAN1 Mailbox 16 Register"
|
|
endif
|
|
group.word (0x2F0+0x04)++0x1
|
|
line.word 0x00 "C1MB16_DLC,CAN1 Mailbox 16 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x2F0+0x06)++0x07
|
|
line.byte 0x00 "C1MB16_D0,CAN1 Mailbox 16 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB16_D1,CAN1 Mailbox 16 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB16_D2,CAN1 Mailbox 16 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB16_D3,CAN1 Mailbox 16 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB16_D4,CAN1 Mailbox 16 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB16_D5,CAN1 Mailbox 16 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB16_D6,CAN1 Mailbox 16 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB16_D7,CAN1 Mailbox 16 Data byte 7 Register"
|
|
group.word (0x2F0+0x0e)++0x01
|
|
line.word 0x00 "C1MB16_TS,CAN1 Mailbox 16 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((15.==60.)||(15.==61.)||(15.==62.)||(15.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "C1MB15_ID,CAN1 Mailbox 15 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x300))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "C1MB15_ID,CAN1 Mailbox 15 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x300))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "C1MB15_ID,CAN1 Mailbox 15 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "C1MB15_ID,CAN1 Mailbox 15 Register"
|
|
endif
|
|
group.word (0x300+0x04)++0x1
|
|
line.word 0x00 "C1MB15_DLC,CAN1 Mailbox 15 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x300+0x06)++0x07
|
|
line.byte 0x00 "C1MB15_D0,CAN1 Mailbox 15 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB15_D1,CAN1 Mailbox 15 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB15_D2,CAN1 Mailbox 15 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB15_D3,CAN1 Mailbox 15 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB15_D4,CAN1 Mailbox 15 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB15_D5,CAN1 Mailbox 15 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB15_D6,CAN1 Mailbox 15 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB15_D7,CAN1 Mailbox 15 Data byte 7 Register"
|
|
group.word (0x300+0x0e)++0x01
|
|
line.word 0x00 "C1MB15_TS,CAN1 Mailbox 15 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((14.==60.)||(14.==61.)||(14.==62.)||(14.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "C1MB14_ID,CAN1 Mailbox 14 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x310))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "C1MB14_ID,CAN1 Mailbox 14 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x310))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "C1MB14_ID,CAN1 Mailbox 14 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "C1MB14_ID,CAN1 Mailbox 14 Register"
|
|
endif
|
|
group.word (0x310+0x04)++0x1
|
|
line.word 0x00 "C1MB14_DLC,CAN1 Mailbox 14 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x310+0x06)++0x07
|
|
line.byte 0x00 "C1MB14_D0,CAN1 Mailbox 14 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB14_D1,CAN1 Mailbox 14 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB14_D2,CAN1 Mailbox 14 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB14_D3,CAN1 Mailbox 14 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB14_D4,CAN1 Mailbox 14 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB14_D5,CAN1 Mailbox 14 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB14_D6,CAN1 Mailbox 14 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB14_D7,CAN1 Mailbox 14 Data byte 7 Register"
|
|
group.word (0x310+0x0e)++0x01
|
|
line.word 0x00 "C1MB14_TS,CAN1 Mailbox 14 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((13.==60.)||(13.==61.)||(13.==62.)||(13.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "C1MB13_ID,CAN1 Mailbox 13 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x320))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "C1MB13_ID,CAN1 Mailbox 13 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x320))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "C1MB13_ID,CAN1 Mailbox 13 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "C1MB13_ID,CAN1 Mailbox 13 Register"
|
|
endif
|
|
group.word (0x320+0x04)++0x1
|
|
line.word 0x00 "C1MB13_DLC,CAN1 Mailbox 13 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x320+0x06)++0x07
|
|
line.byte 0x00 "C1MB13_D0,CAN1 Mailbox 13 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB13_D1,CAN1 Mailbox 13 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB13_D2,CAN1 Mailbox 13 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB13_D3,CAN1 Mailbox 13 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB13_D4,CAN1 Mailbox 13 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB13_D5,CAN1 Mailbox 13 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB13_D6,CAN1 Mailbox 13 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB13_D7,CAN1 Mailbox 13 Data byte 7 Register"
|
|
group.word (0x320+0x0e)++0x01
|
|
line.word 0x00 "C1MB13_TS,CAN1 Mailbox 13 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((12.==60.)||(12.==61.)||(12.==62.)||(12.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "C1MB12_ID,CAN1 Mailbox 12 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x330))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "C1MB12_ID,CAN1 Mailbox 12 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x330))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "C1MB12_ID,CAN1 Mailbox 12 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "C1MB12_ID,CAN1 Mailbox 12 Register"
|
|
endif
|
|
group.word (0x330+0x04)++0x1
|
|
line.word 0x00 "C1MB12_DLC,CAN1 Mailbox 12 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x330+0x06)++0x07
|
|
line.byte 0x00 "C1MB12_D0,CAN1 Mailbox 12 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB12_D1,CAN1 Mailbox 12 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB12_D2,CAN1 Mailbox 12 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB12_D3,CAN1 Mailbox 12 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB12_D4,CAN1 Mailbox 12 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB12_D5,CAN1 Mailbox 12 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB12_D6,CAN1 Mailbox 12 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB12_D7,CAN1 Mailbox 12 Data byte 7 Register"
|
|
group.word (0x330+0x0e)++0x01
|
|
line.word 0x00 "C1MB12_TS,CAN1 Mailbox 12 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((11.==60.)||(11.==61.)||(11.==62.)||(11.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "C1MB11_ID,CAN1 Mailbox 11 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x340))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "C1MB11_ID,CAN1 Mailbox 11 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x340))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "C1MB11_ID,CAN1 Mailbox 11 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "C1MB11_ID,CAN1 Mailbox 11 Register"
|
|
endif
|
|
group.word (0x340+0x04)++0x1
|
|
line.word 0x00 "C1MB11_DLC,CAN1 Mailbox 11 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x340+0x06)++0x07
|
|
line.byte 0x00 "C1MB11_D0,CAN1 Mailbox 11 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB11_D1,CAN1 Mailbox 11 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB11_D2,CAN1 Mailbox 11 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB11_D3,CAN1 Mailbox 11 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB11_D4,CAN1 Mailbox 11 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB11_D5,CAN1 Mailbox 11 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB11_D6,CAN1 Mailbox 11 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB11_D7,CAN1 Mailbox 11 Data byte 7 Register"
|
|
group.word (0x340+0x0e)++0x01
|
|
line.word 0x00 "C1MB11_TS,CAN1 Mailbox 11 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((10.==60.)||(10.==61.)||(10.==62.)||(10.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "C1MB10_ID,CAN1 Mailbox 10 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x350))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "C1MB10_ID,CAN1 Mailbox 10 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x350))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "C1MB10_ID,CAN1 Mailbox 10 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "C1MB10_ID,CAN1 Mailbox 10 Register"
|
|
endif
|
|
group.word (0x350+0x04)++0x1
|
|
line.word 0x00 "C1MB10_DLC,CAN1 Mailbox 10 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x350+0x06)++0x07
|
|
line.byte 0x00 "C1MB10_D0,CAN1 Mailbox 10 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB10_D1,CAN1 Mailbox 10 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB10_D2,CAN1 Mailbox 10 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB10_D3,CAN1 Mailbox 10 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB10_D4,CAN1 Mailbox 10 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB10_D5,CAN1 Mailbox 10 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB10_D6,CAN1 Mailbox 10 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB10_D7,CAN1 Mailbox 10 Data byte 7 Register"
|
|
group.word (0x350+0x0e)++0x01
|
|
line.word 0x00 "C1MB10_TS,CAN1 Mailbox 10 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((9.==60.)||(9.==61.)||(9.==62.)||(9.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "C1MB9_ID,CAN1 Mailbox 9 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x360))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "C1MB9_ID,CAN1 Mailbox 9 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x360))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "C1MB9_ID,CAN1 Mailbox 9 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "C1MB9_ID,CAN1 Mailbox 9 Register"
|
|
endif
|
|
group.word (0x360+0x04)++0x1
|
|
line.word 0x00 "C1MB9_DLC,CAN1 Mailbox 9 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x360+0x06)++0x07
|
|
line.byte 0x00 "C1MB9_D0,CAN1 Mailbox 9 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB9_D1,CAN1 Mailbox 9 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB9_D2,CAN1 Mailbox 9 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB9_D3,CAN1 Mailbox 9 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB9_D4,CAN1 Mailbox 9 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB9_D5,CAN1 Mailbox 9 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB9_D6,CAN1 Mailbox 9 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB9_D7,CAN1 Mailbox 9 Data byte 7 Register"
|
|
group.word (0x360+0x0e)++0x01
|
|
line.word 0x00 "C1MB9_TS,CAN1 Mailbox 9 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((8.==60.)||(8.==61.)||(8.==62.)||(8.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "C1MB8_ID,CAN1 Mailbox 8 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x370))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "C1MB8_ID,CAN1 Mailbox 8 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x370))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "C1MB8_ID,CAN1 Mailbox 8 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "C1MB8_ID,CAN1 Mailbox 8 Register"
|
|
endif
|
|
group.word (0x370+0x04)++0x1
|
|
line.word 0x00 "C1MB8_DLC,CAN1 Mailbox 8 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x370+0x06)++0x07
|
|
line.byte 0x00 "C1MB8_D0,CAN1 Mailbox 8 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB8_D1,CAN1 Mailbox 8 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB8_D2,CAN1 Mailbox 8 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB8_D3,CAN1 Mailbox 8 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB8_D4,CAN1 Mailbox 8 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB8_D5,CAN1 Mailbox 8 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB8_D6,CAN1 Mailbox 8 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB8_D7,CAN1 Mailbox 8 Data byte 7 Register"
|
|
group.word (0x370+0x0e)++0x01
|
|
line.word 0x00 "C1MB8_TS,CAN1 Mailbox 8 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((7.==60.)||(7.==61.)||(7.==62.)||(7.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "C1MB7_ID,CAN1 Mailbox 7 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x380))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "C1MB7_ID,CAN1 Mailbox 7 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x380))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "C1MB7_ID,CAN1 Mailbox 7 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "C1MB7_ID,CAN1 Mailbox 7 Register"
|
|
endif
|
|
group.word (0x380+0x04)++0x1
|
|
line.word 0x00 "C1MB7_DLC,CAN1 Mailbox 7 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x380+0x06)++0x07
|
|
line.byte 0x00 "C1MB7_D0,CAN1 Mailbox 7 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB7_D1,CAN1 Mailbox 7 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB7_D2,CAN1 Mailbox 7 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB7_D3,CAN1 Mailbox 7 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB7_D4,CAN1 Mailbox 7 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB7_D5,CAN1 Mailbox 7 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB7_D6,CAN1 Mailbox 7 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB7_D7,CAN1 Mailbox 7 Data byte 7 Register"
|
|
group.word (0x380+0x0e)++0x01
|
|
line.word 0x00 "C1MB7_TS,CAN1 Mailbox 7 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((6.==60.)||(6.==61.)||(6.==62.)||(6.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "C1MB6_ID,CAN1 Mailbox 6 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x390))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "C1MB6_ID,CAN1 Mailbox 6 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x390))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "C1MB6_ID,CAN1 Mailbox 6 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "C1MB6_ID,CAN1 Mailbox 6 Register"
|
|
endif
|
|
group.word (0x390+0x04)++0x1
|
|
line.word 0x00 "C1MB6_DLC,CAN1 Mailbox 6 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x390+0x06)++0x07
|
|
line.byte 0x00 "C1MB6_D0,CAN1 Mailbox 6 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB6_D1,CAN1 Mailbox 6 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB6_D2,CAN1 Mailbox 6 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB6_D3,CAN1 Mailbox 6 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB6_D4,CAN1 Mailbox 6 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB6_D5,CAN1 Mailbox 6 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB6_D6,CAN1 Mailbox 6 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB6_D7,CAN1 Mailbox 6 Data byte 7 Register"
|
|
group.word (0x390+0x0e)++0x01
|
|
line.word 0x00 "C1MB6_TS,CAN1 Mailbox 6 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((5.==60.)||(5.==61.)||(5.==62.)||(5.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "C1MB5_ID,CAN1 Mailbox 5 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3A0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "C1MB5_ID,CAN1 Mailbox 5 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3A0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "C1MB5_ID,CAN1 Mailbox 5 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "C1MB5_ID,CAN1 Mailbox 5 Register"
|
|
endif
|
|
group.word (0x3A0+0x04)++0x1
|
|
line.word 0x00 "C1MB5_DLC,CAN1 Mailbox 5 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3A0+0x06)++0x07
|
|
line.byte 0x00 "C1MB5_D0,CAN1 Mailbox 5 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB5_D1,CAN1 Mailbox 5 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB5_D2,CAN1 Mailbox 5 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB5_D3,CAN1 Mailbox 5 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB5_D4,CAN1 Mailbox 5 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB5_D5,CAN1 Mailbox 5 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB5_D6,CAN1 Mailbox 5 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB5_D7,CAN1 Mailbox 5 Data byte 7 Register"
|
|
group.word (0x3A0+0x0e)++0x01
|
|
line.word 0x00 "C1MB5_TS,CAN1 Mailbox 5 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((4.==60.)||(4.==61.)||(4.==62.)||(4.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "C1MB4_ID,CAN1 Mailbox 4 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3B0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "C1MB4_ID,CAN1 Mailbox 4 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3B0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "C1MB4_ID,CAN1 Mailbox 4 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "C1MB4_ID,CAN1 Mailbox 4 Register"
|
|
endif
|
|
group.word (0x3B0+0x04)++0x1
|
|
line.word 0x00 "C1MB4_DLC,CAN1 Mailbox 4 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3B0+0x06)++0x07
|
|
line.byte 0x00 "C1MB4_D0,CAN1 Mailbox 4 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB4_D1,CAN1 Mailbox 4 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB4_D2,CAN1 Mailbox 4 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB4_D3,CAN1 Mailbox 4 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB4_D4,CAN1 Mailbox 4 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB4_D5,CAN1 Mailbox 4 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB4_D6,CAN1 Mailbox 4 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB4_D7,CAN1 Mailbox 4 Data byte 7 Register"
|
|
group.word (0x3B0+0x0e)++0x01
|
|
line.word 0x00 "C1MB4_TS,CAN1 Mailbox 4 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((3.==60.)||(3.==61.)||(3.==62.)||(3.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "C1MB3_ID,CAN1 Mailbox 3 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3C0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "C1MB3_ID,CAN1 Mailbox 3 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3C0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "C1MB3_ID,CAN1 Mailbox 3 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "C1MB3_ID,CAN1 Mailbox 3 Register"
|
|
endif
|
|
group.word (0x3C0+0x04)++0x1
|
|
line.word 0x00 "C1MB3_DLC,CAN1 Mailbox 3 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3C0+0x06)++0x07
|
|
line.byte 0x00 "C1MB3_D0,CAN1 Mailbox 3 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB3_D1,CAN1 Mailbox 3 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB3_D2,CAN1 Mailbox 3 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB3_D3,CAN1 Mailbox 3 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB3_D4,CAN1 Mailbox 3 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB3_D5,CAN1 Mailbox 3 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB3_D6,CAN1 Mailbox 3 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB3_D7,CAN1 Mailbox 3 Data byte 7 Register"
|
|
group.word (0x3C0+0x0e)++0x01
|
|
line.word 0x00 "C1MB3_TS,CAN1 Mailbox 3 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((2.==60.)||(2.==61.)||(2.==62.)||(2.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "C1MB2_ID,CAN1 Mailbox 2 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3D0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "C1MB2_ID,CAN1 Mailbox 2 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3D0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "C1MB2_ID,CAN1 Mailbox 2 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "C1MB2_ID,CAN1 Mailbox 2 Register"
|
|
endif
|
|
group.word (0x3D0+0x04)++0x1
|
|
line.word 0x00 "C1MB2_DLC,CAN1 Mailbox 2 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3D0+0x06)++0x07
|
|
line.byte 0x00 "C1MB2_D0,CAN1 Mailbox 2 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB2_D1,CAN1 Mailbox 2 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB2_D2,CAN1 Mailbox 2 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB2_D3,CAN1 Mailbox 2 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB2_D4,CAN1 Mailbox 2 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB2_D5,CAN1 Mailbox 2 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB2_D6,CAN1 Mailbox 2 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB2_D7,CAN1 Mailbox 2 Data byte 7 Register"
|
|
group.word (0x3D0+0x0e)++0x01
|
|
line.word 0x00 "C1MB2_TS,CAN1 Mailbox 2 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((1.==60.)||(1.==61.)||(1.==62.)||(1.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "C1MB1_ID,CAN1 Mailbox 1 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3E0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "C1MB1_ID,CAN1 Mailbox 1 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3E0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "C1MB1_ID,CAN1 Mailbox 1 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "C1MB1_ID,CAN1 Mailbox 1 Register"
|
|
endif
|
|
group.word (0x3E0+0x04)++0x1
|
|
line.word 0x00 "C1MB1_DLC,CAN1 Mailbox 1 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3E0+0x06)++0x07
|
|
line.byte 0x00 "C1MB1_D0,CAN1 Mailbox 1 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB1_D1,CAN1 Mailbox 1 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB1_D2,CAN1 Mailbox 1 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB1_D3,CAN1 Mailbox 1 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB1_D4,CAN1 Mailbox 1 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB1_D5,CAN1 Mailbox 1 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB1_D6,CAN1 Mailbox 1 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB1_D7,CAN1 Mailbox 1 Data byte 7 Register"
|
|
group.word (0x3E0+0x0e)++0x01
|
|
line.word 0x00 "C1MB1_TS,CAN1 Mailbox 1 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
if (((0.==60.)||(0.==61.)||(0.==62.)||(0.==63.))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x1))
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "C1MB0_ID,CAN1 Mailbox 0 Register"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3F0))&0x80000000)==0x00000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x0))
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "C1MB0_ID,CAN1 Mailbox 0 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
elif (((((per.w(ad:0xFFFD1000+0x840))&0x6)==0x4)&&(((per.long(ad:0xFFFD1000+0x3F0))&0x80000000)==0x80000000))||(((per.w(ad:0xFFFD1000+0x840))&0x6)==0x2))
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "C1MB0_ID,CAN1 Mailbox 0 Register"
|
|
bitfld.long 0x0 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x0 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
textline " "
|
|
bitfld.long 0x0 28. " SID10 ,Standard ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 27. " SID9 ,Standard ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 26. " SID8 ,Standard ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SID7 ,Standard ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 24. " SID6 ,Standard ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 23. " SID5 ,Standard ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 22. " SID4 ,Standard ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 21. " SID3 ,Standard ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 20. " SID2 ,Standard ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 19. " SID1 ,Standard ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 18. " SID0 ,Standard ID Bit 0" "Low,High"
|
|
bitfld.long 0x0 17. " EID17 ,Extended ID Bit 17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 16. " EID16 ,Extended ID Bit 16" "Low,High"
|
|
bitfld.long 0x0 15. " EID15 ,Extended ID Bit 15" "Low,High"
|
|
bitfld.long 0x0 14. " EID14 ,Extended ID Bit 14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 13. " EID13 ,Extended ID Bit 13" "Low,High"
|
|
bitfld.long 0x0 12. " EID12 ,Extended ID Bit 12" "Low,High"
|
|
bitfld.long 0x0 11. " EID11 ,Extended ID Bit 11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " EID10 ,Extended ID Bit 10" "Low,High"
|
|
bitfld.long 0x0 9. " EID9 ,Extended ID Bit 9" "Low,High"
|
|
bitfld.long 0x0 8. " EID8 ,Extended ID Bit 8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 7. " EID7 ,Extended ID Bit 7" "Low,High"
|
|
bitfld.long 0x0 6. " EID6 ,Extended ID Bit 6" "Low,High"
|
|
bitfld.long 0x0 5. " EID5 ,Extended ID Bit 5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 4. " EID4 ,Extended ID Bit 4" "Low,High"
|
|
bitfld.long 0x0 3. " EID3 ,Extended ID Bit 3" "Low,High"
|
|
bitfld.long 0x0 2. " EID2 ,Extended ID Bit 2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EID1 ,Extended ID Bit 1" "Low,High"
|
|
bitfld.long 0x0 0. " EID0 ,Extended ID Bit 0" "Low,High"
|
|
else
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "C1MB0_ID,CAN1 Mailbox 0 Register"
|
|
endif
|
|
group.word (0x3F0+0x04)++0x1
|
|
line.word 0x00 "C1MB0_DLC,CAN1 Mailbox 0 Data Length Code Register"
|
|
bitfld.word 0x0 0.--3. " DLC ,Data Length Code Bits" "0 byte,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes,8 bytes"
|
|
group.byte (0x3F0+0x06)++0x07
|
|
line.byte 0x00 "C1MB0_D0,CAN1 Mailbox 0 Data byte 0 Register"
|
|
line.byte 0x01 "C1MB0_D1,CAN1 Mailbox 0 Data byte 1 Register"
|
|
line.byte 0x02 "C1MB0_D2,CAN1 Mailbox 0 Data byte 2 Register"
|
|
line.byte 0x03 "C1MB0_D3,CAN1 Mailbox 0 Data byte 3 Register"
|
|
line.byte 0x04 "C1MB0_D4,CAN1 Mailbox 0 Data byte 4 Register"
|
|
line.byte 0x05 "C1MB0_D5,CAN1 Mailbox 0 Data byte 5 Register"
|
|
line.byte 0x06 "C1MB0_D6,CAN1 Mailbox 0 Data byte 6 Register"
|
|
line.byte 0x07 "C1MB0_D7,CAN1 Mailbox 0 Data byte 7 Register"
|
|
group.word (0x3F0+0x0e)++0x01
|
|
line.word 0x00 "C1MB0_TS,CAN1 Mailbox 0 Time Stamp Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
tree.end
|
|
if (((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.long 0x42c++0x03
|
|
line.long 0x0 "C1MIER1,CAN1 Mailbox Interrupt Enable Register 1"
|
|
bitfld.long 0x00 31. " MB63 ,Mailbox 63 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB62 ,Mailbox 62 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB61 ,Mailbox 61 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB60 ,Mailbox 60 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MB59 ,Mailbox 59 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB58 ,Mailbox 58 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB57 ,Mailbox 57 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB56 ,Mailbox 56 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB55 ,Mailbox 55 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB54 ,Mailbox 54 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB53 ,Mailbox 53 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB52 ,Mailbox 52 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB51 ,Mailbox 51 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB50 ,Mailbox 50 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB49 ,Mailbox 49 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB48 ,Mailbox 48 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB47 ,Mailbox 47 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB46 ,Mailbox 46 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB45 ,Mailbox 45 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB44 ,Mailbox 44 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB43 ,Mailbox 43 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB42 ,Mailbox 42 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB41 ,Mailbox 41 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB40 ,Mailbox 40 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB39 ,Mailbox 39 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB38 ,Mailbox 38 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB37 ,Mailbox 37 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB36 ,Mailbox 36 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB35 ,Mailbox 35 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB34 ,Mailbox 34 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB33 ,Mailbox 33 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB32 ,Mailbox 32 Interrupt enabled" "Disabled,Enabled"
|
|
else
|
|
group.long 0x42c++0x03
|
|
line.long 0x0 "C1MR1,CAN1 Mailbox Interrupt Enable Register 1"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 29. " MB61 ,Receive FIFO Interrupt Generation Timing Control" "Every time,Buffer warning"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB60 ,Receive FIFO Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB57 ,Transmit FIFO Interrupt Generation Timing Control" "Every time,Buffer warning"
|
|
bitfld.long 0x00 24. " MB56 ,Transmit FIFO Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
bitfld.long 0x00 23. " MB55 ,Mailbox 55 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB54 ,Mailbox 54 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB53 ,Mailbox 53 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB52 ,Mailbox 52 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB51 ,Mailbox 51 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB50 ,Mailbox 50 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB49 ,Mailbox 49 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB48 ,Mailbox 48 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB47 ,Mailbox 47 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB46 ,Mailbox 46 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB45 ,Mailbox 45 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB44 ,Mailbox 44 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB43 ,Mailbox 43 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB42 ,Mailbox 42 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB41 ,Mailbox 41 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB40 ,Mailbox 40 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB39 ,Mailbox 39 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB38 ,Mailbox 38 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB37 ,Mailbox 37 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB36 ,Mailbox 36 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB35 ,Mailbox 35 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB34 ,Mailbox 34 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB33 ,Mailbox 33 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB32 ,Mailbox 32 Interrupt enabled" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x43c++0x03
|
|
line.long 0x0 "C1MIER0,CAN1 Mailbox Interrupt Enable Register 0"
|
|
bitfld.long 0x00 31. " MB31IE ,Mailbox 31 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB30IE ,Mailbox 30 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB29IE ,Mailbox 29 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB28IE ,Mailbox 28 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MB27IE ,Mailbox 27 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB26IE ,Mailbox 26 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB25IE ,Mailbox 25 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB24IE ,Mailbox 24 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB23IE ,Mailbox 23 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB22IE ,Mailbox 22 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB21IE ,Mailbox 21 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20IE ,Mailbox 20 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19IE ,Mailbox 19 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB18IE ,Mailbox 18 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17IE ,Mailbox 17 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB16IE ,Mailbox 16 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB15IE ,Mailbox 15 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14IE ,Mailbox 14 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB13IE ,Mailbox 13 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB12IE ,Mailbox 12 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB11IE ,Mailbox 11 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB10IE ,Mailbox 10 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB9IE ,Mailbox 9 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8IE ,Mailbox 8 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7IE ,Mailbox 7 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB6IE ,Mailbox 6 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5IE ,Mailbox 5 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB4IE ,Mailbox 4 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB3IE ,Mailbox 3 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2IE ,Mailbox 2 Interrupt enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB1IE ,Mailbox 1 Interrupt enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB0IE ,Mailbox 0 Interrupt enabled" "Disabled,Enabled"
|
|
tree "Message Control Registers"
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x0))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL63,CAN1 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x0))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL63,CAN1 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x0))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL63,CAN1 Message Control Register 63"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x0)++0x0
|
|
hide.byte 0x00 "C1MCTL63,CAN1 Message Control Register 63"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x1))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL62,CAN1 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x1))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL62,CAN1 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x1))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL62,CAN1 Message Control Register 62"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x1)++0x0
|
|
hide.byte 0x00 "C1MCTL62,CAN1 Message Control Register 62"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x2))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL61,CAN1 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x2))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL61,CAN1 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x2))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL61,CAN1 Message Control Register 61"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x2)++0x0
|
|
hide.byte 0x00 "C1MCTL61,CAN1 Message Control Register 61"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x3))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL60,CAN1 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x3))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL60,CAN1 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x3))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL60,CAN1 Message Control Register 60"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x3)++0x0
|
|
hide.byte 0x00 "C1MCTL60,CAN1 Message Control Register 60"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x4))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL59,CAN1 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x4))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL59,CAN1 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x4))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL59,CAN1 Message Control Register 59"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x4)++0x0
|
|
hide.byte 0x00 "C1MCTL59,CAN1 Message Control Register 59"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x5))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL58,CAN1 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x5))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL58,CAN1 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x5))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL58,CAN1 Message Control Register 58"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x5)++0x0
|
|
hide.byte 0x00 "C1MCTL58,CAN1 Message Control Register 58"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x6))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL57,CAN1 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x6))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL57,CAN1 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x6))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL57,CAN1 Message Control Register 57"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x6)++0x0
|
|
hide.byte 0x00 "C1MCTL57,CAN1 Message Control Register 57"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x800+0x7))&0xc0)==0x40)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL56,CAN1 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x7))&0xc0)==0x80)&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL56,CAN1 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x800+0x7))&0xc0)==(0xc0||0x00))&&(((per.w(ad:0xFFFD1000+0x840))&0x1)==0x0)
|
|
group.byte (0x800+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL56,CAN1 Message Control Register 56"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
else
|
|
hgroup.byte (0x800+0x7)++0x0
|
|
hide.byte 0x00 "C1MCTL56,CAN1 Message Control Register 56"
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x0))&0xc0)==0x40)
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL55,CAN1 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x0))&0xc0)==0x80)
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL55,CAN1 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x0)++0x0
|
|
line.byte 0x00 "C1MCTL55,CAN1 Message Control Register 55"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x1))&0xc0)==0x40)
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL54,CAN1 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x1))&0xc0)==0x80)
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL54,CAN1 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x1)++0x0
|
|
line.byte 0x00 "C1MCTL54,CAN1 Message Control Register 54"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x2))&0xc0)==0x40)
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL53,CAN1 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x2))&0xc0)==0x80)
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL53,CAN1 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x2)++0x0
|
|
line.byte 0x00 "C1MCTL53,CAN1 Message Control Register 53"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x3))&0xc0)==0x40)
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL52,CAN1 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x3))&0xc0)==0x80)
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL52,CAN1 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x3)++0x0
|
|
line.byte 0x00 "C1MCTL52,CAN1 Message Control Register 52"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x4))&0xc0)==0x40)
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL51,CAN1 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x4))&0xc0)==0x80)
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL51,CAN1 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x4)++0x0
|
|
line.byte 0x00 "C1MCTL51,CAN1 Message Control Register 51"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x5))&0xc0)==0x40)
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL50,CAN1 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x5))&0xc0)==0x80)
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL50,CAN1 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x5)++0x0
|
|
line.byte 0x00 "C1MCTL50,CAN1 Message Control Register 50"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x6))&0xc0)==0x40)
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL49,CAN1 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x6))&0xc0)==0x80)
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL49,CAN1 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x6)++0x0
|
|
line.byte 0x00 "C1MCTL49,CAN1 Message Control Register 49"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x7))&0xc0)==0x40)
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL48,CAN1 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x7))&0xc0)==0x80)
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL48,CAN1 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x7)++0x0
|
|
line.byte 0x00 "C1MCTL48,CAN1 Message Control Register 48"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x8))&0xc0)==0x40)
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C1MCTL47,CAN1 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x8))&0xc0)==0x80)
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C1MCTL47,CAN1 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x8)++0x0
|
|
line.byte 0x00 "C1MCTL47,CAN1 Message Control Register 47"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x9))&0xc0)==0x40)
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C1MCTL46,CAN1 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x9))&0xc0)==0x80)
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C1MCTL46,CAN1 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x9)++0x0
|
|
line.byte 0x00 "C1MCTL46,CAN1 Message Control Register 46"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xA))&0xc0)==0x40)
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C1MCTL45,CAN1 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xA))&0xc0)==0x80)
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C1MCTL45,CAN1 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xA)++0x0
|
|
line.byte 0x00 "C1MCTL45,CAN1 Message Control Register 45"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xB))&0xc0)==0x40)
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C1MCTL44,CAN1 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xB))&0xc0)==0x80)
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C1MCTL44,CAN1 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xB)++0x0
|
|
line.byte 0x00 "C1MCTL44,CAN1 Message Control Register 44"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xC))&0xc0)==0x40)
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C1MCTL43,CAN1 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xC))&0xc0)==0x80)
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C1MCTL43,CAN1 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xC)++0x0
|
|
line.byte 0x00 "C1MCTL43,CAN1 Message Control Register 43"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xD))&0xc0)==0x40)
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C1MCTL42,CAN1 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xD))&0xc0)==0x80)
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C1MCTL42,CAN1 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xD)++0x0
|
|
line.byte 0x00 "C1MCTL42,CAN1 Message Control Register 42"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xE))&0xc0)==0x40)
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C1MCTL41,CAN1 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xE))&0xc0)==0x80)
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C1MCTL41,CAN1 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xE)++0x0
|
|
line.byte 0x00 "C1MCTL41,CAN1 Message Control Register 41"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0xF))&0xc0)==0x40)
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C1MCTL40,CAN1 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0xF))&0xc0)==0x80)
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C1MCTL40,CAN1 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0xF)++0x0
|
|
line.byte 0x00 "C1MCTL40,CAN1 Message Control Register 40"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x10))&0xc0)==0x40)
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C1MCTL39,CAN1 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x10))&0xc0)==0x80)
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C1MCTL39,CAN1 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x10)++0x0
|
|
line.byte 0x00 "C1MCTL39,CAN1 Message Control Register 39"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x11))&0xc0)==0x40)
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C1MCTL38,CAN1 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x11))&0xc0)==0x80)
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C1MCTL38,CAN1 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x11)++0x0
|
|
line.byte 0x00 "C1MCTL38,CAN1 Message Control Register 38"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x12))&0xc0)==0x40)
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C1MCTL37,CAN1 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x12))&0xc0)==0x80)
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C1MCTL37,CAN1 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x12)++0x0
|
|
line.byte 0x00 "C1MCTL37,CAN1 Message Control Register 37"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x13))&0xc0)==0x40)
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C1MCTL36,CAN1 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x13))&0xc0)==0x80)
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C1MCTL36,CAN1 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x13)++0x0
|
|
line.byte 0x00 "C1MCTL36,CAN1 Message Control Register 36"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x14))&0xc0)==0x40)
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C1MCTL35,CAN1 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x14))&0xc0)==0x80)
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C1MCTL35,CAN1 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x14)++0x0
|
|
line.byte 0x00 "C1MCTL35,CAN1 Message Control Register 35"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x15))&0xc0)==0x40)
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C1MCTL34,CAN1 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x15))&0xc0)==0x80)
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C1MCTL34,CAN1 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x15)++0x0
|
|
line.byte 0x00 "C1MCTL34,CAN1 Message Control Register 34"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x16))&0xc0)==0x40)
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C1MCTL33,CAN1 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x16))&0xc0)==0x80)
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C1MCTL33,CAN1 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x16)++0x0
|
|
line.byte 0x00 "C1MCTL33,CAN1 Message Control Register 33"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
if (((per.b(ad:0xFFFD1000+0x808+0x17))&0xc0)==0x40)
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C1MCTL32,CAN1 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
elif (((per.b(ad:0xFFFD1000+0x808+0x17))&0xc0)==0x80)
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C1MCTL32,CAN1 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-shot Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not in progress,In progress"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not completed,Completed"
|
|
else
|
|
group.byte (0x808+0x17)++0x0
|
|
line.byte 0x00 "C1MCTL32,CAN1 Message Control Register 32"
|
|
bitfld.byte 0x00 6.--7. " TRMREQ/RECREQ ,Transmit Mailbox Request" ",Reception,Transmission,?..."
|
|
endif
|
|
group.byte 0x820++0x1f
|
|
line.byte 0x0 "C1MCTL31,CAN1 Message Control Register 31"
|
|
bitfld.byte 0x0 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x0 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x0 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1 "C1MCTL30,CAN1 Message Control Register 30"
|
|
bitfld.byte 0x1 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x2 "C1MCTL29,CAN1 Message Control Register 29"
|
|
bitfld.byte 0x2 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x2 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x2 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x2 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x3 "C1MCTL28,CAN1 Message Control Register 28"
|
|
bitfld.byte 0x3 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x3 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x3 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x3 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x4 "C1MCTL27,CAN1 Message Control Register 27"
|
|
bitfld.byte 0x4 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x4 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x4 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x4 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x5 "C1MCTL26,CAN1 Message Control Register 26"
|
|
bitfld.byte 0x5 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x5 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x5 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x5 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x6 "C1MCTL25,CAN1 Message Control Register 25"
|
|
bitfld.byte 0x6 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x6 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x6 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x6 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x7 "C1MCTL24,CAN1 Message Control Register 24"
|
|
bitfld.byte 0x7 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x7 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x7 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x7 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x8 "C1MCTL23,CAN1 Message Control Register 23"
|
|
bitfld.byte 0x8 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x8 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x8 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x8 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x9 "C1MCTL22,CAN1 Message Control Register 22"
|
|
bitfld.byte 0x9 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x9 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x9 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x9 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xA "C1MCTL21,CAN1 Message Control Register 21"
|
|
bitfld.byte 0xA 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xA 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xA 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xA 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xB "C1MCTL20,CAN1 Message Control Register 20"
|
|
bitfld.byte 0xB 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xB 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xB 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xB 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xC "C1MCTL19,CAN1 Message Control Register 19"
|
|
bitfld.byte 0xC 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xC 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xC 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xC 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xD "C1MCTL18,CAN1 Message Control Register 18"
|
|
bitfld.byte 0xD 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xD 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xD 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xD 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xE "C1MCTL17,CAN1 Message Control Register 17"
|
|
bitfld.byte 0xE 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xE 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xE 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xE 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0xF "C1MCTL16,CAN1 Message Control Register 16"
|
|
bitfld.byte 0xF 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0xF 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0xF 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0xF 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x10 "C1MCTL15,CAN1 Message Control Register 15"
|
|
bitfld.byte 0x10 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x10 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x10 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x10 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x11 "C1MCTL14,CAN1 Message Control Register 14"
|
|
bitfld.byte 0x11 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x11 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x11 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x11 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x12 "C1MCTL13,CAN1 Message Control Register 13"
|
|
bitfld.byte 0x12 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x12 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x12 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x12 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x13 "C1MCTL12,CAN1 Message Control Register 12"
|
|
bitfld.byte 0x13 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x13 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x13 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x13 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x14 "C1MCTL11,CAN1 Message Control Register 11"
|
|
bitfld.byte 0x14 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x14 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x14 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x14 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x15 "C1MCTL10,CAN1 Message Control Register 10"
|
|
bitfld.byte 0x15 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x15 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x15 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x15 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x16 "C1MCTL9,CAN1 Message Control Register 9"
|
|
bitfld.byte 0x16 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x16 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x16 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x16 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x17 "C1MCTL8,CAN1 Message Control Register 8"
|
|
bitfld.byte 0x17 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x17 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x17 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x17 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x18 "C1MCTL7,CAN1 Message Control Register 7"
|
|
bitfld.byte 0x18 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x18 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x18 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x18 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x19 "C1MCTL6,CAN1 Message Control Register 6"
|
|
bitfld.byte 0x19 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x19 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x19 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x19 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1A "C1MCTL5,CAN1 Message Control Register 5"
|
|
bitfld.byte 0x1A 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1A 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1A 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1A 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1B "C1MCTL4,CAN1 Message Control Register 4"
|
|
bitfld.byte 0x1B 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1B 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1B 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1B 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1C "C1MCTL3,CAN1 Message Control Register 3"
|
|
bitfld.byte 0x1C 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1C 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1C 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1C 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1D "C1MCTL2,CAN1 Message Control Register 2"
|
|
bitfld.byte 0x1D 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1D 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1D 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1D 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1E "C1MCTL1,CAN1 Message Control Register 1"
|
|
bitfld.byte 0x1E 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1E 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1E 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1E 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
line.byte 0x1F "C1MCTL0,CAN1 Message Control Register 0"
|
|
bitfld.byte 0x1F 6. " RECREQ ,Receive Mailbox Request" "Not requested,Requested"
|
|
bitfld.byte 0x1F 2. " MSGLOST ,Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x1F 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,Invalid"
|
|
bitfld.byte 0x1F 0. " NEWDATA ,Reception Complete Flag" "Not completed,Completed"
|
|
tree.end
|
|
group.byte 0x848++0x0
|
|
line.byte 0x0 "C1RFCR,CAN1 Receive FIFO Control Register"
|
|
bitfld.byte 0x00 7. " RFEST ,Receive FIFO Empty Status" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RFWST ,Receive FIFO Buffer Warning Status" "Not warning,Warning"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RFFST ,Receive FIFO Full Status" "Not full,Full"
|
|
bitfld.byte 0x00 4. " RFMLF ,Receive FIFO Message Lost Flag" "Not lost,Lost"
|
|
textline " "
|
|
bitfld.byte 0x00 1.--3. " RFUST ,Receive FIFO Unread Message Number Status" "0,1,2,3,4,?..."
|
|
bitfld.byte 0x00 0. " RFE ,Receive FIFO Enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xFFFD1000+0x848))&0x1)==0x00)
|
|
rgroup.byte 0x849++0x0
|
|
line.byte 0x0 "C1RFPCR,CAN1 Receive FIFO Pointer Control Register"
|
|
else
|
|
group.byte 0x849++0x0
|
|
line.byte 0x0 "C1RFPCR,CAN1 Receive FIFO Pointer Control Register"
|
|
endif
|
|
group.byte 0x84a++0x0
|
|
line.byte 0x0 "C1TFCR,CAN1 Transmit FIFO Control Register"
|
|
bitfld.byte 0x00 7. " TFEST ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " TFFST ,Transmit FIFO Full Status" "Not full,Full"
|
|
bitfld.byte 0x00 1.--3. " TFUST ,Transmit FIFO Unsent Message Number Status" "0,1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TFE ,Transmit FIFO Enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0xFFFD1000+0x84a))&0x1)==0x00)
|
|
rgroup.byte 0x84b++0x0
|
|
line.byte 0x0 "C1TFPCR,CAN1 Transmit FIFO Pointer Control Register"
|
|
else
|
|
group.byte 0x84b++0x0
|
|
line.byte 0x0 "C1TFPCR,CAN1 Transmit FIFO Pointer Control Register"
|
|
endif
|
|
rgroup.word 0x842++0x01
|
|
line.word 0x0 "C1STR,CAN1 Status Register"
|
|
bitfld.word 0x00 14. " RECST ,Receive Status Flag" "Idle/transmission,Reception"
|
|
textline " "
|
|
bitfld.word 0x00 13. " TRMST ,Transmit Status Flag" "Idle/reception,Transmission/bus-off"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BOST ,Bus-Off Status Flag" "Not bus-off,Bus-off"
|
|
bitfld.word 0x00 11. " EPST ,Error-Passive Status Flag" "Not error-passive,Error-passive"
|
|
bitfld.word 0x00 10. " SLPST ,CAN Sleep Status Flag" "Not CAN sleep,CAN sleep"
|
|
textline " "
|
|
bitfld.word 0x00 9. " HLTST ,CAN Halt Status Flag" "Not CAN halt,CAN halt"
|
|
bitfld.word 0x00 8. " RSTST ,CAN Reset Status Flag" "Not CAN reset,CAN reset"
|
|
bitfld.word 0x00 7. " EST ,Error Status Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TABST ,Transmission Abort Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " FMLST ,FIFO Mailbox Message Lost Status Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " NMLST ,Normal Mailbox Message Lost Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TFST ,Transmit FIFO Status Flag" "Full,Not full"
|
|
bitfld.word 0x00 2. " RFST ,Receive FIFO Status Flag" "Empty,Not empty"
|
|
bitfld.word 0x00 1. " SDST ,SENTDATA Status Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " NDST ,NEWDATA Status Flag" "Not occurred,Occurred"
|
|
wgroup.byte 0x851++0x00
|
|
line.byte 0x0 "C1CSSR,CAN1 Channel Search Support Register"
|
|
rgroup.byte 0x852++0x00
|
|
line.byte 0x0 "C1MSSR,CAN1 Mailbox Search Status Register"
|
|
bitfld.byte 0x00 7. " SEST ,Search Result Status" "Found,Not found"
|
|
bitfld.byte 0x00 0.--5. " MBNST ,Search Result Mailbox Number Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x853++0x00
|
|
line.byte 0x0 "C1MSMR,CAN1 Mailbox Search Mode Register"
|
|
bitfld.byte 0x00 0.--1. " MBSM ,Mailbox Search Mode Select" "Receive,Transmit,Message lost,Channel"
|
|
group.word 0x856++0x01
|
|
line.word 0x0 "C1AFSR,CAN1 Acceptance Filter Support Register"
|
|
group.byte 0x84c++0x01
|
|
line.byte 0x0 "C1EIER,CAN1 Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BLIE ,Bus Lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " OLIE ,Overload Frame Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ORIE ,Receive Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BORIE ,Bus-Off Recovery Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BOEIE ,Bus-Off Entry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EPIE ,Error-Passive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EWIE ,Error-Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "C1EIFR,CAN1 Error Interrupt Factor Judge Register"
|
|
bitfld.byte 0x01 7. " BLIF ,Bus Lock Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " OLIF ,Overload Frame Transmission Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 5. " ORIF ,Receive Overrun Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " BORIF ,Bus-Off Recovery Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 3. " BOEIF ,Bus-Off Entry Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 2. " EPIF ,Error Passive Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " EWIF ,Error Warning Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " BEIF ,Bus Error Detect Flag" "Not detected,Detected"
|
|
rgroup.byte 0x84e++0x01
|
|
line.byte 0x0 "C1RECR,CAN1 Receive Error Count Register"
|
|
line.byte 0x1 "C1TECR,CAN1 Transmit Error Count Register"
|
|
group.byte 0x850++0x00
|
|
line.byte 0x0 "C1ECSR,CAN1 Error Code Store Register"
|
|
bitfld.byte 0x0 7. " EDPM ,Error Display Mode Select" "First detected error,Accumulated error"
|
|
textline " "
|
|
bitfld.byte 0x0 6. " ADEF ,ACK Delimiter Error Flag" "No ACK delimiter,ACK delimiter"
|
|
textline " "
|
|
bitfld.byte 0x0 5. " BE0F ,Bit Error (dominant) Flag" "No error,Error"
|
|
bitfld.byte 0x0 4. " BE1F ,Bit Error (recessive) Flag" "No error,Error"
|
|
bitfld.byte 0x0 3. " CEF ,CRC Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " AEF ,ACK Error Flag" "No error,Error"
|
|
bitfld.byte 0x0 1. " FEF ,Form Error Flag" "No error,Error"
|
|
bitfld.byte 0x0 0. " SEF ,Stuff Error Flag" "No error,Error"
|
|
rgroup.word 0x854++0x01
|
|
line.word 0x0 "C1TSR,CAN1 Time Stamp Register"
|
|
group.byte 0x858++0x00
|
|
line.byte 0x0 "C1TCR,CAN1 Test Control Register"
|
|
bitfld.byte 0x0 1.--2. " TSTM ,CAN Test Mode Select" "Other,Listen-only,External loop back,Internal loop back"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " TSTE ,CAN Test Mode Enable" "Disabled,Enabled"
|
|
group.byte 0x860++0x01
|
|
line.byte 0x0 "C1IER,CAN1 Interrupt Enable Register"
|
|
bitfld.byte 0x0 5. " ERSIE ,Error (ERS) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 4. " RXFIE ,Reception FIFO (RXF) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 3. " TXFIE ,Transmission FIFO (TXF) Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 2. " RXM0IE ,Mailbox 0 Successful Reception (RXM0) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 1. " RXM1IE ,Mailbox 1 to 63 Successful Reception (RXM1) Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0 0. " TXMIE ,Mailbox 32 to 63 Successful Transmission (TXM) Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "C1ISR,CAN1 Interrupt Status Register"
|
|
bitfld.byte 0x01 5. " ERSF ,Error (ERS) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 4. " RXFF ,Reception FIFO (RXF) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 3. " TXFF ,Transmission FIFO (TXF) Interrupt Status" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " RXM0F ,Mailbox 0 Successful Reception (RXM0) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 1. " RXM1F ,Mailbox 1 to 63 Successful Reception (RXM1) Interrupt Status" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " TXMF ,Mailbox 32 to 63 Successful Transmission (TXM) Interrupt Status" "Not detected,Detected"
|
|
group.byte 0x863++0x00
|
|
line.byte 0x0 "C1MBSMR,CAN1 Mailbox Search Mask Register"
|
|
bitfld.byte 0x0 0. " MB0SM ,Mailbox 0 Search Mask" "Not masked,Masked"
|
|
sif cpu()=="R8A7792X"
|
|
group.byte 0x85C++0x00
|
|
line.byte 0x00 "C1PECR,CAN1 Parity Error Control Register"
|
|
bitfld.byte 0x00 7. " PF ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " PIE ,Parity Error Interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " PME ,Parity Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " PM ,Parity Mode" "Operation Mode,Halt mode"
|
|
group.word 0x85E++0x01
|
|
line.word 0x00 "C1PEACR,CAN1 Parity Error Address Capture Register"
|
|
hexmask.word 0x00 0.--10. 1. " PA ,Parity Error Captured Address Bits"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "MIMLCP (MOST Interface Module Light for Content Protection)"
|
|
base ad:0xFFD80000
|
|
width 24.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SWAP_MODE,SWAP_MODE Register"
|
|
bitfld.long 0x00 1. " WORD_SWAP_EN ,Swap word order enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BYTE_SWAP_EN ,Swap byte order enable" "Disabled,Enabled"
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "MOST_MODE1,MOST Mode Register 1"
|
|
bitfld.long 0x00 8. " CONTROL_RX_RDY ,Selects the method to clear the CSCR17.RDY bit of the OS62400" "Manual (software),Auto (hardware)"
|
|
bitfld.long 0x00 7. " PACKET_TX_DMA ,Sets the access type for packet transfer (transmission)" "PIO,DMA"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PACKET_RX_DMA ,Sets the access type for packet transfer (reception)" "PIO,DMA"
|
|
bitfld.long 0x00 0. " PACKET_RX_RDY ,Selects the method to clear the CSCR15.RDY bit of the OS62400" "Manual (software),Auto (hardware)"
|
|
line.long 0x04 "MOST_MODE2,MOST Mode Register 2"
|
|
bitfld.long 0x04 4. " STREAM_MIMLCP0_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " STREAM_MIMLCP0_SOURCE_MODE ,Selects the sound source to be transferred" "6 ch/24 bits/96 kHz,6 ch/24 bits/48 kHz,6 ch/16 bits/96 kHz,6 ch/16 bits/48 kHz,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,6 ch/24 bits/192 kHz,6 ch/16 bits/192 kHz,8 ch/24 bits/96 kHz,8 ch/24 bits/48 kHz,8 ch/16 bits/96 kHz,8 ch/16 bits/48 kHz"
|
|
line.long 0x08 "MOST_MODE3,MOST Mode Register 3"
|
|
bitfld.long 0x08 4. " STREAM_MIMLCP1_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " STREAM_MIMLCP1_SOURCE_MODE ,Selects the sound source to be transferred" "6 ch/24 bits/96 kHz,6 ch/24 bits/48 kHz,6 ch/16 bits/96 kHz,6 ch/16 bits/48 kHz,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,6 ch/24 bits/192 kHz,6 ch/16 bits/192 kHz,8 ch/24 bits/96 kHz,8 ch/24 bits/48 kHz,8 ch/16 bits/96 kHz,8 ch/16 bits/48 kHz"
|
|
group.long 0x24++0x17
|
|
line.long 0x00 "MOST_MODE6,MOST Mode Register 6"
|
|
bitfld.long 0x00 20. " STREAM_MIMLCP2_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " STREAM_MIMLCP2_SOURCE_MODE ,Selects the sound source to be transferred" ",,,,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,?..."
|
|
bitfld.long 0x00 7. " STREAM_MIMLCP7_DMA ,Sets the access type for CPU transfer" "PIO,DMA"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STREAM_MIMLCP7_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x00 0.--3. " STREAM_MIMLCP7_SOURCE_MODE ,Selects the sound source to be transferred" ",,,,,,,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,?..."
|
|
line.long 0x04 "MOST_MODE7,MOST Mode Register 7"
|
|
bitfld.long 0x04 20. " STREAM_MIMLCP3_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x04 16.--19. " STREAM_MIMLCP3_SOURCE_MODE ,Selects the sound source to be transferred" "6 ch/24 bits/96 kHz,6 ch/24 bits/48 kHz,6 ch/16 bits/96 kHz,6 ch/16 bits/48 kHz,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,6 ch/24 bits/192 kHz,6 ch/16 bits/192 kHz,8 ch/24 bits/96 kHz,8 ch/24 bits/48 kHz,8 ch/16 bits/96 kHz,8 ch/16 bits/48 kHz"
|
|
textline " "
|
|
bitfld.long 0x04 4. " STREAM_MIMLCP8_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x04 0.--3. " STREAM_MIMLCP8_SOURCE_MODE ,Selects the sound source to be transferred" ",,,,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,?..."
|
|
line.long 0x08 "MOST_MODE8,Most Mode Register 8"
|
|
bitfld.long 0x08 20. " STREAM_MIMLCP5_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x08 16.--19. " STREAM_MIMLCP5_SOURCE_MODE ,Selects the sound source to be transferred" ",,,,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4. " STREAM_MIMLCP4_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x08 0.--3. " STREAM_MIMLCP4_SOURCE_MODE ,Selects the sound source to be transferred" "6 ch/24 bits/96 kHz,6 ch/24 bits/48 kHz,6 ch/16 bits/96 kHz,6 ch/16 bits/48 kHz,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,6 ch/24 bits/192 kHz,6 ch/16 bits/192 kHz,8 ch/24 bits/96 kHz,8 ch/24 bits/48 kHz,8 ch/16 bits/96 kHz,8 ch/16 bits/48 kHz"
|
|
line.long 0x0c "MOST_MODE9,Most Mode Register 9"
|
|
bitfld.long 0x0c 4. " STREAM_MIMLCP6_TX ,Specifies the stream transfer direction" "Reception,Transmission"
|
|
bitfld.long 0x0c 0.--3. " STREAM_MIMLCP6_SOURCE_MODE ,Selects the sound source to be transferred" ",,,,2 ch/24 bits/192 kHz,2 ch/24 bits/96 kHz,2 ch/24 bits/48 kHz,2 ch/16 bits/192 kHz,2 ch/16 bits/96 kHz,2 ch/16 bits/48 kHz,?..."
|
|
line.long 0x10 "MOST_CONTROL1,MOST Control Register 1"
|
|
bitfld.long 0x10 19. " CONTROL_TX_START ,Controls the start and stop of control transfer (transmission)" "Stopped,Started"
|
|
bitfld.long 0x10 18. " CONTROL_RX_START ,Controls the start and stop of control transfer (reception)" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 17. " PACKET_TX_START ,Controls the start and stop of packet transfer (transmission)" "Stopped,Started"
|
|
bitfld.long 0x10 16. " PACKET_RX_START ,Controls the start and stop of packet transfer (reception)" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 12. " STREAM_MIMLCP6_START ,Controls the start and stop of STREAM_mimlcp6 transfer" "Stopped,Started"
|
|
bitfld.long 0x10 11. " STREAM_MIMLCP5_START ,Controls the start and stop of STREAM_mimlcp5 transfer" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 10. " STREAM_MIMLCP4_START ,Controls the start and stop of STREAM_mimlcp4 transfer" "Stopped,Started"
|
|
bitfld.long 0x10 9. " STREAM_MIMLCP3_START ,Controls the start and stop of STREAM_mimlcp3 transfer" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 8. " STREAM_MIMLCP8_START ,Controls the start and stop of STREAM_mimlcp8 transfer" "Stopped,Started"
|
|
bitfld.long 0x10 7. " STREAM_MIMLCP2_START ,Controls the start and stop of STREAM_mimlcp2 transfer" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 6. " STREAM_MIMLCP7_START ,Controls the start and stop of STREAM_mimlcp7 transfer" "Stopped,Started"
|
|
bitfld.long 0x10 1. " STREAM_MIMLCP1_START ,ontrols the start and stop of STREAM_mimlcp1 transfer" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x10 0. " STREAM_MIMLCP0_START ,ontrols the start and stop of STREAM_mimlcp0 transfer" "Stopped,Started"
|
|
line.long 0x14 "MOST_CONTROL2,MOST Control Register 2"
|
|
bitfld.long 0x14 0. " MLB_ENABLE ,MLB Enable" "Disabled,Enabled"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "FIFO_STATUS,FIFO Status Register"
|
|
bitfld.long 0x00 30. " CTLTX_NOT_FULL ,Indicates the control transmission buffer state" "Full,Not full"
|
|
bitfld.long 0x00 29. " PKTTX_NOT_FULL ,Indicates the packet transmission buffer state" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PHPBIF_MIM_WRITE_NOT_FULL ,Indicates the transmission buffer state during stream transfer" "Full,Not full"
|
|
bitfld.long 0x00 22. " CTLTX_EMPTY ,Indicates the control transmission buffer state" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PKTTX_EMPTY ,Indicates the packet transmission buffer state" "Not empty,Empty"
|
|
bitfld.long 0x00 20. " HPBIF_MIM_WRITE_EMPTY ,Indicates the transmission buffer state during stream transfer" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CTLRX_FULL ,Indicates the control reception buffer state" "Not full,Full"
|
|
bitfld.long 0x00 13. " PKTRX_FULL ,Indicates the packet reception buffer state" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HPBIF_MIM_READ_FULL ,Indicates the reception buffer state during stream transfer" "Not full,Full"
|
|
bitfld.long 0x00 6. " CTLRX_NOT_EMPTY ,Indicates the control reception buffer state" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PKTRX_NOT_EMPTY ,Indicates the packet reception buffer state" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " HPBIF_MIM_READ_NOT_EMPTY ,Indicates the reception buffer state during stream transfer" "Empty,Not empty"
|
|
group.long 0x124++0x07
|
|
line.long 0x00 "FIFO_INT_ENABLE,FIFO Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " CTLTX_NOT_FULL ,Indicates the control transmission buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PKTTX_NOT_FULL ,Indicates the packet transmission buffer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PHPBIF_MIM_WRITE_NOT_FULL ,Indicates the transmission buffer interrupt enable during stream transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CTLTX_EMPTY ,Indicates the control transmission buffer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PKTTX_EMPTY ,Indicates the packet transmission buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " HPBIF_MIM_WRITE_EMPTY ,Indicates the transmission buffer interrupt enable during stream transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CTLRX_FULL ,Indicates the control reception buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PKTRX_FULL ,Indicates the packet reception buffer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " HPBIF_MIM_READ_FULL ,Indicates the reception buffer interrupt during stream transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CTLRX_NOT_EMPTY ,Indicates the control reception buffer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PKTRX_NOT_EMPTY ,Indicates the packet reception buffer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HPBIF_MIM_READ_NOT_EMPTY ,Indicates the reception buffer during stream transfer interupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYSTEM_STATUS1,SYSTEM Status Register 1"
|
|
eventfld.long 0x04 31. " CTLTX_UF ,State of Control Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 30. " PKTTX_UF ,State of Packet Transmission Buffer" "Normal,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 28. " STRTX_UF_MIMLCP6 ,State of STREAM_mimlcp6 Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 27. " STRTX_UF_MIMLCP5 ,State of STREAM_mimlcp5 Transmission Buffer" "Normal,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 26. " STRTX_UF_MIMLCP4 ,State of STREAM_mimlcp4 Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 25. " STRTX_UF_MIMLCP3 ,State of STREAM_mimlcp3 Transmission Buffer" "Normal,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 24. " STRTX_UF_MIMLCP8 ,State of STREAM_mimlcp8 Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 23. " STRTX_UF_MIMLCP2 ,State of STREAM_mimlcp2 Transmission Buffer" "Normal,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 22. " STRTX_UF_MIMLCP7 ,State of STREAM_mimlcp7 Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 17. " STRTX_UF_MIMLCP1 ,State of STREAM_mimlcp1 Transmission Buffer" "Normal,Underflow"
|
|
textline " "
|
|
eventfld.long 0x04 16. " STRTX_UF_MIMLCP0 ,State of STREAM_mimlcp0 Transmission Buffer" "Normal,Underflow"
|
|
eventfld.long 0x04 15. " CTLRX_OF ,State of Control Reception Buffer" "Normal,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 14. " PKTRX_OF ,State of Packet Reception Buffer" "Normal,Overflow"
|
|
eventfld.long 0x04 12. " STRRX_OF_MIMLCP6 ,State of STREAM_mimlcp6 reception buffer" "Normal,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 11. " STRRX_OF_MIMLCP5 ,State of STREAM_mimlcp5 reception buffer" "Normal,Overflow"
|
|
eventfld.long 0x04 10. " STRRX_OF_MIMLCP4 ,State of STREAM_mimlcp4 reception buffer" "Normal,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 9. " STRRX_OF_MIMLCP3 ,State of STREAM_mimlcp3 reception buffer" "Normal,Overflow"
|
|
eventfld.long 0x04 8. " STRRX_OF_MIMLCP8 ,State of STREAM_mimlcp8 reception buffer" "Normal,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 7. " STRRX_OF_MIMLCP2 ,State of STREAM_mimlcp2 reception buffer" "Normal,Overflow"
|
|
eventfld.long 0x04 6. " STRRX_OF_MIMLCP7 ,State of STREAM_mimlcp7 reception buffer" "Normal,Overflow"
|
|
textline " "
|
|
eventfld.long 0x04 1. " STRRX_OF_MIMLCP1 ,State of STREAM_mimlcp1 reception buffer" "Normal,Overflow"
|
|
eventfld.long 0x04 0. " STRRX_OF_MIMLCP0 ,State of STREAM_mimlcp0 reception buffer" "Normal,Overflow"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "SYSTEM_INT_ENABLE1,SYSTEM Interrupt Enable Register 1"
|
|
bitfld.long 0x00 31. " CTLTX_UF ,State of Control Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PKTTX_UF ,State of Packet Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " STRTX_UF_MIMLCP6 ,State of STREAM_mimlcp6 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " STRTX_UF_MIMLCP5 ,State of STREAM_mimlcp5 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " STRTX_UF_MIMLCP4 ,State of STREAM_mimlcp4 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " STRTX_UF_MIMLCP3 ,State of STREAM_mimlcp3 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " STRTX_UF_MIMLCP8 ,State of STREAM_mimlcp8 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " STRTX_UF_MIMLCP2 ,State of STREAM_mimlcp2 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " STRTX_UF_MIMLCP7 ,State of STREAM_mimlcp7 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " STRTX_UF_MIMLCP1 ,State of STREAM_mimlcp1 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " STRTX_UF_MIMLCP0 ,State of STREAM_mimlcp0 Transmission Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CTLRX_OF ,State of Control Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PKTRX_OF ,State of Packet Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " STRRX_OF_MIMLCP6 ,State of STREAM_mimlcp6 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " STRRX_OF_MIMLCP5 ,State of STREAM_mimlcp5 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " STRRX_OF_MIMLCP4 ,State of STREAM_mimlcp4 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " STRRX_OF_MIMLCP3 ,State of STREAM_mimlcp3 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " STRRX_OF_MIMLCP8 ,State of STREAM_mimlcp8 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " STRRX_OF_MIMLCP2 ,State of STREAM_mimlcp2 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " STRRX_OF_MIMLCP7 ,State of STREAM_mimlcp7 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " STRRX_OF_MIMLCP1 ,State of STREAM_mimlcp1 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " STRRX_OF_MIMLCP0 ,State of STREAM_mimlcp0 Reception Buffer Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PACKET_RX_CNT,Packet Count Register"
|
|
bitfld.long 0x00 16.--19. " CONTROL_RX_CNT ,Number of packets received during reception in control transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PACKET_RX_CNT ,Number of packets received during reception in packet transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "SYSTEM_MEM_STATUS1,SYSTEM_MEM Status Register 1"
|
|
bitfld.long 0x00 16. " RCM ,Control_rx_cnt in the packet count register" "0,Not 0"
|
|
bitfld.long 0x00 0. " RPM ,Packet_rx_cnt in the packet count register" "0,Not 0"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SYSTEM_MEM_INT_ENABLE1,SYSTEM_MEM Interrupt Enable Register 1"
|
|
bitfld.long 0x00 16. " RCM ,RCM Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RPM ,RPM INterrupt Enable" "Disabled,Enabled"
|
|
wgroup.long 0x300++0x03
|
|
line.long 0x00 "PACKET_TX,Packet Transmission Data Storing Register"
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "PACKET_RX,Packet Reception Data Storing Register"
|
|
in
|
|
wgroup.long 0x308++0x03
|
|
line.long 0x00 "CONTROL_TX,Control Transmission Data Storing Register"
|
|
rgroup.long 0x30c++0x03
|
|
line.long 0x00 "CONTROL_RX,Control Reception Data Storing Register"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "HPBIF_MIM_STREAM,HPBIF_MIM Stream Data Storing Register"
|
|
group.long 0x800++0x07
|
|
line.long 0x00 "MLBPLL0,MLBPLL Register 0"
|
|
bitfld.long 0x00 0. " MLBPLL_ENABLE , MLB PLL enable" "Disabled,Enabled"
|
|
line.long 0x04 "MLBPLL1,MLBPLL Register 1"
|
|
bitfld.long 0x04 2. " MLBPLL_25 ,Select or deselect the supply of a 25-MHz clock signal on MLB_CLK" "Not supplied,Supplied"
|
|
bitfld.long 0x04 0. " MLBPLL_50 ,Select or deselect the supply of a 50-MHz clock signal on MLB_CLK" "Not supplied,Supplied"
|
|
width 0xb
|
|
tree.end
|
|
tree "MLP (MediaLB+)"
|
|
base ad:0xFFD8E000
|
|
width 7.
|
|
tree "OS62420 registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MLBC0,MediaLB Control 0 Register"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "MS0,MediaLB Channel Status 0 Register"
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MS1,MediaLB Channel Status 1 Register"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MSS,MediaLB System Status Register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "MSD,MediaLB System Data Register"
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "MIEN,MediaLB Interrupt Enable Register"
|
|
group.long 0x3c++0x03
|
|
line.long 0x00 "MLBC1,MediaLB Control 1 Register"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "HCTL,HBI Control Register"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "HCMR0,HBI Channel Mask 0 Register"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "HCER0,HBI Channel Error 0 Register"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "HCBR0,HBI Channel Busy 0 Register"
|
|
else
|
|
group.long 0x88++0x17
|
|
line.long 0x00 "HCMR0,HBI Channel Mask 0 Register"
|
|
line.long 0x04 "HCMR1,HBI Channel Mask 1 Register"
|
|
line.long 0x08 "HCER0,HBI Channel Error 0 Register"
|
|
line.long 0x0c "HCER1,HBI Channel Error 1 Register"
|
|
line.long 0x10 "HCBR0,HBI Channel Busy 0 Register"
|
|
line.long 0x14 "HCBR1,HBI Channel Busy 1 Register"
|
|
endif
|
|
group.long 0xc0++0x0F
|
|
line.long 0x0 "MDAT0,MIF Data 0 Register"
|
|
line.long 0x4 "MDAT1,MIF Data 1 Register"
|
|
line.long 0x8 "MDAT2,MIF Data 2 Register"
|
|
line.long 0xC "MDAT3,MIF Data 3 Register"
|
|
group.long 0xD0++0x0F
|
|
line.long 0x0 "MDWE0,MIF Data Write Enable 0 Register"
|
|
line.long 0x4 "MDWE1,MIF Data Write Enable 1 Register"
|
|
line.long 0x8 "MDWE2,MIF Data Write Enable 2 Register"
|
|
line.long 0xC "MDWE3,MIF Data Write Enable 3 Register"
|
|
group.long 0xe0++0x7
|
|
line.long 0x00 "MCTL,MIF Control Register"
|
|
line.long 0x04 "MADR,MIF Address Register"
|
|
group.long 0x3c0++0x03
|
|
line.long 0x00 "ACTL,AHB Control Register"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x3d0++0x03
|
|
line.long 0x00 "ACSR0,AHB Channel Status 0 Register"
|
|
group.long 0x3d8++0x03
|
|
line.long 0x00 "ACMR0,AHB Channel Mask 0 Register"
|
|
else
|
|
group.long 0x3d0++0x0F
|
|
line.long 0x00 "ACSR0,AHB Channel Status 0 Register"
|
|
line.long 0x04 "ACSR1,AHB Channel Status 1 Register"
|
|
line.long 0x08 "ACMR0,AHB Channel Mask 0 Register"
|
|
line.long 0x0c "ACMR1,AHB Channel Mask 1 Register"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
base ad:0xFFD8E400
|
|
textline " "
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ATM0,Automatic Transfer Mode 0 Register"
|
|
bitfld.long 0x00 31. " ATMPI31 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ATMPI30 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ATMPI29 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ATMPI28 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATMPI27 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATMPI26 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATMPI25 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ATMPI24 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ATMPI23 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ATMPI22 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATMPI21 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ATMPI20 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ATMPI19 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ATMPI18 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ATMPI17 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ATMPI16 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ATMPI15 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ATMPI14 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ATMPI13 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ATMPI12 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ATMPI11 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ATMPI10 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ATMPI9 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ATMPI8 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATMPI7 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ATMPI6 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ATMPI5 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ATMPI4 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ATMPI3 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ATMPI2 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ATMPI1 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 1" "Disabled,Enabled"
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ATM1,Automatic Transfer Mode 1 Register"
|
|
bitfld.long 0x00 31. " ATMPI63 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 63" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ATMPI62 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 62" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ATMPI61 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 61" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ATMPI60 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 60" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATMPI59 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 59" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATMPI58 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATMPI57 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 57" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ATMPI56 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 56" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ATMPI55 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 55" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ATMPI54 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 54" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATMPI53 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 53" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ATMPI52 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ATMPI51 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 51" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ATMPI50 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 50" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ATMPI49 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ATMPI48 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 48" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ATMPI47 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 47" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ATMPI46 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ATMPI45 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 45" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ATMPI44 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 44" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ATMPI43 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ATMPI42 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 42" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ATMPI41 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 41" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ATMPI40 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATMPI39 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 39" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ATMPI38 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ATMPI37 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ATMPI36 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 36" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ATMPI35 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 35" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ATMPI34 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ATMPI33 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 33" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ATMPI32 ,Automatic Transfer Mode (ping buffer page) for Logical Channel 32" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ATM2,Automatic Transfer Mode 2 Register"
|
|
bitfld.long 0x00 31. " ATMPO31 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ATMPO30 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ATMPO29 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ATMPO28 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATMPO27 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATMPO26 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATMPO25 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ATMPO24 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ATMPO23 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ATMPO22 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATMPO21 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ATMPO20 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ATMPO19 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ATMPO18 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ATMPO17 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ATMPO16 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ATMPO15 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ATMPO14 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ATMPO13 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ATMPO12 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ATMPO11 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ATMPO10 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ATMPO9 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ATMPO8 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATMPO7 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ATMPO6 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ATMPO5 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ATMPO4 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ATMPO3 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ATMPO2 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ATMPO1 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 1" "Disabled,Enabled"
|
|
sif (!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ATM3,Automatic Transfer Mode 3 Register"
|
|
bitfld.long 0x00 31. " ATMPO63 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 63" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ATMPO62 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 62" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ATMPO61 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 61" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ATMPO60 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 60" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ATMPO59 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 59" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ATMPO58 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 58" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ATMPO57 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 57" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ATMPO56 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 56" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ATMPO55 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 55" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ATMPO54 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 54" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ATMPO53 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 53" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ATMPO52 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 52" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ATMPO51 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 51" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ATMPO50 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 50" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ATMPO49 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 49" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ATMPO48 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 48" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ATMPO47 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 47" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ATMPO46 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 46" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ATMPO45 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 45" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ATMPO44 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 44" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ATMPO43 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 43" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ATMPO42 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 42" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ATMPO41 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 41" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ATMPO40 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 40" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ATMPO39 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 39" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ATMPO38 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ATMPO37 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 37" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ATMPO36 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 36" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ATMPO35 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 35" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ATMPO34 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ATMPO33 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 33" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ATMPO32 ,Automatic Transfer Mode (pong buffer page) for Logical Channel 32" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x80++0xB
|
|
line.long 0x00 "ASM,Automatic Start Mode Register"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 28. " ASM7 ,Automatic Start Mode 7" "0,1"
|
|
bitfld.long 0x00 24. " ASM6 ,Automatic Start Mode 6" "0,1"
|
|
bitfld.long 0x00 20. " ASM5 ,Automatic Start Mode 5" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASM4 ,Automatic Start Mode 4" "0,1"
|
|
bitfld.long 0x00 12. " ASM3 ,Automatic Start Mode 3" "0,1"
|
|
bitfld.long 0x00 8. " ASM2 ,Automatic Start Mode 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASM1 ,Automatic Start Mode 1" "0,1"
|
|
bitfld.long 0x00 0. " ASM0 ,Automatic Start Mode 0" "0,1"
|
|
else
|
|
bitfld.long 0x00 28. " ASM7 ,Automatic Start Mode 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ASM6 ,Automatic Start Mode 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ASM5 ,Automatic Start Mode 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ASM4 ,Automatic Start Mode 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASM3 ,Automatic Start Mode 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASM2 ,Automatic Start Mode 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ASM1 ,Automatic Start Mode 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASM0 ,Automatic Start Mode 0" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "ADRDEC1,Address Decode Mode 1 Register"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x04 28. " ADEC34 ,Address Decode Mode 34" "0,1"
|
|
bitfld.long 0x04 27. " ADEC33 ,Address Decode Mode 33" "0,1"
|
|
bitfld.long 0x04 26. " ADEC32 ,Address Decode Mode 32" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ADEC31 ,Address Decode Mode 31" "0,1"
|
|
bitfld.long 0x04 24. " ADEC30 ,Address Decode Mode 30" "0,1"
|
|
bitfld.long 0x04 20. " ADEC24 ,Address Decode Mode 24" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ADEC23 ,Address Decode Mode 23" "0,1"
|
|
bitfld.long 0x04 18. " ADEC22 ,Address Decode Mode 22" "0,1"
|
|
bitfld.long 0x04 17. " ADEC21 ,Address Decode Mode 21" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 16. " ADEC20 ,Address Decode Mode 20" "0,1"
|
|
bitfld.long 0x04 12. " ADEC14 ,Address Decode Mode 14" "0,1"
|
|
bitfld.long 0x04 11. " ADEC13 ,Address Decode Mode 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ADEC12 ,Address Decode Mode 12" "0,1"
|
|
bitfld.long 0x04 9. " ADEC11 ,Address Decode Mode 11" "0,1"
|
|
bitfld.long 0x04 8. " ADEC10 ,Address Decode Mode 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ADEC4 ,Address Decode Mode 4" "0,1"
|
|
bitfld.long 0x04 3. " ADEC3 ,Address Decode Mode 3" "0,1"
|
|
bitfld.long 0x04 2. " ADEC2 ,Address Decode Mode 2" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ADEC1 ,Address Decode Mode 1" "0,1"
|
|
bitfld.long 0x04 0. " ADEC0 ,Address Decode Mode 0" "0,1"
|
|
else
|
|
bitfld.long 0x04 29. " ADEC35 ,Address Decode Mode 35" "0,1"
|
|
bitfld.long 0x04 28. " ADEC34 ,Address Decode Mode 34" "0,1"
|
|
bitfld.long 0x04 27. " ADEC33 ,Address Decode Mode 33" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 26. " ADEC32 ,Address Decode Mode 32" "0,1"
|
|
bitfld.long 0x04 25. " ADEC31 ,Address Decode Mode 31" "0,1"
|
|
bitfld.long 0x04 24. " ADEC30 ,Address Decode Mode 30" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ADEC25 ,Address Decode Mode 25" "0,1"
|
|
bitfld.long 0x04 20. " ADEC24 ,Address Decode Mode 24" "0,1"
|
|
bitfld.long 0x04 19. " ADEC23 ,Address Decode Mode 23" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 18. " ADEC22 ,Address Decode Mode 22" "0,1"
|
|
bitfld.long 0x04 17. " ADEC21 ,Address Decode Mode 21" "0,1"
|
|
bitfld.long 0x04 16. " ADEC20 ,Address Decode Mode 20" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ADEC15 ,Address Decode Mode 15" "0,1"
|
|
bitfld.long 0x04 12. " ADEC14 ,Address Decode Mode 14" "0,1"
|
|
bitfld.long 0x04 11. " ADEC13 ,Address Decode Mode 13" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ADEC12 ,Address Decode Mode 12" "0,1"
|
|
bitfld.long 0x04 9. " ADEC11 ,Address Decode Mode 11" "0,1"
|
|
bitfld.long 0x04 8. " ADEC10 ,Address Decode Mode 10" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ADEC5 ,Address Decode Mode 5" "0,1"
|
|
bitfld.long 0x04 4. " ADEC4 ,Address Decode Mode 4" "0,1"
|
|
bitfld.long 0x04 3. " ADEC3 ,Address Decode Mode 3" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ADEC2 ,Address Decode Mode 2" "0,1"
|
|
bitfld.long 0x04 1. " ADEC1 ,Address Decode Mode 1" "0,1"
|
|
bitfld.long 0x04 0. " ADEC0 ,Address Decode Mode 0" "0,1"
|
|
endif
|
|
line.long 0x08 "ADRDEC2,Address Decode Mode 2 Register"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x08 28. " ADEC74 ,Address Decode Mode 74" "0,1"
|
|
bitfld.long 0x08 27. " ADEC73 ,Address Decode Mode 73" "0,1"
|
|
bitfld.long 0x08 26. " ADEC72 ,Address Decode Mode 72" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ADEC71 ,Address Decode Mode 71" "0,1"
|
|
bitfld.long 0x08 24. " ADEC70 ,Address Decode Mode 70" "0,1"
|
|
bitfld.long 0x08 20. " ADEC64 ,Address Decode Mode 64" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ADEC63 ,Address Decode Mode 63" "0,1"
|
|
bitfld.long 0x08 18. " ADEC62 ,Address Decode Mode 62" "0,1"
|
|
bitfld.long 0x08 17. " ADEC61 ,Address Decode Mode 61" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 16. " ADEC60 ,Address Decode Mode 60" "0,1"
|
|
bitfld.long 0x08 12. " ADEC54 ,Address Decode Mode 54" "0,1"
|
|
bitfld.long 0x08 11. " ADEC53 ,Address Decode Mode 53" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 10. " ADEC52 ,Address Decode Mode 52" "0,1"
|
|
bitfld.long 0x08 9. " ADEC51 ,Address Decode Mode 51" "0,1"
|
|
bitfld.long 0x08 8. " ADEC50 ,Address Decode Mode 50" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ADEC44 ,Address Decode Mode 44" "0,1"
|
|
bitfld.long 0x08 3. " ADEC43 ,Address Decode Mode 43" "0,1"
|
|
bitfld.long 0x08 2. " ADEC42 ,Address Decode Mode 42" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ADEC41 ,Address Decode Mode 41" "0,1"
|
|
bitfld.long 0x08 0. " ADEC40 ,Address Decode Mode 40" "0,1"
|
|
else
|
|
bitfld.long 0x08 29. " ADEC75 ,Address Decode Mode 75" "0,1"
|
|
bitfld.long 0x08 28. " ADEC74 ,Address Decode Mode 74" "0,1"
|
|
bitfld.long 0x08 27. " ADEC73 ,Address Decode Mode 73" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 26. " ADEC72 ,Address Decode Mode 72" "0,1"
|
|
bitfld.long 0x08 25. " ADEC71 ,Address Decode Mode 71" "0,1"
|
|
bitfld.long 0x08 24. " ADEC70 ,Address Decode Mode 70" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ADEC65 ,Address Decode Mode 65" "0,1"
|
|
bitfld.long 0x08 20. " ADEC64 ,Address Decode Mode 64" "0,1"
|
|
bitfld.long 0x08 19. " ADEC63 ,Address Decode Mode 63" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 18. " ADEC62 ,Address Decode Mode 62" "0,1"
|
|
bitfld.long 0x08 17. " ADEC61 ,Address Decode Mode 61" "0,1"
|
|
bitfld.long 0x08 16. " ADEC60 ,Address Decode Mode 60" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ADEC55 ,Address Decode Mode 55" "0,1"
|
|
bitfld.long 0x08 12. " ADEC54 ,Address Decode Mode 54" "0,1"
|
|
bitfld.long 0x08 11. " ADEC53 ,Address Decode Mode 53" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 10. " ADEC52 ,Address Decode Mode 52" "0,1"
|
|
bitfld.long 0x08 9. " ADEC51 ,Address Decode Mode 51" "0,1"
|
|
bitfld.long 0x08 8. " ADEC50 ,Address Decode Mode 50" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ADEC45 ,Address Decode Mode 45" "0,1"
|
|
bitfld.long 0x08 4. " ADEC44 ,Address Decode Mode 44" "0,1"
|
|
bitfld.long 0x08 3. " ADEC43 ,Address Decode Mode 43" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ADEC42 ,Address Decode Mode 42" "0,1"
|
|
bitfld.long 0x08 1. " ADEC41 ,Address Decode Mode 41" "0,1"
|
|
bitfld.long 0x08 0. " ADEC40 ,Address Decode Mode 40" "0,1"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ARRE1,Async Rx Response Enable 1 Register"
|
|
bitfld.long 0x00 31. " ARRE31 ,Asynchronous Rx Response Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ARRE30 ,Asynchronous Rx Response Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ARRE29 ,Asynchronous Rx Response Enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ARRE28 ,Asynchronous Rx Response Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ARRE27 ,Asynchronous Rx Response Enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ARRE26 ,Asynchronous Rx Response Enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ARRE25 ,Asynchronous Rx Response Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ARRE24 ,Asynchronous Rx Response Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ARRE23 ,Asynchronous Rx Response Enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ARRE22 ,Asynchronous Rx Response Enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ARRE21 ,Asynchronous Rx Response Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ARRE20 ,Asynchronous Rx Response Enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ARRE19 ,Asynchronous Rx Response Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ARRE18 ,Asynchronous Rx Response Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ARRE17 ,Asynchronous Rx Response Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ARRE16 ,Asynchronous Rx Response Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ARRE15 ,Asynchronous Rx Response Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ARRE14 ,Asynchronous Rx Response Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ARRE13 ,Asynchronous Rx Response Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ARRE12 ,Asynchronous Rx Response Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ARRE11 ,Asynchronous Rx Response Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ARRE10 ,Asynchronous Rx Response Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ARRE9 ,Asynchronous Rx Response Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ARRE8 ,Asynchronous Rx Response Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ARRE7 ,Asynchronous Rx Response Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ARRE6 ,Asynchronous Rx Response Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ARRE5 ,Asynchronous Rx Response Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARRE4 ,Asynchronous Rx Response Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ARRE3 ,Asynchronous Rx Response Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARRE2 ,Asynchronous Rx Response Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARRE1 ,Asynchronous Rx Response Enable 1" "Disabled,Enabled"
|
|
wgroup.long 0x98++0x03
|
|
line.long 0x00 "ARIS1,Async Rx Interrupt Status 1 Register"
|
|
eventfld.long 0x00 31. " ARIS31 ,Asynchronous Rx Interrupt Status 31" "No effect,Interrupt"
|
|
eventfld.long 0x00 30. " ARIS30 ,Asynchronous Rx Interrupt Status 30" "No effect,Interrupt"
|
|
eventfld.long 0x00 29. " ARIS29 ,Asynchronous Rx Interrupt Status 29" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 28. " ARIS28 ,Asynchronous Rx Interrupt Status 28" "No effect,Interrupt"
|
|
eventfld.long 0x00 27. " ARIS27 ,Asynchronous Rx Interrupt Status 27" "No effect,Interrupt"
|
|
eventfld.long 0x00 26. " ARIS26 ,Asynchronous Rx Interrupt Status 26" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ARIS25 ,Asynchronous Rx Interrupt Status 25" "No effect,Interrupt"
|
|
eventfld.long 0x00 24. " ARIS24 ,Asynchronous Rx Interrupt Status 24" "No effect,Interrupt"
|
|
eventfld.long 0x00 23. " ARIS23 ,Asynchronous Rx Interrupt Status 23" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 22. " ARIS22 ,Asynchronous Rx Interrupt Status 22" "No effect,Interrupt"
|
|
eventfld.long 0x00 21. " ARIS21 ,Asynchronous Rx Interrupt Status 21" "No effect,Interrupt"
|
|
eventfld.long 0x00 20. " ARIS20 ,Asynchronous Rx Interrupt Status 20" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ARIS19 ,Asynchronous Rx Interrupt Status 19" "No effect,Interrupt"
|
|
eventfld.long 0x00 18. " ARIS18 ,Asynchronous Rx Interrupt Status 18" "No effect,Interrupt"
|
|
eventfld.long 0x00 17. " ARIS17 ,Asynchronous Rx Interrupt Status 17" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ARIS16 ,Asynchronous Rx Interrupt Status 16" "No effect,Interrupt"
|
|
eventfld.long 0x00 15. " ARIS15 ,Asynchronous Rx Interrupt Status 15" "No effect,Interrupt"
|
|
eventfld.long 0x00 14. " ARIS14 ,Asynchronous Rx Interrupt Status 14" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ARIS13 ,Asynchronous Rx Interrupt Status 13" "No effect,Interrupt"
|
|
eventfld.long 0x00 12. " ARIS12 ,Asynchronous Rx Interrupt Status 12" "No effect,Interrupt"
|
|
eventfld.long 0x00 11. " ARIS11 ,Asynchronous Rx Interrupt Status 11" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ARIS10 ,Asynchronous Rx Interrupt Status 10" "No effect,Interrupt"
|
|
eventfld.long 0x00 9. " ARIS9 ,Asynchronous Rx Interrupt Status 9" "No effect,Interrupt"
|
|
eventfld.long 0x00 8. " ARIS8 ,Asynchronous Rx Interrupt Status 8" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ARIS7 ,Asynchronous Rx Interrupt Status 7" "No effect,Interrupt"
|
|
eventfld.long 0x00 6. " ARIS6 ,Asynchronous Rx Interrupt Status 6" "No effect,Interrupt"
|
|
eventfld.long 0x00 5. " ARIS5 ,Asynchronous Rx Interrupt Status 5" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ARIS4 ,Asynchronous Rx Interrupt Status 4" "No effect,Interrupt"
|
|
eventfld.long 0x00 3. " ARIS3 ,Asynchronous Rx Interrupt Status 3" "No effect,Interrupt"
|
|
eventfld.long 0x00 2. " ARIS2 ,Asynchronous Rx Interrupt Status 2" "No effect,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ARIS1 ,Asynchronous Rx Interrupt Status 1" "No effect,Interrupt"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ARIE1,Async Rx Interrupt Enable 1 Register"
|
|
bitfld.long 0x00 31. " ARIE31 ,Asynchronous Rx Interrupt Enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ARIE30 ,Asynchronous Rx Interrupt Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ARIE29 ,Asynchronous Rx Interrupt Enable 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ARIE28 ,Asynchronous Rx Interrupt Enable 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ARIE27 ,Asynchronous Rx Interrupt Enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ARIE26 ,Asynchronous Rx Interrupt Enable 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ARIE25 ,Asynchronous Rx Interrupt Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ARIE24 ,Asynchronous Rx Interrupt Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ARIE23 ,Asynchronous Rx Interrupt Enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ARIE22 ,Asynchronous Rx Interrupt Enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ARIE21 ,Asynchronous Rx Interrupt Enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " ARIE20 ,Asynchronous Rx Interrupt Enable 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ARIE19 ,Asynchronous Rx Interrupt Enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ARIE18 ,Asynchronous Rx Interrupt Enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ARIE17 ,Asynchronous Rx Interrupt Enable 17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ARIE16 ,Asynchronous Rx Interrupt Enable 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " ARIE15 ,Asynchronous Rx Interrupt Enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ARIE14 ,Asynchronous Rx Interrupt Enable 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ARIE13 ,Asynchronous Rx Interrupt Enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ARIE12 ,Asynchronous Rx Interrupt Enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ARIE11 ,Asynchronous Rx Interrupt Enable 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ARIE10 ,Asynchronous Rx Interrupt Enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ARIE9 ,Asynchronous Rx Interrupt Enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ARIE8 ,Asynchronous Rx Interrupt Enable 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ARIE7 ,Asynchronous Rx Interrupt Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ARIE6 ,Asynchronous Rx Interrupt Enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ARIE5 ,Asynchronous Rx Interrupt Enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ARIE4 ,Asynchronous Rx Interrupt Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ARIE3 ,Asynchronous Rx Interrupt Enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARIE2 ,Asynchronous Rx Interrupt Enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ARIE1 ,Asynchronous Rx Interrupt Enable 1" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "BBCR,AA2S Bridge Control Register"
|
|
bitfld.long 0x00 0.--1. " EN ,Fix these bits to 11" "0,1,2,3"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "BUFDCR,AA2S Buffer Drain Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDC ,Fix these bits to H'00"
|
|
bitfld.long 0x00 17. " WBDE ,This bit is always read as 1. The write value should always be 1" ",1"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PHYCTRL,MLP-PHY Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")
|
|
bitfld.long 0x00 2. " MLB_PLLEN ,PLL Control 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLLEN ,PLL Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LVDSEN ,LVDS Buffer Control" "Disabled,Enabled"
|
|
elif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 2. " MLB_PLLEN ,PLL Control 2" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 1. " PLLEN ,PLL Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LVDSEN ,LVDS Buffer Control" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "512FSEN,512FS Enable Register"
|
|
bitfld.long 0x00 0. " 512FS ,Clock select for MediaLB 3-pin interface" "1024fs,512fs"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ASM2,Automatic Start Mode 2 Register"
|
|
bitfld.long 0x00 0. " ASMR ,Automatic Start Mode for RDY" "0,1"
|
|
endif
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))
|
|
group.long 0x204++0x7
|
|
line.long 0x00 "HWSYNCCR,Hardware Synchronization Control Register"
|
|
bitfld.long 0x00 0.--2. " CNT ,Synchronisation Control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "HWSTARTCR,Hardware Start Control Register"
|
|
bitfld.long 0x04 9. " START_CMD1 ,Transfer Start [cmd_out_route1]" "Stopped,Started"
|
|
bitfld.long 0x04 8. " START_CMD0 ,Transfer Start [cmd_out_route0]" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x04 7. " START_SRC9 ,Transfer Start [src_route9]" "Stopped,Started"
|
|
bitfld.long 0x04 6. " START_SRC6 ,Transfer Start [src_route6]" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x04 5. " START_SRC5 ,Transfer Start [src_route5]" "Stopped,Started"
|
|
bitfld.long 0x04 4. " START_SRC4 ,Transfer Start [src_route4]" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x04 3. " START_SRC3 ,Transfer Start [src_route3]" "Stopped,Started"
|
|
bitfld.long 0x04 2. " START_SRC2 ,Transfer Start [src_route2]" "Stopped,Started"
|
|
textline " "
|
|
bitfld.long 0x04 1. " START_SRC1 ,Transfer Start [src_route1]" "Stopped,Started"
|
|
bitfld.long 0x04 0. " START_SRC0 ,Transfer Start [src_route0]" "Stopped,Started"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SLM (SRU Local Memory)"
|
|
base ad:0xFE584028
|
|
width 12.
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "BUFF_ADDR,Top Address of Buffer Memory for Audio Data transfer"
|
|
button "BUFF_ADDR" "d ad:(ad:0xFE584028)--ad:(ad:0xFE584028+0x1FFC) /long"
|
|
endif
|
|
tree "Channel 0 Control Registers"
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "DCR0,DMA Control 0 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x0)++0x07
|
|
line.long 0x00 "DCMDR0,DMA Command 0 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR0,DMA Stop 0 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x0)++0x03
|
|
line.long 0x00 "DSTSR0,DMA Status 0 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x0)++0x03
|
|
line.long 0x00 "DMDR0,Buffer Size Control 0 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 1 Control Registers"
|
|
group.long (0x00+0x40)++0x03
|
|
line.long 0x00 "DCR1,DMA Control 1 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x40)++0x07
|
|
line.long 0x00 "DCMDR1,DMA Command 1 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR1,DMA Stop 1 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x40)++0x03
|
|
line.long 0x00 "DSTSR1,DMA Status 1 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x40)++0x03
|
|
line.long 0x00 "DMDR1,Buffer Size Control 1 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 2 Control Registers"
|
|
group.long (0x00+0x80)++0x03
|
|
line.long 0x00 "DCR2,DMA Control 2 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x80)++0x07
|
|
line.long 0x00 "DCMDR2,DMA Command 2 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR2,DMA Stop 2 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x80)++0x03
|
|
line.long 0x00 "DSTSR2,DMA Status 2 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x80)++0x03
|
|
line.long 0x00 "DMDR2,Buffer Size Control 2 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 3 Control Registers"
|
|
group.long (0x00+0xC0)++0x03
|
|
line.long 0x00 "DCR3,DMA Control 3 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0xC0)++0x07
|
|
line.long 0x00 "DCMDR3,DMA Command 3 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR3,DMA Stop 3 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0xC0)++0x03
|
|
line.long 0x00 "DSTSR3,DMA Status 3 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0xC0)++0x03
|
|
line.long 0x00 "DMDR3,Buffer Size Control 3 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 4 Control Registers"
|
|
group.long (0x00+0x100)++0x03
|
|
line.long 0x00 "DCR4,DMA Control 4 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x100)++0x07
|
|
line.long 0x00 "DCMDR4,DMA Command 4 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR4,DMA Stop 4 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x100)++0x03
|
|
line.long 0x00 "DSTSR4,DMA Status 4 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x100)++0x03
|
|
line.long 0x00 "DMDR4,Buffer Size Control 4 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 5 Control Registers"
|
|
group.long (0x00+0x140)++0x03
|
|
line.long 0x00 "DCR5,DMA Control 5 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x140)++0x07
|
|
line.long 0x00 "DCMDR5,DMA Command 5 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR5,DMA Stop 5 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x140)++0x03
|
|
line.long 0x00 "DSTSR5,DMA Status 5 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x140)++0x03
|
|
line.long 0x00 "DMDR5,Buffer Size Control 5 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 6 Control Registers"
|
|
group.long (0x00+0x180)++0x03
|
|
line.long 0x00 "DCR6,DMA Control 6 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x180)++0x07
|
|
line.long 0x00 "DCMDR6,DMA Command 6 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR6,DMA Stop 6 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x180)++0x03
|
|
line.long 0x00 "DSTSR6,DMA Status 6 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x180)++0x03
|
|
line.long 0x00 "DMDR6,Buffer Size Control 6 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
tree "Channel 7 Control Registers"
|
|
group.long (0x00+0x1C0)++0x03
|
|
line.long 0x00 "DCR7,DMA Control 7 Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP/SPU2IF"
|
|
elif (cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SSI/SCU/DTCP"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SSI/SCU/DTCP"
|
|
else
|
|
bitfld.long 0x00 13. " SMDL ,Transfer Source Module Select" "MLP,SRU"
|
|
bitfld.long 0x00 5. " DMDL ,Transfer Destination Module Select" "MLP,SRU"
|
|
endif
|
|
wgroup.long (0x04+0x1C0)++0x07
|
|
line.long 0x00 "DCMDR7,DMA Command 7 Register"
|
|
bitfld.long 0x00 0. " DMEN ,Activates DMA" "No effect,Activated"
|
|
line.long 0x04 "DSTPR7,DMA Stop 7 Register"
|
|
bitfld.long 0x04 0. " DMSTP ,Stops DMA transfer" "No effect,Stopped"
|
|
rgroup.long (0x0c+0x1C0)++0x03
|
|
line.long 0x00 "DSTSR7,DMA Status 7 Register"
|
|
bitfld.long 0x00 0. " DMSTS , DMA State" "Stopped,Activated"
|
|
group.long (0x14+0x1C0)++0x03
|
|
line.long 0x00 "DMDR7,Buffer Size Control 7 Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " DMDPT ,Buffer Size Specification"
|
|
tree.end
|
|
textline " "
|
|
rgroup.long 0xfe4++0x03
|
|
line.long 0x00 "DINTSR,Interrupt Status Register"
|
|
bitfld.long 0x00 30. " DTE72 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 29. " DTE71 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 28. " DTE70 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DTE62 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 25. " DTE61 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 24. " DTE60 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DTE52 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 21. " DTE51 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 20. " DTE50 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DTE42 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 17. " DTE41 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 16. " DTE40 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DTE32 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 13. " DTE31 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 12. " DTE30 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DTE22 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 9. " DTE21 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 8. " DTE20 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DTE12 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 5. " DTE11 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 4. " DTE10 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DTE02 ,First plane write end interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 1. " DTE01 ,Buffer full/empty interrupt" "No interrupt,Interupt"
|
|
bitfld.long 0x00 0. " DTE00 ,Buffer overflow/underflow error interrupt" "No interrupt,Interupt"
|
|
wgroup.long 0xfec++0x03
|
|
line.long 0x00 "DINTCR,Interrupt Clear Register"
|
|
eventfld.long 0x00 30. " DTEC72 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 29. " DTEC71 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 28. " DTEC70 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 26. " DTEC62 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 25. " DTEC61 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 24. " DTEC60 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 22. " DTEC52 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 21. " DTEC51 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 20. " DTEC50 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 18. " DTEC42 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 17. " DTEC41 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 16. " DTEC40 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 14. " DTEC32 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 13. " DTEC31 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 12. " DTEC30 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 10. " DTEC22 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 9. " DTEC21 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 8. " DTEC20 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 6. " DTEC12 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 5. " DTEC11 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 4. " DTEC10 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DTEC02 ,First plane write end interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 1. " DTEC01 ,Buffer full/empty interupt clear" "Not cleared,Cleared"
|
|
eventfld.long 0x00 0. " DTEC00 ,Buffer overflow/underflow error interupt clear" "Not cleared,Cleared"
|
|
group.long 0xff4++0x03
|
|
line.long 0x00 "DINTMR,Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DTEM72 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " DTEM71 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DTEM70 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " DTEM62 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " DTEM61 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " DTEM60 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DTEM52 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DTEM51 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " DTEM50 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DTEM42 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DTEM41 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DTEM40 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DTEM32 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DTEM31 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DTEM30 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DTEM22 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DTEM21 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DTEM20 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DTEM12 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DTEM11 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DTEM10 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DTEM02 ,First plane write end interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTEM01 ,Buffer full/empty interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTEM00 ,Buffer overflow/underflow error interupt enable" "Disabled,Enabled"
|
|
rgroup.long 0xffc++0x03
|
|
line.long 0x00 "DACTSR,DMA Activation State Register"
|
|
bitfld.long 0x00 7. " DS7 ,DMA Channel 7 State" "Idle,Act"
|
|
bitfld.long 0x00 6. " DS6 ,DMA Channel 6 State" "Idle,Act"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DS5 ,DMA Channel 5 State" "Idle,Act"
|
|
bitfld.long 0x00 4. " DS4 ,DMA Channel 4 State" "Idle,Act"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DS3 ,DMA Channel 3 State" "Idle,Act"
|
|
bitfld.long 0x00 2. " DS2 ,DMA Channel 2 State" "Idle,Act"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DS1 ,DMA Channel 1 State" "Idle,Act"
|
|
bitfld.long 0x00 0. " DS0 ,DMA Channel 0 State" "Idle,Act"
|
|
group.long 0x1018++0x1f
|
|
line.long 0x0 "SRSTR0,Software Reset 0 Register"
|
|
eventfld.long 0x0 0. " SRST ,Channel 0 Software Reset" "No reset,Reset"
|
|
line.long 0x4 "SRSTR1,Software Reset 1 Register"
|
|
eventfld.long 0x4 0. " SRST ,Channel 1 Software Reset" "No reset,Reset"
|
|
line.long 0x8 "SRSTR2,Software Reset 2 Register"
|
|
eventfld.long 0x8 0. " SRST ,Channel 2 Software Reset" "No reset,Reset"
|
|
line.long 0xC "SRSTR3,Software Reset 3 Register"
|
|
eventfld.long 0xC 0. " SRST ,Channel 3 Software Reset" "No reset,Reset"
|
|
line.long 0x10 "SRSTR4,Software Reset 4 Register"
|
|
eventfld.long 0x10 0. " SRST ,Channel 4 Software Reset" "No reset,Reset"
|
|
line.long 0x14 "SRSTR5,Software Reset 5 Register"
|
|
eventfld.long 0x14 0. " SRST ,Channel 5 Software Reset" "No reset,Reset"
|
|
line.long 0x18 "SRSTR6,Software Reset 6 Register"
|
|
eventfld.long 0x18 0. " SRST ,Channel 6 Software Reset" "No reset,Reset"
|
|
line.long 0x1C "SRSTR7,Software Reset 7 Register"
|
|
eventfld.long 0x1C 0. " SRST ,Channel 7 Software Reset" "No reset,Reset"
|
|
textline ""
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
if (0<2)
|
|
group.long 0x3D8++0x3
|
|
line.long 0x00 "MODE0,Mode 0 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x3D8++0x3
|
|
line.long 0x00 "MODE0,Mode 0 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x3D8+0x04)++0x3
|
|
line.long 0x00 "SMODE0,Source Mode 0 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x3D8+0x08)++0x3
|
|
line.long 0x00 "DALIGN0,Data Alignment 0 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (1<2)
|
|
group.long 0x418++0x3
|
|
line.long 0x00 "MODE1,Mode 1 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x418++0x3
|
|
line.long 0x00 "MODE1,Mode 1 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x418+0x04)++0x3
|
|
line.long 0x00 "SMODE1,Source Mode 1 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x418+0x08)++0x3
|
|
line.long 0x00 "DALIGN1,Data Alignment 1 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (2<2)
|
|
group.long 0x458++0x3
|
|
line.long 0x00 "MODE2,Mode 2 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x458++0x3
|
|
line.long 0x00 "MODE2,Mode 2 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x458+0x04)++0x3
|
|
line.long 0x00 "SMODE2,Source Mode 2 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x458+0x08)++0x3
|
|
line.long 0x00 "DALIGN2,Data Alignment 2 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (3<2)
|
|
group.long 0x498++0x3
|
|
line.long 0x00 "MODE3,Mode 3 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x498++0x3
|
|
line.long 0x00 "MODE3,Mode 3 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x498+0x04)++0x3
|
|
line.long 0x00 "SMODE3,Source Mode 3 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x498+0x08)++0x3
|
|
line.long 0x00 "DALIGN3,Data Alignment 3 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (4<2)
|
|
group.long 0x4D8++0x3
|
|
line.long 0x00 "MODE4,Mode 4 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x4D8++0x3
|
|
line.long 0x00 "MODE4,Mode 4 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x4D8+0x04)++0x3
|
|
line.long 0x00 "SMODE4,Source Mode 4 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x4D8+0x08)++0x3
|
|
line.long 0x00 "DALIGN4,Data Alignment 4 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (5<2)
|
|
group.long 0x518++0x3
|
|
line.long 0x00 "MODE5,Mode 5 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x518++0x3
|
|
line.long 0x00 "MODE5,Mode 5 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x518+0x04)++0x3
|
|
line.long 0x00 "SMODE5,Source Mode 5 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x518+0x08)++0x3
|
|
line.long 0x00 "DALIGN5,Data Alignment 5 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (6<2)
|
|
group.long 0x558++0x3
|
|
line.long 0x00 "MODE6,Mode 6 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x558++0x3
|
|
line.long 0x00 "MODE6,Mode 6 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x558+0x04)++0x3
|
|
line.long 0x00 "SMODE6,Source Mode 6 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x558+0x08)++0x3
|
|
line.long 0x00 "DALIGN6,Data Alignment 6 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
if (7<2)
|
|
group.long 0x598++0x3
|
|
line.long 0x00 "MODE7,Mode 7 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8. " CRYPT ,CRYPT" "Not crypt,Crypt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DTCP ,DTCP" "Not DCPT,DTCP"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
else
|
|
group.long 0x598++0x3
|
|
line.long 0x00 "MODE7,Mode 7 Register"
|
|
bitfld.long 0x00 20. " SFT_DIR ,Select Bit Shift direction" "Left,Right"
|
|
bitfld.long 0x00 16.--19. " SFT_NUM ,Select Bit Shift length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
bitfld.long 0x00 0. " DMA ,DMA" ",DMA"
|
|
else
|
|
bitfld.long 0x00 0. " DMA ,DMA" "PIO,DMA"
|
|
endif
|
|
endif
|
|
group.long (0x598+0x04)++0x3
|
|
line.long 0x00 "SMODE7,Source Mode 7 Register"
|
|
bitfld.long 0x00 0.--3. " SOURCE_MODE ,Select Source Sound Mode" "6ch/24 bit/96 kHz,6ch/24 bit/48 kHz,6ch/16 bit/96 kHz,6ch/16 bit/48 kHz,2ch/24 bit/192 kHz,2ch/24 bit/96 kHz,2ch/24 bit/48 kHz,2ch/16 bit/192 kHz,2ch/16 bit/96 kHz,2ch/16 bit/48 kHz,,6ch/16 bit/192 kHz,8ch/24 bit/96 kHz,8ch/24 bit/48 kHz,8ch/16 bit/96 kHz,8ch/16 bit/48 kHz"
|
|
group.long (0x598+0x08)++0x3
|
|
line.long 0x00 "DALIGN7,Data Alignment 7 Register"
|
|
bitfld.long 0x00 28.--30. " PLACE7 ,Exchange Stream Data 7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " PLACE6 ,Exchange Stream Data 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " PLACE5 ,Exchange Stream Data 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " PLACE4 ,Exchange Stream Data 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " PLACE3 ,Exchange Stream Data 3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " PLACE2 ,Exchange Stream Data 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " PLACE1 ,Exchange Stream Data 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " PLACE0 ,Exchange Stream Data 0" "0,1,2,3,4,5,6,7"
|
|
textline ""
|
|
rgroup.long 0x17D8++0x3
|
|
line.long 0x00 "BUSIFST,Bus Interface Status Register"
|
|
bitfld.long 0x00 23. " WR_NOT_FULL7 ,Transmission Buffer Status 7" "Full,Not full"
|
|
bitfld.long 0x00 22. " WR_NOT_FULL6 ,Transmission Buffer Status 6" "Full,Not full"
|
|
bitfld.long 0x00 21. " WR_NOT_FULL5 ,Transmission Buffer Status 5" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4 ,Transmission Buffer Status 4" "Full,Not full"
|
|
bitfld.long 0x00 19. " WR_NOT_FULL3 ,Transmission Buffer Status 3" "Full,Not full"
|
|
bitfld.long 0x00 18. " WR_NOT_FULL2 ,Transmission Buffer Status 2" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WR_NOT_FULL1 ,Transmission Buffer Status 1" "Full,Not full"
|
|
bitfld.long 0x00 16. " WR_NOT_FULL0 ,Transmission Buffer Status 0" "Full,Not full"
|
|
bitfld.long 0x00 7. " RD_NOT_EMPTY7 ,Receive Buffer Status 7" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RD_NOT_EMPTY6 ,Receive Buffer Status 6" "Empty,Not empty"
|
|
bitfld.long 0x00 5. " RD_NOT_EMPTY5 ,Receive Buffer Status 5" "Empty,Not empty"
|
|
bitfld.long 0x00 4. " RD_NOT_EMPTY4 ,Receive Buffer Status 4" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RD_NOT_EMPTY3 ,Receive Buffer Status 3" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " RD_NOT_EMPTY2 ,Receive Buffer Status 2" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " RD_NOT_EMPTY1 ,Receive Buffer Status 1" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RD_NOT_EMPTY0 ,Receive Buffer Status 0" "Empty,Not empty"
|
|
group.long 0x17DC++0x3
|
|
line.long 0x00 "BUSIFINTEN,Bus Interface Interrupt Enable Register"
|
|
bitfld.long 0x00 23. " WR_NOT_FULL7_IE ,Write interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " WR_NOT_FULL6_IE ,Write interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WR_NOT_FULL5_IE ,Write interrupt enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4_IE ,Write interrupt enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " WR_NOT_FULL3_IE ,Write interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " WR_NOT_FULL2_IE ,Write interrupt enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " WR_NOT_FULL1_IE ,Write interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " WR_NOT_FULL0_IE ,Write interrupt enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RD_NOT_FULL7_IE ,Read interrupt enable 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " RD_NOT_EMPTY6_IE ,Read interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RD_NOT_EMPTY5_IE ,Read interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RD_NOT_EMPTY4_IE ,Read interrupt enable 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RD_NOT_EMPTY3_IE ,Read interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RD_NOT_EMPTY2_IE ,Read interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RD_NOT_EMPTY1_IE ,Read interrupt enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RD_NOT_EMPTY0_IE ,Read interrupt enable 0" "Disabled,Enabled"
|
|
textline ""
|
|
rgroup.long 0x3E8++0x3
|
|
line.long 0x00 "CHINTSR0,Channel 0 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL0 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY0 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE02 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE01 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE00 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x3E8+0x8)++0x3
|
|
line.long 0x00 "CHINTEN0,Channel Interrupt Enable 0 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL0_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY0_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE02_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE01_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE00_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x428++0x3
|
|
line.long 0x00 "CHINTSR1,Channel 1 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL1 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY1 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE12 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE11 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE10 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x428+0x8)++0x3
|
|
line.long 0x00 "CHINTEN1,Channel Interrupt Enable 1 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL1_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY1_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE12_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE11_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE10_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x468++0x3
|
|
line.long 0x00 "CHINTSR2,Channel 2 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL2 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY2 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE22 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE21 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE20 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x468+0x8)++0x3
|
|
line.long 0x00 "CHINTEN2,Channel Interrupt Enable 2 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL2_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY2_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE22_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE21_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE20_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x4A8++0x3
|
|
line.long 0x00 "CHINTSR3,Channel 3 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL3 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY3 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE32 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE31 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE30 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x4A8+0x8)++0x3
|
|
line.long 0x00 "CHINTEN3,Channel Interrupt Enable 3 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL3_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY3_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE32_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE31_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE30_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x00 "CHINTSR4,Channel 4 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY4 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE42 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE41 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE40 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x4E8+0x8)++0x3
|
|
line.long 0x00 "CHINTEN4,Channel Interrupt Enable 4 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL4_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY4_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE42_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE41_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE40_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x528++0x3
|
|
line.long 0x00 "CHINTSR5,Channel 5 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL5 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY5 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE52 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE51 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE50 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x528+0x8)++0x3
|
|
line.long 0x00 "CHINTEN5,Channel Interrupt Enable 5 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL5_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY5_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE52_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE51_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE50_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x568++0x3
|
|
line.long 0x00 "CHINTSR6,Channel 6 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL6 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY6 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE62 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE61 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE60 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x568+0x8)++0x3
|
|
line.long 0x00 "CHINTEN6,Channel Interrupt Enable 6 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL6_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY6_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE62_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE61_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE60_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x5A8++0x3
|
|
line.long 0x00 "CHINTSR7,Channel 7 Interrupt Status Display Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL7 ,Transmission Buffer Status (Write)" "Full,Not full"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY7 ,Transmission Buffer Status (Read)" "Empty,Not empty"
|
|
bitfld.long 0x00 2. " DTE72 ,Buffer Over Flow/ Under Flow Error Interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE71 ,Buffer Full/ Empty Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " DTE70 ,Plane write complete Interrupt" "No interrupt,Interrupt"
|
|
group.long (0x5A8+0x8)++0x3
|
|
line.long 0x00 "CHINTEN7,Channel Interrupt Enable 7 Register"
|
|
bitfld.long 0x00 20. " WR_NOT_FULL7_IE ,Transmission Buffer Status (Write)" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RD_NOT_EMPTY7_IE ,Transmission Buffer Status (Read)" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DTE72_IE ,Buffer Over Flow/ Under Flow Error Interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTE71_IE ,Buffer Full/ Empty Interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DTE70_IE ,Plane write complete Interrupt" "Disabled,Enabled"
|
|
endif
|
|
width 0xb
|
|
tree "Buffers"
|
|
width 14.
|
|
base ad:0xFE580000
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x0++0x03
|
|
hide.long 0x00 "BUSIF0,Bus Interface 0 Register"
|
|
in
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PLANE_1_BUF0,1st plane of BUF0"
|
|
button "Buffer" "d (ad:0xFE580000+0x0)--(ad:0xFE580000+0x0+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x0+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF0,1st plane of BUF0"
|
|
button "Buffer" "d (ad:0xFE580000+0x0+0x200)--(ad:0xFE580000+0x0+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "BUSIF1,Bus Interface 1 Register"
|
|
in
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PLANE_1_BUF1,1st plane of BUF1"
|
|
button "Buffer" "d (ad:0xFE580000+0x400)--(ad:0xFE580000+0x400+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x400+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF1,1st plane of BUF1"
|
|
button "Buffer" "d (ad:0xFE580000+0x400+0x200)--(ad:0xFE580000+0x400+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x800++0x03
|
|
hide.long 0x00 "BUSIF2,Bus Interface 2 Register"
|
|
in
|
|
else
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "PLANE_1_BUF2,1st plane of BUF2"
|
|
button "Buffer" "d (ad:0xFE580000+0x800)--(ad:0xFE580000+0x800+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x800+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF2,1st plane of BUF2"
|
|
button "Buffer" "d (ad:0xFE580000+0x800+0x200)--(ad:0xFE580000+0x800+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0xC00++0x03
|
|
hide.long 0x00 "BUSIF3,Bus Interface 3 Register"
|
|
in
|
|
else
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "PLANE_1_BUF3,1st plane of BUF3"
|
|
button "Buffer" "d (ad:0xFE580000+0xC00)--(ad:0xFE580000+0xC00+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0xC00+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF3,1st plane of BUF3"
|
|
button "Buffer" "d (ad:0xFE580000+0xC00+0x200)--(ad:0xFE580000+0xC00+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x1000++0x03
|
|
hide.long 0x00 "BUSIF4,Bus Interface 4 Register"
|
|
in
|
|
else
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "PLANE_1_BUF4,1st plane of BUF4"
|
|
button "Buffer" "d (ad:0xFE580000+0x1000)--(ad:0xFE580000+0x1000+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x1000+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF4,1st plane of BUF4"
|
|
button "Buffer" "d (ad:0xFE580000+0x1000+0x200)--(ad:0xFE580000+0x1000+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x1400++0x03
|
|
hide.long 0x00 "BUSIF5,Bus Interface 5 Register"
|
|
in
|
|
else
|
|
group.long 0x1400++0x03
|
|
line.long 0x00 "PLANE_1_BUF5,1st plane of BUF5"
|
|
button "Buffer" "d (ad:0xFE580000+0x1400)--(ad:0xFE580000+0x1400+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x1400+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF5,1st plane of BUF5"
|
|
button "Buffer" "d (ad:0xFE580000+0x1400+0x200)--(ad:0xFE580000+0x1400+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x1800++0x03
|
|
hide.long 0x00 "BUSIF6,Bus Interface 6 Register"
|
|
in
|
|
else
|
|
group.long 0x1800++0x03
|
|
line.long 0x00 "PLANE_1_BUF6,1st plane of BUF6"
|
|
button "Buffer" "d (ad:0xFE580000+0x1800)--(ad:0xFE580000+0x1800+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x1800+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF6,1st plane of BUF6"
|
|
button "Buffer" "d (ad:0xFE580000+0x1800+0x200)--(ad:0xFE580000+0x1800+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
hgroup.long 0x1C00++0x03
|
|
hide.long 0x00 "BUSIF7,Bus Interface 7 Register"
|
|
in
|
|
else
|
|
group.long 0x1C00++0x03
|
|
line.long 0x00 "PLANE_1_BUF7,1st plane of BUF7"
|
|
button "Buffer" "d (ad:0xFE580000+0x1C00)--(ad:0xFE580000+0x1C00+0x1ff) /long"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")
|
|
group.long (0x1C00+0x200)++0x03
|
|
line.long 0x00 "PLANE_1_BUF7,1st plane of BUF7"
|
|
button "Buffer" "d (ad:0xFE580000+0x1C00+0x200)--(ad:0xFE580000+0x1C00+0x1ff+0x200) /long"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "IEB (IE Bus)"
|
|
base ad:0xFFFC9000
|
|
width 9.
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "IECTR,IEBus Control Register"
|
|
bitfld.byte 0x0 6. " IOL ,Input/output level" "Low,High"
|
|
bitfld.byte 0x0 5. " DEE ,Broadcast receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 3. " RE ,Receive enable" "Disabled,Enabled"
|
|
wgroup.byte 0x1++0x0
|
|
line.byte 0x0 "IECMR,IEBus Command Register"
|
|
bitfld.byte 0x0 0.--2. " CMD ,Command" "No operation,,Master request,Master abort,Not affected,,,Not affected"
|
|
group.byte 0x2++0x5
|
|
line.byte 0x0 "IEMCR,IEBus Master Control Register"
|
|
bitfld.byte 0x0 7. " SS ,Broadcast/Normal communications select" "Broadcast,Normal"
|
|
bitfld.byte 0x0 4.--6. " RN ,Retransmission counts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.byte 0x0 0.--3. " CTL ,Control" ",,,,,,,,,,,,,,,Data write"
|
|
line.byte 0x1 "IEAR1,IEBus Master Unit Address Register 1"
|
|
bitfld.byte 0x1 4.--7. " IARL4 ,Lower 4 bits of IEBus master unit address" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F"
|
|
bitfld.byte 0x1 2.--3. " IMD ,IEBus communications mode" "0,1,?..."
|
|
line.byte 0x2 "IEAR2,IEBus Master Unit Address Register 2"
|
|
line.byte 0x3 "IESA1,IEBus Slave Address Setting Register 1"
|
|
bitfld.byte 0x3 4.--7. " ISAL4 ,Lower 4 bits of IEBus slave address" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F"
|
|
line.byte 0x4 "IESA2,IEBus Slave Address Setting Register 2"
|
|
line.byte 0x5 "IETBFL,IEBus Transmit Message Length Register"
|
|
rgroup.byte 0x9++0x3
|
|
line.byte 0x0 "IEMA1,IEBus Reception Master Address Register 1"
|
|
bitfld.byte 0x0 4.--7. " IMAL4 ,Lower four bits of IEBus reception master address" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F"
|
|
line.byte 0x1 "IEMA2,IEBus Reception Master Address Register 2"
|
|
line.byte 0x2 "IERCTL,IEBus Receive Control Field Register"
|
|
bitfld.byte 0x2 0.--3. " RCTL ,IEBus receive control field" "00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F"
|
|
line.byte 0x3 "IERBFL,IEBus Receive Message Length Register"
|
|
rgroup.byte 0x10++0x00
|
|
line.byte 0x0 "IEFLG,IEBus General Flag Register"
|
|
bitfld.byte 0x0 7. " CMX ,Command execution status" "Completed,Executed"
|
|
bitfld.byte 0x0 6. " MRQ ,Master communications request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.byte 0x0 4. " SRE ,Slave receive status" "Not executed,Executed"
|
|
bitfld.byte 0x0 1. " RSS ,Receive broadcast bit status" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x0 0. " GG ,General broadcast reception acknowledgement" "Slave/Not acknowledged,Acknowledged"
|
|
group.byte 0x11++0x1
|
|
line.byte 0x0 "IETSR,IEBus Transmit Status Register"
|
|
eventfld.byte 0x0 6. " TXS ,Transmit start" "Not started,Started"
|
|
eventfld.byte 0x0 5. " TXF ,Transmit normal completion" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.byte 0x0 3. " TXEAL ,Arbitration loss" "Not lost,Lost"
|
|
eventfld.byte 0x0 2. " TXETTME ,Transmit timing error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x0 1. " TXERO ,Overflow of maximum number of transmit bytes in one frame" "No overflow,Overflow"
|
|
eventfld.byte 0x0 0. " TXEACK ,Acknowledge bit status" "Not acknowledged,Acknowledged"
|
|
line.byte 0x1 "IEIET,IEBus Transmit Interrupt Enable Register"
|
|
bitfld.byte 0x1 6. " TXSE ,Transmit start interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 5. " TXFE ,Transmit normal completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " TXEALE ,Arbitration loss interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 2. " TXETTMEE ,Transmit timing error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " TXEROE ,Overflow of maximum number of transmit bytes in one frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 0. " TXEACKE ,Acknowledge bit interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x14++0x1
|
|
line.byte 0x0 "IERSR,IEBus Receive Status Register"
|
|
eventfld.byte 0x0 7. " RXBSY ,Receive busy" "Not busy,Busy"
|
|
eventfld.byte 0x0 6. " RXS ,Receive start detection" "Not started,Started"
|
|
textline " "
|
|
eventfld.byte 0x0 5. " RXF ,Receive normal completion" "Not received,Received"
|
|
eventfld.byte 0x0 4. " RXEDE ,Broadcast receive error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x0 3. " RXEOVE ,Receive overrun flag" "No overrun,Overrun"
|
|
eventfld.byte 0x0 2. " RXERTME ,Receive timing error" "No error,Error"
|
|
textline " "
|
|
eventfld.byte 0x0 1. " RXEDLE ,Overflow of maximum number of receive bytes in one frame" "No overflow,Overflow"
|
|
eventfld.byte 0x0 0. " RXEPE ,Parity error" "No error,Error"
|
|
line.byte 0x1 "IEIER,IEBus Receive Interrupt Enable Register"
|
|
bitfld.byte 0x1 7. " RXBSYE ,Receive busy interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 6. " RXSE ,Receive start interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 5. " RXFE ,Receive normal completion enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 4. " RXEDEE ,Broadcast receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 3. " RXEOVEE ,Overrun control flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 2. " RXERTMEE ,Receive timing error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x1 1. " RXEDLEE ,Overflow of maximum number of receive bytes in one frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.byte 0x1 0. " RXEPEE ,Parity error interrupt enable" "Disabled,Enabled"
|
|
group.byte 0x18++0x2
|
|
line.byte 0x0 "IECKCYC,IEBus clock cycle register"
|
|
hexmask.byte 0x0 0.--6. 1. " CKCYC ,Clock period"
|
|
line.byte 0x1 "IECKHP,IEBus clock high-level width register"
|
|
hexmask.byte 0x1 0.--6. 1. " CKHP ,Clock signal width at high level"
|
|
line.byte 0x2 "IECKCNT,IEBus clock control register"
|
|
bitfld.byte 0x2 2. " CKOEN ,Clock output enable" "Input,Output"
|
|
bitfld.byte 0x2 1. " CKSS ,Clock source select" "External clock,Internal clock"
|
|
textline " "
|
|
bitfld.byte 0x2 0. " DIVEN ,Division period enable" "Disabled,Enabled"
|
|
tree "IEBus Transmit Data Buffers"
|
|
width 7.
|
|
hgroup.byte (0x100+0x0)++0x0
|
|
hide.byte 0x0 " TB1 ,IEBus Transmit Data Buffer 1"
|
|
in
|
|
hgroup.byte (0x100+0x1)++0x0
|
|
hide.byte 0x0 " TB2 ,IEBus Transmit Data Buffer 2"
|
|
in
|
|
hgroup.byte (0x100+0x2)++0x0
|
|
hide.byte 0x0 " TB3 ,IEBus Transmit Data Buffer 3"
|
|
in
|
|
hgroup.byte (0x100+0x3)++0x0
|
|
hide.byte 0x0 " TB4 ,IEBus Transmit Data Buffer 4"
|
|
in
|
|
hgroup.byte (0x100+0x4)++0x0
|
|
hide.byte 0x0 " TB5 ,IEBus Transmit Data Buffer 5"
|
|
in
|
|
hgroup.byte (0x100+0x5)++0x0
|
|
hide.byte 0x0 " TB6 ,IEBus Transmit Data Buffer 6"
|
|
in
|
|
hgroup.byte (0x100+0x6)++0x0
|
|
hide.byte 0x0 " TB7 ,IEBus Transmit Data Buffer 7"
|
|
in
|
|
hgroup.byte (0x100+0x7)++0x0
|
|
hide.byte 0x0 " TB8 ,IEBus Transmit Data Buffer 8"
|
|
in
|
|
hgroup.byte (0x100+0x8)++0x0
|
|
hide.byte 0x0 " TB9 ,IEBus Transmit Data Buffer 9"
|
|
in
|
|
hgroup.byte (0x100+0x9)++0x0
|
|
hide.byte 0x0 " TB10 ,IEBus Transmit Data Buffer 10"
|
|
in
|
|
hgroup.byte (0x100+0xA)++0x0
|
|
hide.byte 0x0 " TB11 ,IEBus Transmit Data Buffer 11"
|
|
in
|
|
hgroup.byte (0x100+0xB)++0x0
|
|
hide.byte 0x0 " TB12 ,IEBus Transmit Data Buffer 12"
|
|
in
|
|
hgroup.byte (0x100+0xC)++0x0
|
|
hide.byte 0x0 " TB13 ,IEBus Transmit Data Buffer 13"
|
|
in
|
|
hgroup.byte (0x100+0xD)++0x0
|
|
hide.byte 0x0 " TB14 ,IEBus Transmit Data Buffer 14"
|
|
in
|
|
hgroup.byte (0x100+0xE)++0x0
|
|
hide.byte 0x0 " TB15 ,IEBus Transmit Data Buffer 15"
|
|
in
|
|
hgroup.byte (0x100+0xF)++0x0
|
|
hide.byte 0x0 " TB16 ,IEBus Transmit Data Buffer 16"
|
|
in
|
|
hgroup.byte (0x100+0x10)++0x0
|
|
hide.byte 0x0 " TB17 ,IEBus Transmit Data Buffer 17"
|
|
in
|
|
hgroup.byte (0x100+0x11)++0x0
|
|
hide.byte 0x0 " TB18 ,IEBus Transmit Data Buffer 18"
|
|
in
|
|
hgroup.byte (0x100+0x12)++0x0
|
|
hide.byte 0x0 " TB19 ,IEBus Transmit Data Buffer 19"
|
|
in
|
|
hgroup.byte (0x100+0x13)++0x0
|
|
hide.byte 0x0 " TB20 ,IEBus Transmit Data Buffer 20"
|
|
in
|
|
hgroup.byte (0x100+0x14)++0x0
|
|
hide.byte 0x0 " TB21 ,IEBus Transmit Data Buffer 21"
|
|
in
|
|
hgroup.byte (0x100+0x15)++0x0
|
|
hide.byte 0x0 " TB22 ,IEBus Transmit Data Buffer 22"
|
|
in
|
|
hgroup.byte (0x100+0x16)++0x0
|
|
hide.byte 0x0 " TB23 ,IEBus Transmit Data Buffer 23"
|
|
in
|
|
hgroup.byte (0x100+0x17)++0x0
|
|
hide.byte 0x0 " TB24 ,IEBus Transmit Data Buffer 24"
|
|
in
|
|
hgroup.byte (0x100+0x18)++0x0
|
|
hide.byte 0x0 " TB25 ,IEBus Transmit Data Buffer 25"
|
|
in
|
|
hgroup.byte (0x100+0x19)++0x0
|
|
hide.byte 0x0 " TB26 ,IEBus Transmit Data Buffer 26"
|
|
in
|
|
hgroup.byte (0x100+0x1A)++0x0
|
|
hide.byte 0x0 " TB27 ,IEBus Transmit Data Buffer 27"
|
|
in
|
|
hgroup.byte (0x100+0x1B)++0x0
|
|
hide.byte 0x0 " TB28 ,IEBus Transmit Data Buffer 28"
|
|
in
|
|
hgroup.byte (0x100+0x1C)++0x0
|
|
hide.byte 0x0 " TB29 ,IEBus Transmit Data Buffer 29"
|
|
in
|
|
hgroup.byte (0x100+0x1D)++0x0
|
|
hide.byte 0x0 " TB30 ,IEBus Transmit Data Buffer 30"
|
|
in
|
|
hgroup.byte (0x100+0x1E)++0x0
|
|
hide.byte 0x0 " TB31 ,IEBus Transmit Data Buffer 31"
|
|
in
|
|
hgroup.byte (0x100+0x1F)++0x0
|
|
hide.byte 0x0 " TB32 ,IEBus Transmit Data Buffer 32"
|
|
in
|
|
tree.end
|
|
tree "IEBus Receive Data Buffers"
|
|
hgroup.byte (0x200+0x0)++0x0
|
|
hide.byte 0x0 " RB1 ,IEBus Receive Data Buffer 1"
|
|
in
|
|
hgroup.byte (0x200+0x1)++0x0
|
|
hide.byte 0x0 " RB2 ,IEBus Receive Data Buffer 2"
|
|
in
|
|
hgroup.byte (0x200+0x2)++0x0
|
|
hide.byte 0x0 " RB3 ,IEBus Receive Data Buffer 3"
|
|
in
|
|
hgroup.byte (0x200+0x3)++0x0
|
|
hide.byte 0x0 " RB4 ,IEBus Receive Data Buffer 4"
|
|
in
|
|
hgroup.byte (0x200+0x4)++0x0
|
|
hide.byte 0x0 " RB5 ,IEBus Receive Data Buffer 5"
|
|
in
|
|
hgroup.byte (0x200+0x5)++0x0
|
|
hide.byte 0x0 " RB6 ,IEBus Receive Data Buffer 6"
|
|
in
|
|
hgroup.byte (0x200+0x6)++0x0
|
|
hide.byte 0x0 " RB7 ,IEBus Receive Data Buffer 7"
|
|
in
|
|
hgroup.byte (0x200+0x7)++0x0
|
|
hide.byte 0x0 " RB8 ,IEBus Receive Data Buffer 8"
|
|
in
|
|
hgroup.byte (0x200+0x8)++0x0
|
|
hide.byte 0x0 " RB9 ,IEBus Receive Data Buffer 9"
|
|
in
|
|
hgroup.byte (0x200+0x9)++0x0
|
|
hide.byte 0x0 " RB10 ,IEBus Receive Data Buffer 10"
|
|
in
|
|
hgroup.byte (0x200+0xA)++0x0
|
|
hide.byte 0x0 " RB11 ,IEBus Receive Data Buffer 11"
|
|
in
|
|
hgroup.byte (0x200+0xB)++0x0
|
|
hide.byte 0x0 " RB12 ,IEBus Receive Data Buffer 12"
|
|
in
|
|
hgroup.byte (0x200+0xC)++0x0
|
|
hide.byte 0x0 " RB13 ,IEBus Receive Data Buffer 13"
|
|
in
|
|
hgroup.byte (0x200+0xD)++0x0
|
|
hide.byte 0x0 " RB14 ,IEBus Receive Data Buffer 14"
|
|
in
|
|
hgroup.byte (0x200+0xE)++0x0
|
|
hide.byte 0x0 " RB15 ,IEBus Receive Data Buffer 15"
|
|
in
|
|
hgroup.byte (0x200+0xF)++0x0
|
|
hide.byte 0x0 " RB16 ,IEBus Receive Data Buffer 16"
|
|
in
|
|
hgroup.byte (0x200+0x10)++0x0
|
|
hide.byte 0x0 " RB17 ,IEBus Receive Data Buffer 17"
|
|
in
|
|
hgroup.byte (0x200+0x11)++0x0
|
|
hide.byte 0x0 " RB18 ,IEBus Receive Data Buffer 18"
|
|
in
|
|
hgroup.byte (0x200+0x12)++0x0
|
|
hide.byte 0x0 " RB19 ,IEBus Receive Data Buffer 19"
|
|
in
|
|
hgroup.byte (0x200+0x13)++0x0
|
|
hide.byte 0x0 " RB20 ,IEBus Receive Data Buffer 20"
|
|
in
|
|
hgroup.byte (0x200+0x14)++0x0
|
|
hide.byte 0x0 " RB21 ,IEBus Receive Data Buffer 21"
|
|
in
|
|
hgroup.byte (0x200+0x15)++0x0
|
|
hide.byte 0x0 " RB22 ,IEBus Receive Data Buffer 22"
|
|
in
|
|
hgroup.byte (0x200+0x16)++0x0
|
|
hide.byte 0x0 " RB23 ,IEBus Receive Data Buffer 23"
|
|
in
|
|
hgroup.byte (0x200+0x17)++0x0
|
|
hide.byte 0x0 " RB24 ,IEBus Receive Data Buffer 24"
|
|
in
|
|
hgroup.byte (0x200+0x18)++0x0
|
|
hide.byte 0x0 " RB25 ,IEBus Receive Data Buffer 25"
|
|
in
|
|
hgroup.byte (0x200+0x19)++0x0
|
|
hide.byte 0x0 " RB26 ,IEBus Receive Data Buffer 26"
|
|
in
|
|
hgroup.byte (0x200+0x1A)++0x0
|
|
hide.byte 0x0 " RB27 ,IEBus Receive Data Buffer 27"
|
|
in
|
|
hgroup.byte (0x200+0x1B)++0x0
|
|
hide.byte 0x0 " RB28 ,IEBus Receive Data Buffer 28"
|
|
in
|
|
hgroup.byte (0x200+0x1C)++0x0
|
|
hide.byte 0x0 " RB29 ,IEBus Receive Data Buffer 29"
|
|
in
|
|
hgroup.byte (0x200+0x1D)++0x0
|
|
hide.byte 0x0 " RB30 ,IEBus Receive Data Buffer 30"
|
|
in
|
|
hgroup.byte (0x200+0x1E)++0x0
|
|
hide.byte 0x0 " RB31 ,IEBus Receive Data Buffer 31"
|
|
in
|
|
hgroup.byte (0x200+0x1F)++0x0
|
|
hide.byte 0x0 " RB32 ,IEBus Receive Data Buffer 32"
|
|
in
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "SCIF (Serial Communication Interface with FIFO)"
|
|
tree "Channel 0"
|
|
base ad:0xFFE40000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR0,Receive FIFO Data Register 0"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR0,Transmit FIFO Data Register 0"
|
|
if (((per.w(ad:0xFFE40000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR0,Serial Mode Register 0"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE40000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR0,Serial Mode Register 0"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR0,Serial Mode Register 0"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE40000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR0,Serial Control Register 0"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR0,Serial Control Register 0"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR0,Serial Status Register 0"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR0,Bit Rate Register 0"
|
|
if (((per.w(ad:0xFFE40000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR0,FIFO Control Register 0"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR0,FIFO Control Register 0"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR0,FIFO Data Count Register 0"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR0,Serial Port Register 0"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR0,Line Status Register 0"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR0,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE40000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR0,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR0,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 0"
|
|
line.word 0x00 "DL0,Frequency Division Register 0"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS0,Clock Select Register 0"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFE41000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR1,Receive FIFO Data Register 1"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR1,Transmit FIFO Data Register 1"
|
|
if (((per.w(ad:0xFFE41000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR1,Serial Mode Register 1"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE41000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR1,Serial Mode Register 1"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR1,Serial Mode Register 1"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE41000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR1,Serial Control Register 1"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR1,Serial Control Register 1"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR1,Serial Status Register 1"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR1,Bit Rate Register 1"
|
|
if (((per.w(ad:0xFFE41000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR1,FIFO Control Register 1"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR1,FIFO Control Register 1"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR1,FIFO Data Count Register 1"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR1,Serial Port Register 1"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR1,Line Status Register 1"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR1,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE41000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR1,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR1,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 1"
|
|
line.word 0x00 "DL1,Frequency Division Register 1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS1,Clock Select Register 1"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFE42000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR2,Receive FIFO Data Register 2"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR2,Transmit FIFO Data Register 2"
|
|
if (((per.w(ad:0xFFE42000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR2,Serial Mode Register 2"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE42000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR2,Serial Mode Register 2"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR2,Serial Mode Register 2"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE42000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR2,Serial Control Register 2"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR2,Serial Control Register 2"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR2,Serial Status Register 2"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR2,Bit Rate Register 2"
|
|
if (((per.w(ad:0xFFE42000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR2,FIFO Control Register 2"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR2,FIFO Control Register 2"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR2,FIFO Data Count Register 2"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR2,Serial Port Register 2"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR2,Line Status Register 2"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR2,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE42000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR2,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR2,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 2"
|
|
line.word 0x00 "DL2,Frequency Division Register 2"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS2,Clock Select Register 2"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFE43000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR3,Receive FIFO Data Register 3"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR3,Transmit FIFO Data Register 3"
|
|
if (((per.w(ad:0xFFE43000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR3,Serial Mode Register 3"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE43000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR3,Serial Mode Register 3"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR3,Serial Mode Register 3"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE43000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR3,Serial Control Register 3"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR3,Serial Control Register 3"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR3,Serial Status Register 3"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR3,Bit Rate Register 3"
|
|
if (((per.w(ad:0xFFE43000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR3,FIFO Control Register 3"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR3,FIFO Control Register 3"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR3,FIFO Data Count Register 3"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR3,Serial Port Register 3"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR3,Line Status Register 3"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR3,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE43000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR3,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR3,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 3"
|
|
line.word 0x00 "DL3,Frequency Division Register 3"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS3,Clock Select Register 3"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xFFE44000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR4,Receive FIFO Data Register 4"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR4,Transmit FIFO Data Register 4"
|
|
if (((per.w(ad:0xFFE44000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR4,Serial Mode Register 4"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE44000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR4,Serial Mode Register 4"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR4,Serial Mode Register 4"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE44000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR4,Serial Control Register 4"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR4,Serial Control Register 4"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR4,Serial Status Register 4"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR4,Bit Rate Register 4"
|
|
if (((per.w(ad:0xFFE44000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR4,FIFO Control Register 4"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR4,FIFO Control Register 4"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR4,FIFO Data Count Register 4"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR4,Serial Port Register 4"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR4,Line Status Register 4"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR4,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE44000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR4,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR4,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 4"
|
|
line.word 0x00 "DL4,Frequency Division Register 4"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS4,Clock Select Register 4"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xFFE45000
|
|
width 9.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "SCFRDR5,Receive FIFO Data Register 5"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "SCFTDR5,Transmit FIFO Data Register 5"
|
|
if (((per.w(ad:0xFFE45000))&0xa0)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR5,Serial Mode Register 5"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
elif (((per.w(ad:0xFFE45000))&0xa0)==0x00)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR5,Serial Mode Register 5"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1 bit,2 bits"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SCSMR5,Serial Mode Register 5"
|
|
bitfld.word 0x00 7. " C/A ,Communication mode" "Asynchronous,Synchronous"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8 bits,7 bits"
|
|
textline " "
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1 and 0" "Clkp clock,Clkp/4 clock,Clkp/16 clock,Clkp/64 clock"
|
|
endif
|
|
if (((per.w(ad:0xFFE45000))&0x80)==0x80)
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR5,Serial Control Register 5"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H"||cpu()=="R7S721021")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization output,Internal clk/SCK synchronization output,External clk/SCK synchronization input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK synchronization clk,Internal clk/SCK synchronization clk,External clk/SCK synchronization clk,?..."
|
|
endif
|
|
else
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SCSCR5,Serial Control Register 5"
|
|
sif (cpu()!="RZA1H"&&cpu()!="R7S721021")
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="RZA1H")
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Baud rate generator/SCK input,External clk/SCK input,"
|
|
else
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1 and 0" "Internal clk/SCK input,Internal clk/SCK output,External clk/SCK input,"
|
|
endif
|
|
endif
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SCFSR5,Serial Status Register 5"
|
|
rbitfld.word 0x00 12.--15. " PER[3:0] ,Parity error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.word 0x00 8.--11. " FER[3:0] ,Framing error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "Not ended,Ended"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SCBRR5,Bit Rate Register 5"
|
|
if (((per.w(ad:0xFFE45000))&0x80)==0x80)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR5,FIFO Control Register 5"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger" "1,2,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "SCFCR5,FIFO Control Register 5"
|
|
bitfld.word 0x00 8.--10. " RSTRG[2:0] ,RTS output active trigger" "15,1,4,6,8,10,12,14"
|
|
bitfld.word 0x00 6.--7. " RTRG[1:0] ,Receive FIFO data count trigger " "1,4,8,14"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " TTRG[1:0] ,Transmit FIFO data count trigger" "8(8),4(12),2(14),0(16)"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
endif
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "SCFDR5,FIFO Data Count Register 5"
|
|
bitfld.word 0x00 8.--12. " T[4:0] ,Number of non-transmitted data in SCFTDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R[4:0] ,Number of received data in SCFRDR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SCSPTR5,Serial Port Register 5"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS# pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS# pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock pin input/output" "Not output,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock pin data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Not output,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "SCLSR5,Line Status Register 5"
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021"))
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No error,Error"
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
sif (cpu()=="RZA1H")
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR5,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
sif (cpu()=="R7S721021")
|
|
if (((per.w(ad:0xFFE45000))&0x80)==0x0)
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR5,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
bitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "SCEMR5,Serial Extension Mode Register"
|
|
bitfld.word 0x00 7. " BGDM ,Baud rate generator double-speed mode" "Normal,Double-speed"
|
|
rbitfld.word 0x00 0. " ABCS ,Base clock select in asynchronous mode" "16 times,8 times"
|
|
endif
|
|
endif
|
|
sif ((cpu()!="RZA1H")&&(cpu()!="R7S721021")&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&!cpuis("R8A77980*")&&!cpuis("R8A77970*")&&!(cpuis("R8A77951")||cpuis("R8A77951-*"))&&!cpuis("R8A77995*")&&!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 5"
|
|
line.word 0x00 "DL5,Frequency Division Register 5"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS5,Clock Select Register 5"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
sif (cpu()=="R8A77440")||cpuis("R8A77951")||cpuis("R8A77951-*")||(cpu()=="R8A77930")||(cpu()=="R8A77970")||(cpu()=="R8A77420")
|
|
bitfld.word 0x00 14. " XIN ,Selects the baud rate generator source for the external clock between SCIF_CLK and ZS" "SCIF_CLK,ZS"
|
|
else
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "HSCIF (High Speed Serial Communication Interface with FIFO)"
|
|
tree "Channel 0"
|
|
base ad:0xFFE48000
|
|
width 11.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "HSFRDR,Receive FIFO Data Register"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "HSFTDR,Transmit FIFO Data Register"
|
|
if (((per.w(ad:0xFFE48000))&0x20)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HSSMR,Serial Mode Register"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8-bit,7-bit"
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1-bit,2-bit"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1-0" "S,S/4,S/16,S/64"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HSSMR,Serial Mode Register"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8-bit,7-bit"
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1-bit,2-bit"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1-0" "S,S/4,S/16,S/64"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "HSSCR,Serial Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")
|
|
rbitfld.word 0x00 14.--15. " TOT ,Set the time for a data ready or a timeout" "15 etu,31 etu,47 etu,63 etu"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 14.--15. " TOT ,Set the time for a data ready or a timeout" "15 etu,31 etu,47 etu,63 etu"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1/0" "Internal/HSCK as input,Internal/HSCK as output,External,?..."
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "HSFSR,Serial Status Register"
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "In progress,Ended"
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "HSBRR,Bit Rate Register"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "HSFCR,FIFO Control Register"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "HSFDR,FIFO Data Count Register"
|
|
sif (cpuis("R8A77980*"))||(cpuis("R8A77965*"))||(cpuis("R8A77960*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))||(cpuis("R8A77970*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||(cpu()=="R8A77470*")||(cpu()=="R8A77420*")||(cpu()=="R8A77430*")||(cpu()=="R8A77450*")
|
|
hexmask.word.byte 0x00 8.--15. 1. " T[7:0] ,Number of untransmitted data stored in HSFTDR"
|
|
hexmask.word.byte 0x00 0.--7. 1. " R[7:0] ,Number of received data stored in HSFRDR"
|
|
else
|
|
hexmask.word.byte 0x00 8.--15. 1. " T[7:0] ,Number of untransmitted data in SCFTDR"
|
|
hexmask.word.byte 0x00 0.--7. 1. " R[7:0] ,Number of received data in SCFRDR"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "HSSPTR,Serial Port Register"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS port input/output" "Input,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS port data" "Low level,High level"
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS port input/output" "Input,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS port data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock port input/output" "Input,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock port data" "Low level,High level"
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Input,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "HSLSR,Line Status Register"
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "HSSRR,Sampling Rate Register"
|
|
bitfld.word 0x00 15. " SRE ,Sampling rate register enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " SRDE ,Sampling point register enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--11. " SRHP ,Sampling point register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--4. " SRCYC ,Sampling rate register" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "HSRER,Serial Error Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " PER[6:0] ,Parity error count"
|
|
hexmask.word.byte 0x00 0.--6. 1. " FER[6:0] ,Framing error count"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "HSRTGR,RTS Output Active Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RSTRG[6:0] ,RTS output active trigger count"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "HSRTRGR,Receive FIFO Data Count Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RTRG[6:0] ,Receive FIFO data count trigger"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "HSTTRGR,Transmit FIFO Data Count Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " TTRG[6:0] ,Transmit FIFO data count trigger"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77980*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77995*"))&&(!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 0"
|
|
line.word 0x00 "DL0,Frequency Division Register 0"
|
|
sif cpuis("R8A77470"*)||cpuis("R8A77951*")||cpuis("R8A77951-*")||cpuis("R8A77430*")||cpuis("R8A77440*")
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS0,Clock Select Register 0"
|
|
bitfld.word 0x00 15. " CKS ,Clock output" "SC_CLK,HSCK"
|
|
bitfld.word 0x00 14. " XIN ,Baud rate generator clock source" "SCIF_CLK,ZS"
|
|
elif cpuis("R8A77420*")
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS0,Clock Select Register 0"
|
|
bitfld.word 0x00 15. " CKS ,Clock output" "SC_CLK,HSCK"
|
|
bitfld.word 0x00 14. " XIN ,Baud rate generator clock source" "SCIF_CLK,ZS"
|
|
else
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS0,Clock Select Register 0"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFE49000
|
|
width 11.
|
|
hgroup.byte 0x14++0x00
|
|
hide.byte 0x00 "HSFRDR,Receive FIFO Data Register"
|
|
in
|
|
wgroup.byte 0x0C++0x00
|
|
line.byte 0x00 "HSFTDR,Transmit FIFO Data Register"
|
|
if (((per.w(ad:0xFFE49000))&0x20)==0x20)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HSSMR,Serial Mode Register"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8-bit,7-bit"
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " O/E ,Parity mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1-bit,2-bit"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1-0" "S,S/4,S/16,S/64"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "HSSMR,Serial Mode Register"
|
|
bitfld.word 0x00 6. " CHR ,Character length" "8-bit,7-bit"
|
|
bitfld.word 0x00 5. " PE ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " STOP ,Stop bit length" "1-bit,2-bit"
|
|
bitfld.word 0x00 0.--1. " CKS[1:0] ,Clock select 1-0" "S,S/4,S/16,S/64"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "HSSCR,Serial Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")
|
|
rbitfld.word 0x00 14.--15. " TOT ,Set the time for a data ready or a timeout" "15 etu,31 etu,47 etu,63 etu"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 14.--15. " TOT ,Set the time for a data ready or a timeout" "15 etu,31 etu,47 etu,63 etu"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 11. " TEIE ,Transmit end interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " RIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " TE ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RE ,Receive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " REIE ,Receive error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " TOIE ,Timeout interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CKE[1:0] ,Clock enable 1/0" "Internal/HSCK as input,Internal/HSCK as output,External,?..."
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "HSFSR,Serial Status Register"
|
|
bitfld.word 0x00 7. " ER ,Receive error" "No error,Error"
|
|
bitfld.word 0x00 6. " TEND ,Transmit end" "In progress,Ended"
|
|
bitfld.word 0x00 5. " TDFE ,Transmit FIFO data empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 4. " BRK ,Break detect" "Not detected,Detected"
|
|
rbitfld.word 0x00 3. " FER ,Framing error" "No error,Error"
|
|
rbitfld.word 0x00 2. " PER ,Parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " RDF ,Receive FIFO data full" "Not full,Full"
|
|
bitfld.word 0x00 0. " DR ,Receive data ready" "Not ready,Ready"
|
|
group.byte 0x04++0x01
|
|
line.byte 0x00 "HSBRR,Bit Rate Register"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "HSFCR,FIFO Control Register"
|
|
bitfld.word 0x00 3. " MCE ,Modem control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO data register reset" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " LOOP ,Loopback test" "Disabled,Enabled"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "HSFDR,FIFO Data Count Register"
|
|
sif (cpuis("R8A77980*"))||(cpuis("R8A77965*"))||(cpuis("R8A77960*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))||(cpuis("R8A77970*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||(cpu()=="R8A77470*")||(cpu()=="R8A77420*")||(cpu()=="R8A77430*")||(cpu()=="R8A77450*")
|
|
hexmask.word.byte 0x00 8.--15. 1. " T[7:0] ,Number of untransmitted data stored in HSFTDR"
|
|
hexmask.word.byte 0x00 0.--7. 1. " R[7:0] ,Number of received data stored in HSFRDR"
|
|
else
|
|
hexmask.word.byte 0x00 8.--15. 1. " T[7:0] ,Number of untransmitted data in SCFTDR"
|
|
hexmask.word.byte 0x00 0.--7. 1. " R[7:0] ,Number of received data in SCFRDR"
|
|
endif
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "HSSPTR,Serial Port Register"
|
|
bitfld.word 0x00 7. " RTSIO ,Serial port - RTS port input/output" "Input,Output"
|
|
bitfld.word 0x00 6. " RTSDT ,Serial port - RTS port data" "Low level,High level"
|
|
bitfld.word 0x00 5. " CTSIO ,Serial port - CTS port input/output" "Input,Output"
|
|
bitfld.word 0x00 4. " CTSDT ,Serial port - CTS port data" "Low level,High level"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SCKIO ,Serial port - clock port input/output" "Input,Output"
|
|
bitfld.word 0x00 2. " SCKDT ,Serial port - clock port data" "Low level,High level"
|
|
bitfld.word 0x00 1. " SPB2IO ,Serial port - break input/output" "Input,Output"
|
|
bitfld.word 0x00 0. " SPB2DT ,Serial port - break data" "Low level,High level"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "HSLSR,Line Status Register"
|
|
bitfld.word 0x00 2. " TO ,Timeout" "No timeout,Timeout"
|
|
bitfld.word 0x00 0. " ORER ,Overrun error" "No error,Error"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "HSSRR,Sampling Rate Register"
|
|
bitfld.word 0x00 15. " SRE ,Sampling rate register enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " SRDE ,Sampling point register enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--11. " SRHP ,Sampling point register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--4. " SRCYC ,Sampling rate register" ",,,,,,,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "HSRER,Serial Error Register"
|
|
hexmask.word.byte 0x00 8.--14. 1. " PER[6:0] ,Parity error count"
|
|
hexmask.word.byte 0x00 0.--6. 1. " FER[6:0] ,Framing error count"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "HSRTGR,RTS Output Active Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RSTRG[6:0] ,RTS output active trigger count"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "HSRTRGR,Receive FIFO Data Count Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " RTRG[6:0] ,Receive FIFO data count trigger"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "HSTTRGR,Transmit FIFO Data Count Trigger Register"
|
|
hexmask.word.byte 0x00 0.--6. 1. " TTRG[6:0] ,Transmit FIFO data count trigger"
|
|
sif (cpu()!="RCARH2")&&(cpu()!="RCARM2")&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(!cpuis("R8A77970*"))&&(!cpuis("R8A77980*"))&&(!cpuis("R8A77965*"))&&(!cpuis("R8A77960*"))&&(!cpuis("R8A77995*"))&&(!cpuis("R8A77990*"))
|
|
group.word 0x30++0x01 "BRG 1"
|
|
line.word 0x00 "DL1,Frequency Division Register 1"
|
|
sif cpuis("R8A77470"*)||cpuis("R8A77951*")||cpuis("R8A77951-*")||cpuis("R8A77430*")||cpuis("R8A77440*")
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS1,Clock Select Register 1"
|
|
bitfld.word 0x00 15. " CKS ,Clock output" "SC_CLK,HSCK"
|
|
bitfld.word 0x00 14. " XIN ,Baud rate generator clock source" "SCIF_CLK,ZS"
|
|
elif cpuis("R8A77420*")
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS1,Clock Select Register 1"
|
|
bitfld.word 0x00 15. " CKS ,Clock output" "SC_CLK,HSCK"
|
|
bitfld.word 0x00 14. " XIN ,Baud rate generator clock source" "SCIF_CLK,ZS"
|
|
else
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "CKS1,Clock Select Register 1"
|
|
bitfld.word 0x00 15. " CKS ,Switches the output between the frequency divided clock (SC_CLK) and external clock (SCK)" "SC_CLK,SCK"
|
|
bitfld.word 0x00 14. " XIN ,Selects the clock source for the external baud rate from SCIF_CLK or clks" "SCIF_CLK,clks"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C Bus Interface"
|
|
tree "Channel 0"
|
|
base ad:0xFFC70000
|
|
width 9.
|
|
group.long 0x00++0x3 "Slave Registers"
|
|
line.long 0x00 "ICSC,Slave Control Register"
|
|
bitfld.long 0x00 3. " SDBS ,Slave Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 2. " SIE ,Slave Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GCAE ,General Call Acknowledgement Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FNA ,Forced Non Acknowledgement" "Not forced,Forced"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ICSS,Slave Status Register"
|
|
bitfld.long 0x00 6. " GCAR ,General Call Address Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " STM ,Slave Transmit Mode" "Write,Read"
|
|
bitfld.long 0x00 4. " SSR ,Slave Stop Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDE ,Slave Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SDT ,Slave Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " SDR ,Slave Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAR ,Slave Address Received" "Not received,Received"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ICSIE,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " SSRE ,Slave Stop Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SDEE ,Slave Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SDTE ,Slave Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDRE ,Slave Data Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SARE ,Slave Address Received Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADD[6:0] ,Slave Address"
|
|
group.long 0x04++0x3 "Master Registers"
|
|
line.long 0x00 "ICMC,Master Control Register"
|
|
bitfld.long 0x00 7. " MDBS ,Master Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 6. " FSCL ,Forced SCL" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " FSDA ,Forced SDA" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OBPC ,Override Bus Pin Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MIE ,Master Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TSBE ,Start Byte Transmission Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSB ,Forced Stop onto the Bus" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " ESG ,Enable Start Generation" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "ICMS,Master Status Register"
|
|
bitfld.long 0x00 6. " MNR ,Master NACK Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " MAL ,Master Arbitration Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 4. " MST ,Master Stop Transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDE ,Master Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " MDT ,Master Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " MDR ,Master Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT ,Master Address Transmitted" "Not transmitted,Transmitted"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ICMIE,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " MNRE ,Master NACK Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MALE ,Master Arbitration Lost Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MSTE ,Master Stop Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDEE ,Master Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MDTE ,Master Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MDRE ,Master Data Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MATE ,Master Address Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "ICMA,Master Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SADD[6:0] ,Slave address"
|
|
bitfld.long 0x00 0. " STM1 ,Slave transfer mode" "Write,Read"
|
|
textline " "
|
|
textline " "
|
|
width 12.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ICCC,Clock Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpu()=="R8A7792X")
|
|
hexmask.long.byte 0x00 3.--8. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--2. " CDF ,Clock Division Factor" "1,2,3,4,?..."
|
|
else
|
|
hexmask.long.byte 0x00 2.--7. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--1. " CDF ,Clock Division Factor" "1,2,3,4"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ICRXD/ICTX,Receive/Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXD/TXD ,Receive/Transmit Data"
|
|
sif cpu()!="R8A7792X"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ICCCR,Clock Control Register 2"
|
|
bitfld.long 0x00 2. " CDFD ,CDF Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " HLSE ,HIGH/LOW Separate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SME ,SCL Mask Enable" "Disabled,Enabled"
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "ICMP,SCL Mask Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SMD ,SCL Mask Division"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ICHP,SCL HIGH control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCHD ,SCL HIGH Clock Division"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ICLP,SCL LOW control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCLD ,SCL LOW Clock Division"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFC71000
|
|
width 9.
|
|
group.long 0x00++0x3 "Slave Registers"
|
|
line.long 0x00 "ICSC,Slave Control Register"
|
|
bitfld.long 0x00 3. " SDBS ,Slave Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 2. " SIE ,Slave Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GCAE ,General Call Acknowledgement Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FNA ,Forced Non Acknowledgement" "Not forced,Forced"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ICSS,Slave Status Register"
|
|
bitfld.long 0x00 6. " GCAR ,General Call Address Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " STM ,Slave Transmit Mode" "Write,Read"
|
|
bitfld.long 0x00 4. " SSR ,Slave Stop Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDE ,Slave Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SDT ,Slave Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " SDR ,Slave Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAR ,Slave Address Received" "Not received,Received"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ICSIE,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " SSRE ,Slave Stop Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SDEE ,Slave Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SDTE ,Slave Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDRE ,Slave Data Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SARE ,Slave Address Received Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADD[6:0] ,Slave Address"
|
|
group.long 0x04++0x3 "Master Registers"
|
|
line.long 0x00 "ICMC,Master Control Register"
|
|
bitfld.long 0x00 7. " MDBS ,Master Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 6. " FSCL ,Forced SCL" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " FSDA ,Forced SDA" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OBPC ,Override Bus Pin Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MIE ,Master Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TSBE ,Start Byte Transmission Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSB ,Forced Stop onto the Bus" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " ESG ,Enable Start Generation" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "ICMS,Master Status Register"
|
|
bitfld.long 0x00 6. " MNR ,Master NACK Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " MAL ,Master Arbitration Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 4. " MST ,Master Stop Transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDE ,Master Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " MDT ,Master Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " MDR ,Master Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT ,Master Address Transmitted" "Not transmitted,Transmitted"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ICMIE,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " MNRE ,Master NACK Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MALE ,Master Arbitration Lost Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MSTE ,Master Stop Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDEE ,Master Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MDTE ,Master Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MDRE ,Master Data Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MATE ,Master Address Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "ICMA,Master Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SADD[6:0] ,Slave address"
|
|
bitfld.long 0x00 0. " STM1 ,Slave transfer mode" "Write,Read"
|
|
textline " "
|
|
textline " "
|
|
width 12.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ICCC,Clock Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpu()=="R8A7792X")
|
|
hexmask.long.byte 0x00 3.--8. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--2. " CDF ,Clock Division Factor" "1,2,3,4,?..."
|
|
else
|
|
hexmask.long.byte 0x00 2.--7. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--1. " CDF ,Clock Division Factor" "1,2,3,4"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ICRXD/ICTX,Receive/Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXD/TXD ,Receive/Transmit Data"
|
|
sif cpu()!="R8A7792X"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ICCCR,Clock Control Register 2"
|
|
bitfld.long 0x00 2. " CDFD ,CDF Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " HLSE ,HIGH/LOW Separate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SME ,SCL Mask Enable" "Disabled,Enabled"
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "ICMP,SCL Mask Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SMD ,SCL Mask Division"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ICHP,SCL HIGH control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCHD ,SCL HIGH Clock Division"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ICLP,SCL LOW control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCLD ,SCL LOW Clock Division"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFC72000
|
|
width 9.
|
|
group.long 0x00++0x3 "Slave Registers"
|
|
line.long 0x00 "ICSC,Slave Control Register"
|
|
bitfld.long 0x00 3. " SDBS ,Slave Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 2. " SIE ,Slave Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GCAE ,General Call Acknowledgement Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FNA ,Forced Non Acknowledgement" "Not forced,Forced"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ICSS,Slave Status Register"
|
|
bitfld.long 0x00 6. " GCAR ,General Call Address Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " STM ,Slave Transmit Mode" "Write,Read"
|
|
bitfld.long 0x00 4. " SSR ,Slave Stop Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDE ,Slave Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SDT ,Slave Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " SDR ,Slave Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAR ,Slave Address Received" "Not received,Received"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ICSIE,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " SSRE ,Slave Stop Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SDEE ,Slave Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SDTE ,Slave Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDRE ,Slave Data Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SARE ,Slave Address Received Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADD[6:0] ,Slave Address"
|
|
group.long 0x04++0x3 "Master Registers"
|
|
line.long 0x00 "ICMC,Master Control Register"
|
|
bitfld.long 0x00 7. " MDBS ,Master Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 6. " FSCL ,Forced SCL" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " FSDA ,Forced SDA" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OBPC ,Override Bus Pin Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MIE ,Master Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TSBE ,Start Byte Transmission Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSB ,Forced Stop onto the Bus" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " ESG ,Enable Start Generation" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "ICMS,Master Status Register"
|
|
bitfld.long 0x00 6. " MNR ,Master NACK Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " MAL ,Master Arbitration Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 4. " MST ,Master Stop Transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDE ,Master Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " MDT ,Master Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " MDR ,Master Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT ,Master Address Transmitted" "Not transmitted,Transmitted"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ICMIE,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " MNRE ,Master NACK Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MALE ,Master Arbitration Lost Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MSTE ,Master Stop Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDEE ,Master Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MDTE ,Master Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MDRE ,Master Data Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MATE ,Master Address Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "ICMA,Master Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SADD[6:0] ,Slave address"
|
|
bitfld.long 0x00 0. " STM1 ,Slave transfer mode" "Write,Read"
|
|
textline " "
|
|
textline " "
|
|
width 12.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ICCC,Clock Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpu()=="R8A7792X")
|
|
hexmask.long.byte 0x00 3.--8. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--2. " CDF ,Clock Division Factor" "1,2,3,4,?..."
|
|
else
|
|
hexmask.long.byte 0x00 2.--7. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--1. " CDF ,Clock Division Factor" "1,2,3,4"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ICRXD/ICTX,Receive/Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXD/TXD ,Receive/Transmit Data"
|
|
sif cpu()!="R8A7792X"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ICCCR,Clock Control Register 2"
|
|
bitfld.long 0x00 2. " CDFD ,CDF Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " HLSE ,HIGH/LOW Separate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SME ,SCL Mask Enable" "Disabled,Enabled"
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "ICMP,SCL Mask Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SMD ,SCL Mask Division"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ICHP,SCL HIGH control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCHD ,SCL HIGH Clock Division"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ICLP,SCL LOW control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCLD ,SCL LOW Clock Division"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFC73000
|
|
width 9.
|
|
group.long 0x00++0x3 "Slave Registers"
|
|
line.long 0x00 "ICSC,Slave Control Register"
|
|
bitfld.long 0x00 3. " SDBS ,Slave Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 2. " SIE ,Slave Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " GCAE ,General Call Acknowledgement Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FNA ,Forced Non Acknowledgement" "Not forced,Forced"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "ICSS,Slave Status Register"
|
|
bitfld.long 0x00 6. " GCAR ,General Call Address Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " STM ,Slave Transmit Mode" "Write,Read"
|
|
bitfld.long 0x00 4. " SSR ,Slave Stop Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SDE ,Slave Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " SDT ,Slave Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " SDR ,Slave Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SAR ,Slave Address Received" "Not received,Received"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ICSIE,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 4. " SSRE ,Slave Stop Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SDEE ,Slave Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SDTE ,Slave Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SDRE ,Slave Data Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SARE ,Slave Address Received Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x1c++0x3
|
|
line.long 0x00 "ICSA,Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SADD[6:0] ,Slave Address"
|
|
group.long 0x04++0x3 "Master Registers"
|
|
line.long 0x00 "ICMC,Master Control Register"
|
|
bitfld.long 0x00 7. " MDBS ,Master Data Buffer Select" ",Single"
|
|
bitfld.long 0x00 6. " FSCL ,Forced SCL" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " FSDA ,Forced SDA" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OBPC ,Override Bus Pin Control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MIE ,Master Interface Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TSBE ,Start Byte Transmission Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSB ,Forced Stop onto the Bus" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " ESG ,Enable Start Generation" "Disabled,Enabled"
|
|
group.long 0xc++0x3
|
|
line.long 0x00 "ICMS,Master Status Register"
|
|
bitfld.long 0x00 6. " MNR ,Master NACK Received" "Not received,Received"
|
|
bitfld.long 0x00 5. " MAL ,Master Arbitration Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 4. " MST ,Master Stop Transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDE ,Master Data Empty" "Not empty,Empty"
|
|
bitfld.long 0x00 2. " MDT ,Master Data Transmitted" "Not transmitted,Transmitted"
|
|
bitfld.long 0x00 1. " MDR ,Master Data Received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT ,Master Address Transmitted" "Not transmitted,Transmitted"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "ICMIE,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 6. " MNRE ,Master NACK Received Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MALE ,Master Arbitration Lost Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MSTE ,Master Stop Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MDEE ,Master Data Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MDTE ,Master Data Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MDRE ,Master Data Received Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MATE ,Master Address Transmitted Interrupt Enable" "Disabled,Enabled"
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "ICMA,Master Address Register"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SADD[6:0] ,Slave address"
|
|
bitfld.long 0x00 0. " STM1 ,Slave transfer mode" "Write,Read"
|
|
textline " "
|
|
textline " "
|
|
width 12.
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "ICCC,Clock Control Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8A77940")||(cpu()=="R8A7792X")
|
|
hexmask.long.byte 0x00 3.--8. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--2. " CDF ,Clock Division Factor" "1,2,3,4,?..."
|
|
else
|
|
hexmask.long.byte 0x00 2.--7. 1. " SCGD ,SCL Clock Generation Divider"
|
|
bitfld.long 0x00 0.--1. " CDF ,Clock Division Factor" "1,2,3,4"
|
|
endif
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "ICRXD/ICTX,Receive/Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXD/TXD ,Receive/Transmit Data"
|
|
sif cpu()!="R8A7792X"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ICCCR,Clock Control Register 2"
|
|
bitfld.long 0x00 2. " CDFD ,CDF Disable" "No,Yes"
|
|
bitfld.long 0x00 1. " HLSE ,HIGH/LOW Separate Control Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SME ,SCL Mask Enable" "Disabled,Enabled"
|
|
group.long 0x2c++0x03
|
|
line.long 0x00 "ICMP,SCL Mask Control Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SMD ,SCL Mask Division"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ICHP,SCL HIGH control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCHD ,SCL HIGH Clock Division"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ICLP,SCL LOW control register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCLD ,SCL LOW Clock Division"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "HSPI (Serial Peripheral Interface)"
|
|
tree "Channel 0"
|
|
base ad:0xFFFC7000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPCR,Control Register"
|
|
bitfld.long 0x00 09. " CCA ,Method for Assertion of /HSPI_CS when Continuous Output of the Clock is Enabled" "Half cycle delay,One cycle mask"
|
|
bitfld.long 0x00 08. " CCO ,Sequential Clock Output no data transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " FBS ,First Bit Start" "First edge,Second edge"
|
|
textline " "
|
|
bitfld.long 0x00 06. " CLKP ,Serial Clock Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 05. " IDIV ,Initial Clock Division Ratio" "/16,/128"
|
|
bitfld.long 0x00 00.--04. " CLKC ,Clock Division Count" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
if (((per.l(ad:0xFFFC7000+0x8))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 10. " TXFU ,Transmit FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 09. " TXHA ,Transmit FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 08. " TXEM ,Transmit FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 07. " RXFU ,Receive FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 06. " RXHA ,Receive FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 05. " RXEM ,Receive FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPSCR,System Control Register"
|
|
bitfld.long 0x00 13. " TEIE ,Transmit FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " THIE ,Transmit FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RNIE ,Receive FIFO Not Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RHIE ,Receive FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " RFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " FFEN ,FIFO Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " LMSB ,LSB/MSB First Control" "MSB,LSB"
|
|
bitfld.long 0x00 06. " CSV ,Chip Select Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CSA ,Automatic/Manual Chip Select" "Automatic,Manual"
|
|
bitfld.long 0x00 04. " TFIE ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " ROIE ,Receive Overrun Occured/Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 02. " RXDE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXDE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 00. " MASL ,Master/Slave Select Bit" "Slave,Master"
|
|
line.long 0x04 "SPTBR,Transmit Buffer Register"
|
|
hexmask.long.byte 0x04 00.--07. 1. " TD ,Transmit Data"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SPRBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x00 00.--07. 1. " RD ,Receive Data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SPCR2,Control Register 2"
|
|
bitfld.long 0x00 15. " HFE ,High-speed transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " CKHP ,Serial clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " CKCYC ,Serial clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFFC8000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPCR,Control Register"
|
|
bitfld.long 0x00 09. " CCA ,Method for Assertion of /HSPI_CS when Continuous Output of the Clock is Enabled" "Half cycle delay,One cycle mask"
|
|
bitfld.long 0x00 08. " CCO ,Sequential Clock Output no data transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " FBS ,First Bit Start" "First edge,Second edge"
|
|
textline " "
|
|
bitfld.long 0x00 06. " CLKP ,Serial Clock Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 05. " IDIV ,Initial Clock Division Ratio" "/16,/128"
|
|
bitfld.long 0x00 00.--04. " CLKC ,Clock Division Count" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
if (((per.l(ad:0xFFFC8000+0x8))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 10. " TXFU ,Transmit FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 09. " TXHA ,Transmit FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 08. " TXEM ,Transmit FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 07. " RXFU ,Receive FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 06. " RXHA ,Receive FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 05. " RXEM ,Receive FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPSCR,System Control Register"
|
|
bitfld.long 0x00 13. " TEIE ,Transmit FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " THIE ,Transmit FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RNIE ,Receive FIFO Not Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RHIE ,Receive FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " RFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " FFEN ,FIFO Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " LMSB ,LSB/MSB First Control" "MSB,LSB"
|
|
bitfld.long 0x00 06. " CSV ,Chip Select Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CSA ,Automatic/Manual Chip Select" "Automatic,Manual"
|
|
bitfld.long 0x00 04. " TFIE ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " ROIE ,Receive Overrun Occured/Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 02. " RXDE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXDE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 00. " MASL ,Master/Slave Select Bit" "Slave,Master"
|
|
line.long 0x04 "SPTBR,Transmit Buffer Register"
|
|
hexmask.long.byte 0x04 00.--07. 1. " TD ,Transmit Data"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SPRBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x00 00.--07. 1. " RD ,Receive Data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SPCR2,Control Register 2"
|
|
bitfld.long 0x00 15. " HFE ,High-speed transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " CKHP ,Serial clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " CKCYC ,Serial clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFFC6000
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPCR,Control Register"
|
|
bitfld.long 0x00 09. " CCA ,Method for Assertion of /HSPI_CS when Continuous Output of the Clock is Enabled" "Half cycle delay,One cycle mask"
|
|
bitfld.long 0x00 08. " CCO ,Sequential Clock Output no data transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " FBS ,First Bit Start" "First edge,Second edge"
|
|
textline " "
|
|
bitfld.long 0x00 06. " CLKP ,Serial Clock Polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 05. " IDIV ,Initial Clock Division Ratio" "/16,/128"
|
|
bitfld.long 0x00 00.--04. " CLKC ,Clock Division Count" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
if (((per.l(ad:0xFFFC6000+0x8))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 10. " TXFU ,Transmit FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 09. " TXHA ,Transmit FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 08. " TXEM ,Transmit FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 07. " RXFU ,Receive FIFO Full Flag" "Not full,Full"
|
|
bitfld.long 0x00 06. " RXHA ,Receive FIFO Halfway Flag" "No halfway,Halfway"
|
|
bitfld.long 0x00 05. " RXEM ,Receive FIFO Empty Flag" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPSR,Status Register"
|
|
bitfld.long 0x00 04. " RXOO ,Receive Buffer Overrun Occurred Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 03. " RXOW ,Receive Buffer Overrun Warning Flag" "No overrun,Overrun"
|
|
bitfld.long 0x00 02. " RXFL ,Receive Buffer Full Status Flag" "Read SPRBR,Load SPRBR"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXFN ,Transmit Complete Status Flag" "Not Completed,Completed"
|
|
bitfld.long 0x00 00. " TXFL ,Transmit Buffer Full Status Flag" "SPTBR not full,SPTBR full"
|
|
endif
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "SPSCR,System Control Register"
|
|
bitfld.long 0x00 13. " TEIE ,Transmit FIFO Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " THIE ,Transmit FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RNIE ,Receive FIFO Not Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RHIE ,Receive FIFO Halfway Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 09. " RFIE ,Receive FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 08. " FFEN ,FIFO Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 07. " LMSB ,LSB/MSB First Control" "MSB,LSB"
|
|
bitfld.long 0x00 06. " CSV ,Chip Select Value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CSA ,Automatic/Manual Chip Select" "Automatic,Manual"
|
|
bitfld.long 0x00 04. " TFIE ,Transmit Complete Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " ROIE ,Receive Overrun Occured/Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 02. " RXDE ,Receive DMA Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TXDE ,Transmit DMA Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 00. " MASL ,Master/Slave Select Bit" "Slave,Master"
|
|
line.long 0x04 "SPTBR,Transmit Buffer Register"
|
|
hexmask.long.byte 0x04 00.--07. 1. " TD ,Transmit Data"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SPRBR,Receive Buffer Register"
|
|
hexmask.long.byte 0x00 00.--07. 1. " RD ,Receive Data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SPCR2,Control Register 2"
|
|
bitfld.long 0x00 15. " HFE ,High-speed transfer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--10. " CKHP ,Serial clock high period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " CKCYC ,Serial clock period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "MMC (Multi Media Card interface)"
|
|
tree "Channel 0"
|
|
base ad:0xFFE5A000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CMD_SET,Command Setting Register"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x00 30. " BOOT ,Boot operation" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--29. " CMD ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " RTYP ,Response Type" "No response,6-byte,17-byte,?..."
|
|
bitfld.long 0x00 21. " RBSY ,Response Busy Select" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 19. " WDAT ,Presence/Absence of Data" "Not present,Present"
|
|
bitfld.long 0x00 18. " DWEN ,Read/Write" "Read,Write"
|
|
bitfld.long 0x00 17. " CMLTE ,Single/Multi Block Transfer Select" "Single,Multi"
|
|
bitfld.long 0x00 16. " CMD12EN ,Automatic CMD12 Issuance" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RIDXC ,Response Index Check" "Response index,Check bits,No checking,?..."
|
|
bitfld.long 0x00 12.--13. " RCRC7C ,Response CRC7 Check" "CRC7,Check bits,Internal CRC7,No checking"
|
|
bitfld.long 0x00 10. " CRC16C ,CRC16 Check in Reception" "Checked,Not checked"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x00 9. " BOOTACK ,Receive Boot Acknowledge" "Not acknowledged,Acknowledged"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8. " CRCSTE ,CRC Status Reception" "Received,Not received"
|
|
bitfld.long 0x00 7. " TBIT ,Transmission Bit Setting" "Received,Not received"
|
|
bitfld.long 0x00 6. " OPDM ,Open-Drain Output Mode" "Normal,Open-drain"
|
|
bitfld.long 0x00 3. " SBIT ,Read Data Start Bit Detection Setting" "DATW specified = 0,MMCDAT[0] = 0"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " DATW ,Data Bus Width Setting" "1,4,8,?..."
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "ARG,Argument Register"
|
|
line.long 0x04 "ARG_CMD12,Argument Register for Automatically-Issued CMD12 Register"
|
|
line.long 0x08 "CMD_CTRL,Argument Register for Automatically-Issued CMD12 Register"
|
|
bitfld.long 0x08 0. " BREAK ,Forcible Termination of Command Sequence" "0,1"
|
|
line.long 0x0c "BLOCK_SET,Transfer Block Setting Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " BLKCNT ,Number of Blocks for Transfer"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BLKSIZ ,Transfer Block Size"
|
|
line.long 0x10 "CLK_CTRL,Clock Control Register"
|
|
bitfld.long 0x10 24. " CLKEN ,MMC Clock Output Control" "Not output,Output"
|
|
bitfld.long 0x10 16.--19. " CLKDIV ,MMC Clock Frequency Setting" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x10 12.--13. " SRSPTO ,Response Timeout Setting" "64,128,256,?..."
|
|
newline
|
|
bitfld.long 0x10 8.--11. " SRBSYTO ,Response Busy Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x10 4.--7. " SRWDTO ,Write Data/Read Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
line.long 0x14 "BUF_ACC,Buffer Access Configuration Register"
|
|
bitfld.long 0x14 25. " DMAWEN ,Buffer Write DMA Transfer Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DMAREN ,Buffer Read DMA Transfer Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " BUSW ,Data register access size selection" "32-bit,16-bit"
|
|
bitfld.long 0x14 16. " ATYP ,Buffer access selection" "Not swapped bytw-wise,Swapped byte-wise"
|
|
if ((per.l(ad:0xFFE5A000)&0xc00000)==0x800000)
|
|
rgroup.long 0x20++0x0F
|
|
line.long 0x00 "RESP3,Response Register 3"
|
|
line.long 0x04 "RESP2,Response Register 2"
|
|
line.long 0x08 "RESP1,Response Register 1"
|
|
line.long 0x0C "RESP0,Response Register 0"
|
|
elif ((per.l(ad:0xFFE5A000)&0xc00000)==0x400000)
|
|
hgroup.long 0x20++0x0B
|
|
hide.long 0x00 "RESP3,Response Register 3"
|
|
hide.long 0x04 "RESP2,Response Register 2"
|
|
hide.long 0x08 "RESP1,Response Register 1"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RESP0,Response Register 0"
|
|
else
|
|
hgroup.long 0x20++0x0F
|
|
hide.long 0x00 "RESP3,Response Register 3"
|
|
hide.long 0x04 "RESP2,Response Register 2"
|
|
hide.long 0x08 "RESP1,Response Register 1"
|
|
hide.long 0x0C "RESP0,Response Register 0"
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RESP_CMD12,Response Register for Automatically-Issued CMD12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DATA,Data Register"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BOOT,Boot Operation Setting Register"
|
|
bitfld.long 0x00 28.--31. " BTCLKDIV ,MMC Clock Frequency Setting in Boot Mode" "/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 24.--27. " SBTACKTO ,Boot Acknowledge Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x00 20.--23. " S1STBTDATTO ,1st Boot Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x00 16.--19. " SBTDATTO ,Interval Between Boot Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "INT,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " CMD12DRE ,Automatic CMD12 Issuance Buffer Read Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " CMD12RBE ,Automatic CMD12 Issuance Response Busy Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " CMD12CRE ,Automatic CMD12 Response Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " DTRANE ,Data Transmission Complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 22. " BUFRE ,Buffer Read Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " BUFWEN ,Buffer Write Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " BUFREN ,Buffer Read Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " RBSYE ,Response Busy Complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 16. " CRSPE ,Command/Response Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " CMDVIO ,Command Issuance Error" "No error,Error"
|
|
bitfld.long 0x00 14. " BUFVIO ,Buffer Access Error" "No error,Error"
|
|
bitfld.long 0x00 11. " WDATERR ,Write Data Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 10. " RDATERR ,Read Data Error" "No error,Error"
|
|
bitfld.long 0x00 9. " RIDXERR ,Response Index Error" "No error,Error"
|
|
bitfld.long 0x00 8. " RSPERR ,Response Error" "No error,Error"
|
|
bitfld.long 0x00 4. " CRCSTO ,CRC Status Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 3. " WDATTO ,Write Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 2. " RDATTO ,Read Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 1. " RBSYTO ,Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 0. " RSPTO ,Response Timeout" "No timeout,Timeout"
|
|
line.long 0x04 "INT_EN,Interrupt Enable Register"
|
|
bitfld.long 0x04 26. " MCMD12DRE ,CMD12DRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " MCMD12RBE ,CMD12RBE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MCMD12CRE ,CMD12CRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " MDTRANE ,DTRANE Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " MBUFRE ,BUFRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " MBUFWEN ,BUFWEN Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " MBUFREN ,BUFREN Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " MRBSYE ,RBSYE Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " MCRSPE ,CRSPE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " MCMDVIO ,CMDVIO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " MBUFVIO ,BUFVIO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " MWDATERR ,WDATERR Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " MRDATERR ,RDATERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " MRIDXERR ,RIDXERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MRSPERR ,RSPERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " MCRCSTO ,CRCSTO Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " MWDATTO ,WDATTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " MRDATTO ,RDATTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MRBSYTO ,RBSYTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MRSPTO ,RSPTO Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "HOST_STS1,Status Register 1"
|
|
bitfld.long 0x00 31. " CMDSEQ ,Command Sequence in Progress" "Initialization,Execution"
|
|
bitfld.long 0x00 30. " CMDSIG ,CMD Line Status" "Initialization,Execution"
|
|
bitfld.long 0x00 24.--29. " RSPIDX ,Response Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATSIG ,Indicate the states on the DAT lines"
|
|
hexmask.long.word 0x00 0.--15. 1. " RCVBLK ,Number of Transferred Blocks"
|
|
line.long 0x04 "HOST_STS2,Status Register 2"
|
|
bitfld.long 0x04 31. " CRCSTE ,Command Sequence in Progress" "No error,Error"
|
|
bitfld.long 0x04 30. " CRC16E ,Read Data CRC16 Error" "No error,Error"
|
|
bitfld.long 0x04 29. " AC12CRCE ,Automatic CMD12 Response CRC7 Error" "No error,Error"
|
|
bitfld.long 0x04 28. " RSPCRC7E ,Command Response CRC7 Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 27. " CRCSTEBE ,CRC Status End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 26. " RDATEBE ,Read Data End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 25. " AC12REBE ,Automatic CMD12 Response End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 24. " RSPEBE ,Command Response End Bit Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 23. " AC12IDXE ,Automatic CMD12 Response Index Error" "No error,Error"
|
|
bitfld.long 0x04 22. " RSPIDXE ,Command Response Index Error" "No error,Error"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x04 21. " BTACKPATE ,Boot Acknowledge Pattern Error" "No error,Error"
|
|
bitfld.long 0x04 20. " BTACKEBE ,Boot Acknowledge End Bit Error" "No error,Error"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CRCST ,CRC Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 14. " STRDATTO ,Read Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 13. " DATBSYTO ,Data Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 12. " CRCSTTO ,CRC Status Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x04 11. " AC12BSYTO ,Automatic CMD12 Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 10. " RSPBSYTO ,Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 9. " AC12RSPTO ,Automatic CMD12 Response Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 8. " STRSPTO ,Response Timeout" "No timeout,Timeout"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
newline
|
|
bitfld.long 0x04 7. " BTACKTO ,Boot Acknowledge Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 6. " 1STBTDATTO ,1st Boot Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 5. " BTDATTO ,Interval between Boot Data Timeout" "No timeout,Timeout"
|
|
endif
|
|
sif cpuis("SH7268")||cpuis("SH7269")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DMA_MODE,DMA Mode Setting Register"
|
|
bitfld.long 0x00 0. " DMASEL ,DMA Transfer Size Select" "2-byte or 4-byte,16-byte"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "DETECT,Card Detection/Port Control Register"
|
|
bitfld.long 0x00 14. " CDSIG ,MMC_CD pin status indication" "0,1"
|
|
bitfld.long 0x00 13. " CDRISE ,MMC_CD pin rise detection flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CDFALL ,MMC_CD pin fall detection flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " MCDRISE ,CDRISE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " MCDFALL ,CDFALL interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ADD_MODE,Special mode setting register"
|
|
bitfld.long 0x04 19. " CLKMAIN ,Internal Clock Control" "Normal,Low power consumption"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CTRL2,Clock Control Register 2"
|
|
sif (cpu()=="R8A77440")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")
|
|
bitfld.long 0x00 24.--27. " MMC_CLKU ,Set these bits to H'F before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " MMC_CLKL ,Set these bits to H'F before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " MMC_CLKU ,Set these bits to 4 before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " MMC_CLKL ,Set these bits to 4 before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
bitfld.long 0x00 31. " SWRST ,Software Reset" "No reset,Reset"
|
|
hexmask.long.word 0x00 0.--15. 1. " VERSION ,Version Information"
|
|
sif (cpu()=="R8A77440")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "ODATSEL,Data Output Phase Select Register"
|
|
bitfld.long 0x00 8. " ODTS ,Output Data Timing Select" "Rising,Falling"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFE5B000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CMD_SET,Command Setting Register"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x00 30. " BOOT ,Boot operation" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 24.--29. " CMD ,Command Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 22.--23. " RTYP ,Response Type" "No response,6-byte,17-byte,?..."
|
|
bitfld.long 0x00 21. " RBSY ,Response Busy Select" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 19. " WDAT ,Presence/Absence of Data" "Not present,Present"
|
|
bitfld.long 0x00 18. " DWEN ,Read/Write" "Read,Write"
|
|
bitfld.long 0x00 17. " CMLTE ,Single/Multi Block Transfer Select" "Single,Multi"
|
|
bitfld.long 0x00 16. " CMD12EN ,Automatic CMD12 Issuance" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RIDXC ,Response Index Check" "Response index,Check bits,No checking,?..."
|
|
bitfld.long 0x00 12.--13. " RCRC7C ,Response CRC7 Check" "CRC7,Check bits,Internal CRC7,No checking"
|
|
bitfld.long 0x00 10. " CRC16C ,CRC16 Check in Reception" "Checked,Not checked"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x00 9. " BOOTACK ,Receive Boot Acknowledge" "Not acknowledged,Acknowledged"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 8. " CRCSTE ,CRC Status Reception" "Received,Not received"
|
|
bitfld.long 0x00 7. " TBIT ,Transmission Bit Setting" "Received,Not received"
|
|
bitfld.long 0x00 6. " OPDM ,Open-Drain Output Mode" "Normal,Open-drain"
|
|
bitfld.long 0x00 3. " SBIT ,Read Data Start Bit Detection Setting" "DATW specified = 0,MMCDAT[0] = 0"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " DATW ,Data Bus Width Setting" "1,4,8,?..."
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "ARG,Argument Register"
|
|
line.long 0x04 "ARG_CMD12,Argument Register for Automatically-Issued CMD12 Register"
|
|
line.long 0x08 "CMD_CTRL,Argument Register for Automatically-Issued CMD12 Register"
|
|
bitfld.long 0x08 0. " BREAK ,Forcible Termination of Command Sequence" "0,1"
|
|
line.long 0x0c "BLOCK_SET,Transfer Block Setting Register"
|
|
hexmask.long.word 0x0c 16.--31. 1. " BLKCNT ,Number of Blocks for Transfer"
|
|
hexmask.long.word 0x0c 0.--15. 1. " BLKSIZ ,Transfer Block Size"
|
|
line.long 0x10 "CLK_CTRL,Clock Control Register"
|
|
bitfld.long 0x10 24. " CLKEN ,MMC Clock Output Control" "Not output,Output"
|
|
bitfld.long 0x10 16.--19. " CLKDIV ,MMC Clock Frequency Setting" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,?..."
|
|
bitfld.long 0x10 12.--13. " SRSPTO ,Response Timeout Setting" "64,128,256,?..."
|
|
newline
|
|
bitfld.long 0x10 8.--11. " SRBSYTO ,Response Busy Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x10 4.--7. " SRWDTO ,Write Data/Read Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
line.long 0x14 "BUF_ACC,Buffer Access Configuration Register"
|
|
bitfld.long 0x14 25. " DMAWEN ,Buffer Write DMA Transfer Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DMAREN ,Buffer Read DMA Transfer Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " BUSW ,Data register access size selection" "32-bit,16-bit"
|
|
bitfld.long 0x14 16. " ATYP ,Buffer access selection" "Not swapped bytw-wise,Swapped byte-wise"
|
|
if ((per.l(ad:0xFFE5B000)&0xc00000)==0x800000)
|
|
rgroup.long 0x20++0x0F
|
|
line.long 0x00 "RESP3,Response Register 3"
|
|
line.long 0x04 "RESP2,Response Register 2"
|
|
line.long 0x08 "RESP1,Response Register 1"
|
|
line.long 0x0C "RESP0,Response Register 0"
|
|
elif ((per.l(ad:0xFFE5B000)&0xc00000)==0x400000)
|
|
hgroup.long 0x20++0x0B
|
|
hide.long 0x00 "RESP3,Response Register 3"
|
|
hide.long 0x04 "RESP2,Response Register 2"
|
|
hide.long 0x08 "RESP1,Response Register 1"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "RESP0,Response Register 0"
|
|
else
|
|
hgroup.long 0x20++0x0F
|
|
hide.long 0x00 "RESP3,Response Register 3"
|
|
hide.long 0x04 "RESP2,Response Register 2"
|
|
hide.long 0x08 "RESP1,Response Register 1"
|
|
hide.long 0x0C "RESP0,Response Register 0"
|
|
endif
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "RESP_CMD12,Response Register for Automatically-Issued CMD12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DATA,Data Register"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BOOT,Boot Operation Setting Register"
|
|
bitfld.long 0x00 28.--31. " BTCLKDIV ,MMC Clock Frequency Setting in Boot Mode" "/2,/4,/8,/16,?..."
|
|
bitfld.long 0x00 24.--27. " SBTACKTO ,Boot Acknowledge Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x00 20.--23. " S1STBTDATTO ,1st Boot Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
bitfld.long 0x00 16.--19. " SBTDATTO ,Interval Between Boot Data Timeout Setting" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,2^23,2^24,2^25,2^26,2^27,2^28,2^29"
|
|
endif
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "INT,Interrupt Flag Register"
|
|
bitfld.long 0x00 26. " CMD12DRE ,Automatic CMD12 Issuance Buffer Read Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 25. " CMD12RBE ,Automatic CMD12 Issuance Response Busy Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " CMD12CRE ,Automatic CMD12 Response Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 23. " DTRANE ,Data Transmission Complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 22. " BUFRE ,Buffer Read Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 21. " BUFWEN ,Buffer Write Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 20. " BUFREN ,Buffer Read Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 17. " RBSYE ,Response Busy Complete" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 16. " CRSPE ,Command/Response Complete" "Not completed,Completed"
|
|
bitfld.long 0x00 15. " CMDVIO ,Command Issuance Error" "No error,Error"
|
|
bitfld.long 0x00 14. " BUFVIO ,Buffer Access Error" "No error,Error"
|
|
bitfld.long 0x00 11. " WDATERR ,Write Data Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 10. " RDATERR ,Read Data Error" "No error,Error"
|
|
bitfld.long 0x00 9. " RIDXERR ,Response Index Error" "No error,Error"
|
|
bitfld.long 0x00 8. " RSPERR ,Response Error" "No error,Error"
|
|
bitfld.long 0x00 4. " CRCSTO ,CRC Status Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x00 3. " WDATTO ,Write Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 2. " RDATTO ,Read Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 1. " RBSYTO ,Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x00 0. " RSPTO ,Response Timeout" "No timeout,Timeout"
|
|
line.long 0x04 "INT_EN,Interrupt Enable Register"
|
|
bitfld.long 0x04 26. " MCMD12DRE ,CMD12DRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " MCMD12RBE ,CMD12RBE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MCMD12CRE ,CMD12CRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " MDTRANE ,DTRANE Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " MBUFRE ,BUFRE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " MBUFWEN ,BUFWEN Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " MBUFREN ,BUFREN Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " MRBSYE ,RBSYE Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " MCRSPE ,CRSPE Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " MCMDVIO ,CMDVIO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " MBUFVIO ,BUFVIO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " MWDATERR ,WDATERR Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " MRDATERR ,RDATERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " MRIDXERR ,RIDXERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " MRSPERR ,RSPERR Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " MCRCSTO ,CRCSTO Interrupt Enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " MWDATTO ,WDATTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " MRDATTO ,RDATTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " MRBSYTO ,RBSYTO Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MRSPTO ,RSPTO Interrupt Enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x07
|
|
line.long 0x00 "HOST_STS1,Status Register 1"
|
|
bitfld.long 0x00 31. " CMDSEQ ,Command Sequence in Progress" "Initialization,Execution"
|
|
bitfld.long 0x00 30. " CMDSIG ,CMD Line Status" "Initialization,Execution"
|
|
bitfld.long 0x00 24.--29. " RSPIDX ,Response Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATSIG ,Indicate the states on the DAT lines"
|
|
hexmask.long.word 0x00 0.--15. 1. " RCVBLK ,Number of Transferred Blocks"
|
|
line.long 0x04 "HOST_STS2,Status Register 2"
|
|
bitfld.long 0x04 31. " CRCSTE ,Command Sequence in Progress" "No error,Error"
|
|
bitfld.long 0x04 30. " CRC16E ,Read Data CRC16 Error" "No error,Error"
|
|
bitfld.long 0x04 29. " AC12CRCE ,Automatic CMD12 Response CRC7 Error" "No error,Error"
|
|
bitfld.long 0x04 28. " RSPCRC7E ,Command Response CRC7 Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 27. " CRCSTEBE ,CRC Status End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 26. " RDATEBE ,Read Data End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 25. " AC12REBE ,Automatic CMD12 Response End Bit Error" "No error,Error"
|
|
bitfld.long 0x04 24. " RSPEBE ,Command Response End Bit Error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x04 23. " AC12IDXE ,Automatic CMD12 Response Index Error" "No error,Error"
|
|
bitfld.long 0x04 22. " RSPIDXE ,Command Response Index Error" "No error,Error"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
bitfld.long 0x04 21. " BTACKPATE ,Boot Acknowledge Pattern Error" "No error,Error"
|
|
bitfld.long 0x04 20. " BTACKEBE ,Boot Acknowledge End Bit Error" "No error,Error"
|
|
endif
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CRCST ,CRC Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 14. " STRDATTO ,Read Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 13. " DATBSYTO ,Data Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 12. " CRCSTTO ,CRC Status Timeout" "No timeout,Timeout"
|
|
newline
|
|
bitfld.long 0x04 11. " AC12BSYTO ,Automatic CMD12 Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 10. " RSPBSYTO ,Response Busy Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 9. " AC12RSPTO ,Automatic CMD12 Response Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 8. " STRSPTO ,Response Timeout" "No timeout,Timeout"
|
|
sif !cpuis("SH7268")&&!cpuis("SH7269")
|
|
newline
|
|
bitfld.long 0x04 7. " BTACKTO ,Boot Acknowledge Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 6. " 1STBTDATTO ,1st Boot Data Timeout" "No timeout,Timeout"
|
|
bitfld.long 0x04 5. " BTDATTO ,Interval between Boot Data Timeout" "No timeout,Timeout"
|
|
endif
|
|
sif cpuis("SH7268")||cpuis("SH7269")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DMA_MODE,DMA Mode Setting Register"
|
|
bitfld.long 0x00 0. " DMASEL ,DMA Transfer Size Select" "2-byte or 4-byte,16-byte"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "DETECT,Card Detection/Port Control Register"
|
|
bitfld.long 0x00 14. " CDSIG ,MMC_CD pin status indication" "0,1"
|
|
bitfld.long 0x00 13. " CDRISE ,MMC_CD pin rise detection flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " CDFALL ,MMC_CD pin fall detection flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " MCDRISE ,CDRISE interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " MCDFALL ,CDFALL interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "ADD_MODE,Special mode setting register"
|
|
bitfld.long 0x04 19. " CLKMAIN ,Internal Clock Control" "Normal,Low power consumption"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CTRL2,Clock Control Register 2"
|
|
sif (cpu()=="R8A77440")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")
|
|
bitfld.long 0x00 24.--27. " MMC_CLKU ,Set these bits to H'F before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " MMC_CLKL ,Set these bits to H'F before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
bitfld.long 0x00 24.--27. " MMC_CLKU ,Set these bits to 4 before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " MMC_CLKL ,Set these bits to 4 before using the MMC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "VERSION,Version Register"
|
|
bitfld.long 0x00 31. " SWRST ,Software Reset" "No reset,Reset"
|
|
hexmask.long.word 0x00 0.--15. 1. " VERSION ,Version Information"
|
|
sif (cpu()=="R8A77440")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77450")
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "ODATSEL,Data Output Phase Select Register"
|
|
bitfld.long 0x00 8. " ODTS ,Output Data Timing Select" "Rising,Falling"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SATA (Serial-ATA)"
|
|
base ad:0xFC600100
|
|
width 21.
|
|
tree "OPSH-Navi2G/ATAPI-ATA compatible task registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,Shadow Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Transmit/receive data"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SERR,Shadow Error Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SERR ,Error monitor bit"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "SFEATURES,Shadow Features Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SFEATURES ,Subcommand setup bits"
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SECCNT,Shadow Sector CNT Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SECCNT ,Sector count bits"
|
|
line.long 0x04 "LBALOW,Shadow LBA Low Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LBALOW ,LBA_low address bits"
|
|
line.long 0x08 "LBAMID,Shadow LBA Mid Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LBAMID ,LBA_mid address bits"
|
|
line.long 0x0c "LBAHIGH,Shadow LBA High Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " LBAHIGH ,LBA_high address bits"
|
|
line.long 0x10 "DEVHEAD,Shadow Device/Head Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DEVHEAD ,Device function select bits"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SSTATUS,Shadow Status Register"
|
|
bitfld.long 0x00 7. " BSY ,BSY bit" "0,1"
|
|
bitfld.long 0x00 6. " DRDY ,DRDY bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DFSE ,DF/SE bit" "0,1"
|
|
bitfld.long 0x00 4. " SSTATUS ,Definition varies with the command" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRQ ,DRQ bit" "0,1"
|
|
bitfld.long 0x00 0. " ERR ,ERR/CHK bit" "0,1"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SCOM,Shadow Command Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCOM ,Transmit command setup bits"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SALTSTS,Shadow Alternates Status Register"
|
|
bitfld.long 0x00 7. " ABSY ,BSY bit" "0,1"
|
|
bitfld.long 0x00 6. " ADRDY ,DRDY bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADFSE ,DF/SE bit" "0,1"
|
|
bitfld.long 0x00 4. " SALTSTS ,Definition varies with the command" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADRQ ,DRQ bit" "0,1"
|
|
bitfld.long 0x00 0. " AERR ,ERR/CHK bit" "0,1"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "SDEVCON,Shadow Device Control Register"
|
|
bitfld.long 0x00 7. " HOB ,HOB bit" "0,1"
|
|
bitfld.long 0x00 2. " SRST ,SRST bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NIEN ,nIEN bit" "0,1"
|
|
tree.end
|
|
tree "SH-Navi2G/ATAPI module compatible registers"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ATAPI_CONTROL,ATAPI Control Register"
|
|
bitfld.long 0x00 16. " ISM ,Interrupt Status mode" "IP compatible,CIS interrupt"
|
|
bitfld.long 0x00 11. " DTA32M ,Enables bits 31 to 29 of the descriptor DMA start address in descriptor table operation mode" "SH-Navi1-compatible mode,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RESET ,RESET controls the SATA-IP host core block" "No reset,Reset"
|
|
bitfld.long 0x00 3. " DESE ,Descriptor table operation mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " R/W ,FIFO read/write" "Write,Read"
|
|
bitfld.long 0x00 1. " STOP ,DMA transfer termination" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START ,DMA transfer initialization" "Not in transfer,In transfer"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||cpuis("R8J7795*")||cpuis("R8A7795*")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ATAPI_STATUS,ATAPI Status Register"
|
|
rbitfld.long 0x00 31. " SSBSY ,SSBSY corresponds to INTBSY of the SATAINTSTAT, the BSY bit value of the SSTATUS" "Low,High"
|
|
rbitfld.long 0x00 30. " SSDRDY ,SSDRDY corresponds to INTDRDY of the SATAINTSTAT, the DRDY bit value of the SSTATUS" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " SSDRQ ,SSDRQ corresponds to INTDRQ of the SATAINTSTAT, the DRQ bit value of the Shadow Status register SSTATUS" "Low,High"
|
|
rbitfld.long 0x00 24. " SSERR ,SSER corresponds to INTERR of the SATAINTSTAT, the ERR bit value of the SSTATUS" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SATAINT ,Indicates the status of host-intrq of the SATA-IP block" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SWERR ,Software error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DNEND ,All DMAs successfully ended in descriptor mode" "Not ended,Ended"
|
|
bitfld.long 0x00 5. " DEVTRM ,DMA mode block is terminated before the number of DMA transfer bytes defined in the DMA transfer count register is reached" "Not terminated,Terminated"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " DEVINT ,ATAPI device interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERR ,Host forcibly terminated the DMA transfer" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " NEND ,DMA successfully terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " ACT ,DMA active" "Not active,Active"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ATAPI_STATUS,ATAPI Status Register"
|
|
bitfld.long 0x00 31. " SSBSY ,SSBSY corresponds to INTBSY of the SATAINTSTAT, the BSY bit value of the SSTATUS" "Low,High"
|
|
bitfld.long 0x00 30. " SSDRDY ,SSDRDY corresponds to INTDRDY of the SATAINTSTAT, the DRDY bit value of the SSTATUS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SSDRQ ,SSDRQ corresponds to INTDRQ of the SATAINTSTAT, the DRQ bit value of the Shadow Status register SSTATUS" "Low,High"
|
|
bitfld.long 0x00 24. " SSERR ,SSER corresponds to INTERR of the SATAINTSTAT, the ERR bit value of the SSTATUS" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SATAINT ,Indicates the status of host-intrq of the SATA-IP block" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SWERR ,Software error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DNEND ,All DMAs successfully ended in descriptor mode" "Not ended,Ended"
|
|
bitfld.long 0x00 5. " DEVTRM ,DMA mode block is terminated before the number of DMA transfer bytes defined in the DMA transfer count register is reached" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DEVINT ,ATAPI device interrupt status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERR ,Host forcibly terminated the DMA transfer" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " NEND ,DMA successfully terminated" "Not terminated,Terminated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ACT ,DMA active" "Not active,Active"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ATAPI_INT_ENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " ISATAINT ,SATAINT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ISWERR ,SWERR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDNEND ,DNEND interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IDEVTRM ,DEVTRM interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDEVINT ,DEVINT interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IERR ,ERR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INEND ,NEND interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IACT ,ACT interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0xFC600100+0x80))&0x800)==0x000)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ATAPI_DTB_ADR,Descriptor Table Base Address Register"
|
|
bitfld.long 0x00 31. " DTEND ,DTEND controls the termination of a descriptor DMA operation" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " DDSTA ,DMA start address in descriptor operation"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ATAPI_DTB_ADR,Descriptor Table Base Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " DDSTA ,DMA start address in descriptor operation"
|
|
bitfld.long 0x00 0. " DTEND ,DTEND controls the termination of a descriptor DMA operation" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "ATAPI_DMA_START_ADR,DMA Start Address Register"
|
|
hexmask.long 0x00 2.--31. 0x04 " DSTA ,DMA start address"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ATAPI_DMA_TRANS_CNT,DMA Transfer Count Register"
|
|
hexmask.long 0x00 1.--28. 1. " DTRC ,DMA transfer count"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "ATAPI_CONTROL2,ATAPI Control 2 Register"
|
|
bitfld.long 0x00 2. " LWORDSWAP ,Swapping of upper 32-bit data and lower 32-bit data on 2-longword basis" "Not executed,Executed"
|
|
bitfld.long 0x00 1. " WORDSWAP ,Swapping of upper 16-bit data and lower 16-bit data on longword basis" "Not executed,Executed"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "ATAPI_SIG_ST,ATAPI Signal Status Register"
|
|
bitfld.long 0x00 1. " DPIORDY ,state of the IF signal for PIO transfer" "Low,High"
|
|
bitfld.long 0x00 0. " DMARQ ,ATAPIDMARQ signal status" "Low,High"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "ATAPI_BYTE_SWAP,Byteswap Register"
|
|
bitfld.long 0x00 0. " BYTESWAP ,Swapping of upper 8 bit data and lower 8 bit data in SATA interface" "Not executed,Executed"
|
|
tree.end
|
|
sif (cpu()!="RCARH2"&&cpu()!="RCARM2"&&(!cpuis("R8J7795*"))&&(!cpuis("R8A7795*"))&&(cpu()!="R8A77420")&&(cpu()!="R8A77430")&&(cpu()!="R8A77440"))
|
|
tree "Access control registers for physical layer control registers"
|
|
group.long 0x100++0x0f
|
|
line.long 0x00 "SATAPHYADRR,Physical Layer Control Address Command Register"
|
|
bitfld.long 0x00 10. " PHYRATEMODE ,Specifies the rate (mode) of control for the physical layer" "First generation,Second generation"
|
|
bitfld.long 0x00 8.--9. " PHTCMD ,Specifies a command to control the physical layer" "Idle,Write,Read,?..."
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PHYADD ,Specifies an address in the physical layer control register space"
|
|
line.long 0x04 "SATAPHYWDATA,Physical Layer Control Write Data Register"
|
|
line.long 0x08 "SATAPHYACCEN,Physical Layer Control Enable Register"
|
|
bitfld.long 0x08 0. " PHYLANE ,Target lane to be accessed" "Not accessed,Accessed"
|
|
line.long 0x0c "SATAPHYRESET,Physical Layer Control Reset Register"
|
|
bitfld.long 0x0c 1. " PHYRST ,Asynchronously resets the physical layer control registers" "No reset,Reset"
|
|
bitfld.long 0x0c 0. " PHYSRES ,Synchronously resets the physical layer control registers" "No reset,Reset"
|
|
rgroup.long 0x110++0x07
|
|
line.long 0x00 "SATAPHYRDATA,Physical Layer Control Read Data Register"
|
|
line.long 0x04 "SATAPHYACK,Physical Layer Control Acknowledge Register"
|
|
bitfld.long 0x04 0. " PHYACK ,Completion of control ACK signal" "Not acknowledged,Acknowledged"
|
|
tree.end
|
|
endif
|
|
tree "Serial ATA HOST control registers"
|
|
group.long 0xF2C++0x03
|
|
line.long 0x00 "BISTCONF,BIST Config Register"
|
|
bitfld.long 0x00 0. " LOOPB ,Loopback mode" "No loopback,Loopback"
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "SDATA,Shadow Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,Transmit/receive data"
|
|
rgroup.long 0x1004++0x03
|
|
line.long 0x00 "SSSERR,Shadow Error Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SERR ,Error monitor bit"
|
|
wgroup.long 0x1004++0x03
|
|
line.long 0x00 "SSFEATURES,Shadow Features Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SFEATURES ,Subcommand setup bits"
|
|
group.long 0x1008++0x13
|
|
line.long 0x00 "SSECCNT,Shadow Sector CNT Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SECCNT ,Sector count bits"
|
|
line.long 0x04 "SSLBALOW,Shadow LBA Low Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LBALOW ,LBA_low address bits"
|
|
line.long 0x08 "SSLBAMID,Shadow LBA Mid Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LBAMID ,LBA_mid address bits"
|
|
line.long 0x0c "SSLBAHIGH,Shadow LBA High Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " LBAHIGH ,LBA_high address bits"
|
|
line.long 0x10 "SSDEVHEAD,Shadow Device/Head Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DEVHEAD ,Device function select bits"
|
|
rgroup.long 0x101C++0x03
|
|
line.long 0x00 "SSSTATUS,Shadow Status Register"
|
|
bitfld.long 0x00 7. " BSY ,BSY bit" "0,1"
|
|
bitfld.long 0x00 6. " DRDY ,DRDY bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DFSE ,DF/SE bit" "0,1"
|
|
bitfld.long 0x00 4. " SSTATUS ,Definition varies with the command" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DRQ ,DRQ bit" "0,1"
|
|
bitfld.long 0x00 0. " ERR ,ERR/CHK bit" "0,1"
|
|
wgroup.long 0x101C++0x03
|
|
line.long 0x00 "SSCOM,Shadow Command Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCOM ,Transmit command setup bits"
|
|
rgroup.long 0x1104++0x03
|
|
line.long 0x00 "SSALTSTS,Shadow Alternates Status Register"
|
|
bitfld.long 0x00 7. " ABSY ,BSY bit" "0,1"
|
|
bitfld.long 0x00 6. " ADRDY ,DRDY bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADFSE ,DF/SE bit" "0,1"
|
|
bitfld.long 0x00 4. " SALTSTS ,Definition varies with the command" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADRQ ,DRQ bit" "0,1"
|
|
bitfld.long 0x00 0. " AERR ,ERR/CHK bit" "0,1"
|
|
wgroup.long 0x1104++0x03
|
|
line.long 0x00 "SSDEVCON,Shadow Device Control Register"
|
|
bitfld.long 0x00 7. " HOB ,HOB bit" "0,1"
|
|
bitfld.long 0x00 2. " SRST ,SRST bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NIEN ,nIEN bit" "0,1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A77420")||(cpu()=="R8A77430")
|
|
group.long 0x1220++0x03
|
|
line.long 0x00 "SATAER,SATA Extend Register"
|
|
elif (cpu()=="R8A77440")
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "SATAER,SATA Extend Register"
|
|
endif
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
rgroup.long 0x1120++0x07
|
|
line.long 0x00 "SATAEICCR,SATA Extend ICC Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ICC ,Isochronous Command Completion"
|
|
line.long 0x04 "SATAEAUXR,SATA Extend Auxiliary Register"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "SATAEDEVSLPR,SATA Extend DEVSLP Register"
|
|
bitfld.long 0x00 1. " DEVSLP_EN ,Sleep mode of SATA host IP enable" "Disabled,Enable"
|
|
endif
|
|
rgroup.long 0x1300++0x03
|
|
line.long 0x00 "SCRSSTS,SCR SStatus Register"
|
|
bitfld.long 0x00 8.--11. " IPM ,Interface power manager state monitor bits" "No device/Device not ready,Active,Partial,,,,Slumber,?..."
|
|
bitfld.long 0x00 4.--7. " SPD ,Communication speed monitor bits" "No device/Device not ready,First generation (1.5 Gbps),Second generation (3.0 Gbps),?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DET ,Device communication state monitor bits" "No device/Device not ready,Device not ready,,Device ready,Offline/Loopback,?..."
|
|
group.long 0x1304++0x0B
|
|
line.long 0x00 "SCRSERR,SCR SError Register"
|
|
eventfld.long 0x00 27. " DIAGA ,Sense COMWAKE before detecting a device" "Not occurred,Occurred"
|
|
eventfld.long 0x00 26. " DIAGX ,Sense the change in device connection state" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 25. " DIAGF ,FIS type error bit" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " DIAGT ,Abnormal timing transfer result reception bit" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 23. " DIAGS ,Abnormal state transition bit" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " DIAGH ,Handshake error bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 21. " DIAGC ,CRC error bit" "No error,Error"
|
|
eventfld.long 0x00 20. " DIAGD ,Disparity error bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 19. " DIAGB ,10b/8b decode error bit" "No error,Error"
|
|
eventfld.long 0x00 18. " DIAGW ,COMWAKE detect bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 17. " DIAGI ,Error state bit (Phy internal error)" "No error,Error"
|
|
eventfld.long 0x00 16. " DIAGN ,Transfer Ready state change bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ERRE ,Internal FIFO flow error bit" "No error,Error"
|
|
eventfld.long 0x00 10. " ERRP ,Protocol error bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ERRC ,FIS transmission PhyRdy signal negated bit" "No error,Error"
|
|
eventfld.long 0x00 8. " ERRT ,Data FIS transfer error bit" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERRM ,Communication error recovery monitor bit" "No error,Error"
|
|
eventfld.long 0x00 0. " ERRI ,Retransmission result bit" "No error,Error"
|
|
line.long 0x04 "SCRSCON,SCR SControl Register"
|
|
bitfld.long 0x04 12.--15. " CSPM ,Power Management Mode transition request" "No request,Partial mode,Slumber mode,,Active mode,?..."
|
|
bitfld.long 0x04 8.--11. " CIPM ,Interface Power Management Mode enable" "No limitation,Partial mode disabled,Slumber mode disabled,Partial/Slumber modes disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " CSPD ,Communication speed" "No limitation (3.0 Gbps),First generation (1.5 Gbps),Second generation (3.0 Gbps),?..."
|
|
bitfld.long 0x04 0.--3. " CDET ,RESET/Offline mode bits" "No request,Reset,,,Offline mode,?..."
|
|
line.long 0x08 "SCRSACT,SCR SActive Register"
|
|
bitfld.long 0x08 31. " SACT[31] ,TAG value of B'11111" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " SACT[30] ,TAG value of B'11110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " SACT[29] ,TAG value of B'11101" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " SACT[28] ,TAG value of B'11100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " SACT[27] ,TAG value of B'11011" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " SACT[26] ,TAG value of B'11010" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " SACT[25] ,TAG value of B'11001" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " SACT[24] ,TAG value of B'11000" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " SACT[23] ,TAG value of B'10111" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SACT[22] ,TAG value of B'10110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " SACT[21] ,TAG value of B'10101" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " SACT[20] ,TAG value of B'10100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " SACT[19] ,TAG value of B'10011" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " SACT[18] ,TAG value of B'10010" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " SACT[17] ,TAG value of B'10001" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " SACT[16] ,TAG value of B'10000" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " SACT[15] ,TAG value of B'01111" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " SACT[14] ,TAG value of B'01110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " SACT[13] ,TAG value of B'01101" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SACT[12] ,TAG value of B'01100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SACT[11] ,TAG value of B'01011" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " SACT[10] ,TAG value of B'01010" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " SACT[9] ,TAG value of B'01001" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " SACT[8] ,TAG value of B'01000" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SACT[7] ,TAG value of B'00111" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " SACT[6] ,TAG value of B'00110" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " SACT[5] ,TAG value of B'00101" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " SACT[4] ,TAG value of B'00100" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SACT[3] ,TAG value of B'00011" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " SACT[2] ,TAG value of B'00010" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " SACT[1] ,TAG value of B'00001" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " SACT[0] ,TAG value of B'00000" "Disabled,Enabled"
|
|
hgroup.long 0x1408++0x03
|
|
hide.long 0x00 "SATAINTSTAT,SATA INT Status Register"
|
|
in
|
|
group.long 0x140C++0x03
|
|
line.long 0x00 "SATAINTMASK,SATA INT Mask Register"
|
|
sif (cpu()=="RCARH2")||(cpu()=="RCARM2")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
bitfld.long 0x00 11. " SDBFMSK ,Masks the 'Set Device Bits FIS received' interrupt" "Not masked,Masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " SLUMRMSK ,Mask for the 'request for transition to Slumber mode' interrupt (for DIPM)" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARTITMSK ,Mask for the 'request for transition to Partial mode' interrupt (for DIPM)" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VENDMSK ,Masks the 'Vendor Specific FIS received' interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BISTMSK ,Masks the 'BIST Activate FIS received' interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SLUMMSK ,Masks the 'device reject transition to Slumber mode' interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " PARTIMSK ,Masks the 'device reject transition to Partial mode' interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DMASTMSK ,Masks the 'DMA Setup FIS received' interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " SERRMSK ,Masks the 'SCR SError register (SCRSERR) update' interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERRMSK ,Masks the 'SCR SError register (SCRSERR) ERRE, ERRP, ERRC, ERRT, ERRM, and ERRI bits update' interrupt" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " ERRCRTMSK ,Masks the 'SCR SError register (SCRSERR) ERRE, ERRP, and ERRT bits update' interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ATAMSK ,Masks the 'ATA source (equivalent to P-ATA's INTRQ)' interrupt" "Not masked,Masked"
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")||(cpu()=="R8A77420")||(cpu()=="R8A77430")||(cpu()=="R8A77440")
|
|
group.long 0x1468++0x03
|
|
line.long 0x00 "PHYSTOP,PHY STOP Register"
|
|
bitfld.long 0x00 0. " PHYSTOP ,PHY STOP mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x1520++0x1B
|
|
line.long 0x00 "DMADW0,Rx DMA Setup FIS Dword0 Register"
|
|
bitfld.long 0x00 15. " AUTOACT ,Auto-Activation bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DMAINT ,Interrupt bit" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMADIR ,Data transfer direction bit" "Host -> device,Device -> host"
|
|
bitfld.long 0x00 8.--11. " PMPORT ,Source device ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " FISTYPE ,FIS type bit"
|
|
line.long 0x04 "DMADW1,Rx DMA Setup FIS Dword1 Register"
|
|
hexmask.long 0x04 5.--31. 1. " DMABLOW ,DMA Buffer Identifier Low field value in the DMA Setup"
|
|
bitfld.long 0x04 0.--4. " DMATAG ,TAG field for NCQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x8 "DMADW2,Rx DMA Setup FIS Dword2 Register"
|
|
line.long 0xC "DMADW3,Rx DMA Setup FIS Dword3 Register"
|
|
line.long 0x10 "DMADW4,Rx DMA Setup FIS Dword4 Register"
|
|
line.long 0x14 "DMADW5,Rx DMA Setup FIS Dword5 Register"
|
|
line.long 0x18 "DMADW6,Rx DMA Setup FIS Dword6 Register"
|
|
tree.end
|
|
sif cpuis("R8J7795*")||cpuis("R8A7795*")
|
|
textline " "
|
|
group.long 0xE65E3F24++0x03
|
|
line.long 0x00 "REFSEL,Reference Clock Source Select Register"
|
|
bitfld.long 0x00 0. " REFSEL ,Reference Clock Source Select" "On chip Clock,External Pin"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB (Universal Serial Bus)"
|
|
base ad:0xFFE70800
|
|
width 11.
|
|
if (((per.l(ad:0xFFE70800))&0x1)==0x0)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USBPCTRL0,Port Control 0"
|
|
bitfld.long 0x00 10. " OVC2 ,Switches the OVC input pin for port 2" "OVC2 pin,USB_OVC2 pin"
|
|
bitfld.long 0x00 9. " OVC1/VBUS1 ,Switches the OVC input pin for port 1" "OVC1/VBUS1,USB_OVC1 pin"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OVC0 ,Switches the OVC input pin for port 0" "OVC0,USB_OVC0 pin"
|
|
bitfld.long 0x00 6. " OVC2_ACT ,OVC2 polarity switching [USB_OVC2]" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENC ,sSlects the level for output on the PENC1 pin when function operation is selected" "Low output,High output"
|
|
bitfld.long 0x00 3. " OVC0_ACT ,OVC0 polarity switching [USB_OVC0]" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVC1_ACT ,OVC1 polarity switching [USB_OVC1]" "Active low,Active high"
|
|
bitfld.long 0x00 0. " PORT1 ,Selects host or function for port 1" "Host,Function"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "USBPCTRL0,Port Control 0"
|
|
bitfld.long 0x00 10. " OVC2 ,Switches the OVC input pin for port 2" "OVC2 pin,USB_OVC2 pin"
|
|
bitfld.long 0x00 9. " OVC1/VBUS1 ,Switches the OVC input pin for port 1" "OVC1/VBUS1,USB_OVC1 pin"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OVC0 ,Switches the OVC input pin for port 0" "OVC0,USB_OVC0 pin"
|
|
bitfld.long 0x00 6. " OVC2_ACT ,OVC2 polarity switching [USB_OVC2]" "Connected/Disconnected,Disconnected/Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENC ,sSlects the level for output on the PENC1 pin when function operation is selected" "Low output,High output"
|
|
bitfld.long 0x00 3. " OVC0_ACT ,OVC0 polarity switching [USB_OVC0]" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVC1_ACT ,VBUS1 polarity switching" "Connected/Disconnected,Disconnected/Connected"
|
|
bitfld.long 0x00 0. " PORT1 ,Selects host or function for port 1" "Host,Function"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USBPCTRL1,Port Control 1"
|
|
bitfld.long 0x00 31. " RST ,Resets the USB module" "No reset,Reset"
|
|
bitfld.long 0x00 2. " PHY_RST ,Resets the USB-PHY" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PLL_ENB ,Enables the PLL in the USB-PHY" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PHY_ENB ,Enables the USB-PHY" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "USBST,USB Status"
|
|
bitfld.long 0x00 31. " ACT ,USB module state" "Initializing,Active"
|
|
bitfld.long 0x00 30. " PLL ,USB PLL state" "Not stable,Stable"
|
|
group.long 0x0c++0x03
|
|
line.long 0x00 "USBEH0,EHCI Control 0"
|
|
group.long 0x1c++0x03
|
|
line.long 0x00 "USBOH0,OHCI Control 0"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "USBCTL0,USB Control 0"
|
|
bitfld.long 0x00 7. " CLKSEL ,USB clock mode select" "Crystal oscillator,External clock"
|
|
base ad:0xFFE70000
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "EIIBC1,EHCI IP Internal Control Buffer 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BUF_SET1 ,Internal buffer seting 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BUF_SET2 ,Internal buffer seting 2"
|
|
line.long 0x04 "EIIBC2,EHCI IP Internal Control Buffer 2"
|
|
bitfld.long 0x04 0. " BUF_EN ,EHCI IP internal buffer enable" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "USB 2.0 (Universal Serial Bus 2.0)"
|
|
base ad:0xFFE70000
|
|
width 12.
|
|
rgroup.long 0x00++0x03 "Host Controller Capability Registers"
|
|
line.long 0x00 "HCIVERSION,Version Of The EHCI Standard Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,Host Controller Interface Version Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability Register Length"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "HCSPARAMS,Host Controller Structure Parameters Register"
|
|
bitfld.long 0x00 20.--23. " DPN ,Debug Port Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16. " P_INDI ,Port Indicator" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PRR ,Port Routing Rule" "N_PCC,HCSP-PORTROUTE"
|
|
bitfld.long 0x00 4. " PPC ,Port Power Control" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " N_PORTS ,N_PORTS" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "HCCPARAMS,Parameters Relating Host Controller Capabilities Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x04 4.--7. " IST ,Isochronous Scheduling Threshold" "Not cached,,2 microframes,,,,,,Entire frame,?..."
|
|
bitfld.long 0x04 2. " ASPC ,Asynchronous Schedule Park Capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 1. " PFLF ,Programmable Frame List Flag" "Fixed 1024,Changed 512-256"
|
|
bitfld.long 0x04 0. " 64AC ,64-Bit Addressing Capability" "32-bit,64-bit"
|
|
width 16.
|
|
sif (cpu()=="RCARH2")
|
|
if (((per.long(ad:0xFFE70000+0x04))&0x80)==0x80)
|
|
rgroup.long 0x0c++0x03
|
|
line.long 0x00 "HCSP-PORTROUTE,Companion Host Controller Assign Register"
|
|
else
|
|
hgroup.long 0x0c++0x03
|
|
hide.long 0x00 "HCSP-PORTROUTE,Companion Host Controller Assign"
|
|
endif
|
|
else
|
|
if (((per.long(ad:0xFFE70000+0x04))&0x80)==0x80)
|
|
rgroup.long 0x0c++0x07
|
|
line.quad 0x00 "HCSP-PORTROUTE,Companion Host Controller Assign Register"
|
|
hexmask.quad 0x00 0.--59. 1. " HCSP-PORTROUTE ,Correspondence between N_PORTS ports and companion host controllers"
|
|
else
|
|
hgroup.long 0x0c++0x07
|
|
hide.quad 0x00 "HCSP-PORTROUTE,Companion Host Controller Assign"
|
|
endif
|
|
endif
|
|
width 12.
|
|
sif (cpu()=="RCARH2")
|
|
base ad:0xFFE70000
|
|
endif
|
|
group.long 0x10++0x0F "Host Controller Operational Registers"
|
|
line.long 0x00 "USBCMD,USBCMD Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " ASPMC ,RO Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")
|
|
rbitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "No reset,Reset"
|
|
else
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "No reset,Reset"
|
|
endif
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "1024,512,256,?..."
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run"
|
|
line.long 0x04 "USBSTS,Status Information Register"
|
|
sif (cpu()=="RCARH2")
|
|
hexmask.long.word 0x04 16.--31. 1. "ITC,Interrupt Threshold Control"
|
|
rbitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
rbitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
rbitfld.long 0x04 13. " R ,Reclamation" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x04 12. " HCH ,HC Halted" "Run/Stop==1,Run/Stop==0"
|
|
else
|
|
bitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " R ,Reclamation" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HCH ,HC Halted" "Run/Stop==1,Run/Stop==0"
|
|
endif
|
|
bitfld.long 0x04 5. " IAA ,Interrupt Async Advance" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " HSE ,Host System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLR ,Frame List Rollover" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PCD ,Port Change Detect" "Not detected,Detected"
|
|
bitfld.long 0x04 1. " UEI ,USB Error interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " UI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "USBINTR,On/off Of Hardware Interrupts Register"
|
|
bitfld.long 0x08 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PCDE ,Port Change Detect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " UEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " UIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0c "FRINDEX, Current Frame Number Register"
|
|
hexmask.long.word 0x0C 0.--13. 1. " FI ,Frame Index"
|
|
width 18.
|
|
sif (cpu()=="RCARH2")
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "CTRLDSSEGMENT,CTRLDSSEGMENT Register"
|
|
else
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "CTRLDSSEGMENT,CTRLDSSEGMENT Register"
|
|
endif
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "PERIODICLISTBASE,Periodic Framelist Base Address Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 0x10 " BA ,Base Address"
|
|
line.long 0x04 "ASYNCLISTADDR,Queue Heads Pointer"
|
|
hexmask.long 0x04 5.--31. 0x20 " LPL ,Link Pointer Low"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CONFIGFLAG,Ownership Specification Register"
|
|
bitfld.long 0x00 0. " CF ,Config Flag" "Each port to cHC,All ports to eHC"
|
|
if ((((per.long(ad:0xFFE70000+0x04))&0x80000)==0x80000)&&(((per.long(ad:0xFFE70000+0x54))&0x5)==0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K-state,J-state,?..."
|
|
else
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,SE1"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((per.long(ad:0xFFE70000+0x04))&0x80000)==0x80000)&&(((per.long(ad:0xFFE70000+0x54))&0x5)!=0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "Off,Amber,Greed,?..."
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
elif ((((per.long(ad:0xFFE70000+0x04))&0x80000)==0x00)&&(((per.long(ad:0xFFE70000+0x54))&0x5)==0x1))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K-state,J-state,?..."
|
|
else
|
|
bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,J-state,K-state,SE1"
|
|
endif
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PORTSC(1-N_PORT),Ports And Monitors Port Status Control"
|
|
bitfld.long 0x00 22. " WOE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "Test mode invalid,Test J_state,Test K_state,Test SE0_NAK,Test Packet,Test Force_Enable,?..."
|
|
textline " "
|
|
bitfld.long 0x00 13. " PO ,Port Owner" "Companion,EHCI"
|
|
bitfld.long 0x00 12. " PP ,Port Power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " S ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FPR ,Force Port Resume" "Not detected,Detected"
|
|
bitfld.long 0x00 5. " OC ,Over-Current Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA ,Over-Current Active" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 3. " PEDC ,Port Enable/Disable Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCS ,Current Connect Status" "Device detected,No device detected"
|
|
endif
|
|
sif (cpu()=="RCARH2")
|
|
base ad:0xFFE70000
|
|
width 17.
|
|
tree "PCI Configuration Space for AHB-PCI Bridge"
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "VID_DID,Device/Vendor ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DID ,Device ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " VID ,Vendor ID"
|
|
line.long 0x04 "CMND_STS,Command Status Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Status"
|
|
hexmask.long.word 0x04 0.--15. 1. " COMMAND ,Command"
|
|
line.long 0x08 "REVID_CC,Revision ID/Class Code Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. " CC ,Class Code"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RID ,Revision ID"
|
|
line.long 0x0C "CLS_LT_HT_BIST,Cache Line Size/Latency Timer/Header Type/BIST Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BIST ,BIST"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HT ,Header Type"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " LT ,Latency Timer"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CLS ,Cache Line Size"
|
|
line.long 0x10 "BASEAD,AHB-PCI Bridge Registers Base Address Register"
|
|
line.long 0x14 "WIN1_BASEAD,PCI-AHB Window1 Base Address Register"
|
|
line.long 0x18 "WIN2_BASEAD,PCI-AHB Window2 Base Address Register"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "SSVID_SSID,Subsystem Vendor ID/Subsystem ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SSID ,Subsystem ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " SSVID ,Subsystem Vendor ID"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "INTR_LINE_PIN,Interrupt Line/Pin Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Max_Lat ,Max_Lat"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Min_Gnt ,Min_Gnt"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Interrupt Pin"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Interrupt Line"
|
|
tree.end
|
|
tree "PCI Configuration Space for OHCI Host Logic"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "VID_DID,Device/Vendor ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DID ,Device ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " VID ,Vendor ID"
|
|
line.long 0x04 "CMND_STS,Command Status Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Status"
|
|
hexmask.long.word 0x04 0.--15. 1. " COMMAND ,Command"
|
|
line.long 0x08 "REVID_CC,Revision ID/Class Code Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. " CC ,Class Code"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RID ,Revision ID"
|
|
line.long 0x0C "CLS_LT_HT_BIST,Cache Line Size/Latency Timer/Header Type/BIST Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BIST ,BIST"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HT ,Header Type"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " LT ,Latency Timer"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CLS ,Cache Line Size"
|
|
line.long 0x10 "BASEAD,OHCI Base Address Register"
|
|
group.long 0x2C++0xB
|
|
line.long 0x00 "SSVID_SSID,Subsystem Vendor ID/Subsystem ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SSID ,Subsystem ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " SSVID ,Subsystem Vendor ID"
|
|
line.long 0x04 "EROM_BASEAD,Expansion ROM Base Address Register"
|
|
line.long 0x08 "CAPPTR,CAPPTR Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CAPPTR ,CAPPTR field"
|
|
group.long 0x3C++0xB
|
|
line.long 0x00 "INTR_LINE_PIN,Interrupt Line/Pin Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Max_Lat ,Max_Lat"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Min_Gnt ,Min_Gnt"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Interrupt Pin"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Interrupt Line"
|
|
line.long 0x04 "CAPID_NIP_PMCAP,CAPID/Next item pointer/PMC Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " PMC ,PMC"
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEXT_ITEM_PTR ,Next item pointer"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CAP_ID ,Capability ID"
|
|
line.long 0x08 "PMC_STS_PMCSR,Data/PMCSR_BSE/PMCSR Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA ,Data field"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PMCSR_BSE ,PMCSR_BSE field"
|
|
hexmask.long.word 0x08 0.--15. 1. " PMCSR ,PMCSR field"
|
|
group.long 0xE0++0x7
|
|
line.long 0x00 "EXT1,EXT1 Register"
|
|
line.long 0x04 "EXT2,EXT2 Register"
|
|
group.long 0xF0++0x7
|
|
line.long 0x00 "TRANS_CHARA,Transceiver characteristic Register"
|
|
line.long 0x04 "UTMICTRL,UTMI+ Operation Mode Control Register"
|
|
tree.end
|
|
tree "PCI Configuration Space for EHCI Host Logic"
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "VID_DID,Device/Vendor ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DID ,Device ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " VID ,Vendor ID"
|
|
line.long 0x04 "CMND_STS,Command Status Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Status"
|
|
hexmask.long.word 0x04 0.--15. 1. " COMMAND ,Command"
|
|
line.long 0x08 "REVID_CC,Revision ID/Class Code Register"
|
|
hexmask.long.tbyte 0x08 8.--31. 1. " CC ,Class Code"
|
|
hexmask.long.byte 0x08 0.--7. 1. " RID ,Revision ID"
|
|
line.long 0x0C "CLS_LT_HT_BIST,Cache Line Size/Latency Timer/Header Type/BIST Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " BIST ,BIST"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " HT ,Header Type"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " LT ,Latency Timer"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " CLS ,Cache Line Size"
|
|
line.long 0x10 "BASEAD,OHCI Base Address Register"
|
|
group.long 0x12C++0xB
|
|
line.long 0x00 "SSVID_SSID,Subsystem Vendor ID/Subsystem ID Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " SSID ,Subsystem ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " SSVID ,Subsystem Vendor ID"
|
|
line.long 0x04 "EROM_BASEAD,Expansion ROM Base Address Register"
|
|
line.long 0x08 "CAPPTR,CAPPTR Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CAPPTR ,CAPPTR field"
|
|
group.long 0x13C++0xB
|
|
line.long 0x00 "INTR_LINE_PIN,Interrupt Line/Pin Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " Max_Lat ,Max_Lat"
|
|
hexmask.long.byte 0x00 16.--23. 1. " Min_Gnt ,Min_Gnt"
|
|
hexmask.long.byte 0x00 8.--15. 1. " INTR_PIN ,Interrupt Pin"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " INTR_LINE ,Interrupt Line"
|
|
line.long 0x04 "CAPID_NIP_PMCAP,CAPID/Next item pointer/PMC Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " PMC ,PMC"
|
|
hexmask.long.byte 0x04 8.--15. 1. " NEXT_ITEM_PTR ,Next item pointer"
|
|
hexmask.long.byte 0x04 0.--7. 1. " CAP_ID ,Capability ID"
|
|
line.long 0x08 "PMC_STS_PMCSR,Data/PMCSR_BSE/PMCSR Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA ,Data field"
|
|
hexmask.long.byte 0x08 16.--23. 1. " PMCSR_BSE ,PMCSR_BSE field"
|
|
hexmask.long.word 0x08 0.--15. 1. " PMCSR ,PMCSR field"
|
|
group.long 0x1E0++0x7
|
|
line.long 0x00 "EXT1,EXT1 Register"
|
|
line.long 0x04 "EXT2,EXT2 Register"
|
|
group.long 0x1F0++0x7
|
|
line.long 0x00 "TRANS_CHARA,Transceiver characteristic Register"
|
|
line.long 0x04 "UTMICTRL,UTMI+ Operation Mode Control Register"
|
|
tree.end
|
|
group.long 0x800++0x7
|
|
line.long 0x00 "PCIAHB_WIN1_CTR,PCIAHB_WIN1_CTR Register"
|
|
line.long 0x04 "PCIAHB_WIN2_CTR,PCIAHB_WIN2_CTR Register"
|
|
group.long 0x810++0x7
|
|
line.long 0x00 "AHBPCI_WIN1_CTR,AHBPCI_WIN1_CTR Register"
|
|
line.long 0x04 "AHBPCI_WIN2_CTR,AHBPCI_WIN2_CTR Register"
|
|
group.long 0x820++0x7
|
|
line.long 0x00 "PCI_INT_ENABLE,PCI Interrupt Enable Register"
|
|
line.long 0x04 "PCI_INT_STATUS,PCI Interrupt Status Register"
|
|
group.long 0x830++0x7
|
|
line.long 0x00 "AHB_BUS_CTR,AHB_BUS_CTR Register"
|
|
line.long 0x04 "USBCTR,USBCTR Register"
|
|
group.long 0x840++0x3
|
|
line.long 0x00 "PCI_ARBITER_CTR,PCI_ARBITER_CTR Register"
|
|
group.long 0x848++0x3
|
|
line.long 0x00 "PCI_UNIT_REV,PCI_UNIT_REV Register"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "USB 1.1 (Universal Serial Bus 1.1)"
|
|
base ad:0xFFE70400
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "HCREVISION,Hc Revision Register"
|
|
hexmask.long.byte 0x00 00.--07. 1. " REVISION ,Revision"
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "HCCONTROL,Hc Control Register"
|
|
bitfld.long 0x00 10. " RWCE ,Remote Wakeup Connected Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 09. " RWC ,Remote Wakeup Connected" "Not supported,Supported"
|
|
bitfld.long 0x00 08. " IR ,Interrupt Routing" "Normal,SMI"
|
|
bitfld.long 0x00 06.--07. " HCFS ,Host Controller Functional State" "Reset,Resume,Operation,Suspend"
|
|
textline " "
|
|
bitfld.long 0x00 05. " BLE ,Bulk List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 04. " CLE ,Control List Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 03. " IE ,Isochronous Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 02. " PLE ,Periodic List Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 00.--01. " CBSR[1:0] ,Control Bulk Service Ratio" "1:1,2:1,3:1,4:1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,Hc Command Status Register"
|
|
hexmask.long.byte 0x04 16.--17. 1. " SOC[1:0] ,Scheduling Overrun Count"
|
|
bitfld.long 0x04 03. " OCR ,Ownership Change Request" "Not requested,Requested"
|
|
bitfld.long 0x04 02. " BLF ,Bulk List Filled" "Not processed,Processed"
|
|
bitfld.long 0x04 01. " CLF ,Control List Filled" "Not processed,Processed"
|
|
textline " "
|
|
bitfld.long 0x04 00. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
line.long 0x08 "HCINTERRUPTSTATUS,Hc Interrupt Status Register"
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x08 30. " OC ,Ownership Change" "Not changed,Changed"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 06. " RHSC ,Root Hub Status Change" "Not changed,Changed"
|
|
bitfld.long 0x08 05. " FNO ,Frame Number Overflow" "Not updated,Updated"
|
|
bitfld.long 0x08 04. " UE ,Unrecoverable Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 03. " RD ,Resume Detected" "Not detected,Detected"
|
|
bitfld.long 0x08 02. " SF ,Start Of Frame" "Not initiated,Initiated"
|
|
bitfld.long 0x08 01. " WDH ,Writeback Done Head" "Not updated,Updated"
|
|
bitfld.long 0x08 00. " SO ,Scheduling Overrun" "Not overrun,Overrun"
|
|
line.long 0x0C "HCINTERRUPTENABLE,Hc Interrupt Enable Register"
|
|
bitfld.long 0x0C 31. " MIE ,Master Interrupt Enable" "Not affected,Enabled"
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x0C 30. " OC ,Ownership Change Enable" "Not affected,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x0C 06. " RHSC ,Root Hub Status Change Enable" "Not affected,Enabled"
|
|
bitfld.long 0x0C 05. " FNO ,Frame Number Overflow Enable" "Not affected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 04. " UE ,Unrecoverable Error Enable" "Not affected,Enabled"
|
|
bitfld.long 0x0C 03. " RD ,Resume Detected Enable" "Not affected,Enabled"
|
|
bitfld.long 0x0C 02. " SF ,Start Of Frame Enable" "Not affected,Enabled"
|
|
bitfld.long 0x0C 01. " WDH ,Writeback Done Head Enable" "Not affected,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 00. " SO ,Scheduling Overrun Enable" "Not affected,Enabled"
|
|
line.long 0x10 "HCINTERRUPTDISABLE,Hc Interrupt Disable Register"
|
|
bitfld.long 0x10 31. " MID ,Master Interrupt Disable" "No,Yes"
|
|
sif (cpu()!="RCARH2")
|
|
bitfld.long 0x10 30. " OCD ,Ownership Change Disable" "No,Yes"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 06. " RHSCD ,Root Hub Status Change Disable" "No,Yes"
|
|
bitfld.long 0x10 05. " FNOD ,Frame Number Overflow Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 04. " UED ,Unrecoverable Error Disable" "No,Yes"
|
|
bitfld.long 0x10 03. " RDD ,Resume Detected Disable" "No,Yes"
|
|
bitfld.long 0x10 02. " SFD ,Start Of Frame Disable" "No,Yes"
|
|
bitfld.long 0x10 01. " WDHD ,Writeback Done Head Disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 00. " SOD ,Scheduling Overrun Disable" "No,Yes"
|
|
line.long 0x14 "HCHCCA,HCCA Register"
|
|
hexmask.long.tbyte 0x14 08.--31. 1. " HCCA ,Host Controller Communication Area"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "HCPERIODCURRENTED,Hc Period Current ED Register"
|
|
hexmask.long 0x00 04.--31. 1. " PCED ,Period Current ED"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "HCCONTROLHEADED,Hc Control Head ED Register"
|
|
hexmask.long 0x00 04.--31. 1. " CHED ,Control Head ED"
|
|
line.long 0x04 "HCCONTROLCURRENTED,Hc Control Current ED Register"
|
|
hexmask.long 0x04 04.--31. 1. " CCED ,Control Current ED"
|
|
line.long 0x08 "HCBULKHEADED,Hc Bulk Head ED Register"
|
|
hexmask.long 0x08 04.--31. 1. " BHED ,Bulk Head ED"
|
|
line.long 0x0C "HCBULKCURRENTED,Hc Bulk Current ED Register"
|
|
hexmask.long 0x0C 04.--31. 1. " BCED ,Bulk Current ED"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "HCDONEHEAD,Hc Done Head Register"
|
|
hexmask.long 0x00 04.--31. 1. " DH ,Done Head"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HCFMINTERVAL,Hc Fm Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame Interval Toggle" "Low,High"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,FS Largest Data Packet"
|
|
hexmask.long.word 0x00 00.--13. 1. " FI ,Frame Interval"
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "HCFMREMAINING,Hc Fm Remaining Register"
|
|
sif (cpu()=="RCARH2")
|
|
bitfld.long 0x00 31. " FRT ,Frame Remaining Toggle" "Low,High"
|
|
else
|
|
bitfld.long 0x00 31. " FIT ,Frame Remaining Toggle" "Low,High"
|
|
endif
|
|
hexmask.long.word 0x00 00.--13. 1. " FR ,Frame Remaining"
|
|
line.long 0x04 "HCFMNUMBER,Hc Fm Number Register"
|
|
hexmask.long.word 0x04 00.--15. 1. " FN ,Frame Number"
|
|
group.long 0x040++0x17
|
|
line.long 0x00 "HCPERIODICSTART,Hc Periodic Start Register"
|
|
hexmask.long.word 0x00 00.--13. 1. " PS ,Periodic Start"
|
|
line.long 0x04 "HCLSTHRESHOLD,Hc LS Threshold Register"
|
|
hexmask.long.word 0x04 00.--11. 1. " LST ,LS Threshold"
|
|
line.long 0x08 "HCRHDESCRIPTORA,Hc Rh Descriptor A Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " POTPGT ,Power On To Power Good Time"
|
|
bitfld.long 0x08 12. " NOCP ,No Over Current Protection" "Protected,Not protected"
|
|
bitfld.long 0x08 11. " OCPM ,Over Current Protection Mode" "Reported for all,Not supported"
|
|
bitfld.long 0x08 10. " DT ,Device Type" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 09. " NPS ,No Power Switching" "Switched,Not switched"
|
|
bitfld.long 0x08 08. " PSM ,Power Switching Mode" "Power supplied all,Power supplied each"
|
|
hexmask.long.byte 0x08 00.--07. 1. " NDP ,Number Downstream Ports"
|
|
line.long 0x0C "HCRHDESCRIPTORB,Hc Rh Descriptor B Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " PPCM ,Port Power Control Mask"
|
|
hexmask.long.word 0x0C 00.--15. 1. " DR ,Device Removable"
|
|
line.long 0x10 "HCRHSTATUS,Hc Rh Status Register"
|
|
bitfld.long 0x10 31. " CRWE ,Clear Remote Wakeup Enable" "No effect,Cleared"
|
|
eventfld.long 0x10 17. " OCIC ,Over Current Indicator Change" "Not changed,Changed"
|
|
bitfld.long 0x10 16. " SGP ,Local Power Status Change" "Not changed,Changed"
|
|
bitfld.long 0x10 15. " DRWE ,Device Remote Wakeup Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 01. " OCI ,Over Current Indicator" "Not ever-current,Over-current"
|
|
bitfld.long 0x10 00. " CGP ,Local Power Status/ClearGlobalPower" "No effect,Cleared"
|
|
line.long 0x14 "HCRHPORTSTATUS1,Hc Rh Port Status 1"
|
|
sif (cpu()=="RCARH2")
|
|
eventfld.long 0x14 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
else
|
|
bitfld.long 0x14 20. " PRSC ,Port Reset Status Change" "Not completed,Completed"
|
|
endif
|
|
eventfld.long 0x14 19. " POCIC ,Over Current Status Change" "Not changed,Changed"
|
|
sif (cpu()=="RCARH2")
|
|
eventfld.long 0x14 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
eventfld.long 0x14 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
else
|
|
bitfld.long 0x14 18. " PSSC ,Port Suspend Status Change" "Not completed,Completed"
|
|
bitfld.long 0x14 17. " PESC ,Port Enable Status Change" "Not changed,Changed"
|
|
endif
|
|
textline " "
|
|
eventfld.long 0x14 16. " CSC ,Connect Status Change" "Not changed,Changed"
|
|
bitfld.long 0x14 09. " LSDA ,Low Speed Device Attached" "Full speed,Low speed"
|
|
bitfld.long 0x14 08. " PPS ,Port Power Status" "Turned off,Turned On"
|
|
bitfld.long 0x14 04. " PRS ,Port Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x14 03. " POCI ,Port Over Current Indicator" "Not over-current,Over-current"
|
|
bitfld.long 0x14 02. " PSS ,Port Suspend Status" "Not suspended,Suspended"
|
|
bitfld.long 0x14 01. " PES ,Port Enable Status" "Disabled,Enabled"
|
|
bitfld.long 0x14 00. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TMU (Timer Unit)"
|
|
tree "Timer 0"
|
|
base ad:0xFFD80004
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TSTR0,Timer Start Register 0"
|
|
bitfld.byte 0x00 2. " STR2 , Counter Start 2" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STR1 , Counter Start 1" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " STR0 , Counter Start 0" "Halted,Started"
|
|
group.long 0x4++0x07
|
|
line.long 0x00 "TCOR0,Timer Constant Register 0"
|
|
line.long 0x04 "TCNT0,Timer Counter 0"
|
|
group.word (0x4+0x08)++0x01
|
|
line.word 0x00 "TCR0,Timer Control Register 0"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TCOR1,Timer Constant Register 1"
|
|
line.long 0x04 "TCNT1,Timer Counter 1"
|
|
group.word (0x10+0x08)++0x01
|
|
line.word 0x00 "TCR1,Timer Control Register 1"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "TCOR2,Timer Constant Register 2"
|
|
line.long 0x04 "TCNT2,Timer Counter 2"
|
|
group.word (0x1C+0x08)++0x01
|
|
line.word 0x00 "TCR2,Timer Control Register 2"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR2,Input Capture Register 2"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 1"
|
|
base ad:0xFFD81004
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TSTR1,Timer Start Register 1"
|
|
bitfld.byte 0x00 2. " STR5 , Counter Start 5" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STR4 , Counter Start 4" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " STR3 , Counter Start 3" "Halted,Started"
|
|
group.long 0x4++0x07
|
|
line.long 0x00 "TCOR3,Timer Constant Register 3"
|
|
line.long 0x04 "TCNT3,Timer Counter 3"
|
|
group.word (0x4+0x08)++0x01
|
|
line.word 0x00 "TCR3,Timer Control Register 3"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TCOR4,Timer Constant Register 4"
|
|
line.long 0x04 "TCNT4,Timer Counter 4"
|
|
group.word (0x10+0x08)++0x01
|
|
line.word 0x00 "TCR4,Timer Control Register 4"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "TCOR5,Timer Constant Register 5"
|
|
line.long 0x04 "TCNT5,Timer Counter 5"
|
|
group.word (0x1C+0x08)++0x01
|
|
line.word 0x00 "TCR5,Timer Control Register 5"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR5,Input Capture Register 5"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR5,Input Capture Register 5"
|
|
else
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR5,Input Capture Register 5"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Timer 2"
|
|
base ad:0xFFD82004
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "TSTR2,Timer Start Register 2"
|
|
bitfld.byte 0x00 2. " STR8 , Counter Start 8" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " STR7 , Counter Start 7" "Halted,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " STR6 , Counter Start 6" "Halted,Started"
|
|
group.long 0x4++0x07
|
|
line.long 0x00 "TCOR6,Timer Constant Register 6"
|
|
line.long 0x04 "TCNT6,Timer Counter 6"
|
|
group.word (0x4+0x08)++0x01
|
|
line.word 0x00 "TCR6,Timer Control Register 6"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "TCOR7,Timer Constant Register 7"
|
|
line.long 0x04 "TCNT7,Timer Counter 7"
|
|
group.word (0x10+0x08)++0x01
|
|
line.word 0x00 "TCR7,Timer Control Register 7"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "TCOR8,Timer Constant Register 8"
|
|
line.long 0x04 "TCNT8,Timer Counter 8"
|
|
group.word (0x1C+0x08)++0x01
|
|
line.word 0x00 "TCR8,Timer Control Register 8"
|
|
sif (cpu()=="RCARH2")||(cpu()=="R8A7792X")
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR8,Input Capture Register 8"
|
|
elif (cpu()=="RCARM2")
|
|
bitfld.word 0x00 9. " ICPF ,Input Capture Interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " ICPE ,Input Capture Control" "Disabled,,No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " TPSC ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,,,Count on external clk"
|
|
rgroup.long (0x1C+0x0c)++0x03
|
|
line.long 0x00 "TCPR8,Input Capture Register 8"
|
|
else
|
|
bitfld.word 0x00 8. " UNF ,Underflow Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " UNIE ,Underflow Interrupt Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3.--4. " CKEG ,Clock Edge" "Rising edge,Falling edge,Both edges,Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " CKEG ,Timer Prescaler" "Count on clkp/4,Count on clkp/16,Count on clkp/64,Count on clkp/256,Count on clkp/1024,?..."
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "PWM Timer"
|
|
tree "Channel 0"
|
|
base ad:0xFFE50000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE50000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 1"
|
|
base ad:0xFFE51000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE51000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFE52000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE52000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 3"
|
|
base ad:0xFFE53000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE53000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 4"
|
|
base ad:0xFFE54000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE54000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 5"
|
|
base ad:0xFFE55000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE55000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 6"
|
|
base ad:0xFFE56000
|
|
width 8.
|
|
if (((per.l(ad:0xFFE56000))&0x8000)==0x8000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/2,/2^3,/2^5,/2^7,/2^9,/2^11,/2^13,/2^15,/2^17,/2^19,/2^21,/2^23,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWMCR,PWM Control Register"
|
|
bitfld.long 0x00 16.--19. " CC0 ,Clock control [frequency divider]" "/1,/2^2,/2^4,/2^6,/2^8,/2^10,/2^12,/2^14,/2^16,/2^18,/2^20,/2^22,/2^24,/2^24,/2^24,/2^24"
|
|
bitfld.long 0x00 15. " CCMD ,CC0 frequency division mode" "Normal,Modified"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNC ,PWMCNT set values reflected in timer operation mode" "Irrespective of PWMCR setting,Synchronously with PWMCR"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 5.--6. " FS ,Functional safety use only" "0,1,2,3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " SS0 ,Single pulse output" "Continuous,Single cycle"
|
|
textline " "
|
|
sif (cpuis("R8A77965*"))||(cpuis("R8A77960*"))||(cpuis("R8A77970*"))||(cpuis("R8A77980*"))||(cpuis("R8A77995*"))||(cpuis("R8A77990*"))||((cpuis("R8A77951")||cpuis("R8A77951-*")))
|
|
bitfld.long 0x00 3. " ECEN ,Functional safety use only" "0,1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN0 ,Channel enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWMCNT,PWM Count Register"
|
|
hexmask.long.word 0x00 16.--25. 1. " CYC0 ,PWM cycle"
|
|
hexmask.long.word 0x00 0.--9. 1. " PH0 ,PWM High-Level period"
|
|
sif (cpuis("R8A77980*"))
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWMEI,PWM Error Injection Register"
|
|
bitfld.long 0x00 0. " PWMEI ,PWMEI" "0,1"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "GPS"
|
|
base ad:0xFFD00000
|
|
width 14.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "HSTR,Host status"
|
|
line.long 0x04 "HCMR,Host command"
|
|
line.long 0x08 "HINTR,Host interrupt source"
|
|
line.long 0x0c "GSTR,GPS status"
|
|
line.long 0x10 "GCMR,GPS command"
|
|
line.long 0x14 "GINTR,GPS interrupt source"
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "TIM_LATCH_H,Timer latch"
|
|
line.long 0x04 "TIM_DATA_H,Timer count"
|
|
wgroup.long 0x400++0x03
|
|
line.long 0x00 "H_DATA_RAM,Host data RAM"
|
|
button "RAM" "d (ad:0xFFD00000+0x400)--(ad:0xFFD00000+0x7FF) /long"
|
|
rgroup.long 0xc00++0x03
|
|
line.long 0x00 "GPS_DATA_RAM,GPS data RAM"
|
|
button "RAM" "d (ad:0xFFD00000+0x0C00)--(ad:0xFFD00000+0x17FF) /long"
|
|
group.long 0x3000++0x33
|
|
line.long 0x00 "ENW00,Galileo interrupt enable A"
|
|
line.long 0x04 "ENW01,Galileo interrupt enable B"
|
|
line.long 0x08 "ENS00,Galileo interrupt enable C"
|
|
line.long 0x0c "ENS01,Galileo interrupt enable D"
|
|
line.long 0x10 "EIRR00,Galileo interrupt source A"
|
|
line.long 0x14 "EIRR01,Galileo interrupt source B"
|
|
line.long 0x18 "HSDR00,Galileo select A"
|
|
line.long 0x1c "HSDR01,Galileo select B"
|
|
line.long 0x20 "SAT00,Galileo select C"
|
|
line.long 0x24 "SAT01,Galileo select D"
|
|
line.long 0x28 "DSR00,Galileo flag A"
|
|
line.long 0x2c "DSR01,Galileo flag B"
|
|
line.long 0x30 "VRESET,Galileo software reset"
|
|
group.long 0x3100++0x03
|
|
line.long 0x00 "G_DATA_RAM,Galileo data RAM"
|
|
button "RAM" "d (ad:0xFFD00000+0x3100)--(ad:0xFFD00000+0x333F) /long"
|
|
sif (cpu()=="RCARH2"||cpu()=="RCARM2")
|
|
base ad:0xFFD00000
|
|
group.long 0x4004++0x3
|
|
line.long 0x00 "SPI_INI1,GLONASS set 1"
|
|
group.long 0x4024++0x3
|
|
line.long 0x00 "SPI_ICYC1,GLONASS set 2"
|
|
group.long 0x4044++0x3
|
|
line.long 0x00 "SPI_DCYC1,GLONASS set 3"
|
|
group.long 0x4060++0x7
|
|
line.long 0x00 "SPI_SEL,GLONASS set 4"
|
|
line.long 0x04 "SPI_START,GLONASS set 5"
|
|
rgroup.long 0x4068++0x3
|
|
line.long 0x00 "SPI_FLG,GLONASS operation flag"
|
|
group.long 0x406C++0xB
|
|
line.long 0x00 "SPI_INTMAS,GLONASS interrupt mask"
|
|
line.long 0x04 "SPI_INTFACT,GLONASS interrupt source"
|
|
line.long 0x08 "SPI_INST,GLONASS set 6"
|
|
group.long 0x4080++0x3
|
|
line.long 0x00 "SPI_WDATA0,GLONASS set 7"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree "Gyro-ADC IF"
|
|
base ad:0xFFC5A000
|
|
width 18.
|
|
group.long 0x00++0x0f
|
|
line.long 0x00 "MSR,Mode Select Register"
|
|
bitfld.long 0x00 0.--1. " MODE_SEL ,These bits select the mode to match the ADC in use" "Mode 1 (MB88101A),Mode 2 (ADCS7476),,Mode 3 (MAX1162)"
|
|
line.long 0x04 "SSSR,Start/Stop Setting Register"
|
|
bitfld.long 0x04 0. " STAT ,Starts or stops operation of the Gyro-ADC IF and speed-pulse IF" "Stopped,Started"
|
|
line.long 0x08 "ADCACLSR,ADC Access Clock Length Setting Register"
|
|
hexmask.long.word 0x08 0.--9. 1. " ADC_CLOCK_LENGTH ,Set the count value to create the clock length per one clock cycle for accessing an ADC device"
|
|
line.long 0x0c "125TLSR,1.25-ms Time Length Setting Register"
|
|
hexmask.long.tbyte 0x0c 0.--16. 1. " 1.25MS ,Set the count value for creating a period of 1.25 ms"
|
|
if (((per.l(ad:0xFFC5A000))&0x3)==0x0)
|
|
rgroup.long 0x10++0x0f
|
|
line.long 0x0 "RDAR_0,Realtime Data Acquisition Register 0"
|
|
hexmask.long.word 0x0 0.--11. 1. " AD_CH0_DATA ,Realtime data (12 bits) of ch[0] is indicated in the AD_ch[0]_data[11:0] bits"
|
|
line.long 0x4 "RDAR_1,Realtime Data Acquisition Register 1"
|
|
hexmask.long.word 0x4 0.--11. 1. " AD_CH1_DATA ,Realtime data (12 bits) of ch[1] is indicated in the AD_ch[1]_data[11:0] bits"
|
|
line.long 0x8 "RDAR_2,Realtime Data Acquisition Register 2"
|
|
hexmask.long.word 0x8 0.--11. 1. " AD_CH2_DATA ,Realtime data (12 bits) of ch[2] is indicated in the AD_ch[2]_data[11:0] bits"
|
|
line.long 0xC "RDAR_3,Realtime Data Acquisition Register 3"
|
|
hexmask.long.word 0xC 0.--11. 1. " AD_CH3_DATA ,Realtime data (12 bits) of ch[3] is indicated in the AD_ch[3]_data[11:0] bits"
|
|
elif (((per.l(ad:0xFFC5A000))&0x3)==0x1)
|
|
rgroup.long 0x10++0x1f
|
|
line.long 0x0 "RDAR_0,Realtime Data Acquisition Register 0"
|
|
hexmask.long.word 0x0 0.--14. 1. " AD_CH0_DATA ,Realtime data (15 bits) of ch[0] is indicated in the AD_ch[0]_data[14:0] bits"
|
|
line.long 0x4 "RDAR_1,Realtime Data Acquisition Register 1"
|
|
hexmask.long.word 0x4 0.--14. 1. " AD_CH1_DATA ,Realtime data (15 bits) of ch[1] is indicated in the AD_ch[1]_data[14:0] bits"
|
|
line.long 0x8 "RDAR_2,Realtime Data Acquisition Register 2"
|
|
hexmask.long.word 0x8 0.--14. 1. " AD_CH2_DATA ,Realtime data (15 bits) of ch[2] is indicated in the AD_ch[2]_data[14:0] bits"
|
|
line.long 0xC "RDAR_3,Realtime Data Acquisition Register 3"
|
|
hexmask.long.word 0xC 0.--14. 1. " AD_CH3_DATA ,Realtime data (15 bits) of ch[3] is indicated in the AD_ch[3]_data[14:0] bits"
|
|
line.long 0x10 "RDAR_4,Realtime Data Acquisition Register 4"
|
|
hexmask.long.word 0x10 0.--14. 1. " AD_CH4_DATA ,Realtime data (15 bits) of ch[4] is indicated in the AD_ch[4]_data[14:0] bits"
|
|
line.long 0x14 "RDAR_5,Realtime Data Acquisition Register 5"
|
|
hexmask.long.word 0x14 0.--14. 1. " AD_CH5_DATA ,Realtime data (15 bits) of ch[5] is indicated in the AD_ch[5]_data[14:0] bits"
|
|
line.long 0x18 "RDAR_6,Realtime Data Acquisition Register 6"
|
|
hexmask.long.word 0x18 0.--14. 1. " AD_CH6_DATA ,Realtime data (15 bits) of ch[6] is indicated in the AD_ch[6]_data[14:0] bits"
|
|
line.long 0x1C "RDAR_7,Realtime Data Acquisition Register 7"
|
|
hexmask.long.word 0x1C 0.--14. 1. " AD_CH7_DATA ,Realtime data (15 bits) of ch[7] is indicated in the AD_ch[7]_data[14:0] bits"
|
|
elif (((per.l(ad:0xFFC5A000))&0x3)==0x3)
|
|
rgroup.long 0x10++0x1f
|
|
line.long 0x0 "RDAR_0,Realtime Data Acquisition Register 0"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " AD_CH0_DATA ,Realtime data (24 bits) of ch[0] is indicated in the AD_ch[0]_data[23:0] bits"
|
|
line.long 0x4 "RDAR_1,Realtime Data Acquisition Register 1"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " AD_CH1_DATA ,Realtime data (24 bits) of ch[1] is indicated in the AD_ch[1]_data[23:0] bits"
|
|
line.long 0x8 "RDAR_2,Realtime Data Acquisition Register 2"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " AD_CH2_DATA ,Realtime data (24 bits) of ch[2] is indicated in the AD_ch[2]_data[23:0] bits"
|
|
line.long 0xC "RDAR_3,Realtime Data Acquisition Register 3"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " AD_CH3_DATA ,Realtime data (24 bits) of ch[3] is indicated in the AD_ch[3]_data[23:0] bits"
|
|
line.long 0x10 "RDAR_4,Realtime Data Acquisition Register 4"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " AD_CH4_DATA ,Realtime data (24 bits) of ch[4] is indicated in the AD_ch[4]_data[23:0] bits"
|
|
line.long 0x14 "RDAR_5,Realtime Data Acquisition Register 5"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " AD_CH5_DATA ,Realtime data (24 bits) of ch[5] is indicated in the AD_ch[5]_data[23:0] bits"
|
|
line.long 0x18 "RDAR_6,Realtime Data Acquisition Register 6"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " AD_CH6_DATA ,Realtime data (24 bits) of ch[6] is indicated in the AD_ch[6]_data[23:0] bits"
|
|
line.long 0x1C "RDAR_7,Realtime Data Acquisition Register 7"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " AD_CH7_DATA ,Realtime data (24 bits) of ch[7] is indicated in the AD_ch[7]_data[23:0] bits"
|
|
else
|
|
hgroup.long 0x10++0x1f
|
|
hide.long 0x0 "RDAR_0,Realtime Data Acquisition Register 0"
|
|
hide.long 0x4 "RDAR_1,Realtime Data Acquisition Register 1"
|
|
hide.long 0x8 "RDAR_2,Realtime Data Acquisition Register 2"
|
|
hide.long 0xC "RDAR_3,Realtime Data Acquisition Register 3"
|
|
hide.long 0x10 "RDAR_4,Realtime Data Acquisition Register 4"
|
|
hide.long 0x14 "RDAR_5,Realtime Data Acquisition Register 5"
|
|
hide.long 0x18 "RDAR_6,Realtime Data Acquisition Register 6"
|
|
hide.long 0x1C "RDAR_7,Realtime Data Acquisition Register 7"
|
|
endif
|
|
if (((per.l(ad:0xFFC5A000))&0x3)==0x0)
|
|
rgroup.long 0x30++0x0f
|
|
line.long 0x0 "100ADAR_0,100-ms Added Data Acquisition Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. " AD_CH0_ADD_DATA ,Data obtained by adding average value of eight 12bit ch[0] data items"
|
|
line.long 0x4 "100ADAR_1,100-ms Added Data Acquisition Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. " AD_CH1_ADD_DATA ,Data obtained by adding average value of eight 12bit ch[1] data items"
|
|
line.long 0x8 "100ADAR_2,100-ms Added Data Acquisition Register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. " AD_CH2_ADD_DATA ,Data obtained by adding average value of eight 12bit ch[2] data items"
|
|
line.long 0xC "100ADAR_3,100-ms Added Data Acquisition Register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. " AD_CH3_ADD_DATA ,Data obtained by adding average value of eight 12bit ch[3] data items"
|
|
elif (((per.l(ad:0xFFC5A000))&0x3)==0x1)
|
|
rgroup.long 0x30++0x1f
|
|
line.long 0x0 "100ADAR_0,100-ms Added Data Acquisition Register 0"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. " AD_CH0_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[0] data items"
|
|
line.long 0x4 "100ADAR_1,100-ms Added Data Acquisition Register 1"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. " AD_CH1_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[1] data items"
|
|
line.long 0x8 "100ADAR_2,100-ms Added Data Acquisition Register 2"
|
|
hexmask.long.tbyte 0x8 0.--18. 1. " AD_CH2_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[2] data items"
|
|
line.long 0xC "100ADAR_3,100-ms Added Data Acquisition Register 3"
|
|
hexmask.long.tbyte 0xC 0.--18. 1. " AD_CH3_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[3] data items"
|
|
line.long 0x10 "100ADAR_4,100-ms Added Data Acquisition Register 4"
|
|
hexmask.long.tbyte 0x10 0.--18. 1. " AD_CH4_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[4] data items"
|
|
line.long 0x14 "100ADAR_5,100-ms Added Data Acquisition Register 5"
|
|
hexmask.long.tbyte 0x14 0.--18. 1. " AD_CH5_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[5] data items"
|
|
line.long 0x18 "100ADAR_6,100-ms Added Data Acquisition Register 6"
|
|
hexmask.long.tbyte 0x18 0.--18. 1. " AD_CH6_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[6] data items"
|
|
line.long 0x1C "100ADAR_7,100-ms Added Data Acquisition Register 7"
|
|
hexmask.long.tbyte 0x1C 0.--18. 1. " AD_CH7_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[7] data items"
|
|
elif (((per.l(ad:0xFFC5A000))&0x3)==0x3)
|
|
rgroup.long 0x30++0x1f
|
|
line.long 0x0 "100ADAR_0,100-ms Added Data Acquisition Register 0"
|
|
hexmask.long 0x0 0.--27. 1. " AD_CH0_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[0] data items"
|
|
line.long 0x4 "100ADAR_1,100-ms Added Data Acquisition Register 1"
|
|
hexmask.long 0x4 0.--27. 1. " AD_CH1_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[1] data items"
|
|
line.long 0x8 "100ADAR_2,100-ms Added Data Acquisition Register 2"
|
|
hexmask.long 0x8 0.--27. 1. " AD_CH2_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[2] data items"
|
|
line.long 0xC "100ADAR_3,100-ms Added Data Acquisition Register 3"
|
|
hexmask.long 0xC 0.--27. 1. " AD_CH3_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[3] data items"
|
|
line.long 0x10 "100ADAR_4,100-ms Added Data Acquisition Register 4"
|
|
hexmask.long 0x10 0.--27. 1. " AD_CH4_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[4] data items"
|
|
line.long 0x14 "100ADAR_5,100-ms Added Data Acquisition Register 5"
|
|
hexmask.long 0x14 0.--27. 1. " AD_CH5_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[5] data items"
|
|
line.long 0x18 "100ADAR_6,100-ms Added Data Acquisition Register 6"
|
|
hexmask.long 0x18 0.--27. 1. " AD_CH6_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[6] data items"
|
|
line.long 0x1C "100ADAR_7,100-ms Added Data Acquisition Register 7"
|
|
hexmask.long 0x1C 0.--27. 1. " AD_CH7_ADD_DATA ,Data obtained by adding average value of eight 24bit ch[7] data items"
|
|
else
|
|
hgroup.long 0x30++0x1f
|
|
hide.long 0x0 "100ADAR_0,100-ms Added Data Acquisition Register 0"
|
|
hide.long 0x4 "100ADAR_1,100-ms Added Data Acquisition Register 1"
|
|
hide.long 0x8 "100ADAR_2,100-ms Added Data Acquisition Register 2"
|
|
hide.long 0xC "100ADAR_3,100-ms Added Data Acquisition Register 3"
|
|
hide.long 0x10 "100ADAR_4,100-ms Added Data Acquisition Register 4"
|
|
hide.long 0x14 "100ADAR_5,100-ms Added Data Acquisition Register 5"
|
|
hide.long 0x18 "100ADAR_6,100-ms Added Data Acquisition Register 6"
|
|
hide.long 0x1C "100ADAR_7,100-ms Added Data Acquisition Register 7"
|
|
endif
|
|
if (((per.l(ad:0xFFC5A000))&0x3)==(0x1||0x3))
|
|
rgroup.long 0x50++0x1f
|
|
line.long 0x0 "32WFIFOR8TAV_0,AD ch[0] 10ms data FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. " AD_CH0_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[0] data items"
|
|
line.long 0x4 "32WFIFOR8TAV_1,AD ch[1] 10ms data FIFO"
|
|
hexmask.long.word 0x4 0.--15. 1. " AD_CH1_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[1] data items"
|
|
line.long 0x8 "32WFIFOR8TAV_2,AD ch[2] 10ms data FIFO"
|
|
hexmask.long.word 0x8 0.--15. 1. " AD_CH2_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[2] data items"
|
|
line.long 0xC "32WFIFOR8TAV_3,AD ch[3] 10ms data FIFO"
|
|
hexmask.long.word 0xC 0.--15. 1. " AD_CH3_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[3] data items"
|
|
line.long 0x10 "32WFIFOR8TAV_4,AD ch[4] 10ms data FIFO"
|
|
hexmask.long.word 0x10 0.--15. 1. " AD_CH4_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[4] data items"
|
|
line.long 0x14 "32WFIFOR8TAV_5,AD ch[5] 10ms data FIFO"
|
|
hexmask.long.word 0x14 0.--15. 1. " AD_CH5_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[5] data items"
|
|
line.long 0x18 "32WFIFOR8TAV_6,AD ch[6] 10ms data FIFO"
|
|
hexmask.long.word 0x18 0.--15. 1. " AD_CH6_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[6] data items"
|
|
line.long 0x1C "32WFIFOR8TAV_7,AD ch[7] 10ms data FIFO"
|
|
hexmask.long.word 0x1C 0.--15. 1. " AD_CH7_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[7] data items"
|
|
elif (((per.l(ad:0xFFC5A000))&0x3)==0x3)
|
|
rgroup.long 0x50++0x1f
|
|
line.long 0x0 "32WFIFOR8TAV_0,AD ch[0] 10ms data FIFO"
|
|
hexmask.long.word 0x0 0.--14. 1. " AD_CH0_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[0] data items"
|
|
line.long 0x4 "32WFIFOR8TAV_1,AD ch[1] 10ms data FIFO"
|
|
hexmask.long.word 0x4 0.--14. 1. " AD_CH1_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[1] data items"
|
|
line.long 0x8 "32WFIFOR8TAV_2,AD ch[2] 10ms data FIFO"
|
|
hexmask.long.word 0x8 0.--14. 1. " AD_CH2_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[2] data items"
|
|
line.long 0xC "32WFIFOR8TAV_3,AD ch[3] 10ms data FIFO"
|
|
hexmask.long.word 0xC 0.--14. 1. " AD_CH3_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[3] data items"
|
|
line.long 0x10 "32WFIFOR8TAV_4,AD ch[4] 10ms data FIFO"
|
|
hexmask.long.word 0x10 0.--14. 1. " AD_CH4_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[4] data items"
|
|
line.long 0x14 "32WFIFOR8TAV_5,AD ch[5] 10ms data FIFO"
|
|
hexmask.long.word 0x14 0.--14. 1. " AD_CH5_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[5] data items"
|
|
line.long 0x18 "32WFIFOR8TAV_6,AD ch[6] 10ms data FIFO"
|
|
hexmask.long.word 0x18 0.--14. 1. " AD_CH6_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[6] data items"
|
|
line.long 0x1C "32WFIFOR8TAV_7,AD ch[7] 10ms data FIFO"
|
|
hexmask.long.word 0x1C 0.--14. 1. " AD_CH7_ADD_DATA ,Data obtained by adding average value of eight 15bit ch[7] data items"
|
|
else
|
|
hgroup.long 0x50++0x1f
|
|
hide.long 0x0 "32WFIFOR8TAV_0,AD ch[0] 10ms data FIFO"
|
|
hide.long 0x4 "32WFIFOR8TAV_1,AD ch[1] 10ms data FIFO"
|
|
hide.long 0x8 "32WFIFOR8TAV_2,AD ch[2] 10ms data FIFO"
|
|
hide.long 0xC "32WFIFOR8TAV_3,AD ch[3] 10ms data FIFO"
|
|
hide.long 0x10 "32WFIFOR8TAV_4,AD ch[4] 10ms data FIFO"
|
|
hide.long 0x14 "32WFIFOR8TAV_5,AD ch[5] 10ms data FIFO"
|
|
hide.long 0x18 "32WFIFOR8TAV_6,AD ch[6] 10ms data FIFO"
|
|
hide.long 0x1C "32WFIFOR8TAV_7,AD ch[7] 10ms data FIFO"
|
|
endif
|
|
sif (cpu()=="RCARM2")||(cpu()=="R8A7792X")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FIFOSR,FIFO Status Register"
|
|
eventfld.long 0x00 30. " CH[7]_ERROR ,Channel 7 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 29. " CH[7]_FULL ,Channel 7 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 28. " CH[7]_EMPTY ,Channel 7 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 26. " CH[6]_ERROR ,Channel 6 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 25. " CH[6]_FULL ,Channel 6 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 24. " CH[6]_EMPTY ,Channel 6 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CH[5]_ERROR ,Channel 5 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 21. " CH[5]_FULL ,Channel 5 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 20. " CH[5]_EMPTY ,Channel 5 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CH[4]_ERROR ,Channel 4 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 17. " CH[4]_FULL ,Channel 4 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 16. " CH[4]_EMPTY ,Channel 4 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 14. " CH[3]_ERROR ,Channel 3 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 13. " CH[3]_FULL ,Channel 3 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 12. " CH[3]_EMPTY ,Channel 3 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CH[2]_ERROR ,Channel 2 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 9. " CH[2]_FULL ,Channel 2 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 8. " CH[2]_EMPTY ,Channel 2 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 6. " CH[1]_ERROR ,Channel 1 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 5. " CH[1]_FULL ,Channel 1 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 4. " CH[1]_EMPTY ,Channel 1 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CH[0]_ERROR ,Channel 0 error [read/write]" "No error/No effect,Error/Cleared"
|
|
rbitfld.long 0x00 1. " CH[0]_FULL ,Channel 0 FIFO full" "Not full,Full"
|
|
rbitfld.long 0x00 0. " CH[0]_EMPTY ,Channel 0 FIFO empty" "Not empty,Empty"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "FIFOSR,FIFO Status Register"
|
|
eventfld.long 0x00 30. " CH[7]_ERROR ,Channel 7 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 29. " CH[7]_FULL ,Channel 7 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 28. " CH[7]_EMPTY ,Channel 7 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 26. " CH[6]_ERROR ,Channel 6 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 25. " CH[6]_FULL ,Channel 6 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 24. " CH[6]_EMPTY ,Channel 6 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 22. " CH[5]_ERROR ,Channel 5 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 21. " CH[5]_FULL ,Channel 5 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 20. " CH[5]_EMPTY ,Channel 5 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 18. " CH[4]_ERROR ,Channel 4 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 17. " CH[4]_FULL ,Channel 4 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 16. " CH[4]_EMPTY ,Channel 4 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 14. " CH[3]_ERROR ,Channel 3 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 13. " CH[3]_FULL ,Channel 3 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 12. " CH[3]_EMPTY ,Channel 3 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CH[2]_ERROR ,Channel 2 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 9. " CH[2]_FULL ,Channel 2 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 8. " CH[2]_EMPTY ,Channel 2 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 6. " CH[1]_ERROR ,Channel 1 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 5. " CH[1]_FULL ,Channel 1 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 4. " CH[1]_EMPTY ,Channel 1 FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CH[0]_ERROR ,Channel 0 error [read/write]" "No error/No effect,Error/Cleared"
|
|
bitfld.long 0x00 1. " CH[0]_FULL ,Channel 0 FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 0. " CH[0]_EMPTY ,Channel 0 FIFO empty" "Not empty,Empty"
|
|
endif
|
|
sif (cpu()=="R8A7792X")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "INTR,Interrupt Register"
|
|
bitfld.long 0x00 0. " INT ,Interrupt signal assertion" "Not asserted,Asserted"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "INTENR,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " INTEN ,Interrupt request enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
width 0xb
|
|
tree.end
|
|
tree "Speed-Pulse IF"
|
|
base ad:0xFFC5B000
|
|
width 12.
|
|
group.long 0x00++0x0b
|
|
line.long 0x00 "SPCDR,Speed Pulse Count Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPEED_DATA ,Indicate the speed pulse count in realtime"
|
|
line.long 0x04 "SPFSR,Speed Pulse Filter Setting Register"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " NF_SET ,Specify the value to count (nf_clk) for obtaining the time constant for the filter"
|
|
line.long 0x08 "SPCCR,Speed Pulse Count Clearing Register"
|
|
bitfld.long 0x08 0. " CCLR ,Restarts the speed pulse counters" "No restart,Restart"
|
|
rgroup.long 0x0c++0x07
|
|
line.long 0x00 "SP100LDR,Speed Pulse 100-ms Latch Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPEED_100MS ,Indicate the value obtained by latching the speed pulse count data every 100 ms"
|
|
line.long 0x04 "100INTCR,100-ms INT Count Register"
|
|
bitfld.long 0x04 0.--3. " INT_COUNT ,Indicate the count incremented in synchronization with the INT_100ms interrupt signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "INTSCR,INT Status and Clear Register"
|
|
eventfld.long 0x00 0. " INT ,Indicates whether an interrupt by a 100-ms-cycle trigger has occurred [read/write]" "No interrupt/No effect,Interupt/Cleared"
|
|
rgroup.long 0x100++0x13
|
|
line.long 0x00 "SPOFAR,Speed Pulse Offset A Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SPEED_OFFSET_DATA_A ,Indicate the time elapsed since the latest rising edge of the speed pulse signal until the speed pulse count data register is read"
|
|
line.long 0x04 "SPOFBR,Speed Pulse Offset B Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " SPEED_OFFSET_DATA_B ,Indicate the time elapsed since the latest rising edge of the speed pulse signal until a 100-ms-cycle trigger"
|
|
line.long 0x08 "SPWR,Speed Pulse Width Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " SPEED_WIDTH_DATA ,Indicate the width of the latest speed pulse"
|
|
line.long 0x0c "SPOBAR,Speed Pulse Observe A Register"
|
|
hexmask.long.tbyte 0x0c 0.--23. 1. " SPEED_OBSERVE_DATA_A ,Indicate the time between the rising edges of the speed pulse signal immediately before the speed pulse count data register is read"
|
|
line.long 0x10 "SPOBBR,Speed Pulse Observe B Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " SPEED_OBSERVE_DATA_B ,Indicate the time between the rising edges of the speed pulse signal immediately before a 100-ms-cycle trigger"
|
|
group.long 0x114++0x0b
|
|
line.long 0x00 "SPWCR,Speed Pulse Width Clearing Register"
|
|
bitfld.long 0x00 0. " WCLR ,The following counter register values are reset through manipulation of this bit [elapsed time, pulse width, and observation period register]" "Counting is started,Values are kept at 0"
|
|
line.long 0x04 "SPWTR,Speed Pulse Width Test Register"
|
|
line.long 0x08 "500KHZFCSR,500-kHz Freq. Count Setting Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " 2US ,Specify the count value for creating 2 us"
|
|
width 0xb
|
|
tree.end
|
|
tree "IR (IR Receiver)"
|
|
base ad:0xFFC56000
|
|
width 9.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "IRMODE,IR Mode Register"
|
|
bitfld.long 0x00 7. " RCDENDE ,Receive code end interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RFRENDE ,Receive frame end interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RBUFM ,Receive register mode" "Double buffer mode,Single buffer mode"
|
|
bitfld.long 0x00 4. " INVERT ,Receive signal polarity inversion" "Inverted,Not inverted"
|
|
textline " "
|
|
bitfld.long 0x00 1.--3. " RMODE ,Receive operating mode" "Leader code,No leader code,?..."
|
|
bitfld.long 0x00 0. " RECON ,IR receiver start" "Not started,Started"
|
|
line.long 0x04 "IRCOMM,IR Command Register"
|
|
hexmask.long.byte 0x04 8.--15. 1. " XCM ,Specified compo code"
|
|
bitfld.long 0x04 5.--7. " ARC ,Acknowledge receive code" "Any code,Lower four bits match,Upper four bits match,Compo code match,,Lower four bits not match,Upper four bits not match,Compo code not match"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ICC ,Instruction/compo code check" "Any compo/instruction code,Compo/instruction code inverted match"
|
|
bitfld.long 0x04 0. " RCDM ,Receive code buffer mode" "RCODE11/RCODE21,RCODE11-12/RCODE21-22"
|
|
line.long 0x08 "IRST,IR Status Register"
|
|
bitfld.long 0x08 7. " RCDEND ,Frame receive code end status" "Not completed,Completed"
|
|
bitfld.long 0x08 6. " RFREND ,Frame receive end status" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " RSEL12 ,Receive code buffer specification status" "RCODE11-12,RCODE21-22"
|
|
line.long 0x0C "CPD,CLKP Division Ratio Register"
|
|
hexmask.long.word 0x0C 0.--12. 1. " CPD ,CLKP division ratio"
|
|
line.long 0x10 "LDHL,Leader High Period Register"
|
|
hexmask.long.word 0x10 16.--27. 1. " LDHU ,Leader high period upper limit"
|
|
hexmask.long.word 0x10 0.--11. 1. " LDHL ,Leader high period lower limit"
|
|
line.long 0x14 "LDLL,Leader Low Period Register"
|
|
hexmask.long.word 0x14 16.--27. 1. " LDLU ,Leader low period upper limit"
|
|
hexmask.long.word 0x14 0.--11. 1. " LDLL ,Leader low period lower limit"
|
|
line.long 0x18 "BS0L,0 Bit Period Register"
|
|
hexmask.long.word 0x18 16.--27. 1. " BS0U ,0 bit period upper limit"
|
|
hexmask.long.word 0x18 0.--11. 1. " BS0L ,0 bit period lower limit"
|
|
line.long 0x1C "BS1L,1 Bit Period Register"
|
|
hexmask.long.word 0x1C 16.--27. 1. " BS1U ,1 bit period upper limit"
|
|
hexmask.long.word 0x1C 0.--11. 1. " BS1L ,1 bit period lower limit"
|
|
line.long 0x20 "BSHL,0 Or 1 Bit High Period Register"
|
|
hexmask.long.word 0x20 16.--27. 1. " BSHU ,0 or 1 bit high period upper limit"
|
|
hexmask.long.word 0x20 0.--11. 1. " BSHL ,0 or 1 bit high period lower limit"
|
|
line.long 0x24 "TWP,Trailer Wait Time Register"
|
|
hexmask.long.word 0x24 0.--15. 1. " TWP ,Trailer wait time"
|
|
line.long 0x28 "RNOFBS,Receive Frame Total Bit Number Register"
|
|
bitfld.long 0x28 11.--13. " TN ,Maximum number of times the receiver should attempt to receive a low or high level signal at the reception sampling frequency during leader code reception" "3,4,5,6,7,8,9,10"
|
|
bitfld.long 0x28 8.--10. " DN ,Number of times the receiver should detect a low or high level signal consecutively to determine the pulse level (low or high) during leader code reception" "3,4,5,6,7,8,9,10"
|
|
textline " "
|
|
hexmask.long.byte 0x28 0.--6. 1. " RNOFBS ,Sets the total number of bits in a frame"
|
|
rgroup.long 0x2C++0x0F
|
|
line.long 0x00 "RCODE11,Receive Code 1-1"
|
|
line.long 0x04 "RCODE12,Receive Code 1-2"
|
|
line.long 0x08 "RCODE21,Receive Code 2-1"
|
|
line.long 0x0C "RCODE22,Receive Code 2-2"
|
|
width 0x0B
|
|
tree.end
|
|
tree "THS/TSC (Thermal Sensor)"
|
|
base ad:0xFFC48000
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "IOINTSEL,General I/O/Interrupt Input Mode Select Register"
|
|
bitfld.long 0x00 3. " IOINTSEL3 ,Interrupt input mode when the thermal sensor is used" ",Interrupt input mode"
|
|
bitfld.long 0x00 2. " IOINTSEL2 ,Interrupt input mode when the thermal sensor is used" ",Interrupt input mode"
|
|
bitfld.long 0x00 1. " IOINTSEL1 ,Interrupt input mode when the thermal sensor is used" ",Interrupt input mode"
|
|
bitfld.long 0x00 0. " IOINTSEL0 ,Interrupt input mode when the thermal sensor is used" ",Interrupt input mode"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INTDT,Interrupt status register"
|
|
bitfld.long 0x00 3. " INTDT3 ,INTDT3 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INTDT2 ,INTDT2 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " INTDT1 ,INTDT1 interrupt status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " INTDT0 ,INTDT0 interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x14++0x0b
|
|
line.long 0x00 "INTCLR,Interrupt Clear Register"
|
|
bitfld.long 0x00 3. " INTCLR3 ,INTDT3 interrupt clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " INTCLR2 ,INTDT2 interrupt clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " INTCLR1 ,INTDT1 interrupt clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " INTCLR0 ,INTDT0 interrupt clear" "Not cleared,Cleared"
|
|
line.long 0x04 "INTMSK,Interrupt Mask Register"
|
|
bitfld.long 0x04 3. " INTMSK3 ,INTDT3 interrupt request signal masked" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " INTMSK2 ,INTDT2 interrupt request signal masked" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " INTMSK1 ,INTDT1 interrupt request signal masked" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " INTMSK0 ,INTDT0 interrupt request signal masked" "Masked,Not masked"
|
|
line.long 0x08 "MSKCLR,Interrupt Mask Clear Register"
|
|
bitfld.long 0x08 3. " INTMSK3 ,INTDT3 interrupt mask clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " INTMSK2 ,INTDT2 interrupt mask clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 1. " INTMSK1 ,INTDT1 interrupt mask clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " INTMSK0 ,INTDT0 interrupt mask clear" "Not cleared,Cleared"
|
|
if (((per.l(ad:0xFFC48000+0x2c))&0x1000)==0x1000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "POSNEG,Positive/Negative Logic Select Register"
|
|
bitfld.long 0x00 3. " POSNEG3 ,Selects the edge polarity of the interrupt input signal" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 2. " POSNEG2 ,Selects the edge polarity of the interrupt input signal" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 1. " POSNEG1 ,Selects the edge polarity of the interrupt input signal" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0. " POSNEG0 ,Selects the edge polarity of the interrupt input signal" "Rising edge,Falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "POSNEG,Positive/Negative Logic Select Register"
|
|
bitfld.long 0x00 3. " POSNEG3 ,Selects the edge polarity of the interrupt input signal" "Rising edge,?..."
|
|
bitfld.long 0x00 2. " POSNEG2 ,Selects the edge polarity of the interrupt input signal" "Rising edge,?..."
|
|
bitfld.long 0x00 1. " POSNEG1 ,Selects the edge polarity of the interrupt input signal" "Rising edge,?..."
|
|
bitfld.long 0x00 0. " POSNEG0 ,Selects the edge polarity of the interrupt input signal" "Rising edge,?..."
|
|
endif
|
|
group.long 0x24++0x0b
|
|
line.long 0x00 "EDGLEVEL,Edge/Level Sensing Select Register"
|
|
bitfld.long 0x00 3. " EDGLEVEL3 ,Specifies the method to detect interrupt signal input" "Level,Edge"
|
|
bitfld.long 0x00 2. " EDGLEVEL2 ,Specifies the method to detect interrupt signal input" "Level,Edge"
|
|
bitfld.long 0x00 1. " EDGLEVEL1 ,Specifies the method to detect interrupt signal input" "Level,Edge"
|
|
bitfld.long 0x00 0. " EDGLEVEL0 ,Specifies the method to detect interrupt signal input" "Level,Edge"
|
|
line.long 0x04 "FILONOFF,Chattering Prevention ON/OFF Setting Register"
|
|
bitfld.long 0x04 3. " FILONOFF3 ,Turns on or off the chattering prevention circuit" "Off,On"
|
|
bitfld.long 0x04 2. " FILONOFF2 ,Turns on or off the chattering prevention circuit" "Off,On"
|
|
bitfld.long 0x04 1. " FILONOFF1 ,Turns on or off the chattering prevention circuit" "Off,On"
|
|
bitfld.long 0x04 0. " FILONOFF0 ,Turns on or off the chattering prevention circuit" "Off,On"
|
|
line.long 0x08 "THSCR,THS Control Register"
|
|
bitfld.long 0x08 12. " CPCTL ,Specifies the method to set the offset (CPTAP) of the comparator in the THS" "CPTAP3-0 bits,Automatically by hardware"
|
|
bitfld.long 0x08 8. " THIDLE ,Selects either the normal operating state or the idle state of the THS" "Normal,Idle"
|
|
bitfld.long 0x08 4.--7. " RFTAP[3:0] ,Sets an offset value (RFTAP) of the op amp in the THS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " CPTAP[3:0] ,Sets the offset value (CPTAP) of the comparator in the THS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "THSSR,THS Status Register"
|
|
bitfld.long 0x00 0.--5. " CTEMP[5:0] ,Indicates the current temperature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "INTCTLR,Interrupt Control Register "
|
|
bitfld.long 0x00 24.--29. " CTEMP3 ,Indicates the temperature that causes an INTDT3 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " CTEMP2 ,Indicates the temperature that causes an INTDT2 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. " CTEMP1 ,Indicates the temperature that causes an INTDT1 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. " CTEMP0 ,Indicates the temperature that causes an INTDT0 interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0xb
|
|
tree.end
|
|
tree "SYSC (System Controller)"
|
|
base ad:0xFFD85000
|
|
width 11.
|
|
tree "Common Registers"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "SYSCSR,SYSC Status Register"
|
|
bitfld.long 0x00 1. " PONENB ,SYSC is ready to accept power resume requests" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " POFFENB ,SYSC is ready to accept power shutoff requests" "Not ready,Ready"
|
|
line.long 0x04 "SYSCISR,Interrupt Status Register"
|
|
bitfld.long 0x04 24. " IMP ,Completion of the IMP-X3 power shutoff or power resume processing" "Not completed,Completed"
|
|
bitfld.long 0x04 21. " VDP ,Completion of the VDP power shutoff or power resume processing" "Not completed,Completed"
|
|
bitfld.long 0x04 20. " SGX ,Completion of the SGX power shutoff or power resume processing" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ARM3 ,Completion of the ARM core CPU3 power shutoff or power resume processing" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " ARM2 ,Completion of the ARM core CPU2 power shutoff or power resume processing" "Not completed,Completed"
|
|
bitfld.long 0x04 1. " ARM1 ,Completion of the ARM core CPU1 power shutoff or power resume processing" "Not completed,Completed"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "SYSCISCR,Interrupt status clear register"
|
|
bitfld.long 0x00 24. " IMP ,Clears the IMP bit in the interrupt status register" "No effect,Cleared"
|
|
bitfld.long 0x00 21. " VDP ,Clears the VDP bit in the interrupt status register" "No effect,Cleared"
|
|
bitfld.long 0x00 20. " SGX ,Clears the SGX bit in the interrupt status register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ARM3 ,Clears the ARM3 bit in the interrupt status register" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " ARM2 ,Clears the ARM2 bit in the interrupt status register" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " ARM1 ,Clears the ARM1 bit in the interrupt status register" "No effect,Cleared"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SYSCIER,Interrupt enable register"
|
|
bitfld.long 0x00 24. " IMP ,IMP-X3 power shutoff or power resume processing completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " VDP ,VDP1 power shutoff or power resume processing completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SGX ,SGX power shutoff or power resume processing completion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ARM3 ,Power shutoff or power resume processing for the ARM core CPU3 completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ARM2 ,Power shutoff or power resume processing for the ARM core CPU2 completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ARM1 ,Power shutoff or power resume processing for the ARM core CPU1 completion interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYSCIMR,Interrupt Mask Register"
|
|
bitfld.long 0x04 24. " IMP ,IMP-X3 power shutoff or power resume processing completion interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " VDP ,VDP1 power shutoff or power resume processing completion interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " SGX ,SGX power shutoff or power resume processing completion interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ARM3 ,Power shutoff or power resume processing for the ARM core CPU3 completion interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " ARM2 ,Power shutoff or power resume processing for the ARM core CPU2 completion interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " ARM1 ,Power shutoff or power resume processing for the ARM core CPU1 completion interrupt mask" "Not masked,Masked"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SYSCOFSR,External Event Request Status Register"
|
|
bitfld.long 0x00 11. " FIQ_ARM3 ,Power resume request due to an FIQ interrupt accepted by the ARM core CPU3" "Not accepted,Accepted"
|
|
bitfld.long 0x00 10. " FIQ_ARM2 ,Power resume request due to an FIQ interrupt accepted by the ARM core CPU2" "Not accepted,Accepted"
|
|
bitfld.long 0x00 9. " FIQ_ARM1 ,Power resume request due to an FIQ interrupt accepted by the ARM core CPU1" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_ARM3 ,Power resume request due to an IRQ interrupt accepted by the ARM core CPU3" "Not accepted,Accepted"
|
|
bitfld.long 0x00 6. " IRQ_ARM2 ,Power resume request due to an IRQ interrupt accepted by the ARM core CPU2" "Not accepted,Accepted"
|
|
bitfld.long 0x00 5. " IRQ_ARM1 ,Power resume request due to an IRQ interrupt accepted by the ARM core CPU1" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WFI_ARM3 ,Power resume request due to an WFI instruction execution accepted by the ARM core CPU3" "Not accepted,Accepted"
|
|
bitfld.long 0x00 2. " WFI_ARM2 ,Power resume request due to an WFI instruction execution accepted by the ARM core CPU2" "Not accepted,Accepted"
|
|
bitfld.long 0x00 1. " WFI_ARM1 ,Power resume request due to an WFI instruction execution accepted by the ARM core CPU1" "Not accepted,Accepted"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "SYSCOFSCR,External Event Request Status Clear Register"
|
|
bitfld.long 0x00 11. " FIQ_ARM3 ,Clears the FIQ_ARM3 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " FIQ_ARM2 ,Clears the FIQ_ARM2 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 9. " FIQ_ARM1 ,Clears the FIQ_ARM1 bit in the external event request status register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_ARM3 ,Clears the IRQ_ARM3 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 6. " IRQ_ARM2 ,Clears the IRQ_ARM2 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 5. " IRQ_ARM1 ,Clears the IRQ_ARM1 bit in the external event request status register" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WFI_ARM3 ,Clears the WFI_ARM3 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 2. " WFI_ARM2 ,Clears the WFI_ARM2 bit in the external event request status register" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " WFI_ARM1 ,Clears the WFI_ARM1 bit in the external event request status register" "No effect,Cleared"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SYSCOFSER,External Event Request Status Enable Register"
|
|
bitfld.long 0x00 11. " FIQ_ARM3 ,ARM core CPU3 FIQ interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " FIQ_ARM2 ,ARM core CPU2 FIQ interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " FIQ_ARM1 ,ARM core CPU1 FIQ interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_ARM3 ,ARM core CPU3 IRQ interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IRQ_ARM2 ,ARM core CPU2 IRQ interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRQ_ARM1 ,ARM core CPU1 IRQ interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " WFI_ARM3 ,ARM core CPU3 WFI external event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " WFI_ARM2 ,ARM core CPU2 WFI external event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WFI_ARM1 ,ARM core CPU1 WFI external event interrupt enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Power control Registers for ARM core"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PWRSR0,Power Status Register 0"
|
|
bitfld.long 0x00 7. " PWRUP_ARM3 ,Indicates the non-power-shutoff state of the ARM core CPU3" "No,Yes"
|
|
bitfld.long 0x00 6. " PWRUP_ARM2 ,Indicates the non-power-shutoff state of the ARM core CPU2" "No,Yes"
|
|
bitfld.long 0x00 5. " PWRUP_ARM1 ,Indicates the non-power-shutoff state of the ARM core CPU1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PWRDWN_ARM3 ,Indicates the power-shutoff state of the ARM core CPU3" "No,Yes"
|
|
bitfld.long 0x00 2. " PWRDWN_ARM2 ,Indicates the power-shutoff state of the ARM core CPU2" "No,Yes"
|
|
bitfld.long 0x00 1. " PWRDWN_ARM1 ,Indicates the power-shutoff state of the ARM core CPU1" "No,Yes"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "PWROFFCR0,Power Shutoff Control Register 0"
|
|
bitfld.long 0x00 3. " ARM3 ,Starts the power shutoff sequence for the ARM core CPU3" "No power shutoff,Power shutoff"
|
|
bitfld.long 0x00 2. " ARM2 ,Starts the power shutoff sequence for the ARM core CPU2" "No power shutoff,Power shutoff"
|
|
bitfld.long 0x00 1. " ARM1 ,Starts the power shutoff sequence for the ARM core CPU1" "No power shutoff,Power shutoff"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PWROFFSR0,Power Shutoff Status Register 0"
|
|
bitfld.long 0x00 3. " ARM3 ,Indicates the power shutoff sequence execution status for the ARM core CPU3" "Not executed,Executed"
|
|
bitfld.long 0x00 2. " ARM2 ,Indicates the power shutoff sequence execution status for the ARM core CPU2" "Not executed,Executed"
|
|
bitfld.long 0x00 1. " ARM1 ,Indicates the power shutoff sequence execution status for the ARM core CPU1" "Not executed,Executed"
|
|
wgroup.long 0x4c++0x03
|
|
line.long 0x00 "PWRONCR0,Power Resume Control Register 0"
|
|
bitfld.long 0x00 3. " ARM3 ,Starts the power resume sequence for the ARM core CPU3" "No power resume,Power resume"
|
|
bitfld.long 0x00 2. " ARM2 ,Starts the power resume sequence for the ARM core CPU2" "No power resume,Power resume"
|
|
bitfld.long 0x00 1. " ARM1 ,Starts the power resume sequence for the ARM core CPU1" "No power resume,Power resume"
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "PWRONSR0,Power resume status register 0"
|
|
bitfld.long 0x00 3. " ARM3 ,Indicates the power resume sequence execution status for the ARM core CPU3" "Not executed,Executed"
|
|
bitfld.long 0x00 2. " ARM2 ,Indicates the power resume sequence execution status for the ARM core CPU2" "Not executed,Executed"
|
|
bitfld.long 0x00 1. " ARM1 ,Indicates the power resume sequence execution status for the ARM core CPU1" "Not executed,Executed"
|
|
line.long 0x04 "PWRER0,Power Shutoff/Resume Error Register 0"
|
|
bitfld.long 0x04 3. " ARM3 ,Indicates whether a power shutoff or power resume request to the ARM core CPU3 was not accepted" "Accepted,Not accepted"
|
|
bitfld.long 0x04 2. " ARM2 ,Indicates whether a power shutoff or power resume request to the ARM core CPU2 was not accepted" "Accepted,Not accepted"
|
|
bitfld.long 0x04 1. " ARM1 ,Indicates whether a power shutoff or power resume request to the ARM core CPU1 was not accepted" "Accepted,Not accepted"
|
|
tree.end
|
|
tree.open "Power control Registers for other modules"
|
|
tree "SGX power control registers"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "PWRSR2,Power Status Register 2"
|
|
bitfld.long 0x00 4. " PWRUP ,Indicates the power non-shutoff status of SGX" "No,Yes"
|
|
bitfld.long 0x00 0. " PWRDWN ,Indicates the power shutoff status of a given module" "No,Yes"
|
|
wgroup.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "PWROFFCR2,Power Shutoff Control Register 2"
|
|
bitfld.long 0x00 0. " PWRDWN ,Starts the power shutoff sequence for the SGX" "Not started,Started"
|
|
rgroup.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "PWROFFSR2,Power Shutoff Status Register 2"
|
|
bitfld.long 0x00 0. " DWNSTATE ,Indicates the power shutoff sequence execution status for the SGX" "Not executed,Executed"
|
|
wgroup.long (0xC0+0x0c)++0x03
|
|
line.long 0x00 "PWRONCR2,Power Resume Control Register 2"
|
|
bitfld.long 0x00 0. " PWRUP ,Starts the power resume sequence for the module" "Not started,Started"
|
|
rgroup.long (0xC0+0x10)++0x07
|
|
line.long 0x00 "PWRONSR2,Power Resume Status Register 2"
|
|
bitfld.long 0x00 0. " UPSTATE ,Indicates the power resume sequence execution status for the SGX" "Not executed,Executed"
|
|
line.long 0x04 "PWRER2,Power Shutoff/Resume Error Register 2"
|
|
bitfld.long 0x04 0. " ERR ,Indicates whether a power shutoff or power resume request to the SGX was not accepted" "Accepted,Not accepted"
|
|
tree.end
|
|
tree "VDP1 power control registers"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PWRSR3,Power Status Register 3"
|
|
bitfld.long 0x00 4. " PWRUP ,Indicates the power non-shutoff status of VDP1" "No,Yes"
|
|
bitfld.long 0x00 0. " PWRDWN ,Indicates the power shutoff status of a given module" "No,Yes"
|
|
wgroup.long (0x100+0x04)++0x03
|
|
line.long 0x00 "PWROFFCR3,Power Shutoff Control Register 3"
|
|
bitfld.long 0x00 0. " PWRDWN ,Starts the power shutoff sequence for the VDP1" "Not started,Started"
|
|
rgroup.long (0x100+0x08)++0x03
|
|
line.long 0x00 "PWROFFSR3,Power Shutoff Status Register 3"
|
|
bitfld.long 0x00 0. " DWNSTATE ,Indicates the power shutoff sequence execution status for the VDP1" "Not executed,Executed"
|
|
wgroup.long (0x100+0x0c)++0x03
|
|
line.long 0x00 "PWRONCR3,Power Resume Control Register 3"
|
|
bitfld.long 0x00 0. " PWRUP ,Starts the power resume sequence for the module" "Not started,Started"
|
|
rgroup.long (0x100+0x10)++0x07
|
|
line.long 0x00 "PWRONSR3,Power Resume Status Register 3"
|
|
bitfld.long 0x00 0. " UPSTATE ,Indicates the power resume sequence execution status for the VDP1" "Not executed,Executed"
|
|
line.long 0x04 "PWRER3,Power Shutoff/Resume Error Register 3"
|
|
bitfld.long 0x04 0. " ERR ,Indicates whether a power shutoff or power resume request to the VDP1 was not accepted" "Accepted,Not accepted"
|
|
tree.end
|
|
tree "IMP-X3 power control registers"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "PWRSR4,Power Status Register 4"
|
|
bitfld.long 0x00 4. " PWRUP ,Indicates the power non-shutoff status of IMP-X3" "No,Yes"
|
|
bitfld.long 0x00 0. " PWRDWN ,Indicates the power shutoff status of a given module" "No,Yes"
|
|
wgroup.long (0x140+0x04)++0x03
|
|
line.long 0x00 "PWROFFCR4,Power Shutoff Control Register 4"
|
|
bitfld.long 0x00 0. " PWRDWN ,Starts the power shutoff sequence for the IMP-X3" "Not started,Started"
|
|
rgroup.long (0x140+0x08)++0x03
|
|
line.long 0x00 "PWROFFSR4,Power Shutoff Status Register 4"
|
|
bitfld.long 0x00 0. " DWNSTATE ,Indicates the power shutoff sequence execution status for the IMP-X3" "Not executed,Executed"
|
|
wgroup.long (0x140+0x0c)++0x03
|
|
line.long 0x00 "PWRONCR4,Power Resume Control Register 4"
|
|
bitfld.long 0x00 0. " PWRUP ,Starts the power resume sequence for the module" "Not started,Started"
|
|
rgroup.long (0x140+0x10)++0x07
|
|
line.long 0x00 "PWRONSR4,Power Resume Status Register 4"
|
|
bitfld.long 0x00 0. " UPSTATE ,Indicates the power resume sequence execution status for the IMP-X3" "Not executed,Executed"
|
|
line.long 0x04 "PWRER4,Power Shutoff/Resume Error Register 4"
|
|
bitfld.long 0x04 0. " ERR ,Indicates whether a power shutoff or power resume request to the IMP-X3 was not accepted" "Accepted,Not accepted"
|
|
tree.end
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.open "Coresight ICEReg"
|
|
tree "CPU access"
|
|
base ad:0xFE6CF000
|
|
width 17.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "ICEREGMDRSTCTL,ICEREGMDRSTCTL Register"
|
|
bitfld.long 0x00 15. " RSTRB_CPU3_DERSTZ ,Reset for NEON block in Cortex-A9 CPU3 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RSTRB_CPU2_DERSTZ ,Reset for NEON block in Cortex-A9 CPU2 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTRB_CPU1_DERSTZ ,Reset for NEON block in Cortex-A9 CPU1 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RSTRB_CPU0_DERSTZ ,Reset for NEON block in Cortex-A9 CPU0 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RSTRB_CPU3_CPURSTZ ,Reset for Cortex-A9 CPU3 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTRB_CPU2_CPURSTZ ,Reset for Cortex-A9 CPU2 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RSTRB_CPU1_CPURSTZ ,Reset for Cortex-A9 CPU1 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RSTRB_CPU0_CPURSTZ ,Reset for Cortex-A9 CPU0 (low-active)" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RSTRB_SYS_SYSRSTZ ,System Reset except for debug resources" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RSTRB_CPU_PORSTZ ,Reset for debug resources in the Cortex-A9 subsystem" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RSTRB_CPU_PRSTDBGZ ,Reset for Debug-APB in the Cortex-A9 subsystem" "No reset,Reset"
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textline " "
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bitfld.long 0x00 1. " RSTRB_CPU_SYSRSTZ ,Reset for the Cortex-A9 subsystem except for debug resources (low-active)" "No reset,Reset"
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line.long 0x04 "ICEREGJTTRCSEL,ICEREGJTTRCSEL Register"
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bitfld.long 0x04 25.--26. " TRCCK_DIV_SEL ,Trace Clock Divider Setting" "1/2 of CPU clock [500 MHz (HS)/400 MHz (LS)],1/3 of CPU clock [333 MHz (HS)/266 MHz (LS)],1/4 of CPU clock [250 MHz (HS)/200 MHz (LS)],1/8 of CPU clock [125 MHz (HS)/100 MHz (LS)]"
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textline " "
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bitfld.long 0x04 20. " TRCMUX_SEL ,Trace Output Selection Control" "Determined by PFC,Regardless of PFC"
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textline " "
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bitfld.long 0x04 18.--19. " TRACE_WIDTHSEL ,Determines how many pins are used for trace outputs" ",16 bits,8 bits,?..."
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group.long 0xFB0++0x03
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line.long 0x00 "ICEREGLOCKACCESS,ICEREGLOCKACCESS Register"
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width 0xb
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tree.end
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; tree "Debugger access"
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; base dbg:0x8000F000
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; %include rcarh1/icereg.ph DBG
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; tree.end
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tree.end
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textline ""
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