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27a5f79fcc6b8e95bb98cc32aa40ed94c496dc70
Work/Src/Gen4_R-Car_Trace32/2_Trunk/perstm32wb0.per
woody 6daf21a46d add
2026-06-16 12:20:14 +09:00

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; --------------------------------------------------------------------------------
; @Title: STM32WB0 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2025-05-19 KRZ
; @Manufacturer: STM - ST Microelectronics N.V.
; @Doc: Generated (TRACE32, build: 180057.), based on:
; STM32WB05.svd (Ver. 1.0), STM32WB06.svd (Ver. 1.0),
; STM32WB07.svd (Ver. 1.0), STM32WB09.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: STM32WB05*, STM32WB06*, STM32WB07*, STM32WB09*
; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perstm32wb0.per 19520 2025-05-19 15:21:13Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
elif (CORENAME()=="CORTEXM0+")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
else
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
endif
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (Analog to Digital Converter)"
base ad:0x41006000
rgroup.long 0x0++0x3
line.long 0x0 "VERSION_ID,VERSION_ID register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x0 0.--7. 1. "VERSION_ID,VERSION_ID[7:0]: version of the embedded IP."
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.byte 0x0 0.--7. 1. "VERSION_ID,version of the embedded IP."
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.byte 0x0 0.--7. 1. "VERSION_ID,version of the embedded IP."
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 0.--7. 1. "VERSION_ID,VERSION_ID[7:0]: version of the embedded IP."
newline
endif
group.long 0x4++0x7
line.long 0x0 "CONF,CONF register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 21.--23. "SAMPLE_RATE_MSB,SAMPLE_RATE_MSB: Sample Rate MSB" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 9.--10. "SAMPLE_RATE_LSB,SAMPLE_RATE_LSB: Sample Rate LSB" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 21.--23. "SAMPLE_RATE_MSB,SAMPLE_RATE_MSB: Sample Rate MSB" "0,1,2,3,4,5,6,7"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 20. "VBIAS_PRECH_FORCE,possibility to keep the VBIAS_PRECH enabled to deactivate the filter" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 20. "VBIAS_PRECH_FORCE,possibility to keep the VBIAS_PRECH enabled to deactivate the filter" "0,1"
newline
endif
bitfld.long 0x0 19. "ADC_CONT_1V2,ADC_CONT_1V2: select the input sampling method:" "0: sampling only at conversion start,1: sampling starts at the end of conversion"
newline
bitfld.long 0x0 18. "BIT_INVERT_DIFF,BIT_INVERT_DIFF: invert bit to bit the ADC data output (1's complement) when a differential" "0: no inversion,1: enable the inversion"
bitfld.long 0x0 17. "BIT_INVERT_SN,BIT_INVERT_SN: invert bit to bit the ADC data output (1's complement) when a single" "0: no inversion,1: enable the inversion"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 16. "OVR_DF_CFG,decimation overrun configuration" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 16. "OVR_DF_CFG,decimation overrun configuration" "0,1"
newline
endif
bitfld.long 0x0 15. "OVR_DS_CFG,OVR_DS_CFG: Down Sampler overrun configuration:" "0: the previous data is kept,1: the previous data is lost"
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 14. "DMA_DF_ENA,enable DMA mode for Decimation Filter data path" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 14. "DMA_DF_ENA,enable DMA mode for Decimation Filter data path" "0,1"
newline
endif
bitfld.long 0x0 13. "DMA_DS_ENA,DMA_DS_EN: enable the DMA mode for the Down Sampler data path:" "0: DMA mode is disabled,1: DMA mode is enabled"
newline
bitfld.long 0x0 11.--12. "SAMPLE_RATE,SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC):" "0,1,2,3"
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 9.--10. "SAMPLE_RATE_LSB,SAMPLE_RATE_LSB: Sample Rate LSB" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 7.--8. "OP_MODE,ADC mode selection (= data path selection)" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 7.--8. "OP_MODE,ADC mode selection (= data path selection)" "0,1,2,3"
newline
endif
bitfld.long 0x0 6. "SMPS_SYNCHRO_ENA,SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the" "0: SMPS synchronization is disabled for all ADC..,1: SMPS synchronization is enabled"
hexmask.long.byte 0x0 2.--5. 1. "SEQ_LEN,SEQ_LEN[3:0]: number of conversions in a regular sequence:"
newline
bitfld.long 0x0 1. "SEQUENCE,SEQUENCE: enable the sequence mode (active by default):" "0: sequence mode is disabled,1: sequence mode is enabled"
bitfld.long 0x0 0. "CONT,CONT: regular sequence runs continuously when ADC mode is enabled:" "0: enable the single conversion: when the sequence..,1: enable the continuous conversion: when the.."
line.long 0x4 "CTRL,CTRL register"
bitfld.long 0x4 5. "ADC_LDO_ENA,ADC_LDO_ENA: enable the LDO associated to the ADC block:" "0: disable the ADC LDO,1: enable the ADC LDO"
bitfld.long 0x4 4. "TEST_MODE,TEST_MODE: select the functional or the test mode of the ADC:" "0: functional mode,1: test mode"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 3. "DIG_AUD_MODE,enable the digital audio mode (the data path uses" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 3. "DIG_AUD_MODE,enable the digital audio mode (the data path uses" "0,1"
newline
endif
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 2. "STOP_OP_MODE,STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode Analog audio mode Full" "0: no effect,1: stop on-going ADC mode"
bitfld.long 0x4 1. "START_CONV,START_CONV (1): generate a start pulse to initiate an ADC conversion:" "0: no effect,1: start the ADC conversion"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 2. "STOP_OP_MODE,STOP_OP_MODE (1): stop the on-going OP_MODE (ADC mode Analog audio mode Full" "0: no effect,1: stop on-going ADC mode"
bitfld.long 0x4 1. "START_CONV,START_CONV (1): generate a start pulse to initiate an ADC conversion:" "0: no effect,1: start the ADC conversion"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 2. "STOP_OP_MOD,stop the on-going OP_MODE (ADC mode Analog audio mode Full" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 2. "STOP_OP_MOD,stop the on-going OP_MODE (ADC mode Analog audio mode Full" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 1. "START_CON,generate a start pulse to initiate an ADC conversion" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 1. "START_CON,generate a start pulse to initiate an ADC conversion" "0,1"
newline
endif
bitfld.long 0x4 0. "ADC_ON_OFF,ADC_ON_OFF:" "0: power off the ADC,1: power on the ADC"
sif (cpuis("STM32WB06*"))
group.long 0xC++0x7
line.long 0x0 "OCM_CTRL,Occasionnal mode control register"
bitfld.long 0x0 1. "OCM_ENA,start occasional conversion in analog audio and full" "0,1"
bitfld.long 0x0 0. "OCM_SRC,select the occasional conversion source" "0,1"
line.long 0x4 "PGA_CONF,PGA configuration register"
bitfld.long 0x4 4.--6. "PGA_BIAS,set the microphone bias voltage" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 0.--3. 1. "PGA_GAIN,from 6 to 30 dB"
group.long 0x18++0x3
line.long 0x0 "DF_CONF,Decimation filter configuration register"
bitfld.long 0x0 17. "DF_HALF_D_EN,half dynamic enable." "0,1"
bitfld.long 0x0 16. "DF_HPF_EN,high pass filter enable." "0,1"
newline
bitfld.long 0x0 15. "DF_MICROL_RN,left/right channel selection on digital microphone" "0,1"
hexmask.long.byte 0x0 11.--14. 1. "PDM_RATE,select the PDM clock rate."
newline
bitfld.long 0x0 10. "DF_O_S2U,select signed/unsigned format for data output" "0,1"
bitfld.long 0x0 9. "DF_I_U2S,select signed/unsigned format for input" "0,1"
newline
bitfld.long 0x0 8. "DF_ITP1P2,1.2 fractional interpolator enable" "0,1"
bitfld.long 0x0 7. "DF_CIC_DHF,CIC filter decimator half factor" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "DF_CIC_DEC_FACTOR"
rgroup.long 0x48++0x3
line.long 0x0 "DF_DATAOUT,Decimation filter Data output register"
hexmask.long.word 0x0 0.--15. 1. "DF_DATA,contain the converted data at the output of the"
newline
endif
sif (cpuis("STM32WB07*"))
group.long 0xC++0x3
line.long 0x0 "OCM_CTRL,Occasionnal mode control register"
bitfld.long 0x0 1. "OCM_ENA,start occasional conversion in analog audio and full" "0,1"
bitfld.long 0x0 0. "OCM_SRC,select the occasional conversion source" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
group.long 0x10++0x3
line.long 0x0 "PGA_CONF,PGA configuration register"
bitfld.long 0x0 4.--6. "PGA_BIAS,set the microphone bias voltage" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "PGA_GAIN,from 6 to 30 dB"
newline
endif
group.long 0x14++0x3
line.long 0x0 "SWITCH,SWITCH register"
bitfld.long 0x0 14.--15. "SE_VIN_7,SE_VIN_7[1:0]: input voltage for VINP[3]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 12.--13. "SE_VIN_6,SE_VIN_6[1:0]: input voltage for VINP[2]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 10.--11. "SE_VIN_5,SE_VIN_5[1:0]: input voltage for VINP[1]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 8.--9. "SE_VIN_4,SE_VIN_4[1:0]: input voltage for VINP[0]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 6.--7. "SE_VIN_3,SE_VIN_3[1:0]: input voltage for VINM[3] / VINP[3]-VINM[3]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 4.--5. "SE_VIN_2,SE_VIN_2[1:0]: input voltage for VINM[2] / VINP[2]-VINM[2]" "0: Vinput = 1,1: reserved,?,?"
newline
bitfld.long 0x0 2.--3. "SE_VIN_1,SE_VIN_1[1:0]: input voltage for VINM[1] / VINP[1]-VINM[1]" "0: Vinput = 1,1: reserved,?,?"
bitfld.long 0x0 0.--1. "SE_VIN_0,SE_VIN_0[1:0]: input voltage for VINM[0] / VINP[0]-VINM[0]" "0: Vinput = 1,1: reserved,?,?"
sif (cpuis("STM32WB07*"))
group.long 0x18++0x3
line.long 0x0 "DF_CONF,Decimation filter configuration register"
bitfld.long 0x0 17. "DF_HALF_D_EN,half dynamic enable." "0,1"
bitfld.long 0x0 16. "DF_HPF_EN,high pass filter enable." "0,1"
newline
bitfld.long 0x0 15. "DF_MICROL_RN,left/right channel selection on digital microphone" "0,1"
hexmask.long.byte 0x0 11.--14. 1. "PDM_RATE,select the PDM clock rate."
newline
bitfld.long 0x0 10. "DF_O_S2U,select signed/unsigned format for data output" "0,1"
bitfld.long 0x0 9. "DF_I_U2S,select signed/unsigned format for input" "0,1"
newline
bitfld.long 0x0 8. "DF_ITP1P2,1.2 fractional interpolator enable" "0,1"
bitfld.long 0x0 7. "DF_CIC_DHF,CIC filter decimator half factor" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "DF_CIC_DEC_FACTOR"
newline
endif
group.long 0x1C++0x27
line.long 0x0 "DS_CONF,DS_CONF register"
bitfld.long 0x0 3.--5. "DS_WIDTH,DS_WIDTH[2:0]: program the Down Sampler width of data output (DSDTATA)" "0: DS_DATA output on 12-bit,1: DS_DATA output on 13-bit,?,?,?,?,?,?"
bitfld.long 0x0 0.--2. "DS_RATIO,DS_RATIO[2:0]: program the Down Sampler ratio (N factor)" "0: ratio = 1,1: ratio = 2,?,?,?,?,?,?"
line.long 0x4 "SEQ_1,SEQ_1 register"
hexmask.long.byte 0x4 28.--31. 1. "SEQ7,SEQ7[3:0]: channel number code for 8th conversion of the sequence."
hexmask.long.byte 0x4 24.--27. 1. "SEQ6,SEQ6[3:0]: channel number code for 7th conversion of the sequence."
newline
hexmask.long.byte 0x4 20.--23. 1. "SEQ5,SEQ5[3:0]: channel number code for 6th conversion of the sequence."
hexmask.long.byte 0x4 16.--19. 1. "SEQ4,SEQ4[3:0]: channel number code for 5th conversion of the sequence."
newline
hexmask.long.byte 0x4 12.--15. 1. "SEQ3,SEQ3[3:0]: channel number code for 4th conversion of the sequence."
hexmask.long.byte 0x4 8.--11. 1. "SEQ2,SEQ2[3:0]: channel number code for 3rd conversion of the sequence."
newline
hexmask.long.byte 0x4 4.--7. 1. "SEQ1,SEQ1[3:0]: channel number code for second conversion of the sequence."
hexmask.long.byte 0x4 0.--3. 1. "SEQ0,SEQ0[3:0]: channel number code for first conversion of the sequence"
line.long 0x8 "SEQ_2,SEQ_2 register"
hexmask.long.byte 0x8 28.--31. 1. "SEQ15,SEQ15[3:0]: channel number code for 16th conversion of the sequence."
hexmask.long.byte 0x8 24.--27. 1. "SEQ14,SEQ14[3:0]: channel number code for 15th conversion of the sequence."
newline
hexmask.long.byte 0x8 20.--23. 1. "SEQ13,SEQ13[3:0]: channel number code for 14th conversion of the sequence."
hexmask.long.byte 0x8 16.--19. 1. "SEQ12,SEQ12[3:0]: channel number code for 13th conversion of the sequence."
newline
hexmask.long.byte 0x8 12.--15. 1. "SEQ11,SEQ11[3:0]: channel number code for 12th conversion of the sequence."
hexmask.long.byte 0x8 8.--11. 1. "SEQ10,SEQ10[3:0]: channel number code for 11th conversion of the sequence."
newline
hexmask.long.byte 0x8 4.--7. 1. "SEQ9,SEQ9[3:0]: channel number code for 10th conversion of the sequence."
hexmask.long.byte 0x8 0.--3. 1. "SEQ8,SEQ8[3:0]: channel number code for 9th conversion of the sequence"
line.long 0xC "COMP_1,COMP_1 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0xC 12.--19. 1. "OFFSET1,OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.byte 0xC 12.--18. 1. "OFFSET1,first calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.byte 0xC 12.--18. 1. "OFFSET1,first calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0xC 12.--19. 1. "OFFSET1,OFFSET1[7:0]: first calibration point: offset compensation[7:0] with sign"
newline
endif
hexmask.long.word 0xC 0.--11. 1. "GAIN1,GAIN1[11:0]: first calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x10 "COMP_2,COMP_2 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x10 12.--19. 1. "OFFSET2,OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.byte 0x10 12.--18. 1. "OFFSET2,second calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.byte 0x10 12.--18. 1. "OFFSET2,second calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x10 12.--19. 1. "OFFSET2,OFFSET2[7:0]: second calibration point: offset compensation[7:0] with sign"
newline
endif
hexmask.long.word 0x10 0.--11. 1. "GAIN2,GAIN2[11:0]: second calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x14 "COMP_3,COMP_3 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x14 12.--19. 1. "OFFSET3,OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.byte 0x14 12.--18. 1. "OFFSET3,third calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.byte 0x14 12.--18. 1. "OFFSET3,third calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x14 12.--19. 1. "OFFSET3,OFFSET3[7:0]: third calibration point: offset compensation[7:0] with sign"
newline
endif
hexmask.long.word 0x14 0.--11. 1. "GAIN3,GAIN3[11:0]: third calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x18 "COMP_4,COMP_4 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x18 12.--19. 1. "OFFSET4,OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.byte 0x18 12.--18. 1. "OFFSET4,fourth calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.byte 0x18 12.--18. 1. "OFFSET4,fourth calibration point: signed offset compensation[6:0]"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x18 12.--19. 1. "OFFSET4,OFFSET4[7:0]: fourth calibration point: offset compensation[7:0] with sign"
newline
endif
hexmask.long.word 0x18 0.--11. 1. "GAIN4,GAIN4[11:0]: fourth calibration point: gain AUXADC_GAIN_1V2[11:0]"
line.long 0x1C "COMP_SEL,COMP_SEL register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x1C 16.--17. "OFFSET_GAIN8,OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 14.--15. "OFFSET_GAIN7,OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 12.--13. "OFFSET_GAIN6,OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 10.--11. "OFFSET_GAIN5,OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 8.--9. "OFFSET_GAIN4,OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 6.--7. "OFFSET_GAIN3,OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 4.--5. "OFFSET_GAIN2,OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 2.--3. "OFFSET_GAIN1,OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 0.--1. "OFFSET_GAIN0,OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x1C 16.--17. "OFFSET_GAIN8,OFFSET_GAIN8[1:0]: gain / offset used in ADC differential mode with Vinput range = 3.6V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 14.--15. "OFFSET_GAIN7,OFFSET_GAIN7[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 12.--13. "OFFSET_GAIN6,OFFSET_GAIN6[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 10.--11. "OFFSET_GAIN5,OFFSET_GAIN5[1:0]: gain / offset used in ADC differential mode with Vinput range = 2.4V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 8.--9. "OFFSET_GAIN4,OFFSET_GAIN4[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 6.--7. "OFFSET_GAIN3,OFFSET_GAIN3[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 4.--5. "OFFSET_GAIN2,OFFSET_GAIN2[1:0]: gain / offset used in ADC differential mode with Vinput range = 1.2V:" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
bitfld.long 0x1C 2.--3. "OFFSET_GAIN1,OFFSET_GAIN1[1:0]: gain / offset used in ADC single positive mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
bitfld.long 0x1C 0.--1. "OFFSET_GAIN0,OFFSET_GAIN0[1:0]: gain / offset used in ADC single negative mode with Vinput range =" "0: OFFSET1 and GAIN1 from COMP_1,1: OFFSET2 and GAIN2 from COMP_2,?,?"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 16.--17. "GAIN_OFFSET8,gain / offset used in ADC differential mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 16.--17. "GAIN_OFFSET8,gain / offset used in ADC differential mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 14.--15. "GAIN_OFFSET7,gain / offset used in ADC single positive mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 14.--15. "GAIN_OFFSET7,gain / offset used in ADC single positive mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 12.--13. "GAIN_OFFSET6,gain / offset used in ADC single negative mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 12.--13. "GAIN_OFFSET6,gain / offset used in ADC single negative mode with Vinput range = 3.6V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 10.--11. "GAIN_OFFSET5,gain / offset used in ADC differential mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 10.--11. "GAIN_OFFSET5,gain / offset used in ADC differential mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 8.--9. "GAIN_OFFSET4,gain / offset used in ADC single positive mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 8.--9. "GAIN_OFFSET4,gain / offset used in ADC single positive mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 6.--7. "GAIN_OFFSET3,gain / offset used in ADC single negative mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 6.--7. "GAIN_OFFSET3,gain / offset used in ADC single negative mode with Vinput range = 2.4V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 4.--5. "GAIN_OFFSET2,gain / offset used in ADC differential mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 4.--5. "GAIN_OFFSET2,gain / offset used in ADC differential mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 2.--3. "GAIN_OFFSET1,gain / offset used in ADC single positive mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 2.--3. "GAIN_OFFSET1,gain / offset used in ADC single positive mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 0.--1. "GAIN_OFFSET0,gain / offset used in ADC single negative mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 0.--1. "GAIN_OFFSET0,gain / offset used in ADC single negative mode with Vinput range = 1.2V" "0,1,2,3"
newline
endif
line.long 0x20 "WD_TH,WD_TH register"
hexmask.long.word 0x20 16.--27. 1. "WD_HT,WD_HT[11:0]: analog watchdog high level threshold."
hexmask.long.word 0x20 0.--11. 1. "WD_LT,WD_LT[11:0]: analog watchdog low level threshold."
line.long 0x24 "WD_CONF,WD_CONF register"
hexmask.long.word 0x24 0.--15. 1. "AWD_CHX,AWD_CHX[15:0]: analog watchdog channel selection to define which input channel(s) need"
rgroup.long 0x44++0x3
line.long 0x0 "DS_DATAOUT,DS_DATAOUT register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0x0 0.--15. 1. "DS_DATA,DS_DATA[15:0]: contain the converted data at the output of the Down Sampler."
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x0 0.--15. 1. "DS_DATA,contain the converted data at the output of the Down Sampler"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x0 0.--15. 1. "DS_DATA,contain the converted data at the output of the Down Sampler"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.word 0x0 0.--15. 1. "DS_DATA,DS_DATA[15:0]: contain the converted data at the output of the Down Sampler."
newline
endif
sif (cpuis("STM32WB07*"))
rgroup.long 0x48++0x3
line.long 0x0 "DF_DATAOUT,Decimation filter Data output register"
hexmask.long.word 0x0 0.--15. 1. "DF_DATA,contain the converted data at the output of the"
newline
endif
group.long 0x4C++0x7
line.long 0x0 "IRQ_STATUS,IRQ_STATUS register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 7. "DF_OVRFL_IRQ,set to indicate the decimation filter is saturated." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 7. "DF_OVRFL_IRQ,set to indicate the decimation filter is saturated." "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 6. "OVR_DF_IRQ,set to indicate a decimation filter overrun (a data is lost)" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 6. "OVR_DF_IRQ,set to indicate a decimation filter overrun (a data is lost)" "0,1"
newline
endif
bitfld.long 0x0 5. "OVR_DS_IRQ,OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost)" "0: no effect,1: clear the interrupt"
bitfld.long 0x0 4. "AWD_IRQ,AWD_IRQ: set when an analog watchdog event occurs." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x0 3. "EOS_IRQ,EOS_IRQ: set when a sequence of conversion is completed." "0: no effect,1: clear the interrupt"
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 2. "EODF_IRQ,set when the decimation filter conversion is completed" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 2. "EODF_IRQ,set when the decimation filter conversion is completed" "0,1"
newline
endif
bitfld.long 0x0 1. "EODS_IRQ,EODS_IRQ: set when the Down Sampler conversion is completed." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x0 0. "EOC_IRQ,EOC_IRQ (Used in test mode only): set when the ADC conversion is completed." "0: no effect,1: clear the interrupt"
line.long 0x4 "IRQ_ENABLE,IRQ_ENABLE register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 7. "DF_OVRFL_IRQ_ENA,decimation filter saturation interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 7. "DF_OVRFL_IRQ_ENA,decimation filter saturation interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 6. "OVR_DF_IRQ_ENA,decimation filter overrun interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 6. "OVR_DF_IRQ_ENA,decimation filter overrun interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 5. "OVR_DS_IRQ,OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost)" "0: no effect,1: clear the interrupt"
bitfld.long 0x4 4. "AWD_IRQ,AWD_IRQ: set when an analog watchdog event occurs." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x4 3. "EOS_IRQ,EOS_IRQ: set when a sequence of conversion is completed." "0: no effect,1: clear the interrupt"
bitfld.long 0x4 1. "EODS_IRQ,EODS_IRQ: set when the Down Sampler conversion is completed." "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x4 0. "EOC_IRQ,EOC_IRQ (Used in test mode only): set when the ADC conversion is completed." "0: no effect,1: clear the interrupt"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 5. "OVR_DS_IRQ,OVR_DS_IRQ: set to indicate a Down Sampler overrun (at least one data is lost)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x4 4. "AWD_IRQ,AWD_IRQ: set when an analog watchdog event occurs." "0: no effect,1: clear the interrupt"
bitfld.long 0x4 3. "EOS_IRQ,EOS_IRQ: set when a sequence of conversion is completed." "0: no effect,1: clear the interrupt"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 5. "OVR_DS_IRQ_ENA,Down Sampler overrun interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 5. "OVR_DS_IRQ_ENA,Down Sampler overrun interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 4. "AWD_IRQ_ENA,analog watchdog interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 4. "AWD_IRQ_ENA,analog watchdog interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 3. "EOS_IRQ_ENA,End of regular sequence interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 3. "EOS_IRQ_ENA,End of regular sequence interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 2. "EODF_IRQ_ENA,End of conversion interrupt enable for the decimation filter output" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 2. "EODF_IRQ_ENA,End of conversion interrupt enable for the decimation filter output" "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 1. "EODS_IRQ,EODS_IRQ: set when the Down Sampler conversion is completed." "0: no effect,1: clear the interrupt"
bitfld.long 0x4 0. "EOC_IRQ,EOC_IRQ (Used in test mode only): set when the ADC conversion is completed." "0: no effect,1: clear the interrupt"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 1. "EODS_IRQ_ENA,End of conversion interrupt enable for the Down Sampler output" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 1. "EODS_IRQ_ENA,End of conversion interrupt enable for the Down Sampler output" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 0. "EOC_IRQ_ENA,(Used in test mode only): End of ADC conversion interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 0. "EOC_IRQ_ENA,(Used in test mode only): End of ADC conversion interrupt enable" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
group.long 0x54++0x3
line.long 0x0 "TIMER_CONF,Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it"
bitfld.long 0x0 16. "PRECH_DELAY_SEL,Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "VBIAS_PRECH_DELAY,define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration"
newline
hexmask.long.byte 0x0 0.--7. 1. "ADC_LDO_DELAY,define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion."
newline
endif
sif (cpuis("STM32WB07*"))
group.long 0x54++0x3
line.long 0x0 "TIMER_CONF,Time to add after an LDO Enable or ADC Enable to let the HW to be stable before using it"
bitfld.long 0x0 16. "PRECH_DELAY_SEL,Select the time step PD_STEP for the VBIAS_PRECH_DELAY timer" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "VBIAS_PRECH_DELAY,define the duration of a waiting time starting at rising edge of PGA_EN signal and corresponding to the VBIAS precharge duration"
newline
hexmask.long.byte 0x0 0.--7. 1. "ADC_LDO_DELAY,define the duration of a waiting time to be inserted between the ADC_LDO enable and the ADC ON to let time to the LDO to stabilize before starting a conversion."
newline
endif
tree.end
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "BLUE (Bluetooth LE Controller)"
base ad:0x60000000
group.long 0x4++0xF
line.long 0x0 "INTERRUPT1REG,INTERRUPT1REG register"
bitfld.long 0x0 31. "RCVOK,Receive data OK." "0,1"
bitfld.long 0x0 30. "RCVCRCERR,Receive data fail" "0,1"
newline
bitfld.long 0x0 29. "TIMECAPTURETRIG,A time has been captured in TIMERCAPTUREREG." "0,1"
bitfld.long 0x0 28. "RCVCMD,Received command" "0,1"
newline
bitfld.long 0x0 27. "RCVNOMD,Received low MD bit." "0,1"
bitfld.long 0x0 26. "RCVTIMEOUT,Receive timeout (no preamble found)." "0,1"
newline
bitfld.long 0x0 25. "DONE,Receive/Transmit done." "0,1"
bitfld.long 0x0 24. "TXOK,Previous transmitted packet received OK by the peer device." "0,1"
newline
bitfld.long 0x0 23. "CONFIGERROR,Data pointer configuration error." "0,1"
bitfld.long 0x0 22. "ACTIVE2ERROR,Active2 Radio state error." "0,1"
newline
bitfld.long 0x0 21. "TXRXSKIP,Transmission/Reception skip." "0,1"
bitfld.long 0x0 19. "SEMATIMEOUTERROR,Semaphore timeout error" "0,1"
newline
bitfld.long 0x0 18. "RCVLENGTHERROR,Receive length error." "0,1"
bitfld.long 0x0 16. "NOACTIVELERROR,GlobalStatMach." "0,1"
newline
bitfld.long 0x0 15. "TXDATAREADYERROR,Transmit data pack not ready error" "0,1"
bitfld.long 0x0 14. "ALLTABLEREADYERROR,All RAM Table not ready on time." "0,1"
newline
bitfld.long 0x0 13. "ENCERROR,Encryption error on reception." "0,1"
bitfld.long 0x0 12. "TXERROR_4,Transmission error 4: a CTE issue occurred." "0,1"
newline
bitfld.long 0x0 11. "TXERROR_3,Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state." "0,1"
bitfld.long 0x0 10. "TXERROR_2,Transmission error 2: channel index is greater than 39." "?,?"
newline
bitfld.long 0x0 9. "TXERROR_1,Transmission error 1: a TX skip happened during an on-going transmission." "0,1"
bitfld.long 0x0 8. "TXERROR_0,Transmission error 0: transmit block missing data error." "0,1"
newline
bitfld.long 0x0 7. "SEQDONE,Sequencer end of task." "0,1"
bitfld.long 0x0 5. "RXOVERFLOWERROR,Receive Overflow error." "0,1"
newline
bitfld.long 0x0 4. "ADDPOINTERROR,Address Pointer Error." "0,1"
line.long 0x4 "INTERRUPT2REG,INTERRUPT2REG register"
bitfld.long 0x4 1. "AESLEPRIVINT,AES LE privacy engine." "0,1"
bitfld.long 0x4 0. "AESMANENCINT,AES manual encryption." "0,1"
line.long 0x8 "TIMEOUTDESTREG,TIMEOUTDESTREG register"
bitfld.long 0x8 0.--1. "DESTINATION,Timeout timer Destination" "0,1,2,3"
line.long 0xC "TIMEOUTREG,TIMEOUTREG register"
hexmask.long 0xC 0.--31. 1. "TIMEOUT,Timer1 or Timer2 Timeout value (depending on Destination register)"
rgroup.long 0x14++0x3
line.long 0x0 "TIMERCAPTUREREG,TIMERCAPTUREREG register"
hexmask.long 0x0 0.--31. 1. "TIMERCAPTURE,Interpolated absolute time capture register"
wgroup.long 0x18++0x3
line.long 0x0 "CMDREG,CMDREG register"
bitfld.long 0x0 3. "CLEARSEMAREQ,Semaphore Clear command." "0,1"
bitfld.long 0x0 0. "TXRXSKIP,Transmission/Reception skip command." "0,1"
rgroup.long 0x1C++0xB
line.long 0x0 "STATUSREG,STATUSREG register"
bitfld.long 0x0 31. "RCVOK,Receive data OK status" "0,1"
bitfld.long 0x0 30. "RCVCRCERR,Receive data fail (CRC error or invalid CI field) status." "0,1"
newline
bitfld.long 0x0 29. "TIMECAPTURETRIG,indicates a time has been captured in TIMERCAPTUREREG when set." "0,1"
bitfld.long 0x0 28. "RCVCMD,Received command status (valid only on Data Physical Channel PDU reception)." "0,1"
newline
bitfld.long 0x0 27. "RCVNOMD,Received MD bit status (valid only on Data Physical Channel PDU reception)" "0,1"
bitfld.long 0x0 26. "RCVTIMEOUT,Receive timeout status (no access address found)" "0,1"
newline
bitfld.long 0x0 25. "DONE,Receive/Transmit done status." "0,1"
bitfld.long 0x0 24. "TXOK,Previous transmitted packet received OK by the peer device status." "0,1"
newline
bitfld.long 0x0 23. "CONFIGERROR,Data pointer configuration error status" "0,1"
bitfld.long 0x0 22. "ACTIVE2ERROR,Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step." "0,1"
newline
bitfld.long 0x0 21. "TXRXSKIP,Transmission/Reception skip status." "0,1"
bitfld.long 0x0 19. "SEMATIMEOUTERROR,Semaphore timeout error status" "0,1"
newline
bitfld.long 0x0 18. "RCVLENGTHERROR,Receive length error status" "0,1"
bitfld.long 0x0 16. "NOACTIVELERROR,GlobalStatMach." "0,1"
newline
bitfld.long 0x0 15. "TXDATAREADYERROR,Transmit data pack not ready status." "0,1"
bitfld.long 0x0 14. "ALLTABLEREADYERROR,All RAM Table not ready status" "0,1"
newline
bitfld.long 0x0 13. "ENCERROR,Encryption error on receive status" "0,1"
bitfld.long 0x0 12. "TXERROR_4,Transmission error 4 status" "0,1"
newline
bitfld.long 0x0 11. "TXERROR_3,Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach." "0,1"
bitfld.long 0x0 10. "TXERROR_2,Transmission error 2 status." "0,1"
newline
bitfld.long 0x0 9. "TXERROR_1,Transmission error 1 status" "0,1"
bitfld.long 0x0 8. "TXERROR_0,Transmission error 0 status: Transmit block missing data error." "0,1"
newline
bitfld.long 0x0 7. "SEQDONE,Sequencer end of task status." "0,1"
bitfld.long 0x0 6. "PREVTRANSMIT,Previous event was a Transmission (1) or Reception (0) status" "0,1"
newline
bitfld.long 0x0 5. "RXOVERFLOWERROR,AHB arbiter is full and there is no more storage capability available in RX datapath" "0,1"
bitfld.long 0x0 4. "ADDPOINTERROR,Address Pointer Error status" "0,1"
newline
bitfld.long 0x0 3. "NOTSUPPORTED_FUNCTION,indicates the SW requests an unsupported feature." "0,1"
bitfld.long 0x0 0. "AESONFLYBUSY,AES on the fligh encryption busy status" "0,1"
line.long 0x4 "INTERRUPT1ENABLEREG,INTERRUPT1ENABLEREG register"
bitfld.long 0x4 31. "RCVOK,Receive data OK enable interruption" "0,1"
bitfld.long 0x4 30. "RCVCRCERR,Receive data fail enable interruption" "0,1"
newline
bitfld.long 0x4 29. "TIMECAPTURETRIG,TimerCaptureReg time capture enable interruption" "0,1"
bitfld.long 0x4 28. "RCVCMD,Received command enable interruption" "0,1"
newline
bitfld.long 0x4 27. "RCVNOMD,Received MD bit embedded in the PDU data packet header was zero enable interruption" "0,1"
bitfld.long 0x4 26. "RCVTIMEOUT,Receive timeout enable interruption (no preamble found)" "0,1"
newline
bitfld.long 0x4 25. "DONE,Receive/Transmit done interruption" "0,1"
bitfld.long 0x4 24. "TXOK,Previous transmitted packet received OK enable interruption" "0,1"
newline
bitfld.long 0x4 23. "CONFIGERROR,Data pointer configuration error enable interruption" "0,1"
bitfld.long 0x4 22. "ACTIVE2ERROR,Active2 Radio state error enable interruption" "0,1"
newline
bitfld.long 0x4 21. "TXRXSKIP,Transmission/Reception skip enable interruption" "0,1"
bitfld.long 0x4 19. "SEMATIMEOUTERROR,Semaphore timeout error enable interruption" "0,1"
newline
bitfld.long 0x4 18. "RCVLENGTHERROR,Receive length error enable interruption" "0,1"
bitfld.long 0x4 16. "NOACTIVELERROR,active bit error enable interruption" "0,1"
newline
bitfld.long 0x4 15. "TXDATAREADYERROR,Transmit data pack not ready enable interruption" "0,1"
bitfld.long 0x4 14. "ALLTABLEREADYERROR,All RAM Table not ready enable interruption" "0,1"
newline
bitfld.long 0x4 13. "ENCERROR,Encryption error on receive enable interruption" "0,1"
bitfld.long 0x4 12. "TXERROR_4,Transmission error 4 enable interruption" "0,1"
newline
bitfld.long 0x4 11. "TXERROR_3,Transmission error 3 enable interruption" "0,1"
bitfld.long 0x4 10. "TXERROR_2,Transmission error 2 enable interruption" "0,1"
newline
bitfld.long 0x4 9. "TXERROR_1,Transmission error 1 enable interruption" "0,1"
bitfld.long 0x4 8. "TXERROR_0,Transmission error 0 enable interruption" "0,1"
newline
bitfld.long 0x4 7. "SEQDONE,Sequencer end of task enable interruption" "0,1"
bitfld.long 0x4 5. "RXOVERFLOWERROR,Rx Overflow Error enable interruption" "0,1"
newline
bitfld.long 0x4 4. "ADDPOINTERROR,Address Pointer Error enable interruption" "0,1"
line.long 0x8 "INTERRUPT1LATENCYREG,INTERRUPT1LATENCYREG register"
hexmask.long.byte 0x8 0.--7. 1. "INTERRUPT1LATENCY,relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence."
group.long 0x28++0x1F
line.long 0x0 "MANAESKEY0REG,MANAESKEY0REG register"
hexmask.long 0x0 0.--31. 1. "MANAESKEY_31_0,Manual mode AES key"
line.long 0x4 "MANAESKEY1REG,MANAESKEY1REG register"
hexmask.long 0x4 0.--31. 1. "MANAESKEY_63_32,Manual mode AES key"
line.long 0x8 "MANAESKEY2REG,MANAESKEY2REG register"
hexmask.long 0x8 0.--31. 1. "MANAESKEY_95_64,Manual mode AES key"
line.long 0xC "MANAESKEY3REG,MANAESKEY3REG register"
hexmask.long 0xC 0.--31. 1. "MANAESKEY_127_96,Manual mode AES key"
line.long 0x10 "MANAESCLEARTEXT0REG,MANAESCLEARTEXT0REG register"
hexmask.long 0x10 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x14 "MANAESCLEARTEXT1REG,MANAESCLEARTEXT1REG register"
hexmask.long 0x14 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x18 "MANAESCLEARTEXT2REG,MANAESCLEARTEXT2REG register"
hexmask.long 0x18 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x1C "MANAESCLEARTEXT3REG,MANAESCLEARTEXT3REG register"
hexmask.long 0x1C 0.--31. 1. "AES,Manual Aes Clear Text"
rgroup.long 0x48++0xF
line.long 0x0 "MANAESCIPHERTEXT0REG,MANAESCIPHERTEXT0REG register"
hexmask.long 0x0 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0x4 "MANAESCIPHERTEXT1REG,MANAESCIPHERTEXT1REG register"
hexmask.long 0x4 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0x8 "MANAESCIPHERTEXT2REG,MANAESCIPHERTEXT2REG register"
hexmask.long 0x8 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0xC "MANAESCIPHERTEXT3REG,MANAESCIPHERTEXT3REG register"
hexmask.long 0xC 0.--31. 1. "AES,Manual AES Cipher Text"
group.long 0x58++0x3
line.long 0x0 "MANAESCMDREG,MANAESCMDREG register"
bitfld.long 0x0 1. "INTENA,AES Manual encryption interrupt enable on Interrupt2Reg" "0,1"
bitfld.long 0x0 0. "START,AES Manual encryption Start command." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "MANAESSTATREG,MANAESSTATREG register"
bitfld.long 0x0 0. "BUSY,AES manual encryption busy status" "0,1"
group.long 0x60++0xF
line.long 0x0 "AESLEPRIVPOINTERREG,AESLEPRIVPOINTERREG register"
hexmask.long.tbyte 0x0 0.--23. 1. "POINTER,AES Le privacy pointer"
line.long 0x4 "AESLEPRIVHASHREG,AESLEPRIVHASHREG register"
hexmask.long.tbyte 0x4 0.--23. 1. "HASH,AES Le privacy Reference Hash"
line.long 0x8 "AESLEPRIVPRANDREG,AESLEPRIVPRANDREG register"
hexmask.long.tbyte 0x8 0.--23. 1. "PRAND,AES Le privacy Prand"
line.long 0xC "AESLEPRIVCMDREG,AESLEPRIVCMDREG register"
hexmask.long.byte 0xC 2.--9. 1. "NBKEYS,AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list."
bitfld.long 0xC 1. "INTENA,AES Le privacy interrupt enable on Interrupt2Reg" "0,1"
newline
bitfld.long 0xC 0. "START,AES Le privacy Start command." "0,1"
rgroup.long 0x70++0x3
line.long 0x0 "AESLEPRIVSTATREG,AESLEPRIVSTATREG register"
hexmask.long.byte 0x0 2.--9. 1. "KEYFNDINDEX,AES Le privacy index of the key found in the resolution key list."
bitfld.long 0x0 1. "KEYFND,AES Le privacy key finding status" "0,1"
newline
bitfld.long 0x0 0. "BUSY,AES Le privacy busy status" "0,1"
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
group.long 0x74++0x3
line.long 0x0 "DEBUGCMDREG,DebugCmd register"
hexmask.long.byte 0x0 16.--19. 1. "AESDEBUGMODE,AESDEBUGMODE"
hexmask.long.byte 0x0 2.--5. 1. "SEQDEBUGBUSSEL,SEQDEBUGBUSSEL"
newline
bitfld.long 0x0 1. "SEQDEBUGMODE,SEQDEBUGMODE" "0,1"
bitfld.long 0x0 0. "CLEARDEBUGINT,CLEARDEBUGINT" "0,1"
rgroup.long 0x78++0x3
line.long 0x0 "DEBUGSTATUSREG,DebugStatus register"
bitfld.long 0x0 19. "AESDBG_3,AESDBG_3" "0,1"
bitfld.long 0x0 18. "AESDBG_2,AESDBG_2" "0,1"
newline
bitfld.long 0x0 17. "AESDBG_1,AESDBG_1" "0,1"
bitfld.long 0x0 16. "AESDBG_0,AESDBG_0" "0,1"
newline
hexmask.long.byte 0x0 0.--6. 1. "DEBUGSTATUSREG,DEBUGSTATUSREG"
newline
endif
sif (cpuis("STM32WB09*"))
rgroup.long 0x7C++0x3
line.long 0x0 "STATUS2REG,STATUS2REG register"
bitfld.long 0x0 31. "ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR,AHB access error flag." "0,1"
bitfld.long 0x0 30. "ANTENNASWITCHINGPATTERNACCESSERROR,timing error flag related to Antenna Pattern not read on-time." "0,1"
newline
bitfld.long 0x0 29. "IQSAMPLESMISSINGERROR,IQ sample internal buffer overflow error flag." "0,1"
hexmask.long.byte 0x0 1.--7. 1. "IQSAMPLESNUMBER,indicate the number of IQ samples stored in the RAM buffer addressed by StatMach."
newline
bitfld.long 0x0 0. "IQSAMPLESREADY,indicates if IQ samples have been received on the last reception." "0,1"
newline
endif
tree.end
endif
sif (cpuis("STM32WB05*"))
tree "BLUE_REG (Bluetooth LE Controller)"
base ad:0x60000000
group.long 0x4++0xF
line.long 0x0 "INTERRUPT1REG,INTERRUPT1REG register"
bitfld.long 0x0 31. "RCVOK,Receive data OK." "0,1"
newline
bitfld.long 0x0 30. "RCVCRCERR,Receive data fail" "0,1"
newline
bitfld.long 0x0 29. "TIMECAPTURETRIG,A time has been captured in TIMERCAPTUREREG." "0,1"
newline
bitfld.long 0x0 28. "RCVCMD,Received command" "0,1"
newline
bitfld.long 0x0 27. "RCVNOMD,Received low MD bit." "0,1"
newline
bitfld.long 0x0 26. "RCVTIMEOUT,Receive timeout (no preamble found)." "0,1"
newline
bitfld.long 0x0 25. "DONE,Receive/Transmit done." "0,1"
newline
bitfld.long 0x0 24. "TXOK,Previous transmitted packet received OK by the peer device." "0,1"
newline
bitfld.long 0x0 23. "CONFIGERROR,Data pointer configuration error." "0,1"
newline
bitfld.long 0x0 22. "ACTIVE2ERROR,Active2 Radio state error." "0,1"
newline
bitfld.long 0x0 21. "TXRXSKIP,Transmission/Reception skip." "0,1"
newline
bitfld.long 0x0 19. "SEMATIMEOUTERROR,Semaphore timeout error" "0,1"
newline
bitfld.long 0x0 18. "RCVLENGTHERROR,Receive length error." "0,1"
newline
bitfld.long 0x0 16. "NOACTIVELERROR,GlobalStatMach." "0,1"
newline
bitfld.long 0x0 15. "TXDATAREADYERROR,Transmit data pack not ready error" "0,1"
newline
bitfld.long 0x0 14. "ALLTABLEREADYERROR,All RAM Table not ready on time." "0,1"
newline
bitfld.long 0x0 13. "ENCERROR,Encryption error on reception." "0,1"
newline
bitfld.long 0x0 12. "TXERROR_4,Transmission error 4: a CTE issue occurred." "0,1"
newline
bitfld.long 0x0 11. "TXERROR_3,Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state." "0,1"
newline
bitfld.long 0x0 10. "TXERROR_2,Transmission error 2: channel index is greater than 39." "?,?"
newline
bitfld.long 0x0 9. "TXERROR_1,Transmission error 1: a TX skip happened during an on-going transmission." "?,1: a TX skip happened during an on-going transmission"
newline
bitfld.long 0x0 8. "TXERROR_0,Transmission error 0: transmit block missing data error." "0: transmit block missing data error,?"
newline
bitfld.long 0x0 7. "SEQDONE,Sequencer end of task." "0,1"
newline
bitfld.long 0x0 5. "RXOVERFLOWERROR,Receive Overflow error." "0,1"
newline
bitfld.long 0x0 4. "ADDPOINTERROR,Address Pointer Error." "0,1"
line.long 0x4 "INTERRUPT2REG,INTERRUPT2REG register"
bitfld.long 0x4 1. "AESLEPRIVINT,AES LE privacy engine." "0,1"
newline
bitfld.long 0x4 0. "AESMANENCINT,AES manual encryption." "0,1"
line.long 0x8 "TIMEOUTDESTREG,TIMEOUTDESTREG register"
bitfld.long 0x8 0.--1. "DESTINATION,Timeout timer Destination" "0,1,2,3"
line.long 0xC "TIMEOUTREG,TIMEOUTREG register"
hexmask.long 0xC 0.--31. 1. "TIMEOUT,Timer1 or Timer2 Timeout value (depending on Destination register)"
rgroup.long 0x14++0x3
line.long 0x0 "TIMERCAPTUREREG,TIMERCAPTUREREG register"
hexmask.long 0x0 0.--31. 1. "TIMERCAPTURE,Interpolated absolute time capture register"
wgroup.long 0x18++0x3
line.long 0x0 "CMDREG,CMDREG register"
bitfld.long 0x0 3. "CLEARSEMAREQ,Semaphore Clear command." "0,1"
newline
bitfld.long 0x0 0. "TXRXSKIP,Transmission/Reception skip command." "0,1"
rgroup.long 0x1C++0xB
line.long 0x0 "STATUSREG,STATUSREG register"
bitfld.long 0x0 31. "RCVOK,Receive data OK status" "0,1"
newline
bitfld.long 0x0 30. "RCVCRCERR,Receive data fail (CRC error or invalid CI field) status." "0,1"
newline
bitfld.long 0x0 29. "TIMECAPTURETRIG,indicates a time has been captured in TIMERCAPTUREREG when set." "0,1"
newline
bitfld.long 0x0 28. "RCVCMD,Received command status (valid only on Data Physical Channel PDU reception)." "0,1"
newline
bitfld.long 0x0 27. "RCVNOMD,Received MD bit status (valid only on Data Physical Channel PDU reception)" "0,1"
newline
bitfld.long 0x0 26. "RCVTIMEOUT,Receive timeout status (no access address found)" "0,1"
newline
bitfld.long 0x0 25. "DONE,Receive/Transmit done status." "0,1"
newline
bitfld.long 0x0 24. "TXOK,Previous transmitted packet received OK by the peer device status." "0,1"
newline
bitfld.long 0x0 23. "CONFIGERROR,Data pointer configuration error status" "0,1"
newline
bitfld.long 0x0 22. "ACTIVE2ERROR,Indicates the Radio FSM was not in ACTIVE2 state when the Sequencer reaches the end of 1st INIT step." "0,1"
newline
bitfld.long 0x0 21. "TXRXSKIP,Transmission/Reception skip status." "0,1"
newline
bitfld.long 0x0 19. "SEMATIMEOUTERROR,Semaphore timeout error status" "0,1"
newline
bitfld.long 0x0 18. "RCVLENGTHERROR,Receive length error status" "0,1"
newline
bitfld.long 0x0 16. "NOACTIVELERROR,GlobalStatMach." "0,1"
newline
bitfld.long 0x0 15. "TXDATAREADYERROR,Transmit data pack not ready status." "0,1"
newline
bitfld.long 0x0 14. "ALLTABLEREADYERROR,All RAM Table not ready status" "0,1"
newline
bitfld.long 0x0 13. "ENCERROR,Encryption error on receive status" "0,1"
newline
bitfld.long 0x0 12. "TXERROR_4,Transmission error 4 status" "0,1"
newline
bitfld.long 0x0 11. "TXERROR_3,Transmission error 3: error while waiting for the confirmation the Radio FSM is in TX state (timeout defined in GlobalStatMach." "0,1"
newline
bitfld.long 0x0 10. "TXERROR_2,Transmission error 2 status." "0,1"
newline
bitfld.long 0x0 9. "TXERROR_1,Transmission error 1 status" "0,1"
newline
bitfld.long 0x0 8. "TXERROR_0,Transmission error 0 status: Transmit block missing data error." "0,1"
newline
bitfld.long 0x0 7. "SEQDONE,Sequencer end of task status." "0,1"
newline
bitfld.long 0x0 6. "PREVTRANSMIT,Previous event was a Transmission (1) or Reception (0) status" "0,1"
newline
bitfld.long 0x0 5. "RXOVERFLOWERROR,AHB arbiter is full and there is no more storage capability available in RX datapath" "0,1"
newline
bitfld.long 0x0 4. "ADDPOINTERROR,Address Pointer Error status" "0,1"
newline
bitfld.long 0x0 3. "NOTSUPPORTED_FUNCTION,indicates the SW requests an unsupported feature." "0,1"
newline
bitfld.long 0x0 0. "AESONFLYBUSY,AES on the fligh encryption busy status" "0,1"
line.long 0x4 "INTERRUPT1ENABLEREG,INTERRUPT1ENABLEREG register"
bitfld.long 0x4 31. "RCVOK,Receive data OK enable interruption" "0,1"
newline
bitfld.long 0x4 30. "RCVCRCERR,Receive data fail enable interruption" "0,1"
newline
bitfld.long 0x4 29. "TIMECAPTURETRIG,TimerCaptureReg time capture enable interruption" "0,1"
newline
bitfld.long 0x4 28. "RCVCMD,Received command enable interruption" "0,1"
newline
bitfld.long 0x4 27. "RCVNOMD,Received MD bit embedded in the PDU data packet header was zero enable interruption" "0,1"
newline
bitfld.long 0x4 26. "RCVTIMEOUT,Receive timeout enable interruption (no preamble found)" "0,1"
newline
bitfld.long 0x4 25. "DONE,Receive/Transmit done interruption" "0,1"
newline
bitfld.long 0x4 24. "TXOK,Previous transmitted packet received OK enable interruption" "0,1"
newline
bitfld.long 0x4 23. "CONFIGERROR,Data pointer configuration error enable interruption" "0,1"
newline
bitfld.long 0x4 22. "ACTIVE2ERROR,Active2 Radio state error enable interruption" "0,1"
newline
bitfld.long 0x4 21. "TXRXSKIP,Transmission/Reception skip enable interruption" "0,1"
newline
bitfld.long 0x4 19. "SEMATIMEOUTERROR,Semaphore timeout error enable interruption" "0,1"
newline
bitfld.long 0x4 18. "RCVLENGTHERROR,Receive length error enable interruption" "0,1"
newline
bitfld.long 0x4 16. "NOACTIVELERROR,active bit error enable interruption" "0,1"
newline
bitfld.long 0x4 15. "TXDATAREADYERROR,Transmit data pack not ready enable interruption" "0,1"
newline
bitfld.long 0x4 14. "ALLTABLEREADYERROR,All RAM Table not ready enable interruption" "0,1"
newline
bitfld.long 0x4 13. "ENCERROR,Encryption error on receive enable interruption" "0,1"
newline
bitfld.long 0x4 12. "TXERROR_4,Transmission error 4 enable interruption" "0,1"
newline
bitfld.long 0x4 11. "TXERROR_3,Transmission error 3 enable interruption" "0,1"
newline
bitfld.long 0x4 10. "TXERROR_2,Transmission error 2 enable interruption" "0,1"
newline
bitfld.long 0x4 9. "TXERROR_1,Transmission error 1 enable interruption" "0,1"
newline
bitfld.long 0x4 8. "TXERROR_0,Transmission error 0 enable interruption" "0,1"
newline
bitfld.long 0x4 7. "SEQDONE,Sequencer end of task enable interruption" "0,1"
newline
bitfld.long 0x4 5. "RXOVERFLOWERROR,Rx Overflow Error enable interruption" "0,1"
newline
bitfld.long 0x4 4. "ADDPOINTERROR,Address Pointer Error enable interruption" "0,1"
line.long 0x8 "INTERRUPT1LATENCYREG,INTERRUPT1LATENCYREG register"
hexmask.long.byte 0x8 0.--7. 1. "INTERRUPT1LATENCY,relative time counter started on irq_BLE_int1 (BLE_TXRX) occurrence."
group.long 0x28++0x1F
line.long 0x0 "MANAESKEY0REG,MANAESKEY0REG register"
hexmask.long 0x0 0.--31. 1. "MANAESKEY_31_0,Manual mode AES key"
line.long 0x4 "MANAESKEY1REG,MANAESKEY1REG register"
hexmask.long 0x4 0.--31. 1. "MANAESKEY_63_32,Manual mode AES key"
line.long 0x8 "MANAESKEY2REG,MANAESKEY2REG register"
hexmask.long 0x8 0.--31. 1. "MANAESKEY_95_64,Manual mode AES key"
line.long 0xC "MANAESKEY3REG,MANAESKEY3REG register"
hexmask.long 0xC 0.--31. 1. "MANAESKEY_127_96,Manual mode AES key"
line.long 0x10 "MANAESCLEARTEXT0REG,MANAESCLEARTEXT0REG register"
hexmask.long 0x10 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x14 "MANAESCLEARTEXT1REG,MANAESCLEARTEXT1REG register"
hexmask.long 0x14 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x18 "MANAESCLEARTEXT2REG,MANAESCLEARTEXT2REG register"
hexmask.long 0x18 0.--31. 1. "AES,Manual Aes Clear Text"
line.long 0x1C "MANAESCLEARTEXT3REG,MANAESCLEARTEXT3REG register"
hexmask.long 0x1C 0.--31. 1. "AES,Manual Aes Clear Text"
rgroup.long 0x48++0xF
line.long 0x0 "MANAESCIPHERTEXT0REG,MANAESCIPHERTEXT0REG register"
hexmask.long 0x0 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0x4 "MANAESCIPHERTEXT1REG,MANAESCIPHERTEXT1REG register"
hexmask.long 0x4 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0x8 "MANAESCIPHERTEXT2REG,MANAESCIPHERTEXT2REG register"
hexmask.long 0x8 0.--31. 1. "AES,Manual AES Cipher Text"
line.long 0xC "MANAESCIPHERTEXT3REG,MANAESCIPHERTEXT3REG register"
hexmask.long 0xC 0.--31. 1. "AES,Manual AES Cipher Text"
group.long 0x58++0x3
line.long 0x0 "MANAESCMDREG,MANAESCMDREG register"
bitfld.long 0x0 1. "INTENA,AES Manual encryption interrupt enable on Interrupt2Reg" "0,1"
newline
bitfld.long 0x0 0. "START,AES Manual encryption Start command." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "MANAESSTATREG,MANAESSTATREG register"
bitfld.long 0x0 0. "BUSY,AES manual encryption busy status" "0,1"
group.long 0x60++0xF
line.long 0x0 "AESLEPRIVPOINTERREG,AESLEPRIVPOINTERREG register"
hexmask.long.tbyte 0x0 0.--23. 1. "POINTER,AES Le privacy pointer"
line.long 0x4 "AESLEPRIVHASHREG,AESLEPRIVHASHREG register"
hexmask.long.tbyte 0x4 0.--23. 1. "HASH,AES Le privacy Reference Hash"
line.long 0x8 "AESLEPRIVPRANDREG,AESLEPRIVPRANDREG register"
hexmask.long.tbyte 0x8 0.--23. 1. "PRAND,AES Le privacy Prand"
line.long 0xC "AESLEPRIVCMDREG,AESLEPRIVCMDREG register"
hexmask.long.byte 0xC 2.--9. 1. "NBKEYS,AES Le privacy number of keys pointed by AesLePrivPointerReg (points to the resolution key list."
newline
bitfld.long 0xC 1. "INTENA,AES Le privacy interrupt enable on Interrupt2Reg" "0,1"
newline
bitfld.long 0xC 0. "START,AES Le privacy Start command." "0,1"
rgroup.long 0x70++0x3
line.long 0x0 "AESLEPRIVSTATREG,AESLEPRIVSTATREG register"
hexmask.long.byte 0x0 2.--9. 1. "KEYFNDINDEX,AES Le privacy index of the key found in the resolution key list."
newline
bitfld.long 0x0 1. "KEYFND,AES Le privacy key finding status" "0,1"
newline
bitfld.long 0x0 0. "BUSY,AES Le privacy busy status" "0,1"
rgroup.long 0x7C++0x3
line.long 0x0 "STATUS2REG,STATUS2REG register"
bitfld.long 0x0 31. "ANTENNA_SWITCHING_PATTERN_ADDRESS_ERROR,AHB access error flag." "0,1"
newline
bitfld.long 0x0 30. "ANTENNASWITCHINGPATTERNACCESSERROR,timing error flag related to Antenna Pattern not read on-time." "0,1"
newline
bitfld.long 0x0 29. "IQSAMPLESMISSINGERROR,IQ sample internal buffer overflow error flag." "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "IQSAMPLESNUMBER,indicate the number of IQ samples stored in the RAM buffer addressed by StatMach."
newline
bitfld.long 0x0 0. "IQSAMPLESREADY,indicates if IQ samples have been received on the last reception." "0,1"
tree.end
endif
tree "CRC (Cyclic Redundancy Check)"
base ad:0x48200000
group.long 0x0++0xB
line.long 0x0 "CRC_DR,CRC data register"
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
line.long 0x4 "CRC_IDR,CRC independent data register"
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
line.long 0x8 "CRC_CR,CRC control register"
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
group.long 0x10++0x7
line.long 0x0 "CRC_INIT,CRC initial value"
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
line.long 0x4 "CRC_POL,CRC polynomial"
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
tree.end
tree "DMA (Direct Memory Access Controller)"
base ad:0x48700000
rgroup.long 0x0++0x3
line.long 0x0 "DMA_ISR,DMA_ISR register"
bitfld.long 0x0 31. "TE1F8,TEIF8: Channel 8 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 30. "HTIF8,HTIF8: Channel 8 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 29. "TCIF8,TCIF8: Channel 8 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 28. "GIF8,GIF8: Channel 8 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 27. "TE1F7,TEIF7: Channel 7 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 26. "HTIF7,HTIF7: Channel 7 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 25. "TCIF7,TCIF7: Channel 7 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 24. "GIF7,GIF7: Channel 7 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 23. "TE1F6,TEIF6: Channel 6 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 22. "HTIF6,HTIF6: Channel 6 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 21. "TCIF6,TCIF6: Channel 6 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 20. "GIF6,GIF6: Channel 6 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 19. "TEIF5,TEIF5: Channel 5 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 18. "HTIF5,HTIF5: Channel 5 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 17. "TCIF5,TCIF5: Channel 5 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 16. "GIF5,GIF5: Channel 5 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 15. "TEIF4,TEIF4: Channel 4 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 14. "HTIF4,HTIF4: Channel 4 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 13. "TCIF4,TCIF4: Channel 4 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 12. "GIF4,GIF4: Channel 4 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 11. "TEIF3,TEIF3: Channel 3 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 10. "HTIF3,HTIF3: Channel 3 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 9. "TCIF3,TCIF3: Channel 3 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 8. "GIF3,GIF3: Channel 3 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 7. "TEIF2,TEIF2: Channel 2 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 6. "HTIF2,HTIF2: Channel 2 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 5. "TCIF2,TCIF2: Channel 2 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 4. "GIF2,GIF2: Channel 2 global interrupt flag" "0: No TE,1: A TE"
newline
bitfld.long 0x0 3. "TEIF1,TEIF1: Channel 1 transfer error flag.." "0: No transfer error,1: A transfer error"
bitfld.long 0x0 2. "HTIF1,HTIF1: Channel 1 half transfer flag" "0: No half transfer,1: A half transfer"
newline
bitfld.long 0x0 1. "TCIF1,TCIF1: Channel 1 transfer complete flag" "0: No transfer complete,1: A transfer complete"
bitfld.long 0x0 0. "GIF1,GIF1: Channel 1 global interrupt flag" "0: No TE,1: A TE"
wgroup.long 0x4++0x3
line.long 0x0 "DMA_IFCR,DMA_IFCR register"
bitfld.long 0x0 31. "CTEIF8,CTEIF8: Channel 8 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 30. "CHTIF8,CHTIF8: Channel 8 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 29. "CTCIF8,CTCIF8: Channel 8 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 28. "CGIF8,CGIF8: Channel 8 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 27. "CTEIF7,CTEIF7: Channel 7 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 26. "CHTIF7,CHTIF7: Channel 7 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 25. "CTCIF7,CTCIF7: Channel 7 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 24. "CGIF7,CGIF7: Channel 7 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 23. "CTEIF6,CTEIF6: Channel 6 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 22. "CHTIF6,CHTIF6: Channel 6 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 21. "CTCIF6,CTCIF6: Channel 6 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 20. "CGIF6,CGIF6: Channel 6 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 19. "CTEIF5,CTEIF5: Channel 5 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 18. "CHTIF5,CHTIF5: Channel 5 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 17. "CTCIF5,CTCIF5: Channel 5 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 16. "CGIF5,CGIF5: Channel 5 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 15. "CTEIF4,CTEIF4: Channel 4 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 14. "CHTIF4,CHTIF4: Channel 4 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 13. "CTCIF4,CTCIF4: Channel 4 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 12. "CGIF4,CGIF4: Channel 4 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 11. "CTEIF3,CTEIF3: Channel 3 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 10. "CHTIF3,CHTIF3: Channel 3 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 9. "CTCIF3,CTCIF3: Channel 3 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 8. "CGIF3,CGIF3: Channel 3 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 7. "CTEIF2,CTEIF2: Channel 2 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 6. "CHTIF2,CHTIF2: Channel 2 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 5. "CTCIF2,CTCIF2: Channel 2 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 4. "CGIF2,CGIF2: Channel 2 global interrupt clear" "0: No effect,1: Clears the GIF"
newline
bitfld.long 0x0 3. "CTEIF1,CTEIF1: Channel 1 transfer error clear" "0: No effect,1: Clears the corresponding TEIF flag in the.."
bitfld.long 0x0 2. "CHTIF1,CHTIF1: Channel 1 half transfer clear" "0: No effect,1: Clears the corresponding HTIF flag in the.."
newline
bitfld.long 0x0 1. "CTCIF1,CTCIF1: Channel 1 transfer complete clear" "0: No effect,1: Clears the corresponding TCIF flag in the.."
bitfld.long 0x0 0. "CGIF1,CGIF1: Channel 1 global interrupt clear" "0: No effect,1: Clears the GIF"
group.long 0x8++0xF
line.long 0x0 "DMA_CCR1,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR1,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR1,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR1,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x1C++0xF
line.long 0x0 "DMA_CCR2,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR2,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR2,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR2,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x30++0xF
line.long 0x0 "DMA_CCR3,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR3,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR3,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR3,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x44++0xF
line.long 0x0 "DMA_CCR4,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR4,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR4,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR4,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x58++0xF
line.long 0x0 "DMA_CCR5,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR5,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR5,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR5,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x6C++0xF
line.long 0x0 "DMA_CCR6,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR6,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR6,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR6,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x80++0xF
line.long 0x0 "DMA_CCR7,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR7,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR7,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR7,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
group.long 0x94++0xF
line.long 0x0 "DMA_CCR8,DMA_CCRx register"
bitfld.long 0x0 14. "MEM2MEM,MEM2MEM: Memory to memory mode" "0: Memory to memory mode disabled,1: Memory to memory mode enabled"
bitfld.long 0x0 12.--13. "PL,PL[1:0]: Channel priority level" "0: Low,1: Medium,?,?"
newline
bitfld.long 0x0 10.--11. "MSIZE,MSIZE[1:0]: Memory size" "0: 8-bits,1: 16-bits,?,?"
bitfld.long 0x0 8.--9. "PSIZE,PSIZE[1:0]: Peripheral size" "0: 8-bits,1: 16-bits,?,?"
newline
bitfld.long 0x0 7. "MINC,MINC: Memory increment mode" "0: Memory increment mode disabled,1: Memory increment mode enabled"
bitfld.long 0x0 6. "PINC,PINC: Peripheral increment mode" "0: Peripheral increment mode disabled,1: Peripheral increment mode enabled"
newline
bitfld.long 0x0 5. "CIRC,CIRC: Circular mode" "0: Circular mode disabled,1: Circular mode enabled"
bitfld.long 0x0 4. "DIR,DIR: Data transfer direction" "0: Read from peripheral,1: Read from memory"
newline
bitfld.long 0x0 3. "TEIE,TEIE: Transfer error interrupt enable" "0: TE interrupt disabled,1: TE interrupt enabled"
bitfld.long 0x0 2. "HTIE,HTIE: Half transfer interrupt enable" "0: HT interrupt disabled,1: HT interrupt enabled"
newline
bitfld.long 0x0 1. "TCIE,TCIE: Transfer complete interrupt enable" "0: TC interrupt disabled,1: TC interrupt enabled"
bitfld.long 0x0 0. "EN,EN: Channel enable" "0: Channel disabled,1: Channel enabled"
line.long 0x4 "DMA_CNDTR8,DMA_CNDTRx register"
hexmask.long.word 0x4 0.--15. 1. "NDT,NDT[15:0]: Number of data to transfer"
line.long 0x8 "DMA_CPAR8,DMA_CPARx register"
hexmask.long 0x8 0.--31. 1. "PA,PA[31:0]: Peripheral address"
line.long 0xC "DMA_CMAR8,DMA_CMARx register"
hexmask.long 0xC 0.--31. 1. "MA,MA[31:0]: Memory address"
tree.end
tree "DMAMUX (Direct Memory Access Multiplexer)"
base ad:0x48800000
group.long 0x0++0x1F
line.long 0x0 "C0CR,CxCR register"
hexmask.long.byte 0x0 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x4 "C1CR,CxCR register"
hexmask.long.byte 0x4 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x8 "C2CR,CxCR register"
hexmask.long.byte 0x8 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0xC "C3CR,CxCR register"
hexmask.long.byte 0xC 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x10 "C4CR,CxCR register"
hexmask.long.byte 0x10 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x14 "C5CR,CxCR register"
hexmask.long.byte 0x14 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x18 "C6CR,CxCR register"
hexmask.long.byte 0x18 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
line.long 0x1C "C7CR,CxCR register"
hexmask.long.byte 0x1C 0.--4. 1. "DMAREQ_ID,DMAREQ_ID[4:0]: DMA REQuest IDentification"
tree.end
tree "FLASH_CTRL (Flash Controller)"
base ad:0x40001000
group.long 0x0++0x13
line.long 0x0 "COMMAND,COMMAND register"
hexmask.long.byte 0x0 0.--7. 1. "COMMAND,Macro commands for flash operations (may require DATA0...DATA3 to be set):"
line.long 0x4 "CONFIG,CONFIG register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 4.--5. "WAIT_STATE,Add latency to flash read opeations:" "0: no latency,1: 1 clock cycle latency,?,?"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 4.--5. "WAIT_STATES,Number of wait states to be inserted on Flash read (AHB accesses)" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 4.--5. "WAIT_STATES,Number of wait states to be inserted on Flash read (AHB accesses)" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 4.--5. "WAIT_STATE,Add latency to flash read opeations:" "0: no latency,1: 1 clock cycle latency,?,?"
newline
endif
bitfld.long 0x4 2. "DIS_GROUP_WRITE,Burst write Control:" "0: burst write allowed,1: burst write forbidden"
bitfld.long 0x4 1. "REMAP,CPU access routing (it supersedes PREMAP configuration):" "0: FLASH memory addressed,1: SRAM0 memory addressed"
line.long 0x8 "IRQSTAT,IRQSTAT register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x8 5. "FNREADY_MIS,(1: clear 0: inactive) FNREADY_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 2. "CMDBUSYERR_MIS,(1: clear 0: inactive) CMDBUSYERR_MIS flag" "0: inactive,1: clear"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 5. "FNREADY_MIS,(1: clear 0: inactive) FNREADY_MIS flag" "0: inactive,1: clear"
newline
endif
bitfld.long 0x8 4. "READOK_MIS,(1: clear 0: inactive) READOK_MIS flag" "0: inactive,1: clear"
bitfld.long 0x8 3. "ILLCMD_MIS,(1: clear 0: inactive) ILLCMD_MIS flag" "0: inactive,1: clear"
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 2. "CMDERR_MIS,Command error masked interrupt status." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 2. "CMDERR_MIS,Command error masked interrupt status." "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 2. "CMDBUSYERR_MIS,(1: clear 0: inactive) CMDBUSYERR_MIS flag" "0: inactive,1: clear"
newline
endif
bitfld.long 0x8 1. "CMDSTART_MIS,(1: clear 0: inactive) CMDSTART_MIS flag" "0: inactive,1: clear"
newline
bitfld.long 0x8 0. "CMDDONE_MIS,(1: clear 0: inactive) CMDDONE_MIS flag" "0: inactive,1: clear"
line.long 0xC "IRQMASK,IRQMASK register"
sif (cpuis("STM32WB05*"))
bitfld.long 0xC 5. "FNREADYM,(1: mask 0: inactive) FNREADY_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 2. "CMDBUSYERRM,(1: mask 0: inactive) CMDBUSYERR_MIS mask" "0: inactive,1: mask"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 5. "FNREADYM,(1: mask 0: inactive) FNREADY_MIS mask" "0: inactive,1: mask"
newline
endif
bitfld.long 0xC 4. "READOKM,(1: mask 0: inactive) READOK_MIS mask" "0: inactive,1: mask"
bitfld.long 0xC 3. "ILLCMDM,(1: mask 0: inactive) ILLCMD_MIS mask" "0: inactive,1: mask"
sif (cpuis("STM32WB06*"))
bitfld.long 0xC 2. "CMDERRM,Command error mask." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0xC 2. "CMDERRM,Command error mask." "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 2. "CMDBUSYERRM,(1: mask 0: inactive) CMDBUSYERR_MIS mask" "0: inactive,1: mask"
newline
endif
bitfld.long 0xC 1. "CMDSTARTM,(1: mask 0: inactive) CMDSTART_MIS mask" "0: inactive,1: mask"
newline
bitfld.long 0xC 0. "CMDDONEM,(1: mask 0: inactive) CMDDONE_MIS mask" "0: inactive,1: mask"
line.long 0x10 "IRQRAW,IRQRAW register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x10 5. "CMDSLEEPERR_RIS,(1: active 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1)" "0: inactive,1: active"
bitfld.long 0x10 2. "CMDBUSYERR_RIS,(1: active 0: inactive) COMMAND issued while flash busy" "0: inactive,1: active"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x10 5. "CMDSLEEPERR_RIS,(1: active 0: inactive) COMMAND issued while flash in sleep-mode (SLM=1)" "0: inactive,1: active"
newline
endif
bitfld.long 0x10 4. "READOK_RIS,(1: active 0: inactive) READ COMMAND completed successfully" "0: inactive,1: active"
bitfld.long 0x10 3. "ILLCMD_RIS,(1: active 0: inactive) Illegal command issued" "0: inactive,1: active"
sif (cpuis("STM32WB06*"))
bitfld.long 0x10 2. "CMDERR_RIS,Command error raw/unmasked interrupt status" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x10 2. "CMDERR_RIS,Command error raw/unmasked interrupt status" "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x10 2. "CMDBUSYERR_RIS,(1: active 0: inactive) COMMAND issued while flash busy" "0: inactive,1: active"
newline
endif
bitfld.long 0x10 1. "CMDSTART_RIS,(1: active 0: inactive) COMMAND sequence started" "0: inactive,1: active"
newline
bitfld.long 0x10 0. "CMDDONE_RIS,(1: active 0: inactive) COMMAND sequence ended" "0: inactive,1: active"
rgroup.long 0x14++0x3
line.long 0x0 "SIZE,SIZE register"
sif (cpuis("STM32WB05*"))
rbitfld.long 0x0 21.--22. "PACKAGE_SIZE,Package selection:" "0,1,2,3"
rbitfld.long 0x0 20. "JTAG_DISABLE,Flash+JTAG protection (0: no JTAG protection - see FLASH_SECURE 1: Flash and JTAG protected)" "0: no JTAG protection,1: Flash and JTAG protected"
rbitfld.long 0x0 17. "RAM_SIZE,RAM memory size selection:" "0: 16kb,1: 32kb"
newline
hexmask.long.tbyte 0x0 0.--16. 1. "FLASH_SIZE,Maximum valid address for flash memory:"
newline
endif
sif (cpuis("STM32WB09*"))
rbitfld.long 0x0 21.--22. "PACKAGE_SIZE,Package selection:" "0: CSP,?,?,?"
rbitfld.long 0x0 20. "JTAG_DISABLE,Flash+JTAG protection (0: no JTAG protection see FLASH_SECURE 1: Flash and JTAG protected)" "0: no JTAG protection see FLASH_SECURE,1: Flash and JTAG protected"
newline
endif
sif (cpuis("STM32WB06*"))
rbitfld.long 0x0 20. "SWD_DISABLE,Flash+SWD protection:" "0: No SWD protection,1: Flash and SWD protected"
newline
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0x0 20. "SWD_DISABLE,Flash+SWD protection:" "0: No SWD protection,1: Flash and SWD protected"
newline
endif
rbitfld.long 0x0 19. "FLASH_SECURE,Flash memory protection (0: no key present 1: key present)" "0: no key present,1: key present"
newline
sif (cpuis("STM32WB09*"))
rbitfld.long 0x0 17. "RAM_SIZE,RAM memory size selection:" "0: 16kb,1: 32kb"
hexmask.long.tbyte 0x0 0.--16. 1. "FLASH_SIZE,Maximum valid address for flash memory:"
newline
endif
sif (cpuis("STM32WB06*"))
rbitfld.long 0x0 17.--18. "RAM_SIZE,RAM memory size selection:" "0: 32kb,1: 32kb,?,?"
newline
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0x0 17.--18. "RAM_SIZE,RAM memory size selection:" "0: 32kb,1: 32kb,?,?"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x0 0.--15. 1. "FLASH_SIZE,Maximum valid address for flash memory:"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x0 0.--15. 1. "FLASH_SIZE,Maximum valid address for flash memory:"
newline
endif
group.long 0x18++0x3
line.long 0x0 "ADDRESS,ADDRESS register"
hexmask.long.word 0x0 6.--15. 1. "XADDR,Flash row address offset to be used with some COMMAND"
hexmask.long.byte 0x0 0.--5. 1. "YADDR,Flash column address offset to be used with some COMMAND"
rgroup.long 0x24++0x3
line.long 0x0 "LFSRVAL,LFSRVAL register"
hexmask.long 0x0 0.--31. 1. "LFSRVAL,Flash read data CRC signature"
group.long 0x34++0x7
line.long 0x0 "PAGEPROT0,PAGEPROT0 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x0 24.--30. 1. "SEGOFFSET1,Second segment 7-bit page protection offset (first page number in protected segment)"
hexmask.long.byte 0x0 16.--22. 1. "SEGSIZE1,Second segment 7-bit page protection size (number of pages to protect in segment first page included)"
hexmask.long.byte 0x0 8.--14. 1. "SEGOFFSET0,First segment 7-bit page protection offset (first page number in protected segment)"
newline
hexmask.long.byte 0x0 0.--6. 1. "SEGSIZE0,First segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 24.--30. 1. "SEGOFFSET1,Second segment 7-bit page protection offset (first page number in protected segment)"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x0 16.--31. 1. "SEG1,Second segment definition. See SEG0 description for details on SEG1[31:16] content"
newline
hexmask.long.word 0x0 0.--15. 1. "SEG0,First segment definition."
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x0 16.--31. 1. "SEG1,Second segment definition. See SEG0 description for details on SEG1[31:16] content"
hexmask.long.word 0x0 0.--15. 1. "SEG0,First segment definition."
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 16.--22. 1. "SEGSIZE1,Second segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 8.--14. 1. "SEGOFFSET0,First segment 7-bit page protection offset (first page number in protected segment)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 0.--6. 1. "SEGSIZE0,First segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
line.long 0x4 "PAGEPROT1,PAGEPROT1 register"
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x4 24.--30. 1. "SEGOFFSET3,Fourth segment 7-bit page protection offset (first page number in protected segment)"
hexmask.long.byte 0x4 16.--22. 1. "SEGSIZE3,Fourth segment 7-bit page protection size (number of pages to protect in segment first page included)"
hexmask.long.byte 0x4 8.--14. 1. "SEGOFFSET2,Third segment 7-bit page protection offset (first page number in protected segment)"
newline
hexmask.long.byte 0x4 0.--6. 1. "SEGSIZE2,Third segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x4 24.--30. 1. "SEGOFFSET3,Fourth segment 7-bit page protection offset (first page number in protected segment)"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x4 16.--31. 1. "SEG3,Fourth segment definition. See PAGEPROT0 SEG0 description for details on SEG3[15:0] content."
newline
hexmask.long.word 0x4 0.--15. 1. "SEG2,Third segment definition. See PAGEPROT0 SEG0 description for details on SEG2[15:0] content"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x4 16.--31. 1. "SEG3,Fourth segment definition. See PAGEPROT0 SEG0 description for details on SEG3[15:0] content."
hexmask.long.word 0x4 0.--15. 1. "SEG2,Third segment definition. See PAGEPROT0 SEG0 description for details on SEG2[15:0] content"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x4 16.--22. 1. "SEGSIZE3,Fourth segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x4 8.--14. 1. "SEGOFFSET2,Third segment 7-bit page protection offset (first page number in protected segment)"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x4 0.--6. 1. "SEGSIZE2,Third segment 7-bit page protection size (number of pages to protect in segment first page included)"
newline
endif
group.long 0x40++0xF
line.long 0x0 "DATA0,DATA0 register"
hexmask.long 0x0 0.--31. 1. "DATA0,Value to be used as DATA for any COMMAND of type WRITE and compare value for MASSREAD"
line.long 0x4 "DATA1,DATA1 register"
hexmask.long 0x4 0.--31. 1. "DATA1,Value to be used as DATA for any COMMAND of type WRITE"
line.long 0x8 "DATA2,DATA2 register"
hexmask.long 0x8 0.--31. 1. "DATA2,Value to be used as DATA for any COMMAND of type WRITE"
line.long 0xC "DATA3,DATA3 register"
hexmask.long 0xC 0.--31. 1. "DATA3,Value to be used as DATA for any COMMAND of type WRITE"
tree.end
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "GLOBALSTATMACH"
base ad:0x200000C0
group.long 0x0++0x1B
line.long 0x0 "WORD0,WORD0 register"
hexmask.long 0x0 0.--31. 1. "RadioConfigPtr,Radio Configuration address Pointer."
line.long 0x4 "WORD1,WORD1 register"
hexmask.long.byte 0x4 24.--31. 1. "Timer2InitDelayNoCal,Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM."
hexmask.long.byte 0x4 16.--23. 1. "Timer12InitDelayCal,Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM."
hexmask.long.byte 0x4 8.--15. 1. "WakeupInitDelay,Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM."
newline
bitfld.long 0x4 7. "Active,Must be at '1' when the trig event (Wakeup Timer Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence." "0,1"
hexmask.long.byte 0x4 0.--6. 1. "CurStMachNum,current connection machine number."
line.long 0x8 "WORD2,WORD2 register"
hexmask.long.byte 0x8 24.--31. 1. "ReceiveNoCalDelayChk,Delay between RX request sent to the Radio FSM and the start pulse to the receive block."
hexmask.long.byte 0x8 16.--23. 1. "ReceiveCalDelayChk,Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block."
hexmask.long.byte 0x8 8.--15. 1. "TransmitNoCalDelayChk,Delay between TX request sent to the Radio FSM and the start pulse to the transmit block."
newline
hexmask.long.byte 0x8 0.--7. 1. "TransmitCalDelayChk,Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block."
line.long 0xC "WORD3,WORD3 register"
bitfld.long 0xC 31. "TimeCapture,- 0: No capture is requested to monitor the Bluetooth LE sequence." "0: No capture is requested to monitor the Bluetooth..,?"
bitfld.long 0xC 30. "TimeCaptureSel,- 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event)." "0: the captured time,?"
hexmask.long.byte 0xC 24.--29. 1. "TxdelayEnd,Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer."
newline
hexmask.long.byte 0xC 16.--23. 1. "TxdelayStart,Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator."
hexmask.long.byte 0xC 8.--15. 1. "TxdataReadyCheck,Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table."
hexmask.long.byte 0xC 0.--7. 1. "ConfigEndDuration,Duration for the Sequencer to execute the final configuration."
line.long 0x10 "WORD4,WORD4 register"
hexmask.long.tbyte 0x10 8.--27. 1. "RcvTimeout,Receive window timeout."
hexmask.long.byte 0x10 0.--7. 1. "TxReadyTimeout,Transmission ready timeout."
line.long 0x14 "WORD5,WORD5 register"
bitfld.long 0x14 31. "IntConfigError,Configuration error interrupt enable." "0,1"
bitfld.long 0x14 30. "IntActive2Err,not in ACTIVE2 information from Radio FSM received on time interrupt enable." "0,1"
bitfld.long 0x14 29. "intTxRxSkip,Transmission or reception skip interrupt enable." "0,1"
newline
bitfld.long 0x14 28. "IntSeqDone,Sequencer end of task interrupt enable." "0,1"
bitfld.long 0x14 26. "IntSemaTimeoutError,Semaphore timeout error interrupt enable." "0,1"
bitfld.long 0x14 25. "IntRcvLengthError,Too long received payload length interrupt enable." "0,1"
newline
bitfld.long 0x14 23. "IntNoActiveLError,Active bit low value reading interrupt enable." "0,1"
bitfld.long 0x14 22. "IntTxDataReadyError,Transmission data payload ready error interrupt enable." "0,1"
bitfld.long 0x14 21. "IntAllTableReadyError,All table ready error interrupt enable." "0,1"
newline
bitfld.long 0x14 20. "IntAddPointError,Address pointer error interrupt enable." "0,1"
bitfld.long 0x14 2. "ChkFlagAutoClearEna,Active bit Auto Clear Enable." "0,1"
bitfld.long 0x14 0. "AutoTxRxskipEn,Automatic transfer (TX or RX) skip enable." "0,1"
line.long 0x18 "WORD6,WORD6 register"
hexmask.long.byte 0x18 0.--6. 1. "DefaultAntennaID,Default Antenna ID corresponding to the number of the antenna used to receive/transmit:"
tree.end
endif
sif (cpuis("STM32WB05*"))
tree "GLOBALSTATMACH_REG"
base ad:0x200000C0
group.long 0x0++0x1B
line.long 0x0 "WORD0,WORD0 register"
hexmask.long 0x0 0.--31. 1. "RadioConfigPtr,Radio Configuration address Pointer."
line.long 0x4 "WORD1,WORD1 register"
hexmask.long.byte 0x4 24.--31. 1. "Timer2InitDelayNoCal,Delay between Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM."
hexmask.long.byte 0x4 16.--23. 1. "Timer12InitDelayCal,Delay between Timer1 or Timer2 trig event on Sequencer and RX/TX request sending to the Radio FSM."
hexmask.long.byte 0x4 8.--15. 1. "WakeupInitDelay,Delay between wakeup timer trig event on Sequencer and RX/TX request sending to the Radio FSM."
newline
bitfld.long 0x4 7. "Active,Must be at '1' when the trig event (Wakeup Timer Timer1 or Timer2) occurs to starts a Bluetooth LE link layer sequence." "0,1"
hexmask.long.byte 0x4 0.--6. 1. "CurStMachNum,current connection machine number."
line.long 0x8 "WORD2,WORD2 register"
hexmask.long.byte 0x8 24.--31. 1. "ReceiveNoCalDelayChk,Delay between RX request sent to the Radio FSM and the start pulse to the receive block."
hexmask.long.byte 0x8 16.--23. 1. "ReceiveCalDelayChk,Delay between RX request sent to the Radio FSM and the start pulse sent to the receive block."
hexmask.long.byte 0x8 8.--15. 1. "TransmitNoCalDelayChk,Delay between TX request sent to the Radio FSM and the start pulse to the transmit block."
newline
hexmask.long.byte 0x8 0.--7. 1. "TransmitCalDelayChk,Delay between TX request sent to the Radio FSM and the start pulse sent to the transmit block."
line.long 0xC "WORD3,WORD3 register"
bitfld.long 0xC 31. "TimeCapture,- 0: No capture is requested to monitor the Bluetooth LE sequence." "0: No capture is requested to monitor the Bluetooth..,?"
bitfld.long 0xC 30. "TimeCaptureSel,- 0: the captured time (absolute time) corresponds to the end of 1st INIT step in the sequence (InitDelay timeout event)." "0: the captured time,?"
hexmask.long.byte 0xC 24.--29. 1. "TxdelayEnd,Delay added between the last bit transmission to the modulator and the end of transmission information for the Sequencer."
newline
hexmask.long.byte 0xC 16.--23. 1. "TxdelayStart,Delay added between the moment the Radio FSM is in TX mode (PA ramp up done and power present on the antenna) and the first bit transmission to the modulator."
hexmask.long.byte 0xC 8.--15. 1. "TxdataReadyCheck,Duration for the Sequencer to get the TxDataReady and DataPtr information in TxRxPack table."
hexmask.long.byte 0xC 0.--7. 1. "ConfigEndDuration,Duration for the Sequencer to execute the final configuration."
line.long 0x10 "WORD4,WORD4 register"
hexmask.long.tbyte 0x10 8.--27. 1. "RcvTimeout,Receive window timeout."
hexmask.long.byte 0x10 0.--7. 1. "TxReadyTimeout,Transmission ready timeout."
line.long 0x14 "WORD5,WORD5 register"
bitfld.long 0x14 31. "IntConfigError,Configuration error interrupt enable." "0,1"
bitfld.long 0x14 30. "IntActive2Err,not in ACTIVE2 information from Radio FSM received on time interrupt enable." "0,1"
bitfld.long 0x14 29. "intTxRxSkip,Transmission or reception skip interrupt enable." "0,1"
newline
bitfld.long 0x14 28. "IntSeqDone,Sequencer end of task interrupt enable." "0,1"
bitfld.long 0x14 26. "IntSemaTimeoutError,Semaphore timeout error interrupt enable." "0,1"
bitfld.long 0x14 25. "IntRcvLengthError,Too long received payload length interrupt enable." "0,1"
newline
bitfld.long 0x14 23. "IntNoActiveLError,Active bit low value reading interrupt enable." "0,1"
bitfld.long 0x14 22. "IntTxDataReadyError,Transmission data payload ready error interrupt enable." "0,1"
bitfld.long 0x14 21. "IntAllTableReadyError,All table ready error interrupt enable." "0,1"
newline
bitfld.long 0x14 20. "IntAddPointError,Address pointer error interrupt enable." "0,1"
bitfld.long 0x14 2. "ChkFlagAutoClearEna,Active bit Auto Clear Enable." "0,1"
bitfld.long 0x14 0. "AutoTxRxskipEn,Automatic transfer (TX or RX) skip enable." "0,1"
line.long 0x18 "WORD6,WORD6 register"
hexmask.long.byte 0x18 0.--6. 1. "DefaultAntennaID,Default Antenna ID corresponding to the number of the antenna used to receive/transmit:"
tree.end
endif
tree "GPIO (General-purpose I/Os)"
base ad:0x0
sif (cpuis("STM32WB05*")||cpuis("STM32WB09*"))
tree "GPIOA"
base ad:0x48000000
group.long 0x0++0xF
line.long 0x0 "MODER,MODER register"
bitfld.long 0x0 22.--23. "MODE11,MODE11[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 20.--21. "MODE10,MODE10[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 18.--19. "MODE9,MODE9[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 16.--17. "MODE8,MODE8[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,MODE3[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,MODE2[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,MODE1[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,MODE0[1:0]Port A configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
line.long 0x4 "OTYPER,OTYPER register"
bitfld.long 0x4 11. "OT11,OT11: Port A configuration bits" "0,1"
bitfld.long 0x4 10. "OT10,OT10: Port A configuration bits" "0,1"
bitfld.long 0x4 9. "OT9,OT9: Port A configuration bits" "0,1"
bitfld.long 0x4 8. "OT8,OT8: Port A configuration bits" "0,1"
bitfld.long 0x4 3. "OT3,OT3: Port A configuration bits" "0,1"
bitfld.long 0x4 2. "OT2,OT2: Port A configuration bits" "0,1"
bitfld.long 0x4 1. "OT1,OT1: Port A configuration bits" "0,1"
bitfld.long 0x4 0. "OT0,OT0: Port A configuration bits" "0,1"
line.long 0x8 "OSPEEDR,OSPEEDR register"
bitfld.long 0x8 22.--23. "OSPEED11,OSPEED11[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 20.--21. "OSPEED10,OSPEED10[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 18.--19. "OSPEED9,OSPEED9[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 16.--17. "OSPEED8,OSPEED8[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPEED3,OSPEED3[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPEED2,OSPEED2[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPEED1,OSPEED1[1:0]: Port A configuration bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPEED0,OSPEED0[1:0]: Port A configuration bits" "0,1,2,3"
line.long 0xC "PUPDR,PUPDR register"
bitfld.long 0xC 22.--23. "PUPD11,PUPD11: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 20.--21. "PUPD10,PUPD10: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 18.--19. "PUPD9,PUPD9: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 16.--17. "PUPD8,PUPD8: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUPD3,PUPD3: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUPD2,PUPD2: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 2.--3. "PUPD1,PUPD1: Port A configuration bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUPD0,PUPD0: Port A configuration bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "IDR,IDR register"
bitfld.long 0x0 11. "ID11,ID11: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 10. "ID10,ID10: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 9. "ID9,ID9: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 8. "ID8,ID8: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 3. "ID3,ID3: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 2. "ID2,ID2: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 1. "ID1,ID1: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 0. "ID0,ID0: Port A input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
group.long 0x14++0x3
line.long 0x0 "ODR,ODR register"
bitfld.long 0x0 11. "OD11,OD11: Port A output data bit" "0,1"
bitfld.long 0x0 10. "OD10,OD10: Port A output data bit" "0,1"
bitfld.long 0x0 9. "OD9,OD9: Port A output data bit" "0,1"
bitfld.long 0x0 8. "OD8,OD8: Port A output data bit" "0,1"
bitfld.long 0x0 3. "OD3,OD3: Port A output data bit" "0,1"
bitfld.long 0x0 2. "OD2,OD2: Port A output data bit" "0,1"
bitfld.long 0x0 1. "OD1,OD1: Port A output data bit" "0,1"
bitfld.long 0x0 0. "OD0,OD0: Port A output data bit" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BSRR,BSRR register"
bitfld.long 0x0 27. "BR11,BR11: Port A reset bit y" "0,1"
bitfld.long 0x0 26. "BR10,BR10: Port A reset bit y" "0,1"
bitfld.long 0x0 25. "BR9,BR9: Port A reset bit y" "0,1"
bitfld.long 0x0 24. "BR8,BR8: Port A reset bit y" "0,1"
bitfld.long 0x0 19. "BR3,BR3: Port A reset bit y" "0,1"
bitfld.long 0x0 18. "BR2,BR2: Port A reset bit y" "0,1"
bitfld.long 0x0 17. "BR1,BR1: Port A reset bit y" "0,1"
bitfld.long 0x0 16. "BR0,BR0: Port A reset bit y" "0,1"
bitfld.long 0x0 11. "BS11,BS11: Port A set bit y" "0,1"
bitfld.long 0x0 10. "BS10,BS10: Port A set bit y" "0,1"
bitfld.long 0x0 9. "BS9,BS9: Port A set bit y" "0,1"
newline
bitfld.long 0x0 8. "BS8,BS8: Port A set bit y" "0,1"
bitfld.long 0x0 3. "BS3,BS3: Port A set bit y" "0,1"
bitfld.long 0x0 2. "BS2,BS2: Port A set bit y" "0,1"
bitfld.long 0x0 1. "BS1,BS1: Port A set bit y" "0,1"
bitfld.long 0x0 0. "BS0,BS0: Port A set bit y" "0,1"
group.long 0x1C++0xB
line.long 0x0 "LCKR,LCKR register"
bitfld.long 0x0 16. "LCKK,LCKK: Lock key" "0,1"
bitfld.long 0x0 11. "LCK11,LCK11: Port A lock bit 11" "0,1"
bitfld.long 0x0 10. "LCK10,LCK10: Port A lock bit 10" "0,1"
bitfld.long 0x0 9. "LCK9,LCK9: Port A lock bit 9" "0,1"
bitfld.long 0x0 8. "LCK8,LCK8: Port A lock bit 8" "0,1"
bitfld.long 0x0 3. "LCK3,LCK3: Port A lock bit 3" "0,1"
bitfld.long 0x0 2. "LCK2,LCK2: Port A lock bit 2" "0,1"
bitfld.long 0x0 1. "LCK1,LCK1: Port A lock bit 1" "0,1"
bitfld.long 0x0 0. "LCK0,LCK0: Port A lock bit 0" "0,1"
line.long 0x4 "AFRL,AFRL register"
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,y[3:0]: Alternate function selection for port A pin y (y = 0..7)"
line.long 0x8 "AFRH,AFRH register"
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,y[3:0]: Alternate function selection for port A pin y (y = 8..15)"
wgroup.long 0x28++0x3
line.long 0x0 "BRR,BRR register"
bitfld.long 0x0 11. "BR11,BR11: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 10. "BR10,BR10: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 9. "BR9,BR9: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 8. "BR8,BR8: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 3. "BR3,BR3: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 2. "BR2,BR2: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 1. "BR1,BR1: Port A reset bit y (y = 0..15)" "0,1"
bitfld.long 0x0 0. "BR0,BR0: Port A reset bit y (y = 0..15)" "0,1"
tree.end
endif
sif (cpuis("STM32WB05*")||cpuis("STM32WB09*"))
tree "GPIOB"
base ad:0x48100000
group.long 0x0++0xF
line.long 0x0 "MODER,MODER register"
bitfld.long 0x0 30.--31. "MODE15,MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 10.--11. "MODE5,MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 4.--5. "MODE2,MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "MODE1,MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
line.long 0x4 "OTYPER,OTYPER register"
bitfld.long 0x4 15. "OT15,OT15: Port B configuration bits" "0,1"
bitfld.long 0x4 14. "OT14,OT14: Port B configuration bits" "0,1"
bitfld.long 0x4 13. "OT13,OT13: Port B configuration bits" "0,1"
bitfld.long 0x4 12. "OT12,OT12: Port B configuration bits" "0,1"
bitfld.long 0x4 7. "OT7,OT7: Port B configuration bits" "0,1"
bitfld.long 0x4 6. "OT6,OT6: Port B configuration bits" "0,1"
bitfld.long 0x4 5. "OT5,OT5: Port B configuration bits" "0,1"
bitfld.long 0x4 4. "OT4,OT4: Port B configuration bits" "0,1"
bitfld.long 0x4 3. "OT3,OT3: Port B configuration bits" "0,1"
bitfld.long 0x4 2. "OT2,OT2: Port B configuration bits" "0,1"
newline
bitfld.long 0x4 1. "OT1,OT1: Port B configuration bits" "0,1"
bitfld.long 0x4 0. "OT0,OT0: Port B configuration bits" "0,1"
line.long 0x8 "OSPEEDR,OSPEEDR register"
bitfld.long 0x8 30.--31. "OSPEED15,OSPEED15[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPEED14,OSPEED14[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPEED13,OSPEED13[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPEED12,OSPEED12[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPEED7,OSPEED7[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPEED6,OSPEED6[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPEED5,OSPEED5[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 8.--9. "OSPEED4,OSPEED4[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPEED3,OSPEED3[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 4.--5. "OSPEED2,OSPEED2[1:0]: Port B configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "OSPEED1,OSPEED1[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPEED0,OSPEED0[1:0]: Port B configuration bits" "0,1,2,3"
line.long 0xC "PUPDR,PUPDR register"
bitfld.long 0xC 30.--31. "PUPD15,PUPD15: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUPD14,PUPD14: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUPD13,PUPD13: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUPD12,PUPD12: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUPD7,PUPD7: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUPD6,PUPD6: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUPD5,PUPD5: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 8.--9. "PUPD4,PUPD4: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUPD3,PUPD3: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 4.--5. "PUPD2,PUPD2: Port B configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "PUPD1,PUPD1: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 0.--1. "PUPD0,PUPD0: Port B configuration bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "IDR,IDR register"
bitfld.long 0x0 15. "ID15,ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 14. "ID14,ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 13. "ID13,ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 12. "ID12,ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 7. "ID7,ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 6. "ID6,ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 5. "ID5,ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 4. "ID4,ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 3. "ID3,ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 2. "ID2,ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 1. "ID1,ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 0. "ID0,ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
group.long 0x14++0x3
line.long 0x0 "ODR,ODR register"
bitfld.long 0x0 15. "OD15,OD15: Port B output data bit" "0,1"
bitfld.long 0x0 14. "OD14,OD14: Port B output data bit" "0,1"
bitfld.long 0x0 13. "OD13,OD13: Port B output data bit" "0,1"
bitfld.long 0x0 12. "OD12,OD12: Port B output data bit" "0,1"
bitfld.long 0x0 7. "OD7,OD7: Port B output data bit" "0,1"
bitfld.long 0x0 6. "OD6,OD6: Port B output data bit" "0,1"
bitfld.long 0x0 5. "OD5,OD5: Port B output data bit" "0,1"
bitfld.long 0x0 4. "OD4,OD4: Port B output data bit" "0,1"
bitfld.long 0x0 3. "OD3,OD3: Port B output data bit" "0,1"
bitfld.long 0x0 2. "OD2,OD2: Port B output data bit" "0,1"
newline
bitfld.long 0x0 1. "OD1,OD1: Port B output data bit" "0,1"
bitfld.long 0x0 0. "OD0,OD0: Port B output data bit" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BSRR,BSRR register"
bitfld.long 0x0 31. "BR15,BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 30. "BR14,BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 29. "BR13,BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 28. "BR12,BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 23. "BR7,BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 22. "BR6,BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 21. "BR5,BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 20. "BR4,BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 19. "BR3,BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 18. "BR2,BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
newline
bitfld.long 0x0 17. "BR1,BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 16. "BR0,BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 15. "BS15,BS15: Port B set bit 15" "0,1"
bitfld.long 0x0 14. "BS14,BS14: Port B set bit 14" "0,1"
bitfld.long 0x0 13. "BS13,BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 12. "BS12,BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 7. "BS7,BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 6. "BS6,BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 5. "BS5,BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 4. "BS4,BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
newline
bitfld.long 0x0 3. "BS3,BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 2. "BS2,BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 1. "BS1,BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 0. "BS0,BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
group.long 0x1C++0xF
line.long 0x0 "LCKR,LCKR register"
bitfld.long 0x0 16. "LCKK,LCKK: Lock key" "0,1"
bitfld.long 0x0 15. "LCK15,LCK15: Port B lock bit 15" "0,1"
bitfld.long 0x0 14. "LCK14,LCK14: Port B lock bit 14" "0,1"
bitfld.long 0x0 13. "LCK13,LCK13: Port B lock bit 13" "0,1"
bitfld.long 0x0 12. "LCK12,LCK12: Port B lock bit 12" "0,1"
bitfld.long 0x0 7. "LCK7,LCK7: Port B lock bit 7" "0,1"
bitfld.long 0x0 6. "LCK6,LCK6: Port B lock bit 6" "0,1"
bitfld.long 0x0 5. "LCK5,LCK5: Port B lock bit 5" "0,1"
bitfld.long 0x0 4. "LCK4,LCK4: Port B lock bit 4" "0,1"
bitfld.long 0x0 3. "LCK3,LCK3: Port B lock bit 3" "0,1"
newline
bitfld.long 0x0 2. "LCK2,LCK2: Port B lock bit 2" "0,1"
bitfld.long 0x0 1. "LCK1,LCK1: Port B lock bit 1" "0,1"
bitfld.long 0x0 0. "LCK0,LCK0: Port B lock bit 0" "0,1"
line.long 0x4 "AFRL,AFRL register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
line.long 0x8 "AFRH,AFRH register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
line.long 0xC "BRR,BRR register"
bitfld.long 0xC 15. "BR15,BR15: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 14. "BR14,BR14: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 13. "BR13,BR13: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 12. "BR12,BR12 Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 7. "BR7,BR7: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 6. "BR6,BR6: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 5. "BR5,BR5: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 4. "BR4,BR4: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 3. "BR3,BR3: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 2. "BR2,BR2: Port B reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0xC 1. "BR1,BR1: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 0. "BR0,BR0: Port B reset bit y (y = 0..15)" "0,1"
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "GPIOA"
base ad:0x48000000
group.long 0x0++0xF
line.long 0x0 "GPIOA_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODER15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 28.--29. "MODER14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 26.--27. "MODER13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 24.--25. "MODER12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 22.--23. "MODER11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 20.--21. "MODER10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 18.--19. "MODER9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 16.--17. "MODER8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 14.--15. "MODER7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 12.--13. "MODER6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 10.--11. "MODER5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 8.--9. "MODER4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 6.--7. "MODER3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 4.--5. "MODER2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
newline
bitfld.long 0x0 2.--3. "MODER1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
bitfld.long 0x0 0.--1. "MODER0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode"
line.long 0x4 "GPIOA_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOA_IDR,GPIO port input data register"
bitfld.long 0x0 15. "IDR15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "IDR14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "IDR13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "IDR12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "IDR11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "IDR10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "IDR9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "IDR8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "IDR7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "IDR6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "IDR5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "IDR4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "IDR3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "IDR2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "IDR1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "IDR0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOA_ODR,GPIO port output data register"
bitfld.long 0x0 15. "ODR15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "ODR14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ODR13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "ODR12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ODR11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "ODR10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ODR9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "ODR8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ODR7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "ODR6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ODR5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "ODR4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ODR3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "ODR2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ODR1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "ODR0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODRx bit,1: Resets the corresponding ODRx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODRx bit,1: Sets the corresponding ODRx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOA_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFR7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFR6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFR5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFR4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFR3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFR2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFR1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFR0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFR15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFR14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFR13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFR12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFR11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFR10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFR9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFR8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOA_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "GPIOB"
base ad:0x48100000
group.long 0x0++0xF
line.long 0x0 "MODER,MODER register"
bitfld.long 0x0 30.--31. "MODE15,MODE15[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 28.--29. "MODE14,MODE14[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 26.--27. "MODE13,MODE13[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 24.--25. "MODE12,MODE12[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 14.--15. "MODE7,MODE7[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 12.--13. "MODE6,MODE6[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 10.--11. "MODE5,MODE5[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 8.--9. "MODE4,MODE4[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 6.--7. "MODE3,MODE3[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "MODE2,MODE2[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 2.--3. "MODE1,MODE1[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
bitfld.long 0x0 0.--1. "MODE0,MODE0[1:0]Port B configuration bits. These bits are written by software to configure the I/O mode." "0,1,2,3"
line.long 0x4 "OTYPER,OTYPER register"
bitfld.long 0x4 15. "OT15,OT15: Port B configuration bits" "0,1"
bitfld.long 0x4 14. "OT14,OT14: Port B configuration bits" "0,1"
bitfld.long 0x4 13. "OT13,OT13: Port B configuration bits" "0,1"
bitfld.long 0x4 12. "OT12,OT12: Port B configuration bits" "0,1"
bitfld.long 0x4 7. "OT7,OT7: Port B configuration bits" "0,1"
bitfld.long 0x4 6. "OT6,OT6: Port B configuration bits" "0,1"
bitfld.long 0x4 5. "OT5,OT5: Port B configuration bits" "0,1"
bitfld.long 0x4 4. "OT4,OT4: Port B configuration bits" "0,1"
bitfld.long 0x4 3. "OT3,OT3: Port B configuration bits" "0,1"
newline
bitfld.long 0x4 2. "OT2,OT2: Port B configuration bits" "0,1"
bitfld.long 0x4 1. "OT1,OT1: Port B configuration bits" "0,1"
bitfld.long 0x4 0. "OT0,OT0: Port B configuration bits" "0,1"
line.long 0x8 "OSPEEDR,OSPEEDR register"
bitfld.long 0x8 30.--31. "OSPEED15,OSPEED15[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 28.--29. "OSPEED14,OSPEED14[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 26.--27. "OSPEED13,OSPEED13[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 24.--25. "OSPEED12,OSPEED12[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 14.--15. "OSPEED7,OSPEED7[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 12.--13. "OSPEED6,OSPEED6[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 10.--11. "OSPEED5,OSPEED5[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 8.--9. "OSPEED4,OSPEED4[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 6.--7. "OSPEED3,OSPEED3[1:0]: Port B configuration bits" "0,1,2,3"
newline
bitfld.long 0x8 4.--5. "OSPEED2,OSPEED2[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 2.--3. "OSPEED1,OSPEED1[1:0]: Port B configuration bits" "0,1,2,3"
bitfld.long 0x8 0.--1. "OSPEED0,OSPEED0[1:0]: Port B configuration bits" "0,1,2,3"
line.long 0xC "PUPDR,PUPDR register"
bitfld.long 0xC 30.--31. "PUPD15,PUPD15: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 28.--29. "PUPD14,PUPD14: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 26.--27. "PUPD13,PUPD13: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 24.--25. "PUPD12,PUPD12: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 14.--15. "PUPD7,PUPD7: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 12.--13. "PUPD6,PUPD6: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 10.--11. "PUPD5,PUPD5: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 8.--9. "PUPD4,PUPD4: Port B configuration bits" "0,1,2,3"
bitfld.long 0xC 6.--7. "PUPD3,PUPD3: Port B configuration bits" "0,1,2,3"
newline
bitfld.long 0xC 4.--5. "PUPD2,PUPD2: Port B configuration bits" "0: No pullup,1: Pullup,?,?"
bitfld.long 0xC 2.--3. "PUPD1,PUPD1: Port B configuration bits" "0: No pullup,1: Pullup,?,?"
bitfld.long 0xC 0.--1. "PUPD0,PUPD0: Port B configuration bits" "0,1,2,3"
rgroup.long 0x10++0x3
line.long 0x0 "IDR,IDR register"
bitfld.long 0x0 15. "ID15,ID15: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 14. "ID14,ID14: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 13. "ID13,ID13: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 12. "ID12,ID12: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 7. "ID7,ID7: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 6. "ID6,ID6: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 5. "ID5,ID5: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 4. "ID4,ID4: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 3. "ID3,ID3: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
newline
bitfld.long 0x0 2. "ID2,ID2: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 1. "ID1,ID1: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
bitfld.long 0x0 0. "ID0,ID0: Port B input data bit.These bits are read-only. They contain the input value of the corresponding I/O port" "0,1"
group.long 0x14++0x3
line.long 0x0 "ODR,ODR register"
bitfld.long 0x0 15. "OD15,OD15: Port B output data bit" "0,1"
bitfld.long 0x0 14. "OD14,OD14: Port B output data bit" "0,1"
bitfld.long 0x0 13. "OD13,OD13: Port B output data bit" "0,1"
bitfld.long 0x0 12. "OD12,OD12: Port B output data bit" "0,1"
bitfld.long 0x0 7. "OD7,OD7: Port B output data bit" "0,1"
bitfld.long 0x0 6. "OD6,OD6: Port B output data bit" "0,1"
bitfld.long 0x0 5. "OD5,OD5: Port B output data bit" "0,1"
bitfld.long 0x0 4. "OD4,OD4: Port B output data bit" "0,1"
bitfld.long 0x0 3. "OD3,OD3: Port B output data bit" "0,1"
newline
bitfld.long 0x0 2. "OD2,OD2: Port B output data bit" "0,1"
bitfld.long 0x0 1. "OD1,OD1: Port B output data bit" "0,1"
bitfld.long 0x0 0. "OD0,OD0: Port B output data bit" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "BSRR,BSRR register"
bitfld.long 0x0 31. "BR15,BR15: Port B reset bit 15 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 30. "BR14,BR14: Port B reset bit 14 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 29. "BR13,BR13: Port B reset bit 13 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 28. "BR12,BR12: Port B reset bit 12 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 23. "BR7,BR7: Port B reset bit 7 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 22. "BR6,BR6: Port B reset bit 6 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 21. "BR5,BR5: Port B reset bit 5 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 20. "BR4,BR4: Port B reset bit 4 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 19. "BR3,BR3: Port B reset bit 3 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
newline
bitfld.long 0x0 18. "BR2,BR2: Port B reset bit 2 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 17. "BR1,BR1: Port B reset bit 1 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 16. "BR0,BR0: Port B reset bit 0 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 15. "BS15,BS15: Port B set bit 15" "0,1"
bitfld.long 0x0 14. "BS14,BS14: Port B set bit 14" "0,1"
bitfld.long 0x0 13. "BS13,BS13: Port B set bit 13 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 12. "BS12,BS12: Port B set bit 12 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 7. "BS7,BS7: Port B set bit 7 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 6. "BS6,BS6: Port B set bit 6 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
newline
bitfld.long 0x0 5. "BS5,BS5: Port B set bit 5 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 4. "BS4,BS4: Port B set bit 4 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 3. "BS3,BS3: Port B set bit 3 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 2. "BS2,BS2: Port B set bit 2 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 1. "BS1,BS1: Port B set bit 1 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
bitfld.long 0x0 0. "BS0,BS0: Port B set bit 0 These bits are write-only. A read to these bits returns the value 0x0000." "0,1"
group.long 0x1C++0xF
line.long 0x0 "LCKR,LCKR register"
bitfld.long 0x0 16. "LCKK,LCKK: Lock key" "0,1"
bitfld.long 0x0 15. "LCK15,LCK15: Port B lock bit 15" "0,1"
bitfld.long 0x0 14. "LCK14,LCK14: Port B lock bit 14" "0,1"
bitfld.long 0x0 13. "LCK13,LCK13: Port B lock bit 13" "0,1"
bitfld.long 0x0 12. "LCK12,LCK12: Port B lock bit 12" "0,1"
bitfld.long 0x0 7. "LCK7,LCK7: Port B lock bit 7" "0,1"
bitfld.long 0x0 6. "LCK6,LCK6: Port B lock bit 6" "0,1"
bitfld.long 0x0 5. "LCK5,LCK5: Port B lock bit 5" "0,1"
bitfld.long 0x0 4. "LCK4,LCK4: Port B lock bit 4" "0,1"
newline
bitfld.long 0x0 3. "LCK3,LCK3: Port B lock bit 3" "0,1"
bitfld.long 0x0 2. "LCK2,LCK2: Port B lock bit 2" "0,1"
bitfld.long 0x0 1. "LCK1,LCK1: Port B lock bit 1" "0,1"
bitfld.long 0x0 0. "LCK0,LCK0: Port B lock bit 0" "0,1"
line.long 0x4 "AFRL,AFRL register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,y[3:0]: Alternate function selection for port B pin y (y = 0..7)"
line.long 0x8 "AFRH,AFRH register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,y[3:0]: Alternate function selection for port B pin y (y = 8..15)"
line.long 0xC "BRR,BRR register"
bitfld.long 0xC 15. "BR15,BR15: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 14. "BR14,BR14: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 13. "BR13,BR13: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 12. "BR12,BR12 Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 7. "BR7,BR7: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 6. "BR6,BR6: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 5. "BR5,BR5: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 4. "BR4,BR4: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 3. "BR3,BR3: Port B reset bit y (y = 0..15)" "0,1"
newline
bitfld.long 0xC 2. "BR2,BR2: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 1. "BR1,BR1: Port B reset bit y (y = 0..15)" "0,1"
bitfld.long 0xC 0. "BR0,BR0: Port B reset bit y (y = 0..15)" "0,1"
tree.end
endif
tree.end
tree "I2C (Inter Integrated Circuit)"
base ad:0x0
tree "I2C1"
base ad:0x41000000
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C control register 1"
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
newline
bitfld.long 0x0 21. "SMBDEN,SMBus device default address enable" "0: Device default address disabled. Address..,1: Device default address enabled. Address.."
bitfld.long 0x0 20. "SMBHEN,SMBus host address enable" "0: Host address disabled. Address 0b0001000x is..,1: Host address enabled. Address 0b0001000x is ACKed."
newline
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
newline
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
newline
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
newline
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
newline
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
newline
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
newline
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
newline
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C control register 2"
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
newline
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
newline
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
newline
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
newline
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
newline
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
line.long 0xC "I2C_OAR2,I2C own address 2 register"
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMINGR,I2C timing register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
newline
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t<sub>LOW</sub> detection flag" "0,1"
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
newline
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
newline
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
newline
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
newline
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
newline
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
newline
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
newline
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
newline
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
newline
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PECR,I2C PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
tree.end
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "I2C2"
base ad:0x41001000
group.long 0x0++0x1B
line.long 0x0 "I2C2_CR1,I2C2_CR1 register"
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: SMBus Alert pin,1: SMBus Alert pin"
newline
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address enable" "0: Device default address disabled,1: Device default address enabled"
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0: Host address disabled,1: Host address enabled"
newline
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled,1: General call enabled"
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
rbitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt enable" "0: Stop detection,1: Stop detection"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge,1: Not acknowledge"
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match,1: Address match"
newline
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive,1: Receive"
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit,1: Transmit"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C2_CR2,I2C2_CR2 register"
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer,1: PEC transmission/reception is requested"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
newline
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
newline
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte,1: a NACK is sent after current received byte"
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
newline
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
bitfld.long 0x4 12. "HEAD10R,Ten bit (10-bit) address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
newline
bitfld.long 0x4 11. "ADD10,Ten-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
newline
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address"
line.long 0x8 "I2C2_OAR1,I2C2_OAR1 register"
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled,1: Own address 1 enabled"
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address,1: Own address 1 is a 10-bit address"
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface address"
line.long 0xC "I2C2_OAR2,I2C2_OAR2 register"
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled,1: Own address 2 enabled"
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and dont care,?,?,?,?,?,?"
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C2_TIMING,I2C2_TIMING register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C2_TIMEOUT,I2C2_TIMEOUT register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled"
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMEOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
line.long 0x18 "I2C2_ISR,I2C2_ISR register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer,1: Read transfer"
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
newline
rbitfld.long 0x18 12. "TIMEOUT,Timeout or tLOW detection flag" "0,1"
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
newline
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
newline
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
newline
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
newline
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
newline
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
newline
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C2_ICR,I2C2_ICR register"
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag clear" "0,1"
newline
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
newline
bitfld.long 0x0 9. "ARLOCF,Arbitration Lost flag clear" "0,1"
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
newline
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
newline
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C2_PECR,I2C2_PECR register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C2_RXDR,I2C2_RXDR register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Eight bit (8-bit) receive data"
group.long 0x28++0x3
line.long 0x0 "I2C2_TXDR,I2C2_TXDR register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Eight bits (8-bit) transmit data"
tree.end
endif
tree.end
tree "IWDG (Independent Watchdog)"
base ad:0x40003000
wgroup.long 0x0++0x3
line.long 0x0 "IWDG_KR,IWDG_KR register"
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value."
group.long 0x4++0x7
line.long 0x0 "IWDG_PR,IWDG_PR register"
bitfld.long 0x0 0.--2. "PR,Prescaler divider." "0: divider/4,1: divider/8,?,?,?,?,?,?"
line.long 0x4 "IWDG_RLR,IWDG_RLR register"
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value."
rgroup.long 0xC++0x3
line.long 0x0 "IWDG_SR,IWDG_SR register"
bitfld.long 0x0 2. "WVU,Watchdog counter window value update." "0,1"
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update." "0,1"
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update." "0,1"
group.long 0x10++0x3
line.long 0x0 "IWDG_WINR,IWDG_WINR register"
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value."
tree.end
tree "LPUART (Universal Asynchronous Receiver Transmitter)"
base ad:0x41005000
group.long 0x0++0xF
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 31. "RXFFIE,RXFFIE :RXFIFO Full interrupt enable" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFEIE :TXFIFO empty interrupt enable" "0,1"
bitfld.long 0x0 29. "FIFOEN,FIFOEN :FIFO mode enable" "0,1"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
bitfld.long 0x0 1. "UESM,UESM: LPUART enable in Stop mode" "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
endif
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT[4:0]: Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT[4:0]: Driver Enable deassertion time"
bitfld.long 0x0 14. "CMIE,CMIE: Character match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MME,MME: Mute mode enable" "0,1"
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 12. "M0,M0: Word length" "0,1"
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 12. "M0,M0: Word length" "0,1"
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
endif
bitfld.long 0x0 11. "WAKE,WAKE: Receiver wakeup method" "0,1"
bitfld.long 0x0 10. "PCE,PCE: Parity control enable" "0,1"
newline
bitfld.long 0x0 9. "PS,PS: Parity selection" "0,1"
bitfld.long 0x0 8. "PEIE,PEIE: PE interrupt enable" "0,1"
bitfld.long 0x0 7. "TXEIE_TXFNFIE,TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,TCIE: Transmission complete interrupt enable" "0,1"
bitfld.long 0x0 5. "RXNEIE_RXFNEIE,RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLEIE: IDLE interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TE,TE: Transmitter enable" "0,1"
bitfld.long 0x0 2. "RE,RE: Receiver enable" "0,1"
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 1. "UESM,UESM: LPUART enable in Stop mode" "0,1"
endif
bitfld.long 0x0 0. "UE,UE: USART enable" "0,1"
line.long 0x4 "CR2,CR2 register"
hexmask.long.byte 0x4 24.--31. 1. "ADD,ADD[7:0]: Address of the USART node"
bitfld.long 0x4 19. "MSBFIRST,MSBFIRST: Most significant bit first" "0,1"
bitfld.long 0x4 18. "DATAINV,DATAINV: Binary data inversion" "0: H,1: L"
bitfld.long 0x4 17. "TXINV,TXINV: TX pin active level inversion" "0,1"
bitfld.long 0x4 16. "RXINV,RXINV: RX pin active level inversion" "0,1"
bitfld.long 0x4 15. "SWAP,SWAP: Swap TX/RX pins" "0,1"
newline
bitfld.long 0x4 12.--13. "STOP,STOP[1:0]: STOP bits" "0,1,2,3"
bitfld.long 0x4 4. "ADDM7,ADDM7:7-bit Address Detection/4-bit Address Detection" "0,1"
line.long 0x8 "CR3,CR3 register"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG: TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 28. "RXFTIE,RXFTIE: RXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG: Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 23. "TXFTIE,TXFTIE: TXFIFO threshold interrupt enable" "0,1"
sif (cpuis("STM32WB05*"))
bitfld.long 0x8 22. "WUFIE,WUFIE: Wakeup from Stop mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUS,WUS[1:0]: Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 22. "WUFIE,WUFIE: Wakeup from Stop mode interrupt enable" "0,1"
bitfld.long 0x8 20.--21. "WUS,WUS[1:0]: Wakeup from Stop mode interrupt flag selection" "0,1,2,3"
endif
bitfld.long 0x8 15. "DEP,DEP: Driver enable polarity selection" "0,1"
bitfld.long 0x8 14. "DEM,DEM: Driver enable mode" "0,1"
bitfld.long 0x8 13. "DDRE,DDRE: DMA Disable on Reception Error" "0,1"
bitfld.long 0x8 12. "OVRDIS,OVRDIS: Overrun Disable" "0,1"
newline
bitfld.long 0x8 10. "CTSIE,CTSIE: CTS interrupt enable" "0,1"
bitfld.long 0x8 9. "CTSE,CTSE: CTS enable" "0,1"
bitfld.long 0x8 8. "RTSE,RTSE: RTS enable" "0,1"
bitfld.long 0x8 7. "DMAT,DMAT: DMA enable transmitter" "0,1"
bitfld.long 0x8 6. "DMAR,DMAR: DMA enable receiver" "0,1"
bitfld.long 0x8 3. "HDSEL,HDSEL: Half-duplex selection" "0,1"
newline
bitfld.long 0x8 0. "EIE,EIE: Error interrupt enable" "0,1"
line.long 0xC "BRR,BRR register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR[19:0]"
wgroup.long 0x18++0x3
line.long 0x0 "RQR,RQR register"
bitfld.long 0x0 4. "TXFRQ,TXFRQ: Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,RXFRQ: Receive data flush request" "0,1"
bitfld.long 0x0 2. "MMRQ,MMRQ: Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,SBKRQ: Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "ISR,ISR register"
bitfld.long 0x0 27. "TXFT,TXFT: TXFIFO threshold flag" "0,1"
bitfld.long 0x0 26. "RXFT,RXFT: RXFIFO threshold flag" "0,1"
bitfld.long 0x0 24. "RXFF,RXFF: RXFIFO Full" "0,1"
bitfld.long 0x0 23. "TXFE,TXFE: TXFIFO Empty" "0,1"
bitfld.long 0x0 22. "REACK,REACK: Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,TEACK: Transmit enable acknowledge flag" "0,1"
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 20. "WUF,WUF: Wakeup from Stop mode flag" "0,1"
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 20. "WUF,WUF: Wakeup from Stop mode flag" "0,1"
endif
bitfld.long 0x0 19. "RWU,RWU: Receiver wakeup from Mute mode" "0,1"
bitfld.long 0x0 18. "SBKF,SBKF: Send break flag" "0,1"
bitfld.long 0x0 17. "CMF,CMF: Character match flag" "0,1"
bitfld.long 0x0 16. "BUSY,BUSY: Busy flag" "0,1"
newline
bitfld.long 0x0 10. "CTS,CTS: CTS flag" "0,1"
bitfld.long 0x0 9. "CTSIF,CTSIF: CTS interrupt flag" "0,1"
bitfld.long 0x0 7. "TXE_TXFNF,TXE/TXFNF: Transmit data register empty/TXFIFO not full" "0,1"
bitfld.long 0x0 6. "TC,TC: Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE_RXFNE,RXNE/RXFNE:Read data register not empty/RXFIFO not empty" "0,1"
bitfld.long 0x0 4. "IDLE,IDLE: Idle line detected" "0,1"
newline
bitfld.long 0x0 3. "ORE,ORE: Overrun error" "0,1"
bitfld.long 0x0 2. "NF,NF: START bit Noise detection flag" "0,1"
bitfld.long 0x0 1. "FE,FE: Framing error" "0,1"
bitfld.long 0x0 0. "PE,PE: Parity error" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "ICR,ICR register"
bitfld.long 0x0 20. "WUCF,WUCF: Wakeup from Stop mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,CMCF: Character match clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTSCF: CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,TCCF: Transmission complete clear flag" "0,1"
bitfld.long 0x0 4. "IDLECF,IDLECF: Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,ORECF: Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,NECF: Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,FECF: Framing error clear flag" "0,1"
bitfld.long 0x0 0. "PECF,PECF: Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDR,RDR register"
hexmask.long.word 0x0 0.--8. 1. "RDR,RDR[8:0]: Receive data value"
group.long 0x28++0x7
line.long 0x0 "TDR,TDR register"
hexmask.long.word 0x0 0.--8. 1. "TDR,TDR[8:0]: Transmit data value"
line.long 0x4 "PRESC,PRESC register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER[3:0]: Clock prescaler"
tree.end
tree "PKA (Public Key Accelerator)"
base ad:0x48300000
sif (cpuis("STM32WB05*"))
group.long 0x0++0x3
line.long 0x0 "PKA_CR,PKA_CR register"
bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when ADDRERRF"
bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when RAMERRF"
newline
bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when PROCENDF"
hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code"
newline
bitfld.long 0x0 2. "SECLVL,Security enable." "0: No side channel countermeasure,1: Square and Multiply always / Double and Add always"
bitfld.long 0x0 1. "START,Start the operation" "0: No operation,1: Writing 1' to this bit starts the operation.."
newline
bitfld.long 0x0 0. "EN,Peripheral enable." "0: Disable PKA,1: Enable PKA"
rgroup.long 0x4++0x3
line.long 0x0 "PKA_SR,PKA_SR register"
bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No Address error,1: Address access is out of range"
bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occured while the.."
newline
bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed"
bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress,1: An operation is in progress"
group.long 0x8++0x3
line.long 0x0 "PKA_CLRFR,PKA_CLRFR register"
bitfld.long 0x0 20. "ADDRERRFC,Clear Address error flag" "0: No action,1: Clear the ADDRERRF flag"
bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag"
newline
bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag"
endif
sif (cpuis("STM32WB06*"))
group.long 0x0++0xB
line.long 0x0 "PKA_CSR,PKA_CSR register"
bitfld.long 0x0 7. "SFT_RST,PKA software reset." "0,1"
rbitfld.long 0x0 1. "READY,PKA readiness status." "0: The PKA is still computing,1: The PKA is ready to start a new calculation"
newline
bitfld.long 0x0 0. "GO,PKA start processing command." "0,1"
line.long 0x4 "PKA_ISR,PKA_ISR register"
bitfld.long 0x4 3. "ADD_ERR,AHB Address error interrupt." "0,1"
bitfld.long 0x4 2. "RAM_ERR,RAM read / write access error interrupt." "0,1"
newline
bitfld.long 0x4 0. "PROC_END,PKA process ending interrupt. When read:" "0: No new event detected,1: The PKA process is ended"
line.long 0x8 "PKA_IEN,PKA_IEN register"
bitfld.long 0x8 3. "ADDERR_EN,AHB Address error interrupt enable." "0,1"
bitfld.long 0x8 2. "RAMERR_EN,RAM access error interrupt enable." "0,1"
newline
bitfld.long 0x8 0. "READY_EN,READY interrupt enable." "0,1"
endif
sif (cpuis("STM32WB07*"))
group.long 0x0++0xB
line.long 0x0 "PKA_CSR,PKA_CSR register"
bitfld.long 0x0 7. "SFT_RST,PKA software reset." "0,1"
rbitfld.long 0x0 1. "READY,PKA readiness status." "0: The PKA is still computing,1: The PKA is ready to start a new calculation"
newline
bitfld.long 0x0 0. "GO,PKA start processing command." "0,1"
line.long 0x4 "PKA_ISR,PKA_ISR register"
bitfld.long 0x4 3. "ADD_ERR,AHB Address error interrupt." "0,1"
bitfld.long 0x4 2. "RAM_ERR,RAM read / write access error interrupt." "0,1"
newline
bitfld.long 0x4 0. "PROC_END,PKA process ending interrupt. When read:" "0: No new event detected,1: The PKA process is ended"
line.long 0x8 "PKA_IEN,PKA_IEN register"
bitfld.long 0x8 3. "ADDERR_EN,AHB Address error interrupt enable." "0,1"
bitfld.long 0x8 2. "RAMERR_EN,RAM access error interrupt enable." "0,1"
newline
bitfld.long 0x8 0. "READY_EN,READY interrupt enable." "0,1"
endif
sif (cpuis("STM32WB09*"))
group.long 0x0++0x3
line.long 0x0 "PKA_CR,PKA_CR register"
bitfld.long 0x0 23. "FAULTERRORCODEIE,Fault error code interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when FAULTERRORCODEF"
bitfld.long 0x0 22. "FAULTFSMIE,Fault FSM interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when FAULTFSMF"
newline
bitfld.long 0x0 20. "ADDRERRIE,Address error interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when ADDRERRF"
bitfld.long 0x0 19. "RAMERRIE,RAM error interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when RAMERRF"
newline
bitfld.long 0x0 17. "PROCENDIE,End of operation interrupt enable" "0: Interrupt is disabled,1: An interrupt is generated when PROCENDF"
hexmask.long.byte 0x0 8.--13. 1. "MODE,PKA operation code"
newline
bitfld.long 0x0 2. "SECLVL,Security enable." "0: No side channel countermeasure,1: Square and Multiply always / Double and Add always"
bitfld.long 0x0 1. "START,Start the operation" "0: No operation,1: Writing '1' to this bit starts the operation.."
newline
bitfld.long 0x0 0. "EN,Peripheral enable." "0: Disable PKA,1: Enable PKA"
rgroup.long 0x4++0x3
line.long 0x0 "PKA_SR,PKA_SR register"
bitfld.long 0x0 23. "FAULTERRORCODEF,Fault error code error flag" "0: No fault has been detected,1: A fault has altered the execution of the.."
bitfld.long 0x0 22. "FAULTFSMF,Fault fsm error flag" "0: No fault has been detected,1: A fault on fsm has been detected"
newline
bitfld.long 0x0 20. "ADDRERRF,Address error flag" "0: No Address error,1: Address access is out of range"
bitfld.long 0x0 19. "RAMERRF,PKA RAM error flag" "0: No PKA RAM access error,1: An AHB access to the PKA RAM occured while the.."
newline
bitfld.long 0x0 17. "PROCENDF,PKA End of Operation flag" "0: Operation in progress,1: PKA operation is completed"
bitfld.long 0x0 16. "BUSY,PKA operation is in progress" "0: No operation is in progress,1: An operation is in progress"
group.long 0x8++0x3
line.long 0x0 "PKA_CLRFR,PKA_CLRFR register"
bitfld.long 0x0 20. "ADDRERRFC,Clear Address error flag" "0: No action,1: Clear the ADDRERRF flag"
bitfld.long 0x0 19. "RAMERRFC,Clear PKA RAM error flag" "0: No action,1: Clear the RAMERRF flag"
newline
bitfld.long 0x0 17. "PROCENDFC,Clear PKA End of Operation flag" "0: No action,1: Clear the PROCENDF flag"
endif
tree.end
tree "PWRC (Power Controller)"
base ad:0x48500000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 8. "ENBORL,ENBORL: Enable BORL reset supervising during RUN mode." "0: No BORL is monitored during RUN mode,1: BORL is monitored during RUN mode"
bitfld.long 0x0 6.--7. "SELBORH,SELBORH[1:0]: BORH selection of Vbor threshold" "0: BORH Level 1 (VBOR1): threshold level for above..,1: BORH Level 2 (VBOR2): threshold level for above..,2: BORH Level 3 (VBOR3): threshold level for above..,3: BORH Level 4(VBOR4): threshold level for above.."
newline
bitfld.long 0x0 5. "ENBORH,ENBORH: enable BORH configuration" "0: BORH off (VBOR0): threshold level for above..,1: BORH is enabled threshold level depends on.."
bitfld.long 0x0 3. "IBIAS_RUN_STATE,IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is" "0: IBIAS control is disabled,1: IBIAS control is enabled"
newline
bitfld.long 0x0 2. "IBIAS_RUN_AUTO,IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode." "0: IBIAS control is manual,1: IBIAS control is automatic"
bitfld.long 0x0 1. "ENSDNBOR,ENSDNBOR: Enable BOR supply monitoring during shutdown mode." "0: the PD_ALL_SHUTDOWN signal is set during..,1: the PD_ALL_SHUTDOWN signal is not set during.."
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 8. "ENBORL,ENBORL: Enable BORL reset supervising during RUN mode." "0: No BORL is monitored during RUN mode,1: BORL is monitored during RUN mode"
bitfld.long 0x0 6.--7. "SELBORH,SELBORH[1:0]: BORH selection of Vbor threshold" "0: BORH Level 1 (VBOR1): threshold level for above..,1: BORH Level 2 (VBOR2): threshold level for above..,2: BORH Level 3 (VBOR3): threshold level for above..,3: BORH Level 4(VBOR4): threshold level for above.."
newline
bitfld.long 0x0 5. "ENBORH,ENBORH: enable BORH configuration" "0: BORH off (VBOR0): threshold level for above..,1: BORH is enabled threshold level depends on.."
newline
endif
bitfld.long 0x0 4. "APC,APC Apply Pull-up and pull-down configuration from CPU" "0: the PUCRx and PDCRx are not used to control the..,1: the I/O pull-up and pull-down configurations.."
newline
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 3. "IBIAS_RUN_STATE,IBIAS_RUN_STATE: Enable/Disable IBIAS during RUN mode when automatic mode is" "0: IBIAS control is disabled,1: IBIAS control is enabled"
bitfld.long 0x0 2. "IBIAS_RUN_AUTO,IBIAS_RUN_AUTO: Enable automatic IBIAS control during RUN/DEEPSTOP mode." "0: IBIAS control is manual,1: IBIAS control is automatic"
newline
bitfld.long 0x0 1. "ENSDNBOR,ENSDNBOR: Enable BOR supply monitoring during shutdown mode." "0: the PD_ALL_SHUTDOWN signal is set during..,1: the PD_ALL_SHUTDOWN signal is not set during.."
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 1. "ENSDNBOR,Enable BOR reset supervising during SHUTDOWN mode." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 1. "ENSDNBOR,Enable BOR reset supervising during SHUTDOWN mode." "0,1"
newline
endif
bitfld.long 0x0 0. "LPMS,LPMS Low Power Mode Selection" "0: Deep Stop mode (default),1: Shutdown mode"
line.long 0x4 "CR2,CR2 register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 10. "LSILPMUFEN,LSI LPMU force enable." "0,1"
bitfld.long 0x4 9. "ENTS,Enable the temperature sensor." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 10. "LSILPMUFEN,LSI LPMU force enable." "0,1"
bitfld.long 0x4 9. "ENTS,Enable the temperature sensor." "0,1"
newline
endif
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 9. "ENTS,ENTS: Enable Temperature Sensor" "0: Temperature sensor is disabled,1: Temperature sensor is enabled"
bitfld.long 0x4 8. "GPIORET,GPIORET: GPIO retention enable." "0: GPIO don't retain their status during DEEPSTOP..,1: GPIO retain their status during DEEPSTOP and.."
newline
bitfld.long 0x4 4. "DBGRET,DBGRET: PA2 and PA3 retention enable after DEEPSTOP" "0: PA2,1: PA2"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 9. "ENTS,ENTS: Enable Temperature Sensor" "0: Temperature sensor is disabled,1: Temperature sensor is enabled"
newline
bitfld.long 0x4 8. "GPIORET,GPIORET: GPIO retention enable." "0: GPIO don't retain their status during DEEPSTOP..,1: GPIO retain their status during DEEPSTOP and.."
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 7. "RAMRET3,Enables the RAM3 bank retention in DEEPSTOP mode." "0: Temperature sensor is disabled,1: Temperature sensor is enabled"
newline
bitfld.long 0x4 6. "RAMRET2,Enables the RAM2 bank retention in DEEPSTOP mode." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 7. "RAMRET3,Enables the RAM3 bank retention in DEEPSTOP mode." "0: Temperature sensor is disabled,1: Temperature sensor is enabled"
newline
bitfld.long 0x4 6. "RAMRET2,Enables the RAM2 bank retention in DEEPSTOP mode." "0,1"
newline
endif
bitfld.long 0x4 5. "RAMRET1,RAMRET1: RAM1 retention during low power mode" "0: RAM1 bank is disabled during low power mode (by..,1: RAM1 bank is powered during low power mode"
newline
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 4. "DBGRET,DBGRET: PA2 and PA3 retention enable after DEEPSTOP" "0: PA2,1: PA2"
newline
endif
bitfld.long 0x4 1.--3. "PVDLS,PVDLS[2:0] Programmable Voltage Detector Level selection" "0: 2.05 V - Lowest level,1: 2.20 V,2: 2.36 V,3: 2.52 V,4: 2.64 V,5: 2.81 V,6: 2.91 V - Highest level,7: External input analog voltage (compare.."
newline
bitfld.long 0x4 0. "PVDE,PVDE Programmable Voltage Detector Enable" "0,1"
line.long 0x8 "CR3,CR3 register"
bitfld.long 0x8 15. "EIWL,EIWL: Enable wakeup on Internal event (RTC)." "0: Wakeup on internal line is disabled,1: Wakeup on internal line is enabled"
sif (cpuis("STM32WB05*"))
bitfld.long 0x8 14. "EIWL2,EIWL2: Enable wakeup on Internal event (LPUART)." "0: Wakeup on internal line is disabled,1: Wakeup on internal line is enabled"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 14. "EIWL2,EIWL2: Enable wakeup on Internal event (LPUART)." "0: Wakeup on internal line is disabled,1: Wakeup on internal line is enabled"
newline
endif
bitfld.long 0x8 13. "EWBLEHCPU,EWBLEHCPU: Enable wakeup on BLE Host CPU event." "0: Wakeup on BLE Host CPU line is disabled,1: Wakeup on BLE Host CPU line is enabled"
newline
bitfld.long 0x8 12. "EWBLE,EWBLE: Enable wakeup on BLE event." "0: Wakeup on BLE line is disabled,1: Wakeup on BLE line is enabled"
bitfld.long 0x8 11. "EWU11,EWU11 Enable WakeUp line 11 (PA11)" "0,1"
newline
bitfld.long 0x8 10. "EWU10,EWU10 Enable WakeUp line 10 (PA10)" "0,1"
bitfld.long 0x8 9. "EWU9,EWU9 Enable WakeUp line 9 (PA9)" "0,1"
newline
bitfld.long 0x8 8. "EWU8,EWU8 Enable WakeUp line 8 (PA8)" "0,1"
bitfld.long 0x8 7. "EWU7,EWU7 Enable WakeUp line 7 (PB7)" "0,1"
newline
bitfld.long 0x8 6. "EWU6,EWU6 Enable WakeUp line 6 (PB6)" "0,1"
bitfld.long 0x8 5. "EWU5,EWU5 Enable WakeUp line 5 (PB5)" "0,1"
newline
bitfld.long 0x8 4. "EWU4,EWU4 Enable WakeUp line 4 (PB4)" "0,1"
bitfld.long 0x8 3. "EWU3,EWU3 Enable WakeUp line 3 (PB3)" "0,1"
newline
bitfld.long 0x8 2. "EWU2,EWU2 Enable WakeUp line 2 (PB2)" "0,1"
bitfld.long 0x8 1. "EWU1,EWU1 Enable WakeUp line 1 (PB1)" "0,1"
newline
bitfld.long 0x8 0. "EWU0,EWU0 Enable WakeUp line 0 (PB0)" "0,1"
line.long 0xC "CR4,CR4 register"
bitfld.long 0xC 11. "WUP11,WUP11 Wake-up Line Polarity 11 (PA11)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 10. "WUP10,WUP10 Wake-up Line Polarity 10 (PA10)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 9. "WUP9,WUP9 Wake-up Line Polarity 9 (PA9)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 8. "WUP8,WUP8 Wake-up Line Polarity 8 (PA8)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 7. "WUP7,WUP7 Wake-up Line Polarity 7 (PB7)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 6. "WUP6,WUP6 Wake-up Line Polarity 6 (PB6)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 5. "WUP5,WUP5 Wake-up Line Polarity 5 (PB5)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 4. "WUP4,WUP4 Wake-up Line Polarity 4 (PB4)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 3. "WUP3,WUP3 Wake-up Line Polarity 3 (PB3)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 2. "WUP2,WUP2 Wake-up Line Polarity 2 (PB2)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 1. "WUP1,WUP1 Wake-up Line Polarity 1 (PB1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 0. "WUP0,WUP0 Wake-up Line Polarity 0 (PB0)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
line.long 0x10 "SR1,SR1 register"
rbitfld.long 0x10 15. "IWUF,IWUF: Internal wakeup flag (RTC)." "0: no wakeup from RTC occurred since last clear,1: a wakeup from RTC occurred since last clear"
sif (cpuis("STM32WB05*"))
rbitfld.long 0x10 14. "IWUF2,IWUF2: Internal wakeup 2 flag (LPUART)." "0: no wakeup from LPUART occurred since last clear,1: a wakeup from LPUART occurred since last clear"
newline
endif
sif (cpuis("STM32WB09*"))
rbitfld.long 0x10 14. "IWUF2,IWUF2: Internal wakeup 2 flag (LPUART)." "0: no wakeup from LPUART occurred since last clear,1: a wakeup from LPUART occurred since last clear"
newline
endif
bitfld.long 0x10 13. "WBLEHCPUF,WBLEHCPUF: BLE Host CPU wakeup flag." "0: no wakeup from BLE Host CPU occurred since last..,1: a wakeup from BLE Host CPU occurred since last.."
newline
bitfld.long 0x10 12. "WBLEF,WBLEF: BLE wakeup flag." "0: no wakeup from BLE occurred since last clear,1: a wakeup from BLE occurred since last clear"
bitfld.long 0x10 11. "WUF11,WUF11 WakeUp Flag 11 (PA11)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 10. "WUF10,WUF10 WakeUp Flag 10 (PA10)" "0: no effect,1: clear the interrupt"
bitfld.long 0x10 9. "WUF9,WUF9 WakeUp Flag 9 (PA9)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 8. "WUF8,WUF8 WakeUp Flag 8 (PA8)" "0: no effect,1: clear the interrupt"
bitfld.long 0x10 7. "WUF7,WUF7 WakeUp Flag 7 (PB7)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 6. "WUF6,WUF6 WakeUp Flag 6 (PB6)" "0: no effect,1: clear the interrupt"
bitfld.long 0x10 5. "WUF5,WUF5 WakeUp Flag 5 (PB5)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 4. "WUF4,WUF4 WakeUp Flag 4 (PB4)" "0: no effect,1: clear the interrupt"
bitfld.long 0x10 3. "WUF3,WUF3 WakeUp Flag 3 (PB3)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 2. "WUF2,WUF2 WakeUp Flag 2 (PB2)" "0: no effect,1: clear the interrupt"
bitfld.long 0x10 1. "WUF1,WUF1 WakeUp Flag 1 (PB1)" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x10 0. "WUF0,WUF0 WakeUp Flag 0 (PB0)" "0: no effect,1: clear the interrupt"
rgroup.long 0x14++0x3
line.long 0x0 "SR2,SR2 register"
hexmask.long.byte 0x0 12.--15. 1. "IOBOOTVAL,Bit3: PA11 input value on VDD33 latched at POR"
bitfld.long 0x0 11. "PVDO,PVDO: Power Voltage Detector Output" "0,1"
newline
bitfld.long 0x0 9. "REGMS,REGMS: Regulator Main LDO Started" "0: Main regulator is not ready.,1: Main regulator is ready."
bitfld.long 0x0 8. "REGLPS,REGLPS: Regulator Low Power Started" "0: LP regulator is not ready.,1: LP regulator is ready."
newline
sif (cpuis("STM32WB05*"))
hexmask.long.byte 0x0 4.--7. 1. "IOBOOTVAL2,Bit3: PB15 input value on VDD33 latched at POR"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.byte 0x0 4.--7. 1. "IOBOOTVAL2,Bit3: PB15 input value on VDD33 latched at POR"
newline
endif
bitfld.long 0x0 2. "SMPSRDY,SMPSRDY: SMPS Ready Status" "0: SMPS regulator is not ready,1: SMPS regulator is ready."
bitfld.long 0x0 1. "SMPSENR,SMPSENR: SMPS Enable Control Replica" "0,1"
newline
bitfld.long 0x0 0. "SMPSBYPR,SMPSBYPR: SMPS Force Bypass Control Replica" "0,1"
group.long 0x1C++0x1F
line.long 0x0 "CR5,CR5 register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 13.--14. "SMPS_PRECH_CUR_SEL,SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current" "0: 2.5mA,1: 5mA,2: 10mA,3: 20mA (default)"
bitfld.long 0x0 7. "SMPSFRDY,SMPSFB Force ready check" "0: no effect (by default),1: SMPS is considered READY"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 13.--14. "SMPS_PRECH_CUR_SEL,SMPS_PRECH_CUR_SEL[1:0] Selection for SMPS PRECHARGE limit current" "0: 2.5mA,1: 5mA,2: 10mA,3: 20mA (default)"
newline
endif
bitfld.long 0x0 12. "CLKDETR_DISABLE,CLKDETR_DISABLE: disable SMPS clock detection" "0: SMPS clock detection enabled (default),1: SMPS clock detection disabled"
newline
bitfld.long 0x0 11. "SMPS_ENA_DCM,SMPS_ENA_DCM: enable discontinuous conduction mode" "0: disable,1: enable"
bitfld.long 0x0 10. "NOSMPS,NOSMPS: No SMPS Mode" "0: No effect SMPS is enabled.,1: SMPS is disabled;"
newline
bitfld.long 0x0 9. "SMPSFBYP,SMPSFB Force SMPS Regulator in bypass mode" "0: no effect (by default),1: SMPS is disabled and bypassed (ENABLE_3V3=0 and.."
bitfld.long 0x0 8. "SMPSLPOPEN,SMPSLPOPEN: In Low Power mode SMPS is in OPEN mode (instead of PRECHARGE mode)." "0: in Low Power mode SMPS is in PRECHARGE output..,1: in Low Power mode SMPS is disabled output is.."
newline
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 7. "SMPSFRDY,SMPSFB Force ready check" "0: no effect (by default),1: SMPS is considered READY"
newline
endif
bitfld.long 0x0 4.--5. "SMPSBOMSEL,SMPSBOMSEL: SMPS BOM Selection:" "0: BOM1,1: BOM2 (default),2: BOM3,3: n/a"
newline
hexmask.long.byte 0x0 0.--3. 1. "SMPSLVL,SMPSLVL[3:0] SMPS Output Level Voltage Selection"
line.long 0x4 "PUCRA,PUCRA register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0x4 0.--15. 1. "PU,PU[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x4 0.--15. 1. "PUA,PUA[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x4 0.--15. 1. "PUA,PUA[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.word 0x4 0.--15. 1. "PU,PU[x] : Pull Up"
newline
endif
line.long 0x8 "PDCRA,PDCRA register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0x8 0.--15. 1. "PD,PD[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x8 0.--15. 1. "PDA,PDA[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x8 0.--15. 1. "PDA,PDA[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.word 0x8 0.--15. 1. "PD,PD[x]: Pull Down"
newline
endif
line.long 0xC "PUCRB,PUCRB register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0xC 0.--15. 1. "PU,PU[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0xC 0.--15. 1. "PUB,PUB[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0xC 0.--15. 1. "PUB,PUB[x] : Pull Up"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.word 0xC 0.--15. 1. "PU,PU[x] : Pull Up"
newline
endif
line.long 0x10 "PDCRB,PDCRB register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0x10 0.--15. 1. "PD,PD[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x10 0.--15. 1. "PDB,PDB[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x10 0.--15. 1. "PDB,PDB[x]: Pull Down"
newline
endif
sif (cpuis("STM32WB09*"))
hexmask.long.word 0x10 0.--15. 1. "PD,PD[x]: Pull Down"
newline
endif
line.long 0x14 "CR6,CR6 register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x14 15. "EWU27,Enable wakeup on PA15 I/O event." "0,1"
bitfld.long 0x14 14. "EWU26,Enable wakeup on PA14 I/O event." "0,1"
newline
bitfld.long 0x14 13. "EWU25,Enable wakeup on PA13 I/O event." "0,1"
bitfld.long 0x14 12. "EWU24,Enable wakeup on PA12 I/O event." "0,1"
newline
bitfld.long 0x14 11. "EWU23,Enable wakeup on PB11 I/O event." "0,1"
bitfld.long 0x14 10. "EWU22,Enable wakeup on PB10 I/O event." "0,1"
newline
bitfld.long 0x14 9. "EWU21,Enable wakeup on PB9 I/O event." "0,1"
bitfld.long 0x14 8. "EWU20,Enable wakeup on PB8 I/O event." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x14 15. "EWU27,Enable wakeup on PA15 I/O event." "0,1"
bitfld.long 0x14 14. "EWU26,Enable wakeup on PA14 I/O event." "0,1"
newline
bitfld.long 0x14 13. "EWU25,Enable wakeup on PA13 I/O event." "0,1"
bitfld.long 0x14 12. "EWU24,Enable wakeup on PA12 I/O event." "0,1"
newline
bitfld.long 0x14 11. "EWU23,Enable wakeup on PB11 I/O event." "0,1"
bitfld.long 0x14 10. "EWU22,Enable wakeup on PB10 I/O event." "0,1"
newline
bitfld.long 0x14 9. "EWU21,Enable wakeup on PB9 I/O event." "0,1"
bitfld.long 0x14 8. "EWU20,Enable wakeup on PB8 I/O event." "0,1"
newline
endif
bitfld.long 0x14 7. "EWU19,EWU19 Enable WakeUp line 19 (PB15)" "0,1"
bitfld.long 0x14 6. "EWU18,EWU18 Enable WakeUp line 18 (PB14)" "0,1"
newline
bitfld.long 0x14 5. "EWU17,EWU17 Enable WakeUp line 17 (PB13)" "0,1"
bitfld.long 0x14 4. "EWU16,EWU16 Enable WakeUp line 16 (PB12)" "0,1"
newline
bitfld.long 0x14 3. "EWU15,EWU15 Enable WakeUp line 15 (PA3)" "0,1"
bitfld.long 0x14 2. "EWU14,EWU14 Enable WakeUp line 14 (PA2)" "0,1"
newline
bitfld.long 0x14 1. "EWU13,EWU13 Enable WakeUp line 13 (PA1)" "0,1"
bitfld.long 0x14 0. "EWU12,EWU12 Enable WakeUp line 12 (PA0)" "0,1"
line.long 0x18 "CR7,CR7 register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x18 15. "WUP27,Wake-up polarity for PB15 IO event." "0,1"
bitfld.long 0x18 14. "WUP26,Wake-up polarity for PB14 IO event." "0,1"
newline
bitfld.long 0x18 13. "WUP25,Wake-up polarity for PB13 IO event." "0,1"
bitfld.long 0x18 12. "WUP24,Wake-up polarity for PB12 IO event." "0,1"
newline
bitfld.long 0x18 11. "WUP23,Wake-up polarity for PB11 IO event." "0,1"
bitfld.long 0x18 10. "WUP22,Wake-up polarity for PB10 IO event." "0,1"
newline
bitfld.long 0x18 9. "WUP21,Wake-up polarity for PB9 IO event." "0,1"
bitfld.long 0x18 8. "WUP20,Wake-up polarity for PB8 IO event." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x18 15. "WUP27,Wake-up polarity for PB15 IO event." "0,1"
bitfld.long 0x18 14. "WUP26,Wake-up polarity for PB14 IO event." "0,1"
newline
bitfld.long 0x18 13. "WUP25,Wake-up polarity for PB13 IO event." "0,1"
bitfld.long 0x18 12. "WUP24,Wake-up polarity for PB12 IO event." "0,1"
newline
bitfld.long 0x18 11. "WUP23,Wake-up polarity for PB11 IO event." "0,1"
bitfld.long 0x18 10. "WUP22,Wake-up polarity for PB10 IO event." "0,1"
newline
bitfld.long 0x18 9. "WUP21,Wake-up polarity for PB9 IO event." "0,1"
bitfld.long 0x18 8. "WUP20,Wake-up polarity for PB8 IO event." "0,1"
newline
endif
bitfld.long 0x18 7. "WUP19,WUP19 Wake-up Line Polarity 19 (PB15)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0x18 6. "WUP18,WUP18 Wake-up Line Polarity 18 (PB14)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0x18 5. "WUP17,WUP17 Wake-up Line Polarity 17 (PB13)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0x18 4. "WUP16,WUP16 Wake-up Line Polarity 16 (PB12)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0x18 3. "WUP15,WUP15 Wake-up Line Polarity 15 (PA3)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0x18 2. "WUP14,WUP14 Wake-up Line Polarity 14 (PA2)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0x18 1. "WUP13,WUP13 Wake-up Line Polarity 13 (PA1)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0x18 0. "WUP12,WUP12 Wake-up Line Polarity 12 (PA0)" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
line.long 0x1C "SR3,SR3 register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x1C 15. "WUF27,PB15 I/O wake-up flag." "0,1"
bitfld.long 0x1C 14. "WUF26,PB14 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 13. "WUF25,PB13 I/O wake-up flag." "0,1"
bitfld.long 0x1C 12. "WUF24,PB12 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 11. "WUF23,PB11 I/O wake-up flag." "0,1"
bitfld.long 0x1C 10. "WUF22,PB10 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 9. "WUF21,PB9 I/O wake-up flag." "0,1"
bitfld.long 0x1C 8. "WUF20,PB8 I/O wake-up flag." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x1C 15. "WUF27,PB15 I/O wake-up flag." "0,1"
bitfld.long 0x1C 14. "WUF26,PB14 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 13. "WUF25,PB13 I/O wake-up flag." "0,1"
bitfld.long 0x1C 12. "WUF24,PB12 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 11. "WUF23,PB11 I/O wake-up flag." "0,1"
bitfld.long 0x1C 10. "WUF22,PB10 I/O wake-up flag." "0,1"
newline
bitfld.long 0x1C 9. "WUF21,PB9 I/O wake-up flag." "0,1"
bitfld.long 0x1C 8. "WUF20,PB8 I/O wake-up flag." "0,1"
newline
endif
bitfld.long 0x1C 7. "WUF19,WUF19 WakeUp Flag 19 PB15" "0: no effect,1: clear the interrupt"
bitfld.long 0x1C 6. "WUF18,WUF18 WakeUp Flag 18 PB14" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x1C 5. "WUF17,WUF17 WakeUp Flag 17 PB13" "0: no effect,1: clear the interrupt"
bitfld.long 0x1C 4. "WUF16,WUF16 WakeUp Flag 16 PB12" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x1C 3. "WUF15,WUF15 WakeUp Flag 15 PA3" "0: no effect,1: clear the interrupt"
bitfld.long 0x1C 2. "WUF14,WUF14 WakeUp Flag 14 PA2" "0: no effect,1: clear the interrupt"
newline
bitfld.long 0x1C 1. "WUF13,WUF13 WakeUp Flag 13 PA1" "0: no effect,1: clear the interrupt"
bitfld.long 0x1C 0. "WUF12,WUF12 WakeUp Flag 12 PA0" "0: no effect,1: clear the interrupt"
sif (cpuis("STM32WB06*"))
group.long 0x40++0x3
line.long 0x0 "IOxCFG,IOxCFG register"
bitfld.long 0x0 14.--15. "IOCFG7,Drive configuration for PA7." "0,1,2,3"
bitfld.long 0x0 12.--13. "IOCFG6,Drive configuration for PA6." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "IOCFG5,Drive configuration for PA5." "0,1,2,3"
bitfld.long 0x0 8.--9. "IOCFG4,Drive configuration for PA4." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "IOCFG3,Drive configuration for PA11." "0,1,2,3"
bitfld.long 0x0 4.--5. "IOCFG2,Drive configuration for PA10." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "IOCFG1,Drive configuration for PA9." "0,1,2,3"
bitfld.long 0x0 0.--1. "IOCFG0,Drive configuration for PA8." "0,1,2,3"
newline
endif
sif (cpuis("STM32WB07*"))
group.long 0x40++0x3
line.long 0x0 "IOxCFG,IOxCFG register"
bitfld.long 0x0 14.--15. "IOCFG7,Drive configuration for PA7." "0,1,2,3"
bitfld.long 0x0 12.--13. "IOCFG6,Drive configuration for PA6." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "IOCFG5,Drive configuration for PA5." "0,1,2,3"
bitfld.long 0x0 8.--9. "IOCFG4,Drive configuration for PA4." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "IOCFG3,Drive configuration for PA11." "0,1,2,3"
bitfld.long 0x0 4.--5. "IOCFG2,Drive configuration for PA10." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "IOCFG1,Drive configuration for PA9." "0,1,2,3"
bitfld.long 0x0 0.--1. "IOCFG0,Drive configuration for PA8." "0,1,2,3"
newline
endif
group.long 0x84++0x7
line.long 0x0 "DBGR,DBGR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 13.--15. "DIS_PRECH,DIS_PRECH[2:0]: disable precharge during deepstop (debug)" "0,1,2,3,4,5,6,7"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 13.--15. "DIS_PRECH,DIS_PRECH[2:0]: disable precharge during deepstop (debug)" "0,1,2,3,4,5,6,7"
newline
endif
bitfld.long 0x0 0. "DEEPSTOP2,DEEPSTOP2: DEEPSTOP2 low power saving emulation enable." "0: normal DEEPSTOP will be applied,1: DEEPSTOP2"
line.long 0x4 "EXTSRR,EXTSRR register"
bitfld.long 0x4 10. "RFPHASEF,RFPHASEF RFPHASE Flag" "0: RF IP does not require attention,1: RF IP awake and requesting system attention"
bitfld.long 0x4 9. "DEEPSTOPF,DEEPSTOPF System DeepStop Flag" "0: System has not been in DEEPSTOP mode,1: System has been in DEEPSTOP mode"
tree.end
tree "RADIO"
base ad:0x0
sif (cpuis("STM32WB05*"))
tree "RADIO_CONTROL_REG"
base ad:0x60001000
rgroup.long 0x0++0x3
line.long 0x0 "RADIO_CONTROL_ID,RADIO_CONTROL_ID register"
hexmask.long.byte 0x0 12.--15. 1. "PRODUCT,incremented on major features add-on like new Bluetooth LE SIG version support"
hexmask.long.byte 0x0 8.--11. 1. "VERSION,Cut Number"
hexmask.long.byte 0x0 4.--7. 1. "REVISION,Incremented for metal fix version"
group.long 0x4++0x3
line.long 0x0 "CLK32COUNT_REG,CLK32COUNT_REG register"
hexmask.long.word 0x0 0.--8. 1. "SLOW_COUNT,program the window length (in slow clock period) for slow clock measurement."
rgroup.long 0x8++0x7
line.long 0x0 "CLK32PERIOD_REG,CLK32PERIOD_REG register"
hexmask.long.tbyte 0x0 0.--18. 1. "SLOW_PERIOD,indicates slow clock period information."
line.long 0x4 "CLK32FREQUENCY_REG,CLK32FREQUENCY_REG register"
hexmask.long 0x4 0.--26. 1. "SLOW_FREQUENCY,value equal to (2^39/ SLOW_PERIOD)."
group.long 0x10++0x7
line.long 0x0 "RADIO_CONTROL_IRQ_STATUS,RADIO_CONTROL_IRQ_STATUS register"
hexmask.long.byte 0x0 8.--13. 1. "RADIO_FSM_IRQ,Radio FSM interrupt status (aka RfFsm_event_irq)."
bitfld.long 0x0 0. "SLOW_CLK_IRQ,slow clock measurement end of calculation interrupt status" "0,1"
line.long 0x4 "RADIO_CONTROL_IRQ_ENABLE,RADIO_CONTROL_IRQ_ENABLE register"
hexmask.long.byte 0x4 8.--13. 1. "RADIO_FSM_IRQ_MASK,mask for each RfFsm_event (Radio FSM) interrupt."
bitfld.long 0x4 0. "SLOW_CLK_IRQ_MASK,mask slow clock measurement interrupt" "0,1"
tree.end
endif
sif (cpuis("STM32WB05*"))
tree "RADIO_REG_REG"
base ad:0x60001500
group.long 0x0++0x1B
line.long 0x0 "AA0_DIG_USR,AA0_DIG_USR register"
hexmask.long.byte 0x0 0.--7. 1. "AA_7_0,Least significant byte of the Bluetooth LE Access Address code"
line.long 0x4 "AA1_DIG_USR,AA1_DIG_USR register"
hexmask.long.byte 0x4 0.--7. 1. "AA_15_8,Next byte of the Bluetooth LE Access Address code."
line.long 0x8 "AA2_DIG_USR,AA2_DIG_USR register"
hexmask.long.byte 0x8 0.--7. 1. "AA_23_16,Next byte of the Bluetooth LE Access Address code"
line.long 0xC "AA3_DIG_USR,AA3_DIG_USR register"
hexmask.long.byte 0xC 0.--7. 1. "AA_31_24,Most significant byte of the Bluetooth LE Access Address code."
line.long 0x10 "DEM_MOD_DIG_USR,DEM_MOD_DIG_USR register"
hexmask.long.byte 0x10 1.--7. 1. "CHANNEL_NUM,Index for internal lock up table in which the synthesizer setup is contained."
line.long 0x14 "RADIO_FSM_USR,RADIO_FSM_USR register"
hexmask.long.byte 0x14 3.--7. 1. "PA_POWER,PA Power coefficient."
bitfld.long 0x14 2. "EN_CALIB_SYNTH,SYNTH calibration enable bit." "0,1"
bitfld.long 0x14 1. "EN_CALIB_CBP,CBP calibration enable bit." "0,1"
line.long 0x18 "PHYCTRL_DIG_USR,PHYCTRL_DIG_USR register"
bitfld.long 0x18 0.--2. "RXTXPHY,RXTXPHY selection." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "AFC1_DIG_ENG,AFC1_DIG_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "AFC_DELAY_BEFORE,Set the decay factor of the AFC loop before Access Address detection"
hexmask.long.byte 0x0 0.--3. 1. "AFC_DELAY_AFTER,Set the decay factor of the AFC loop after Access Address detection"
group.long 0x54++0x3
line.long 0x0 "CR0_DIG_ENG,CR0_DIG_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "CR_GAIN_BEFORE,Set the gain of the clock recovery loop before Access Address detection to the value"
hexmask.long.byte 0x0 0.--3. 1. "CR_GAIN_AFTER,Set the gain of the clock recovery loop before Access Address detection to the value"
group.long 0x68++0x7
line.long 0x0 "CR0_LR,CR0_LR register"
hexmask.long.byte 0x0 4.--7. 1. "CR_LR_GAIN_BEFORE,Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use"
hexmask.long.byte 0x0 0.--3. 1. "CR_LR_GAIN_AFTER,Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use"
line.long 0x4 "VIT_CONF_DIG_ENG,VIT_CONF_DIG_ENG register"
hexmask.long.byte 0x4 2.--7. 1. "SPARE,spare"
bitfld.long 0x4 0. "VIT_EN,Viterbi enable" "0,1"
group.long 0x84++0xB
line.long 0x0 "LR_PD_THR_DIG_ENG,LR_PD_THR_DIG_ENG register"
hexmask.long.byte 0x0 0.--7. 1. "LR_PD_THR,preamble detect threshold value"
line.long 0x4 "LR_RSSI_THR_DIG_ENG,LR_RSSI_THR_DIG_ENG register"
hexmask.long.byte 0x4 0.--7. 1. "LR_RSSI_THR,RSSI or peak threshold value"
line.long 0x8 "LR_AAC_THR_DIG_ENG,LR_AAC_THR_DIG_ENG register"
hexmask.long.byte 0x8 0.--7. 1. "LR_AAC_THR,address coded correlation threshold"
group.long 0xA8++0x3
line.long 0x0 "SYNTHCAL0_DIG_ENG,SYNTHCAL0_DIG_ENG register"
bitfld.long 0x0 6.--7. "SYNTH_IF_FREQ_CAL,Define the frequency applied on the PLL during calibration phase" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "SYNTHCAL_DEBUG_BUS_SEL,for Debug purpose"
group.long 0xF0++0x3
line.long 0x0 "DTB5_DIG_ENG,DTB5_DIG_ENG register"
bitfld.long 0x0 5. "PORT_SELECTED_0,force port_selected[0] signal" "0,1"
bitfld.long 0x0 4. "PORT_SELECTED_EN,enable port selection" "0,1"
bitfld.long 0x0 3. "INITIALIZE,Force INITIALIZE signal (emulate a token request of the IP_BLE)" "0,1"
bitfld.long 0x0 2. "RX_ACTIVE,Force RX_ACTIVE signal" "0,1"
newline
bitfld.long 0x0 1. "TX_ACTIVE,Force TX_ACTIVE signal" "0,1"
bitfld.long 0x0 0. "RXTX_START_SEL,enable the possibility to control some signals by the other register bits instead of system design:" "0,1"
group.long 0x148++0x3
line.long 0x0 "RXADC_ANA_USR,RXADC_ANA_USR register"
bitfld.long 0x0 7. "RXADC_DELAYTRIM_Q_TST_SEL,Enable the SW overload on RXADX delay trimming" "0,1"
bitfld.long 0x0 6. "RXADC_DELAYTRIM_I_TST_SEL,Enable the SW overload on RXADX delay trimming" "0,1"
bitfld.long 0x0 3.--5. "RFD_RXADC_DELAYTRIM_Q,ADC loop delay control bits for Q channel to apply when SW overload is enabled" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "RFD_RXADC_DELAYTRIM_I,ADC loop delay control bits for I channel to apply when SW overload is enabled" "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x0 "LDO_ANA_ENG,LDO_ANA_ENG register"
bitfld.long 0x0 0. "RFD_RF_REG_BYPASS,RF_REG Bypass mode:" "0,1"
group.long 0x174++0x7
line.long 0x0 "CBIAS0_ANA_ENG,CBIAS0_ANA_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "RFD_CBIAS_IPTAT_TRIM,overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1)"
hexmask.long.byte 0x0 0.--3. 1. "RFD_CBIAS_IBIAS_TRIM,overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1)"
line.long 0x4 "CBIAS1_ANA_ENG,CBIAS1_ANA_ENG register"
bitfld.long 0x4 7. "CBIAS0_TRIM_TST_SEL,When set RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings" "0,1"
rgroup.long 0x180++0x1B
line.long 0x0 "SYNTHCAL0_DIG_OUT,SYNTHCAL0_DIG_OUT register"
hexmask.long.byte 0x0 0.--6. 1. "VCO_CALAMP_OUT_6_0,VCO CALAMP value"
line.long 0x4 "SYNTHCAL1_DIG_OUT,SYNTHCAL1_DIG_OUT register"
hexmask.long.byte 0x4 0.--3. 1. "VCO_CALAMP_OUT_10_7,VCO CALAMP value"
line.long 0x8 "SYNTHCAL2_DIG_OUT,SYNTHCAL2_DIG_OUT register"
hexmask.long.byte 0x8 0.--6. 1. "VCO_CALFREQ_OUT,VCO CALFREQ value"
line.long 0xC "SYNTHCAL3_DIG_OUT,SYNTHCAL3_DIG_OUT register"
hexmask.long.byte 0xC 0.--7. 1. "SYNTHCAL_DEBUG_BUS,Calibration debug bus."
line.long 0x10 "SYNTHCAL4_DIG_OUT,SYNTHCAL4_DIG_OUT register"
hexmask.long.byte 0x10 0.--5. 1. "MOD_REF_DAC_WORD_OUT,Calibration word"
line.long 0x14 "SYNTHCAL5_DIG_OUT,SYNTHCAL5_DIG_OUT register"
hexmask.long.byte 0x14 0.--3. 1. "CBP_CALIB_WORD,CBP Calibration word"
line.long 0x18 "FSM_STATUS_DIG_OUT,FSM_STATUS_DIG_OUT register"
bitfld.long 0x18 7. "SYNTH_CAL_ERROR,PLL calibration error" "0,1"
hexmask.long.byte 0x18 0.--4. 1. "STATUS,RF FSM state:"
rgroup.long 0x1A4++0xF
line.long 0x0 "RSSI0_DIG_OUT,RSSI0_DIG_OUT register"
hexmask.long.byte 0x0 0.--7. 1. "RSSI_MEAS_OUT_7_0,Measure of the received signal strength."
line.long 0x4 "RSSI1_DIG_OUT,RSSI1_DIG_OUT register"
hexmask.long.byte 0x4 0.--7. 1. "RSSI_MEAS_OUT_15_8,Measure of the received signal strength"
line.long 0x8 "AGC_DIG_OUT,AGC_DIG_OUT register"
hexmask.long.byte 0x8 0.--3. 1. "AGC_ATT_OUT,AGC attenuation value"
line.long 0xC "DEMOD_DIG_OUT,DEMOD_DIG_OUT register"
bitfld.long 0xC 4. "RX_END,rx_end" "0,1"
bitfld.long 0xC 3. "PD_FOUND,pd_found" "0,1"
bitfld.long 0xC 2. "AAC_FOUND,aac_found" "0,1"
bitfld.long 0xC 0.--1. "CI_FIELD,CI field" "0,1,2,3"
group.long 0x1BC++0xB
line.long 0x0 "AGC2_ANA_TST,AGC2_ANA_TST register"
bitfld.long 0x0 1.--3. "AGC_ANTENNAE_USR_TRIM,the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "AGC2_ANA_TST_SEL,Selection:" "0,1"
line.long 0x4 "AGC0_DIG_ENG,AGC0_DIG_ENG register"
bitfld.long 0x4 6. "AGC_ENABLE,Enable AGC" "0,1"
hexmask.long.byte 0x4 0.--5. 1. "AGC_THR_HIGH,High AGC threshold"
line.long 0x8 "AGC1_DIG_ENG,AGC1_DIG_ENG register"
bitfld.long 0x8 7. "AGC_LOCK_SYNC,AGC locks when Access Address is detected (recommended)" "0,1"
bitfld.long 0x8 6. "AGC_AUTOLOCK,AGC locks when level is steady between high threshold and lock threshold" "0,1"
hexmask.long.byte 0x8 0.--5. 1. "AGC_THR_LOW_6,Low threshold for 6dB steps"
group.long 0x1E8++0x27
line.long 0x0 "AGC10_DIG_ENG,AGC10_DIG_ENG register"
bitfld.long 0x0 4.--5. "ATT_ANT_0,Attenuation at Antenna Level for the AGC step 0:" "0: ,?,?,?"
bitfld.long 0x0 3. "ATT_LNA_0,Attenuation at LNA Level for the AGC step 0:" "0: ,?"
bitfld.long 0x0 0.--2. "ATT_IF_0,Attenuation at IF Level for the AGC step 0:" "0: ,?,?,?,?,?,?,?"
line.long 0x4 "AGC11_DIG_ENG,AGC11_DIG_ENG register"
bitfld.long 0x4 4.--5. "ATT_ANT_1,Attenuation at Antenna Level for the AGC step 1" "0,1,2,3"
bitfld.long 0x4 3. "ATT_LNA_1,Attenuation at LNA Level for the AGC step 1" "0,1"
bitfld.long 0x4 0.--2. "ATT_IF_1,Attenuation at IF Level for the AGC step 1" "0,1,2,3,4,5,6,7"
line.long 0x8 "AGC12_DIG_ENG,AGC12_DIG_ENG register"
bitfld.long 0x8 4.--5. "ATT_ANT_2,Attenuation at Antenna Level for the AGC step 2" "0,1,2,3"
bitfld.long 0x8 3. "ATT_LNA_2,Attenuation at LNA Level for the AGC step 2" "0,1"
bitfld.long 0x8 0.--2. "ATT_IF_2,Attenuation at IF Level for the AGC step 2" "0,1,2,3,4,5,6,7"
line.long 0xC "AGC13_DIG_ENG,AGC13_DIG_ENG register"
bitfld.long 0xC 4.--5. "ATT_ANT_3,Attenuation at Antenna Level for the AGC step 3" "0,1,2,3"
bitfld.long 0xC 3. "ATT_LNA_3,Attenuation at LNA Level for the AGC step 3" "0,1"
bitfld.long 0xC 0.--2. "ATT_IF_3,Attenuation at IF Level for the AGC step 3" "0,1,2,3,4,5,6,7"
line.long 0x10 "AGC14_DIG_ENG,AGC14_DIG_ENG register"
bitfld.long 0x10 4.--5. "ATT_ANT_4,Attenuation at Antenna Level for the AGC step 4" "0,1,2,3"
bitfld.long 0x10 3. "ATT_LNA_4,Attenuation at LNA Level for the AGC step 4" "0,1"
bitfld.long 0x10 0.--2. "ATT_IF_4,Attenuation at IF Level for the AGC step 4" "0,1,2,3,4,5,6,7"
line.long 0x14 "AGC15_DIG_ENG,AGC15_DIG_ENG register"
bitfld.long 0x14 4.--5. "ATT_ANT_5,Attenuation at Antenna Level for the AGC step 5" "0,1,2,3"
bitfld.long 0x14 3. "ATT_LNA_5,Attenuation at LNA Level for the AGC step 5" "0,1"
bitfld.long 0x14 0.--2. "ATT_IF_5,Attenuation at IF Level for the AGC step 5" "0,1,2,3,4,5,6,7"
line.long 0x18 "AGC16_DIG_ENG,AGC16_DIG_ENG register"
bitfld.long 0x18 4.--5. "ATT_ANT_6,Attenuation at Antenna Level for the AGC step 6" "0,1,2,3"
bitfld.long 0x18 3. "ATT_LNA_6,Attenuation at LNA Level for the AGC step 6" "0,1"
bitfld.long 0x18 0.--2. "ATT_IF_6,Attenuation at IF Level for the AGC step 6" "0,1,2,3,4,5,6,7"
line.long 0x1C "AGC17_DIG_ENG,AGC17_DIG_ENG register"
bitfld.long 0x1C 4.--5. "ATT_ANT_7,Attenuation at Antenna Level for the AGC step 7" "0,1,2,3"
bitfld.long 0x1C 3. "ATT_LNA_7,Attenuation at LNA Level for the AGC step 7" "0,1"
bitfld.long 0x1C 0.--2. "ATT_IF_7,Attenuation at IF Level for the AGC step 7" "0,1,2,3,4,5,6,7"
line.long 0x20 "AGC18_DIG_ENG,AGC18_DIG_ENG register"
bitfld.long 0x20 4.--5. "ATT_ANT_8,Attenuation at Antenna Level for the AGC step 8" "0,1,2,3"
bitfld.long 0x20 3. "ATT_LNA_8,Attenuation at LNA Level for the AGC step 8" "0,1"
bitfld.long 0x20 0.--2. "ATT_IF_8,Attenuation at IF Level for the AGC step 8" "0,1,2,3,4,5,6,7"
line.long 0x24 "AGC19_DIG_ENG,AGC19_DIG_ENG register"
bitfld.long 0x24 4.--5. "ATT_ANT_9,Attenuation at Antenna Level for the AGC step 9" "0,1,2,3"
bitfld.long 0x24 3. "ATT_LNA_9,Attenuation at LNA Level for the AGC step 9" "0,1"
bitfld.long 0x24 0.--2. "ATT_IF_9,Attenuation at IF Level for the AGC step 9" "0,1,2,3,4,5,6,7"
rgroup.long 0x224++0x7
line.long 0x0 "RXADC_HW_TRIM_OUT,RXADC_HW_TRIM_OUT register"
bitfld.long 0x0 3.--5. "HW_RXADC_DELAYTRIM_Q,control bits of the RX ADC loop delay for Q channel (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "HW_RXADC_DELAYTRIM_I,control bits of the RX ADC loop delay for I channel (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
line.long 0x4 "CBIAS0_HW_TRIM_OUT,CBIAS0_HW_TRIM_OUT register"
hexmask.long.byte 0x4 4.--7. 1. "HW_CBIAS_IPTAT_TRIM,CBIAS current (provided by the HW trimming automatically loaded on POR)."
hexmask.long.byte 0x4 0.--3. 1. "HW_CBIAS_IBIAS_TRIM,CBIAS current (provided by the HW trimming automatically loaded on POR)."
rgroup.long 0x230++0x3
line.long 0x0 "AGC_HW_TRIM_OUT,AGC_HW_TRIM_OUT register"
bitfld.long 0x0 1.--3. "HW_AGC_ANTENNAE_TRIM,AGC trim value (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x13
line.long 0x0 "DEMOD_IQ2_DIG_TST,DEMOD_IQ2_DIG_TST register"
bitfld.long 0x0 2.--3. "EXTCFG_TRIG_SELECTION,Defines the trigger/anchor point of the IQ sampling when extended configuration is enabled:" "0,1,2,3"
bitfld.long 0x0 0.--1. "EXTCFG_SAMPLING_TIME,Defines the sampling time when extended configuration is enabled:" "0,1,2,3"
line.long 0x4 "ANTSW0_DIG_USR,ANTSW0_DIG_USR register"
hexmask.long.byte 0x4 0.--6. 1. "RX_TIME_TO_SAMPLE,specifies the exact timing of the first I/Q sampling in the reference period."
line.long 0x8 "ANTSW1_DIG_USR,ANTSW1_DIG_USR register"
hexmask.long.byte 0x8 0.--5. 1. "RX_TIME_TO_SWITCH,specifies the exact timing of the antenna switching at receiver level (in AoA)."
line.long 0xC "ANTSW2_DIG_USR,ANTSW2_DIG_USR register"
hexmask.long.byte 0xC 0.--6. 1. "TX_TIME_TO_SWITCH,specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD)."
line.long 0x10 "ANTSW3_DIG_USR,ANTSW3_DIG_USR register"
hexmask.long.byte 0x10 0.--6. 1. "TX_TIME_TO_SWITCH_2M,specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD)."
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "RADIO_CONTROL"
base ad:0x60001000
rgroup.long 0x0++0x3
line.long 0x0 "RADIO_CONTROL_ID,RADIO_CONTROL_ID register"
hexmask.long.byte 0x0 12.--15. 1. "PRODUCT,incremented on major features add-on like new Bluetooth LE SIG version support"
hexmask.long.byte 0x0 8.--11. 1. "VERSION,Cut Number"
hexmask.long.byte 0x0 4.--7. 1. "REVISION,Incremented for metal fix version"
group.long 0x4++0x3
line.long 0x0 "CLK32COUNT_REG,CLK32COUNT_REG register"
hexmask.long.word 0x0 0.--8. 1. "SLOW_COUNT,program the window length (in slow clock period) for slow clock measurement."
rgroup.long 0x8++0x7
line.long 0x0 "CLK32PERIOD_REG,CLK32PERIOD_REG register"
hexmask.long.tbyte 0x0 0.--18. 1. "SLOW_PERIOD,indicates slow clock period information."
line.long 0x4 "CLK32FREQUENCY_REG,CLK32FREQUENCY_REG register"
hexmask.long 0x4 0.--26. 1. "SLOW_FREQUENCY,value equal to (2^39/ SLOW_PERIOD)."
group.long 0x10++0x7
line.long 0x0 "RADIO_CONTROL_IRQ_STATUS,RADIO_CONTROL_IRQ_STATUS register"
hexmask.long.byte 0x0 8.--13. 1. "RADIO_FSM_IRQ,Radio FSM interrupt status (aka RfFsm_event_irq)."
bitfld.long 0x0 0. "SLOW_CLK_IRQ,slow clock measurement end of calculation interrupt status" "0,1"
line.long 0x4 "RADIO_CONTROL_IRQ_ENABLE,RADIO_CONTROL_IRQ_ENABLE register"
hexmask.long.byte 0x4 8.--13. 1. "RADIO_FSM_IRQ_MASK,mask for each RfFsm_event (Radio FSM) interrupt."
bitfld.long 0x4 0. "SLOW_CLK_IRQ_MASK,mask slow clock measurement interrupt" "0,1"
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "RADIO"
base ad:0x60001500
group.long 0x0++0x1B
line.long 0x0 "AA0_DIG_USR,AA0_DIG_USR register"
hexmask.long.byte 0x0 0.--7. 1. "AA_7_0,Least significant byte of the Bluetooth LE Access Address code"
line.long 0x4 "AA1_DIG_USR,AA1_DIG_USR register"
hexmask.long.byte 0x4 0.--7. 1. "AA_15_8,Next byte of the Bluetooth LE Access Address code."
line.long 0x8 "AA2_DIG_USR,AA2_DIG_USR register"
hexmask.long.byte 0x8 0.--7. 1. "AA_23_16,Next byte of the Bluetooth LE Access Address code"
line.long 0xC "AA3_DIG_USR,AA3_DIG_USR register"
hexmask.long.byte 0xC 0.--7. 1. "AA_31_24,Most significant byte of the Bluetooth LE Access Address code."
line.long 0x10 "DEM_MOD_DIG_USR,DEM_MOD_DIG_USR register"
hexmask.long.byte 0x10 1.--7. 1. "CHANNEL_NUM,Index for internal lock up table in which the synthesizer setup is contained."
line.long 0x14 "RADIO_FSM_USR,RADIO_FSM_USR register"
hexmask.long.byte 0x14 3.--7. 1. "PA_POWER,PA Power coefficient."
bitfld.long 0x14 2. "EN_CALIB_SYNTH,SYNTH calibration enable bit." "0,1"
bitfld.long 0x14 1. "EN_CALIB_CBP,CBP calibration enable bit." "0,1"
line.long 0x18 "PHYCTRL_DIG_USR,PHYCTRL_DIG_USR register"
bitfld.long 0x18 0.--2. "RXTXPHY,RXTXPHY selection." "0,1,2,3,4,5,6,7"
group.long 0x48++0x3
line.long 0x0 "AFC1_DIG_ENG,AFC1_DIG_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "AFC_DELAY_BEFORE,Set the decay factor of the AFC loop before Access Address detection"
hexmask.long.byte 0x0 0.--3. 1. "AFC_DELAY_AFTER,Set the decay factor of the AFC loop after Access Address detection"
group.long 0x54++0x3
line.long 0x0 "CR0_DIG_ENG,CR0_DIG_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "CR_GAIN_BEFORE,Set the gain of the clock recovery loop before Access Address detection to the value"
hexmask.long.byte 0x0 0.--3. 1. "CR_GAIN_AFTER,Set the gain of the clock recovery loop before Access Address detection to the value"
group.long 0x68++0x7
line.long 0x0 "CR0_LR,CR0_LR register"
hexmask.long.byte 0x0 4.--7. 1. "CR_LR_GAIN_BEFORE,Set the gain of the clock recovery loop before Access Address detection to the value 2^(-CR_LR_GAIN_ BEFORE) when the coded PHY is in use"
hexmask.long.byte 0x0 0.--3. 1. "CR_LR_GAIN_AFTER,Set the gain of the clock recovery loop after Access Address detection to the value 2^(-CR_LR_GAIN_ AFTER) when the coded PHY is in use"
line.long 0x4 "VIT_CONF_DIG_ENG,VIT_CONF_DIG_ENG register"
hexmask.long.byte 0x4 2.--7. 1. "SPARE,spare"
bitfld.long 0x4 0. "VIT_EN,Viterbi enable" "0,1"
group.long 0x84++0xB
line.long 0x0 "LR_PD_THR_DIG_ENG,LR_PD_THR_DIG_ENG register"
hexmask.long.byte 0x0 0.--7. 1. "LR_PD_THR,preamble detect threshold value"
line.long 0x4 "LR_RSSI_THR_DIG_ENG,LR_RSSI_THR_DIG_ENG register"
hexmask.long.byte 0x4 0.--7. 1. "LR_RSSI_THR,RSSI or peak threshold value"
line.long 0x8 "LR_AAC_THR_DIG_ENG,LR_AAC_THR_DIG_ENG register"
hexmask.long.byte 0x8 0.--7. 1. "LR_AAC_THR,address coded correlation threshold"
group.long 0xA8++0x3
line.long 0x0 "SYNTHCAL0_DIG_ENG,SYNTHCAL0_DIG_ENG register"
bitfld.long 0x0 6.--7. "SYNTH_IF_FREQ_CAL,Define the frequency applied on the PLL during calibration phase" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "SYNTHCAL_DEBUG_BUS_SEL,for Debug purpose"
group.long 0xF0++0x3
line.long 0x0 "DTB5_DIG_ENG,DTB5_DIG_ENG register"
bitfld.long 0x0 5. "PORT_SELECTED_0,force port_selected[0] signal" "0,1"
bitfld.long 0x0 4. "PORT_SELECTED_EN,enable port selection" "0,1"
bitfld.long 0x0 3. "INITIALIZE,Force INITIALIZE signal (emulate a token request of the IP_BLE)" "0,1"
bitfld.long 0x0 2. "RX_ACTIVE,Force RX_ACTIVE signal" "0,1"
newline
bitfld.long 0x0 1. "TX_ACTIVE,Force TX_ACTIVE signal" "0,1"
bitfld.long 0x0 0. "RXTX_START_SEL,enable the possibility to control some signals by the other register bits instead of system design:" "0,1"
group.long 0x148++0x3
line.long 0x0 "RXADC_ANA_USR,RXADC_ANA_USR register"
bitfld.long 0x0 7. "RXADC_DELAYTRIM_Q_TST_SEL,Enable the SW overload on RXADX delay trimming" "0,1"
bitfld.long 0x0 6. "RXADC_DELAYTRIM_I_TST_SEL,Enable the SW overload on RXADX delay trimming" "0,1"
bitfld.long 0x0 3.--5. "RFD_RXADC_DELAYTRIM_Q,ADC loop delay control bits for Q channel to apply when SW overload is enabled" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "RFD_RXADC_DELAYTRIM_I,ADC loop delay control bits for I channel to apply when SW overload is enabled" "0,1,2,3,4,5,6,7"
group.long 0x154++0x3
line.long 0x0 "LDO_ANA_ENG,LDO_ANA_ENG register"
bitfld.long 0x0 0. "RFD_RF_REG_BYPASS,RF_REG Bypass mode:" "0,1"
group.long 0x174++0x7
line.long 0x0 "CBIAS0_ANA_ENG,CBIAS0_ANA_ENG register"
hexmask.long.byte 0x0 4.--7. 1. "RFD_CBIAS_IPTAT_TRIM,overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1)"
hexmask.long.byte 0x0 0.--3. 1. "RFD_CBIAS_IBIAS_TRIM,overloaded value for cbias current trimming (when CBIAS0_TRIM_TST_SEL = 1)"
line.long 0x4 "CBIAS1_ANA_ENG,CBIAS1_ANA_ENG register"
bitfld.long 0x4 7. "CBIAS0_TRIM_TST_SEL,When set RFD_CBIAS_(IPTAT/IBIAS)_TRIM are used instead of HW trimmings" "0,1"
rgroup.long 0x180++0x1B
line.long 0x0 "SYNTHCAL0_DIG_OUT,SYNTHCAL0_DIG_OUT register"
hexmask.long.byte 0x0 0.--6. 1. "VCO_CALAMP_OUT_6_0,VCO CALAMP value"
line.long 0x4 "SYNTHCAL1_DIG_OUT,SYNTHCAL1_DIG_OUT register"
hexmask.long.byte 0x4 0.--3. 1. "VCO_CALAMP_OUT_10_7,VCO CALAMP value"
line.long 0x8 "SYNTHCAL2_DIG_OUT,SYNTHCAL2_DIG_OUT register"
hexmask.long.byte 0x8 0.--6. 1. "VCO_CALFREQ_OUT,VCO CALFREQ value"
line.long 0xC "SYNTHCAL3_DIG_OUT,SYNTHCAL3_DIG_OUT register"
hexmask.long.byte 0xC 0.--7. 1. "SYNTHCAL_DEBUG_BUS,Calibration debug bus."
line.long 0x10 "SYNTHCAL4_DIG_OUT,SYNTHCAL4_DIG_OUT register"
hexmask.long.byte 0x10 0.--5. 1. "MOD_REF_DAC_WORD_OUT,Calibration word"
line.long 0x14 "SYNTHCAL5_DIG_OUT,SYNTHCAL5_DIG_OUT register"
hexmask.long.byte 0x14 0.--3. 1. "CBP_CALIB_WORD,CBP Calibration word"
line.long 0x18 "FSM_STATUS_DIG_OUT,FSM_STATUS_DIG_OUT register"
bitfld.long 0x18 7. "SYNTH_CAL_ERROR,PLL calibration error" "0,1"
hexmask.long.byte 0x18 0.--4. 1. "STATUS,RF FSM state:"
rgroup.long 0x1A4++0xF
line.long 0x0 "RSSI0_DIG_OUT,RSSI0_DIG_OUT register"
hexmask.long.byte 0x0 0.--7. 1. "RSSI_MEAS_OUT_7_0,Measure of the received signal strength."
line.long 0x4 "RSSI1_DIG_OUT,RSSI1_DIG_OUT register"
hexmask.long.byte 0x4 0.--7. 1. "RSSI_MEAS_OUT_15_8,Measure of the received signal strength"
line.long 0x8 "AGC_DIG_OUT,AGC_DIG_OUT register"
hexmask.long.byte 0x8 0.--3. 1. "AGC_ATT_OUT,AGC attenuation value"
line.long 0xC "DEMOD_DIG_OUT,DEMOD_DIG_OUT register"
bitfld.long 0xC 4. "RX_END,rx_end" "0,1"
bitfld.long 0xC 3. "PD_FOUND,pd_found" "0,1"
bitfld.long 0xC 2. "AAC_FOUND,aac_found" "0,1"
bitfld.long 0xC 0.--1. "CI_FIELD,CI field" "0,1,2,3"
group.long 0x1BC++0xB
line.long 0x0 "AGC2_ANA_TST,AGC2_ANA_TST register"
bitfld.long 0x0 1.--3. "AGC_ANTENNAE_USR_TRIM,the AGC antenna trimming value ( when AGC2_ANA_TST_SEL = 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "AGC2_ANA_TST_SEL,Selection:" "0,1"
line.long 0x4 "AGC0_DIG_ENG,AGC0_DIG_ENG register"
bitfld.long 0x4 6. "AGC_ENABLE,Enable AGC" "0,1"
hexmask.long.byte 0x4 0.--5. 1. "AGC_THR_HIGH,High AGC threshold"
line.long 0x8 "AGC1_DIG_ENG,AGC1_DIG_ENG register"
bitfld.long 0x8 7. "AGC_LOCK_SYNC,AGC locks when Access Address is detected (recommended)" "0,1"
bitfld.long 0x8 6. "AGC_AUTOLOCK,AGC locks when level is steady between high threshold and lock threshold" "0,1"
hexmask.long.byte 0x8 0.--5. 1. "AGC_THR_LOW_6,Low threshold for 6dB steps"
group.long 0x1E8++0x27
line.long 0x0 "AGC10_DIG_ENG,AGC10_DIG_ENG register"
bitfld.long 0x0 4.--5. "ATT_ANT_0,Attenuation at Antenna Level for the AGC step 0:" "0: ,?,?,?"
bitfld.long 0x0 3. "ATT_LNA_0,Attenuation at LNA Level for the AGC step 0:" "0: ,?"
bitfld.long 0x0 0.--2. "ATT_IF_0,Attenuation at IF Level for the AGC step 0:" "0: ,?,?,?,?,?,?,?"
line.long 0x4 "AGC11_DIG_ENG,AGC11_DIG_ENG register"
bitfld.long 0x4 4.--5. "ATT_ANT_1,Attenuation at Antenna Level for the AGC step 1" "0,1,2,3"
bitfld.long 0x4 3. "ATT_LNA_1,Attenuation at LNA Level for the AGC step 1" "0,1"
bitfld.long 0x4 0.--2. "ATT_IF_1,Attenuation at IF Level for the AGC step 1" "0,1,2,3,4,5,6,7"
line.long 0x8 "AGC12_DIG_ENG,AGC12_DIG_ENG register"
bitfld.long 0x8 4.--5. "ATT_ANT_2,Attenuation at Antenna Level for the AGC step 2" "0,1,2,3"
bitfld.long 0x8 3. "ATT_LNA_2,Attenuation at LNA Level for the AGC step 2" "0,1"
bitfld.long 0x8 0.--2. "ATT_IF_2,Attenuation at IF Level for the AGC step 2" "0,1,2,3,4,5,6,7"
line.long 0xC "AGC13_DIG_ENG,AGC13_DIG_ENG register"
bitfld.long 0xC 4.--5. "ATT_ANT_3,Attenuation at Antenna Level for the AGC step 3" "0,1,2,3"
bitfld.long 0xC 3. "ATT_LNA_3,Attenuation at LNA Level for the AGC step 3" "0,1"
bitfld.long 0xC 0.--2. "ATT_IF_3,Attenuation at IF Level for the AGC step 3" "0,1,2,3,4,5,6,7"
line.long 0x10 "AGC14_DIG_ENG,AGC14_DIG_ENG register"
bitfld.long 0x10 4.--5. "ATT_ANT_4,Attenuation at Antenna Level for the AGC step 4" "0,1,2,3"
bitfld.long 0x10 3. "ATT_LNA_4,Attenuation at LNA Level for the AGC step 4" "0,1"
bitfld.long 0x10 0.--2. "ATT_IF_4,Attenuation at IF Level for the AGC step 4" "0,1,2,3,4,5,6,7"
line.long 0x14 "AGC15_DIG_ENG,AGC15_DIG_ENG register"
bitfld.long 0x14 4.--5. "ATT_ANT_5,Attenuation at Antenna Level for the AGC step 5" "0,1,2,3"
bitfld.long 0x14 3. "ATT_LNA_5,Attenuation at LNA Level for the AGC step 5" "0,1"
bitfld.long 0x14 0.--2. "ATT_IF_5,Attenuation at IF Level for the AGC step 5" "0,1,2,3,4,5,6,7"
line.long 0x18 "AGC16_DIG_ENG,AGC16_DIG_ENG register"
bitfld.long 0x18 4.--5. "ATT_ANT_6,Attenuation at Antenna Level for the AGC step 6" "0,1,2,3"
bitfld.long 0x18 3. "ATT_LNA_6,Attenuation at LNA Level for the AGC step 6" "0,1"
bitfld.long 0x18 0.--2. "ATT_IF_6,Attenuation at IF Level for the AGC step 6" "0,1,2,3,4,5,6,7"
line.long 0x1C "AGC17_DIG_ENG,AGC17_DIG_ENG register"
bitfld.long 0x1C 4.--5. "ATT_ANT_7,Attenuation at Antenna Level for the AGC step 7" "0,1,2,3"
bitfld.long 0x1C 3. "ATT_LNA_7,Attenuation at LNA Level for the AGC step 7" "0,1"
bitfld.long 0x1C 0.--2. "ATT_IF_7,Attenuation at IF Level for the AGC step 7" "0,1,2,3,4,5,6,7"
line.long 0x20 "AGC18_DIG_ENG,AGC18_DIG_ENG register"
bitfld.long 0x20 4.--5. "ATT_ANT_8,Attenuation at Antenna Level for the AGC step 8" "0,1,2,3"
bitfld.long 0x20 3. "ATT_LNA_8,Attenuation at LNA Level for the AGC step 8" "0,1"
bitfld.long 0x20 0.--2. "ATT_IF_8,Attenuation at IF Level for the AGC step 8" "0,1,2,3,4,5,6,7"
line.long 0x24 "AGC19_DIG_ENG,AGC19_DIG_ENG register"
bitfld.long 0x24 4.--5. "ATT_ANT_9,Attenuation at Antenna Level for the AGC step 9" "0,1,2,3"
bitfld.long 0x24 3. "ATT_LNA_9,Attenuation at LNA Level for the AGC step 9" "0,1"
bitfld.long 0x24 0.--2. "ATT_IF_9,Attenuation at IF Level for the AGC step 9" "0,1,2,3,4,5,6,7"
rgroup.long 0x224++0x7
line.long 0x0 "RXADC_HW_TRIM_OUT,RXADC_HW_TRIM_OUT register"
bitfld.long 0x0 3.--5. "HW_RXADC_DELAYTRIM_Q,control bits of the RX ADC loop delay for Q channel (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--2. "HW_RXADC_DELAYTRIM_I,control bits of the RX ADC loop delay for I channel (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
line.long 0x4 "CBIAS0_HW_TRIM_OUT,CBIAS0_HW_TRIM_OUT register"
hexmask.long.byte 0x4 4.--7. 1. "HW_CBIAS_IPTAT_TRIM,CBIAS current (provided by the HW trimming automatically loaded on POR)."
hexmask.long.byte 0x4 0.--3. 1. "HW_CBIAS_IBIAS_TRIM,CBIAS current (provided by the HW trimming automatically loaded on POR)."
rgroup.long 0x230++0x3
line.long 0x0 "AGC_HW_TRIM_OUT,AGC_HW_TRIM_OUT register"
bitfld.long 0x0 1.--3. "HW_AGC_ANTENNAE_TRIM,AGC trim value (provided by the HW trimming automatically loaded on POR)." "0,1,2,3,4,5,6,7"
group.long 0x23C++0x13
line.long 0x0 "DEMOD_IQ2_DIG_TST,DEMOD_IQ2_DIG_TST register"
bitfld.long 0x0 2.--3. "EXTCFG_TRIG_SELECTION,Defines the trigger/anchor point of the IQ sampling when extended configuration is enabled:" "0,1,2,3"
bitfld.long 0x0 0.--1. "EXTCFG_SAMPLING_TIME,Defines the sampling time when extended configuration is enabled:" "0,1,2,3"
line.long 0x4 "ANTSW0_DIG_USR,ANTSW0_DIG_USR register"
hexmask.long.byte 0x4 0.--6. 1. "RX_TIME_TO_SAMPLE,specifies the exact timing of the first I/Q sampling in the reference period."
line.long 0x8 "ANTSW1_DIG_USR,ANTSW1_DIG_USR register"
hexmask.long.byte 0x8 0.--5. 1. "RX_TIME_TO_SWITCH,specifies the exact timing of the antenna switching at receiver level (in AoA)."
line.long 0xC "ANTSW2_DIG_USR,ANTSW2_DIG_USR register"
hexmask.long.byte 0xC 0.--6. 1. "TX_TIME_TO_SWITCH,specifies the exact timing of the antenna switching during transmission at LE_1M baud rate (in AoD)."
line.long 0x10 "ANTSW3_DIG_USR,ANTSW3_DIG_USR register"
hexmask.long.byte 0x10 0.--6. 1. "TX_TIME_TO_SWITCH_2M,specifies the exact timing of the antenna switching during transmission at LE_2M baud rate (in AoD)."
tree.end
endif
tree.end
tree "RCC (Reset and Clock Controller)"
base ad:0x48400000
group.long 0x0++0x3
line.long 0x0 "CR,CR register"
rbitfld.long 0x0 17. "HSERDY,External High Speed Clock ready flag." "0: HSE oscillator not ready,1: HSE oscillator ready"
bitfld.long 0x0 16. "HSEON,External High Speed Clock enable." "0: HSE oscillator OFF,1: HSE oscillator ON"
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 15. "FMRAT,Force MR_BLE active transmission status (for debug purpose)" "0: no effect,1: active_transmission is force to '1' whatever.."
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 15. "FMRAT,Force MR_BLE active transmission status (for debug purpose)" "0: no effect,1: active_transmission is force to '1' whatever.."
newline
endif
rbitfld.long 0x0 14. "HSIPLLRDY,Internal High Speed Clock PLL ready flag." "0: PLL is unlocked,1: PLL is locked"
bitfld.long 0x0 13. "HSIPLLON,Internal High Speed Clock PLL enable" "0: PLL is OFF,1: PLL is ON"
newline
bitfld.long 0x0 12. "HSEPLLBUFON,External High Speed Clock Buffer for PLL RF2G4 enable." "0: HSE PLL Buffer OFF,1: HSE PLL Buffer ON"
rbitfld.long 0x0 10. "HSIRDY,Internal High Speed clock ready flag." "0: internal RC 64 MHz oscillator not ready,1: internal RC 64 MHz oscillator ready"
newline
bitfld.long 0x0 7.--9. "LOCKDET_NSTOP,Lock detector Nstop value" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6. "LSEBYP,External Low Speed Clock bypass." "0: LSE oscillator bypass OFF,1: LSE oscillator bypass ON"
newline
rbitfld.long 0x0 5. "LSERDY,External Low Speed Clock ready flag." "0: LSE oscillator not ready,1: LSE oscillator ready"
bitfld.long 0x0 4. "LSEON,External Low Speed Clock enable." "0: LSE oscillator OFF,1: LSE oscillator ON"
newline
rbitfld.long 0x0 3. "LSIRDY,Internal Low Speed oscillator Ready" "0: LSI RC oscillator not ready,1: LSI RC oscillator ready"
bitfld.long 0x0 2. "LSION,Internal Low Speed oscillator enable" "0: LSI RC oscillator OFF,1: LSI RC oscillator ON"
group.long 0x8++0x3
line.long 0x0 "CFGR,CFGR register"
bitfld.long 0x0 29.--31. "CCOPRE,Configurable Clock Output Prescaler." "0: CCO clock is divided by 1,1: CCO clock is divided by 2,2: CCO clock is divided by 4,3: CCO clock is divided by 8,4: CCO clock is divided by 16,?,?,?"
bitfld.long 0x0 26.--28. "MCOSEL,Main Configurable Clock Output Selection." "0: MCO output disabled no clock on MCO,1: system clock selected,2: na,3: internal RC 64 MHz (HSI) oscillator clock..,4: external oscillator (HSE) clock selected,5: internal RC 64 MHz (HSI) oscillator divided by..,6: SMPS clock selected,7: AUX ADC ANA clock selected"
newline
bitfld.long 0x0 24.--25. "LCOSEL,Low speed Configurable Clock Output Selection." "0: LCO output disabled no clock on LCO,1: internal 32 KHz (LSI_LPMU) oscillator clock..,2: internal 32 KHz (LSI) oscillator clock selected,3: external 32 KHz (LSE) oscillator clock selected"
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 23. "SPI2I2SCLKSEL,Selection of I2S clock:" "0,1"
newline
bitfld.long 0x0 22. "SPI3I2SCLKSEL,Selection of I2S1 clock:" "0: 16MHz peripheral clock (default),1: 32MHz peripheral clock"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 23. "SPI2I2SCLKSEL,Selection of I2S clock:" "0,1"
newline
bitfld.long 0x0 22. "SPI3I2SCLKSEL,Selection of I2S1 clock:" "0: 16MHz peripheral clock (default),1: 32MHz peripheral clock"
newline
endif
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 22.--23. "SPI3I2SCLKSEL,Selection of I2S1 clock:" "0: 16MHz peripheral clock (default),1: 32MHz peripheral clock,?,?"
newline
bitfld.long 0x0 19. "LCOEN,LCO output enable" "0,1"
bitfld.long 0x0 18. "IOBOOSTCLKEXTEN,IO BOOSTER clock enable as external clock" "0: does not use rcc clock (default),1: uses rcc clock"
newline
bitfld.long 0x0 13. "LPUCLKSEL,Selection of LPUART clock:" "0: 16MHz peripheral clock (default),1: LSE clock"
rbitfld.long 0x0 8.--10. "CLKSYSDIV_STATUS,CLKSYSDIV_STATUS: system clock frequency status" "0: system clock frequency is 64 MHz,1: system clock frequency is 32 MHz,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "HSESEL_STATUS,Clock source selection Status" "0: HSI clock source is requested (default),1: HSE clock source is requested"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 22.--23. "SPI3I2SCLKSEL,Selection of I2S1 clock:" "0: 16MHz peripheral clock (default),1: 32MHz peripheral clock,?,?"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 19. "LCOEN,LCO output enable" "0,1"
bitfld.long 0x0 18. "IOBOOSTCLKEXTEN,IO BOOSTER clock enable as external clock" "0: does not use rcc clock (default),1: uses rcc clock"
newline
endif
bitfld.long 0x0 17. "IOBOOSTEN,IO BOOSTER enable" "0: does not enable IO BOOSTER,1: enable IO BOOSTER"
bitfld.long 0x0 15.--16. "CLKSLOWSEL,slow clock source selection" "0: LSILMPU oscillator clock (default),1: LSE oscillator clock used as slow clock,2: LSI oscillator clock used as slow clock,3: HSI_64M divided by 2048 used as slow clock"
newline
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 13. "LPUCLKSEL,Selection of LPUART clock:" "0: 16MHz peripheral clock (default),1: LSE clock"
newline
endif
bitfld.long 0x0 12. "SMPSDIV,SMPS clock prescaling factor to generate 4MHz or 8MHz" "0: div 2 when ANADIV=2 or 4 (default ),1: div 4 when ANADIV=1 or 2"
newline
sif (cpuis("STM32WB09*"))
rbitfld.long 0x0 8.--10. "CLKSYSDIV_STATUS,CLKSYSDIV_STATUS: system clock frequency status" "0: system clock frequency is 64 MHz,1: system clock frequency is 32 MHz,?,?,?,?,?,?"
newline
endif
bitfld.long 0x0 5.--7. "CLKSYSDIV,CLKSYSDIV: system clock divided factor from HSI_64M." "0: system clock frequency is 64 MHz,1: system clock frequency is 32 MHz,?,?,?,?,?,?"
newline
sif (cpuis("STM32WB09*"))
rbitfld.long 0x0 3. "HSESEL_STATUS,Clock source selection Status" "0: HSI clock source is requested (default),1: HSE clock source is requested"
newline
endif
bitfld.long 0x0 2. "STOPHSI,Stop HSI clock source request" "0: HSI is enabled (default),1: disable HSI is requested"
newline
bitfld.long 0x0 1. "HSESEL,Clock source selection request:" "0: HSI clock source is requested (default),1: HSE clock source is requested"
bitfld.long 0x0 0. "SMPSINV,bit to control inversion of the SMPS clock" "0: SMPS clock not inverted (default value),1: SMPS clock inverted (for debug)"
group.long 0x18++0xB
line.long 0x0 "CIER,CIER register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 9. "LPURSTIE,LPURSTIE: LPUART reset release interrupt enable." "0: LPUART reset release interrupt is disabled,1: LPUART reset release interrupt is enabled"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 9. "LPURSTIE,LPURSTIE: LPUART reset release interrupt enable." "0: LPUART reset release interrupt is disabled,1: LPUART reset release interrupt is enabled"
newline
endif
bitfld.long 0x0 8. "WDGRSTIE,WDGRSTIE: Watchdog reset end Interrupt Enable." "0: interrupt disabled,1: interrupt enabled"
bitfld.long 0x0 7. "RTCRSTIE,RTCRSTIE: RTC reset end Interrupt Enable." "0: HSI PLL unlock detection interrupt disabled,1: HSI PLL unlock detection interrupt enabled"
newline
bitfld.long 0x0 6. "HSIPLLUNLOCKDETIE,HSIPLLUNLOCKDETIE: HSI PLL unlock detection Interrupt Enable." "0: HSI PLL unlock detection interrupt disabled,1: HSI PLL unlock detection interrupt enabled"
bitfld.long 0x0 5. "HSIPLLRDYIE,HSI PLL Ready Interrupt Enable." "0: HSI PLL ready interrupt disabled,1: HSI PLL ready interrupt enabled"
newline
bitfld.long 0x0 4. "HSERDYIE,HSE Ready Interrupt Enable" "0: HSE ready interrupt disabled,1: HSE ready interrupt enabled"
bitfld.long 0x0 3. "HSIRDYIE,HSI Ready Interrupt Enable." "0: HSI ready interrupt disabled,1: HSI ready interrupt enabled"
newline
bitfld.long 0x0 1. "LSERDYIE,LSE Ready Interrupt Enable." "0: LSE ready interrupt disabled,1: LSE ready interrupt enabled"
bitfld.long 0x0 0. "LSIRDYIE,LSI Ready Interrupt Enable." "0: LSI ready interrupt disabled,1: LSI ready interrupt enabled"
line.long 0x4 "CIFR,CIFR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 9. "LPURSTF,LPUART reset release flag" "0: no LPUART reset release event occurred,1: LPUART reset release event occurred"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 9. "LPURSTF,LPUART reset release flag" "0: no LPUART reset release event occurred,1: LPUART reset release event occurred"
newline
endif
bitfld.long 0x4 8. "WDGRSTIF,WDG reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
bitfld.long 0x4 7. "RTCRSTIF,RTC reset end Interrupt Flag. Raised when reset is released on 32kHz clock" "0,1"
newline
bitfld.long 0x4 6. "HSIPLLUNLOCKDETIF,HSIPLLUNLOCKDETIF: HSI PLL unlock detection Interrupt Flag." "0,1"
bitfld.long 0x4 5. "HSIPLLRDYIF,HSI PLL Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSI..,1: Clock ready interrupt caused by the HSI PLL64.."
newline
bitfld.long 0x4 4. "HSERDYIF,HSE Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE.."
bitfld.long 0x4 3. "HSIRDYIF,HSI Ready Interrupt Flag." "0: No clock ready interrupt caused by the HSI..,1: Clock ready interrupt caused by the HSI.."
newline
bitfld.long 0x4 1. "LSERDYIF,LSE Ready Interrupt Flag." "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE.."
bitfld.long 0x4 0. "LSIRDYIF,LSI Ready Interrupt flag" "0: No clock ready interrupt caused by the internal..,1: Clock ready interrupt caused by the internal RC.."
line.long 0x8 "CSCMDR,CSCMDR register"
bitfld.long 0x8 7. "EOFSEQ_IRQ,End of Sequence flag" "0: No end of sequence event occured,1: End of sequece event occured"
bitfld.long 0x8 6. "EOFSEQ_IE,End of sequence Interrupt Enable." "0: End of sequence interrupt disabled,1: End of sequence interrupt enabled"
newline
rbitfld.long 0x8 4.--5. "STATUS,Status of clock switch sequence" "0: IDLE no switch requested,1: ONGOING clock frequency switch is ongoing,2: DONE clock frequency switch done,?"
bitfld.long 0x8 1.--3. "CLKSYSDIV_REQ,system clock dividing factor from HSI_64M requested" "0: div 1 (sys clock 64M),1: div 2 (sys clock 32M),2: div 4 (sys clock 16M),3: div 8 (sys clock 8M),4: div 16 (sys clock 4M),5: div 32 (sys clock 2M),6: div 64 (sys clock 1M),?"
newline
bitfld.long 0x8 0. "REQUEST,Request for system clock switching" "0: To cancel an ongiong request - still possible..,1: To update the system clock frequency"
group.long 0x30++0xB
line.long 0x0 "AHBRSTR,AHBRSTR register"
bitfld.long 0x0 18. "RNGRST,RNG reset" "0: does not reset,1: resets"
bitfld.long 0x0 16. "PKARST,PKA reset" "0: does not reset,1: resets"
newline
bitfld.long 0x0 12. "CRCRST,CRC reset" "0: does not reset CRC,1: resets CRC"
bitfld.long 0x0 3. "GPIOBRST,GPIOB reset" "0: does not reset,1: resets"
newline
bitfld.long 0x0 2. "GPIOARST,GPIOA reset" "0: does not reset,1: resets"
bitfld.long 0x0 0. "DMARST,DMA and DMAMUX reset" "0: does not reset DMA,1: resets DMA"
line.long 0x4 "APB0RSTR,APB0RSTR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 14. "WDRST,WATCHDOG reset" "0: does not reset,1: resets"
bitfld.long 0x4 2. "TIM17RST,TIM17 reset" "0: TIM17 IP is not under reset,1: TIM17 IP is under reset"
newline
bitfld.long 0x4 1. "TIM16RST,TIM16 reset" "0: TIM16 IP is not under reset,1: TIM16 IP is under reset"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 14. "WDGRST,WATCHDOG reset" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 14. "WDGRST,WATCHDOG reset" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 14. "WDRST,WATCHDOG reset" "0: does not reset,1: resets"
newline
endif
bitfld.long 0x4 12. "RTCRST,RTC reset" "0: does not reset,1: resets"
bitfld.long 0x4 8. "SYSCFGRST,SYSTEM CONFIG reset" "0: does not reset,1: resets"
newline
sif (cpuis("STM32WB09*"))
bitfld.long 0x4 2. "TIM17RST,TIM17 reset" "0: TIM17 IP is not under reset,1: TIM17 IP is under reset"
bitfld.long 0x4 1. "TIM16RST,TIM16 reset" "0: TIM16 IP is not under reset,1: TIM16 IP is under reset"
newline
endif
bitfld.long 0x4 0. "TIM1RST,TIM1: Advanced Timer reset" "0: does not reset,1: resets"
line.long 0x8 "APB1RSTR,APB1RSTR register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 23. "I2C2RST,2C2 reset." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 23. "I2C2RST,2C2 reset." "0,1"
newline
endif
sif (cpuis("STM32WB05*"))
bitfld.long 0x8 21. "I2C21RST,I2C1 reset" "0: does not reset,1: resets"
bitfld.long 0x8 4. "AUXADCRST,AUXADC reset for Aux-ADC digital clock" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 21. "I2C21RST,I2C1 reset" "0: does not reset,1: resets"
newline
endif
bitfld.long 0x8 14. "SPI3RST,SPI3 reset" "0: does not reset,1: resets"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 12. "SPI2RST,SPI2 reset." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 12. "SPI2RST,SPI2 reset." "0,1"
newline
endif
bitfld.long 0x8 10. "USARTRST,USART reset" "0: does not reset,1: resets"
bitfld.long 0x8 8. "LPUARTRST,LPUART reset" "0: does not reset,1: resets"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 4. "ADCRST,ADC reset." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 4. "ADCRST,ADC reset." "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 4. "AUXADCRST,AUXADC reset for Aux-ADC digital clock" "0: does not reset,1: resets"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 0. "SPI1RST,SPI1 reset" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 0. "SPI1RST,SPI1 reset" "0,1"
newline
endif
group.long 0x40++0x3
line.long 0x0 "APB2RSTR,APB2RSTR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 0. "BLERST,BLE reset." "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 0. "MRBLERST,MR_BLE (Bluetooth radio) reset." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 0. "MRBLERST,MR_BLE (Bluetooth radio) reset." "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x0 0. "BLERST,BLE reset." "0,1"
newline
endif
group.long 0x50++0xB
line.long 0x0 "AHBENR,AHBENR register"
bitfld.long 0x0 18. "RNGEN,RNG clock enable" "0: does not enable,1: enable"
bitfld.long 0x0 16. "PKAEN,PKA clock enable" "0: does not enable,1: enable"
newline
bitfld.long 0x0 12. "CRCEN,CRC enable" "0: does not enable,1: enable"
bitfld.long 0x0 3. "GPIOBEN,GPIOB enable. It must be enabled by default" "0,1"
newline
bitfld.long 0x0 2. "GPIOAEN,GPIOA enable. It must be enabled by default" "0,1"
bitfld.long 0x0 0. "DMAEN,DMA and DMAMUX enable" "0: does not enable,1: enable"
line.long 0x4 "APB0ENR,APB0ENR register"
bitfld.long 0x4 14. "WDGEN,Watchdog clock enable." "0: does not enable,1: enable"
bitfld.long 0x4 12. "RTCEN,RTC clock enable" "0: does not enable,1: enable"
newline
bitfld.long 0x4 8. "SYSCFGEN,SYSTEM CONFIG enable" "0: does not enable,1: enable"
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 2. "TIM17EN,TIM17 enable" "0: TIM17 IP is clock gated,1: TIM17 IP is clocked"
newline
bitfld.long 0x4 1. "TIM16EN,TIM16 enable" "0: TIM16 IP is clock gated,1: TIM16 IP is clocked"
bitfld.long 0x4 0. "TIM2EN,TIM2: Advanced Timer clock enable" "0: does not enable,1: enable"
newline
endif
sif (cpuis("STM32WB09*"))
newline
bitfld.long 0x4 2. "TIM17EN,TIM17 enable" "0: TIM17 IP is clock gated,1: TIM17 IP is clocked"
bitfld.long 0x4 1. "TIM16EN,TIM16 enable" "0: TIM16 IP is clock gated,1: TIM16 IP is clocked"
newline
bitfld.long 0x4 0. "TIM2EN,TIM2: Advanced Timer clock enable" "0: does not enable,1: enable"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 0. "TIM1EN,TIM1 enable" "0: does not enable,1: enable"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 0. "TIM1EN,TIM1 enable" "0: does not enable,1: enable"
newline
endif
line.long 0x8 "APB1ENR,APB1ENR register"
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 23. "I2C2EN,I2C2 enable." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 23. "I2C2EN,I2C2 enable." "0,1"
newline
endif
bitfld.long 0x8 21. "I2C1EN,I2C1 clock enable" "0: does not enable,1: enable"
bitfld.long 0x8 14. "SPI3EN,SPI3 clock enable" "0: does not enable,1: enable"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 12. "SPI2EN,SPI2 enable" "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 12. "SPI2EN,SPI2 enable" "0,1"
newline
endif
bitfld.long 0x8 10. "USART1EN,USART clock enable" "0: does not enable,1: enable"
bitfld.long 0x8 8. "LPUARTEN,LPUART clock enable" "0: does not enable,1: enable"
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0x8 5. "ADCANAEN,ADC clock enable for Aux-ADC analog clock" "0: does not enable,1: enable"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 5. "ADCANAEN,ADC clock enable for the analog part of the ADC block." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 5. "ADCANAEN,ADC clock enable for the analog part of the ADC block." "0,1"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x8 5. "ADCANAEN,ADC clock enable for Aux-ADC analog clock" "0: does not enable,1: enable"
newline
endif
bitfld.long 0x8 4. "ADCDIGEN,AUXADC clock enable for Aux-ADC digital clock" "0: does not enable,1: enable"
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 0. "SPI1EN,SPI1 enable." "0: does not enable,1: enable"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 0. "SPI1EN,SPI1 enable." "0: does not enable,1: enable"
newline
endif
group.long 0x60++0x3
line.long 0x0 "APB2ENR,APB2ENR register"
bitfld.long 0x0 2. "CLKBLEDIV,MR_BLE clock frequency selection when RCC_APB2ENR.MRBLEEN=1" "0: 32MHz,1: 16MHz"
bitfld.long 0x0 0. "MRBLEEN,MR_BLE enable" "0: MR_BLE IP is clock gated,1: MR_BLE IP is clocked"
group.long 0x94++0x7
line.long 0x0 "CSR,CSR register"
rbitfld.long 0x0 30. "LOCKUPRSTF,LOCK UP reset flag from CM0" "0: No lockup reset occurred,1: lockup reset occurred"
rbitfld.long 0x0 29. "WDGRSTF,Watchdog reset flag" "0: No watchdog reset occurred,1: Watchdog reset occurred"
newline
rbitfld.long 0x0 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred"
rbitfld.long 0x0 27. "PORRSTF,POWER reset flag" "0: No POWER reset occurred,1: POWER reset occurred"
newline
rbitfld.long 0x0 26. "PADRSTF,SYSTEM reset flag" "0: No reset from pad occurred,1: Reset from pad occurred"
bitfld.long 0x0 23. "RMVF,Remove reset flag" "0: Nothing done,1: Reset the value of the reset flags"
line.long 0x4 "RFSWHSECR,RFSWHSECR register"
hexmask.long.byte 0x4 8.--13. 1. "SWXOTUNE,RF-HSE capacitor bank tuning value by SW"
bitfld.long 0x4 7. "SWXOTUNEEN,RF-HSE capacitor bank tuning by SW enable" "0,1"
newline
bitfld.long 0x4 4.--6. "GMC,High Speed External XO current control" "0: max 0.0 001: max 0.57 mA/V,?,2: max 0.78 mA/V,3: max 1.13 mA/V (Default),4: max 0.61 mA/V,5: max 1.65 mA/V,6: max 2.12 mA/V,7: max 2.84 mA/V"
bitfld.long 0x4 3. "SATRG,Sense Amplifier threshold" "0: the bias current is confronted to a reference..,1: the bias current is confronted to a reference.."
rgroup.long 0x9C++0x3
line.long 0x0 "RFHSECR,RFHSECR register"
hexmask.long.byte 0x0 0.--5. 1. "XOTUNE,RF-HSE capacitor bank tuning"
tree.end
sif (cpuis("STM32WB05*")||cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "RNG (True Random Number Generator)"
base ad:0x48600000
group.long 0x0++0x7
line.long 0x0 "RNG_CR,RNG_CR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x0 3. "TST_CLK,RNG Test Clock bit." "0,1"
bitfld.long 0x0 2. "RNG_DIS,RNG Disable bit." "0,1"
newline
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 3. "TST_CLK,Reset reveal clock error flags when writing a '1' without resetting the whole TRNG." "0: no reset,1: reset revclk flag"
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 3. "TST_CLK,Reset reveal clock error flags when writing a '1' without resetting the whole TRNG." "0: no reset,1: reset revclk flag"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x0 1. "RNG_DIS,This bit enables or disables the random number generator." "0: RNG is enabled,1: RNG is disabled"
endif
sif (cpuis("STM32WB06*"))
bitfld.long 0x0 1. "RNG_DIS,This bit enables or disables the random number generator." "0: RNG is enabled,1: RNG is disabled"
endif
line.long 0x4 "RNG_SR,RNG_SR register"
sif (cpuis("STM32WB05*"))
bitfld.long 0x4 2. "FAULT,Fault Reveal bit." "0,1"
rbitfld.long 0x4 1. "REVCLK,RNGCLK Clock Reveal bit." "0,1"
newline
rbitfld.long 0x4 0. "RNGRDY,New Random Value Ready." "0,1"
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0x4 2. "FAULT,Fault reveal bit." "0: Internal clock for RNG clock is present.,1: Internal RNG clock is not present."
newline
rbitfld.long 0x4 1. "REVCLK,RNGCLK clock reveal bit." "0: At least one oscillator is ON,1: All oscillators are down"
rbitfld.long 0x4 0. "RNGRDY,New random value ready" "0: Normal operation.,1: RNG is disabled."
newline
endif
sif (cpuis("STM32WB06*"))
rbitfld.long 0x4 2. "FAULT,Fault reveal bit." "0: Internal clock for RNG clock is present.,1: Internal RNG clock is not present."
rbitfld.long 0x4 1. "REVCLK,RNGCLK clock reveal bit." "0: At least one oscillator is ON,1: All oscillators are down"
endif
rgroup.long 0x8++0x3
line.long 0x0 "RNG_VAL,RNG_VAL register"
sif (cpuis("STM32WB05*"))
hexmask.long.word 0x0 0.--15. 1. "RANDOM_VALUE,Random Value"
endif
sif (cpuis("STM32WB06*"))
hexmask.long.word 0x0 0.--15. 1. "RND_VAL,Random value"
newline
endif
sif (cpuis("STM32WB07*"))
hexmask.long.word 0x0 0.--15. 1. "RND_VAL,Random value"
endif
sif (cpuis("STM32WB06*"))
rgroup.long 0x4++0x3
line.long 0x0 "RNG_SR,RNG_SR register"
endif
sif (cpuis("STM32WB07*"))
rgroup.long 0x4++0x3
line.long 0x0 "RNG_SR,RNG_SR register"
endif
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "RRM (Radio Resource Manager)"
base ad:0x60001400
group.long 0x10++0xB
line.long 0x0 "UDRA_CTRL0,UDRA_CTRL0 register"
bitfld.long 0x0 0. "RELOAD_RDCFGPTR,reload the radio configuration pointer from RAM." "0,1"
line.long 0x4 "UDRA_IRQ_ENABLE,UDRA_IRQ_ENABLE register"
bitfld.long 0x4 2. "CMD_END,UDRA interrupt enable (command end)" "0,1"
bitfld.long 0x4 1. "CMD_START,UDRA interrupt enable (command start)" "0,1"
bitfld.long 0x4 0. "RADIO_CFG_PTR_RELOADED,UDRA interrupt enable (reload radio config pointer)" "0,1"
line.long 0x8 "UDRA_IRQ_STATUS,UDRA_IRQ_STATUS register"
bitfld.long 0x8 2. "CMD_END,On read returns the UDRA command end interrupt status" "0,1"
bitfld.long 0x8 1. "CMD_STARD,On read returns the UDRA command start interrupt status." "0,1"
bitfld.long 0x8 0. "RADIO_CFG_PTR_RELOADED,On read returns the UDRA reload radio configuration pointer interrupt status." "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "UDRA_RADIO_CFG_PTR,UDRA_RADIO_CFG_PTR register"
hexmask.long 0x0 0.--31. 1. "RADIO_CONFIG_ADDRESS,UDRA radio configuration address."
group.long 0x20++0xF
line.long 0x0 "SEMA_IRQ_ENABLE,SEMA_IRQ_ENABLE register"
bitfld.long 0x0 1. "UNLOCK,semaphore unlocked (=no port selected) interrupt enable" "0,1"
bitfld.long 0x0 0. "LOCK,semaphore locked (= one port granted) interrupt enable" "0,1"
line.long 0x4 "SEMA_IRQ_STATUS,SEMA_IRQ_STATUS register"
bitfld.long 0x4 1. "UNLOCK,On read returns the semaphore unlocked interrupt status." "0,1"
bitfld.long 0x4 0. "LOCK,On read returns the semaphore locked interrupt status." "0,1"
line.long 0x8 "BLE_IRQ_ENABLE,BLE_IRQ_ENABLE register"
bitfld.long 0x8 4. "PORT_CMD_END,IP_BLE Port command end interrup enable" "0,1"
bitfld.long 0x8 3. "PORT_CMD_START,IP_BLE Port command start interrup enable" "0,1"
bitfld.long 0x8 1. "PORT_RELEASE,IP_BLE Port release interrupt enable" "0,1"
bitfld.long 0x8 0. "PORT_GRANT,IP_BLE Port grant interrupt enable" "0,1"
line.long 0xC "BLE_IRQ_STATUS,BLE_IRQ_STATUS register"
bitfld.long 0xC 4. "CMD_END,IP_BLE hardware port command end interrupt status." "0,1"
bitfld.long 0xC 3. "CMD_START,IP_BLE hardware port command start interrupt status." "0,1"
bitfld.long 0xC 1. "PORT_RELEASE,IP_BLE hardware port released interrupt status." "0,1"
bitfld.long 0xC 0. "PORT_GRANT,IP_BLE hardware port granted interrupt status:" "0,1"
group.long 0x60++0xF
line.long 0x0 "VP_CPU_CMD_BUS,VP_CPU_CMD_BUS register"
bitfld.long 0x0 3. "COMMAND_REQ,CPU Virtual port command request:" "0,1"
bitfld.long 0x0 0.--2. "COMMAND,command number" "0,1,2,3,4,5,6,7"
line.long 0x4 "VP_CPU_SEMA_BUS,VP_CPU_SEMA_BUS register"
bitfld.long 0x4 3. "TAKE_REQ,semaphore token request:" "0,1"
bitfld.long 0x4 0.--2. "TAKE_PRIO,semaphore priority: priority value (between 0 and 7) of the take request." "0,1,2,3,4,5,6,7"
line.long 0x8 "VP_CPU_IRQ_ENABLE,VP_CPU_IRQ_ENABLE register"
bitfld.long 0x8 4. "PORT_CMD_END,CPU virtual port command end interrup enable" "0,1"
bitfld.long 0x8 3. "PORT_CMD_START,CPU virtual port command start interrup enable" "0,1"
bitfld.long 0x8 1. "PORT_RELEASE,CPU virtual port release interrupt enable" "0,1"
bitfld.long 0x8 0. "PORT_GRANT,CPU virtual port grant interrupt enable" "0,1"
line.long 0xC "VP_CPU_IRQ_STATUS,VP_CPU_IRQ_STATUS register"
bitfld.long 0xC 4. "CMD_END,CPU virtual port command end interrupt status." "0,1"
bitfld.long 0xC 3. "CMD_START,CPU virtual port command start interrupt status." "0,1"
bitfld.long 0xC 2. "PORT_PREEMPT,CPU virtual port preemption (at semaphore level) interrupt status." "0,1"
bitfld.long 0xC 1. "PORT_RELEASE,virtual port released interrupt status." "0,1"
newline
bitfld.long 0xC 0. "PORT_GRANT,CPU virtual port granted interrupt status." "0,1"
tree.end
endif
sif (cpuis("STM32WB05*"))
tree "RRM_REG (Radio Resource Manager)"
base ad:0x60001400
group.long 0x10++0xB
line.long 0x0 "UDRA_CTRL0,UDRA_CTRL0 register"
bitfld.long 0x0 0. "RELOAD_RDCFGPTR,reload the radio configuration pointer from RAM." "0,1"
line.long 0x4 "UDRA_IRQ_ENABLE,UDRA_IRQ_ENABLE register"
bitfld.long 0x4 2. "CMD_END,UDRA interrupt enable (command end)" "0,1"
bitfld.long 0x4 1. "CMD_START,UDRA interrupt enable (command start)" "0,1"
bitfld.long 0x4 0. "RADIO_CFG_PTR_RELOADED,UDRA interrupt enable (reload radio config pointer)" "0,1"
line.long 0x8 "UDRA_IRQ_STATUS,UDRA_IRQ_STATUS register"
bitfld.long 0x8 2. "CMD_END,On read returns the UDRA command end interrupt status" "0,1"
bitfld.long 0x8 1. "CMD_STARD,On read returns the UDRA command start interrupt status." "0,1"
bitfld.long 0x8 0. "RADIO_CFG_PTR_RELOADED,On read returns the UDRA reload radio configuration pointer interrupt status." "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "UDRA_RADIO_CFG_PTR,UDRA_RADIO_CFG_PTR register"
hexmask.long 0x0 0.--31. 1. "RADIO_CONFIG_ADDRESS,UDRA radio configuration address."
group.long 0x20++0xF
line.long 0x0 "SEMA_IRQ_ENABLE,SEMA_IRQ_ENABLE register"
bitfld.long 0x0 1. "UNLOCK,semaphore unlocked (=no port selected) interrupt enable" "0,1"
bitfld.long 0x0 0. "LOCK,semaphore locked (= one port granted) interrupt enable" "0,1"
line.long 0x4 "SEMA_IRQ_STATUS,SEMA_IRQ_STATUS register"
bitfld.long 0x4 1. "UNLOCK,On read returns the semaphore unlocked interrupt status." "0,1"
bitfld.long 0x4 0. "LOCK,On read returns the semaphore locked interrupt status." "0,1"
line.long 0x8 "BLE_IRQ_ENABLE,BLE_IRQ_ENABLE register"
bitfld.long 0x8 4. "PORT_CMD_END,IP_BLE Port command end interrup enable" "0,1"
bitfld.long 0x8 3. "PORT_CMD_START,IP_BLE Port command start interrup enable" "0,1"
bitfld.long 0x8 1. "PORT_RELEASE,IP_BLE Port release interrupt enable" "0,1"
bitfld.long 0x8 0. "PORT_GRANT,IP_BLE Port grant interrupt enable" "0,1"
line.long 0xC "BLE_IRQ_STATUS,BLE_IRQ_STATUS register"
bitfld.long 0xC 4. "CMD_END,IP_BLE hardware port command end interrupt status." "0,1"
bitfld.long 0xC 3. "CMD_START,IP_BLE hardware port command start interrupt status." "0,1"
bitfld.long 0xC 1. "PORT_RELEASE,IP_BLE hardware port released interrupt status." "0,1"
bitfld.long 0xC 0. "PORT_GRANT,IP_BLE hardware port granted interrupt status:" "0,1"
group.long 0x60++0xF
line.long 0x0 "VP_CPU_CMD_BUS,VP_CPU_CMD_BUS register"
bitfld.long 0x0 3. "COMMAND_REQ,CPU Virtual port command request:" "0,1"
bitfld.long 0x0 0.--2. "COMMAND,command number" "0,1,2,3,4,5,6,7"
line.long 0x4 "VP_CPU_SEMA_BUS,VP_CPU_SEMA_BUS register"
bitfld.long 0x4 3. "TAKE_REQ,semaphore token request:" "0,1"
bitfld.long 0x4 0.--2. "TAKE_PRIO,semaphore priority: priority value (between 0 and 7) of the take request." "0,1,2,3,4,5,6,7"
line.long 0x8 "VP_CPU_IRQ_ENABLE,VP_CPU_IRQ_ENABLE register"
bitfld.long 0x8 4. "PORT_CMD_END,CPU virtual port command end interrup enable" "0,1"
bitfld.long 0x8 3. "PORT_CMD_START,CPU virtual port command start interrup enable" "0,1"
bitfld.long 0x8 1. "PORT_RELEASE,CPU virtual port release interrupt enable" "0,1"
bitfld.long 0x8 0. "PORT_GRANT,CPU virtual port grant interrupt enable" "0,1"
line.long 0xC "VP_CPU_IRQ_STATUS,VP_CPU_IRQ_STATUS register"
bitfld.long 0xC 4. "CMD_END,CPU virtual port command end interrupt status." "0,1"
bitfld.long 0xC 3. "CMD_START,CPU virtual port command start interrupt status." "0,1"
bitfld.long 0xC 2. "PORT_PREEMPT,CPU virtual port preemption (at semaphore level) interrupt status." "0,1"
bitfld.long 0xC 1. "PORT_RELEASE,virtual port released interrupt status." "0,1"
newline
bitfld.long 0xC 0. "PORT_GRANT,CPU virtual port granted interrupt status." "0,1"
tree.end
endif
tree "RTC (Real-time Clock)"
base ad:0x40004000
group.long 0x0++0x17
line.long 0x0 "RTC_TR,RTC_TR register"
bitfld.long 0x0 22. "PM,AM/PM notation." "0: AM or 24-hour format,1: PM"
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
line.long 0x4 "RTC_DR,RTC_DR register"
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format."
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format."
newline
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,?"
bitfld.long 0x4 12. "MT,Month tens in BCD format." "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format."
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format."
line.long 0x8 "RTC_CR,RTC_CR register"
bitfld.long 0x8 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
bitfld.long 0x8 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,?,?"
newline
bitfld.long 0x8 20. "POL,Output polarity" "0: The pin is high when ALRAF/WUTF is asserted,1: The pin is low when ALRAF/WUTF is asserted"
bitfld.long 0x8 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
newline
bitfld.long 0x8 18. "BKP,Backup" "0,1"
bitfld.long 0x8 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time"
newline
bitfld.long 0x8 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time"
bitfld.long 0x8 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
newline
bitfld.long 0x8 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
bitfld.long 0x8 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
newline
bitfld.long 0x8 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
bitfld.long 0x8 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
newline
bitfld.long 0x8 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values,1: Calendar values"
bitfld.long 0x8 0.--2. "WUCKSEL,Wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,?,?,?,?,?,?"
line.long 0xC "RTC_ISR,RTC_ISR register"
bitfld.long 0xC 16. "RECALPF,Recalibration pending Flag" "0,1"
bitfld.long 0xC 10. "WUTF,Wakeup timer flag" "0,1"
newline
bitfld.long 0xC 8. "ALRAF,Alarm A flag" "0,1"
bitfld.long 0xC 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0xC 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
bitfld.long 0xC 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
newline
bitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed,1: Wakeup timer configuration update allowed"
bitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
newline
endif
sif (cpuis("STM32WB06*"))
rbitfld.long 0xC 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0xC 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
endif
bitfld.long 0xC 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
newline
sif (cpuis("STM32WB06*"))
rbitfld.long 0xC 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0xC 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
endif
bitfld.long 0xC 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
newline
sif (cpuis("STM32WB06*"))
rbitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed,1: Wakeup timer configuration update allowed"
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed,1: Wakeup timer configuration update allowed"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed,1: Wakeup timer configuration update allowed"
endif
sif (cpuis("STM32WB07*"))
rbitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
endif
sif (cpuis("STM32WB06*"))
rbitfld.long 0xC 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
endif
line.long 0x10 "RTC_PRER,RTC_PRER register"
hexmask.long.byte 0x10 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
hexmask.long.word 0x10 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
line.long 0x14 "RTC_WUTR,RTC_WUTR register"
hexmask.long.word 0x14 0.--15. 1. "WUT,Wakeup auto-reload value bits"
group.long 0x1C++0x3
line.long 0x0 "RTC_ALRMAR,RTC_ALRMAR register"
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in Alarm A comparison"
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day"
newline
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format." "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format."
newline
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in Alarm A comparison"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
newline
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
newline
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in Alarm A comparison"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in Alarm A comparison"
newline
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
wgroup.long 0x24++0x3
line.long 0x0 "RTC_WPR,RTC_WPR register"
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
rgroup.long 0x28++0x3
line.long 0x0 "RTC_SSR,RTC_SSR register"
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
wgroup.long 0x2C++0x3
line.long 0x0 "RTC_SHIFTR,RTC_SHIFTR register"
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
group.long 0x3C++0x3
line.long 0x0 "RTC_CALR,RTC_CALR register"
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5 ppm" "0: No RTCCLK pulses are added,1: One RTCCLK pulse is effectively inserted every.."
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
newline
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
group.long 0x44++0x3
line.long 0x0 "RTC_ALRMASSR,RTC_ALRMASSR register"
hexmask.long.byte 0x0 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
hexmask.long.word 0x0 0.--14. 1. "SS,Sub seconds value"
group.long 0x50++0x7
line.long 0x0 "RTC_BKP0R,RTC_BKP0R register"
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x4 "RTC_BKP1R,RTC_BKP1R register"
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
tree "SPI3"
base ad:0x41007000
group.word 0x0++0x1
line.word 0x0 "SPIx_CR1,SPI control register 1"
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
newline
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
newline
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
newline
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
group.word 0x4++0x1
line.word 0x0 "SPIx_CR2,SPI control register 2"
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
newline
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
newline
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
group.word 0x8++0x1
line.word 0x0 "SPIx_SR,SPI status register"
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
newline
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
newline
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
newline
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
newline
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
group.word 0xC++0x1
line.word 0x0 "SPIx_DR,SPI data register"
hexmask.word 0x0 0.--15. 1. "DR,Data register"
group.word 0x10++0x1
line.word 0x0 "SPIx_CRCPR,SPI CRC polynomial register"
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.word 0x14++0x1
line.word 0x0 "SPIx_RXCRCR,SPI Rx CRC register"
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
rgroup.word 0x18++0x1
line.word 0x0 "SPIx_TXCRCR,SPI Tx CRC register"
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
group.word 0x1C++0x1
line.word 0x0 "SPIx_I2SCFGR,SPIx_I2S configuration register"
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
newline
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
newline
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I<sup>2</sup>S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
newline
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
newline
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
group.word 0x20++0x1
line.word 0x0 "SPIx_I2SPR,SPIx_I2S prescaler register"
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
newline
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
tree.end
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "SPI2"
base ad:0x41003000
group.long 0x0++0x13
line.long 0x0 "SPI2_CR1,SPI2_CR1 register"
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable. This bit enables half-duplex communication using" "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled,1: Output enabled"
newline
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation Enabled"
bitfld.long 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer,1: Next transmit value is from Tx CRC register"
newline
bitfld.long 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.long 0x0 10. "RXONLY,Receive only mode enabled." "0: Full duplex,1: Output disabled"
newline
bitfld.long 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.long 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,?,?,?,?,?,?"
bitfld.long 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.long 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.long 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
line.long 0x4 "SPI2_CR2,SPI2_CR2 register"
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
newline
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked"
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked"
newline
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.long 0x4 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.long 0x4 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
line.long 0x8 "SPI2_SR,SPI2_SR register"
rbitfld.long 0x8 11.--12. "FTLVL,FIFO Transmission Level" "0: FIFO empty,1: 1/4 FIFO,?,?"
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,?,?"
newline
rbitfld.long 0x8 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.long 0x8 7. "BSY,Busy flag" "0: SPI,1: SPI"
newline
rbitfld.long 0x8 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.long 0x8 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
rbitfld.long 0x8 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
newline
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0: No more empty space in Tx buffer,1: At least one empty space in Tx buffer"
newline
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
line.long 0xC "SPI2_DR,SPI2_DR register"
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
line.long 0x10 "SPI2_CRCPR,SPI2_CRCPR register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "SPI2_RXCRCR,SPI2_RXCRCR register"
hexmask.long.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
line.long 0x4 "SPI2_TXCRCR,SPI2_TXCRCR register"
hexmask.long.word 0x4 0.--15. 1. "TXCRC,Tx CRC register"
group.long 0x1C++0x7
line.long 0x0 "SPI2_I2SCFGR,SPI2_I2SCFGR register"
bitfld.long 0x0 12. "ASTREN,Asynchronous start enable." "0: The Asynchronous start is disabled,1: The Asynchronous start is enabled"
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
newline
bitfld.long 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave,1: Slave,?,?"
newline
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard,?,?"
newline
bitfld.long 0x0 3. "CKPOL,Steady state clock polarity" "0: I2S clock steady state is low level,1: I2S clock steady state is high level"
bitfld.long 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,?,?"
newline
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
line.long 0x4 "SPI2_I2SPR,SPI2_I2SPR register"
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
bitfld.long 0x4 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is ="
newline
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2S linear prescaler"
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "SPI1"
base ad:0x41002000
group.long 0x0++0x13
line.long 0x0 "SPI1_CR1,SPI1_CR1 register"
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode enable. This bit enables half-duplex communication using" "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled,1: Output enabled"
newline
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation Enabled"
bitfld.long 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer,1: Next transmit value is from Tx CRC register"
newline
bitfld.long 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.long 0x0 10. "RXONLY,Receive only mode enabled." "0: Full duplex,1: Output disabled"
newline
bitfld.long 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.long 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,?,?,?,?,?,?"
bitfld.long 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.long 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.long 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
line.long 0x4 "SPI1_CR2,SPI1_CR2 register"
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
newline
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked"
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked"
newline
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.long 0x4 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.long 0x4 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
line.long 0x8 "SPI1_SR,SPI1_SR register"
rbitfld.long 0x8 11.--12. "FTLVL,FIFO Transmission Level" "0: FIFO empty,1: 1/4 FIFO,?,?"
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,?,?"
newline
rbitfld.long 0x8 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.long 0x8 7. "BSY,Busy flag" "0: SPI,1: SPI"
newline
rbitfld.long 0x8 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.long 0x8 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
rbitfld.long 0x8 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
newline
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0: No more empty space in Tx buffer,1: At least one empty space in Tx buffer"
newline
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
line.long 0xC "SPI1_DR,SPI1_DR register"
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
line.long 0x10 "SPI1_CRCPR,SPI1_CRCPR register"
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.long 0x14++0x7
line.long 0x0 "SPI1_RXCRCR,SPI1_RXCRCR register"
hexmask.long.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
line.long 0x4 "SPI1_TXCRCR,SPI1_TXCRCR register"
hexmask.long.word 0x4 0.--15. 1. "TXCRC,Tx CRC register"
group.long 0x1C++0x7
line.long 0x0 "SPI1_I2SCFGR,SPI1_I2SCFGR register"
bitfld.long 0x0 12. "ASTREN,Asynchronous start enable." "0: The Asynchronous start is disabled,1: The Asynchronous start is enabled"
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
newline
bitfld.long 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave,1: Slave,?,?"
newline
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
bitfld.long 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard,?,?"
newline
bitfld.long 0x0 3. "CKPOL,Steady state clock polarity" "0: I2S clock steady state is low level,1: I2S clock steady state is high level"
bitfld.long 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,?,?"
newline
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
line.long 0x4 "SPI1_I2SPR,SPI1_I2SPR register"
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
bitfld.long 0x4 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is ="
newline
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,I2S linear prescaler"
tree.end
endif
tree.end
tree "SYSTEM_CTRL (System Controller)"
base ad:0x40000000
rgroup.long 0x0++0x7
line.long 0x0 "DIE_ID,DIE_ID register"
hexmask.long.byte 0x0 8.--11. 1. "PRODUCT,Product version."
hexmask.long.byte 0x0 4.--7. 1. "VERSION,Cut version"
newline
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Cut revision (metal fix)"
line.long 0x4 "JTAG_ID,JTAG_ID register"
hexmask.long.byte 0x4 28.--31. 1. "VERSION_NUMBER,Version"
hexmask.long.word 0x4 12.--27. 1. "PART_NUMBER,Part number"
newline
hexmask.long.word 0x4 1.--11. 1. "MANUF_ID,Manufacturer ID"
group.long 0x8++0x1F
line.long 0x0 "I2C_FMP_CTRL,I2C_FMP_CTRL register"
bitfld.long 0x0 3. "I2C1_PB7_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PB7 I/O." "0: PB7 pin operated in standard mode,1: FM+ mode is enabled on PB7 pin"
bitfld.long 0x0 2. "I2C1_PB6_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PB6 I/O." "0: PB6 pin operated in standard mode,1: FM+ mode is enabled on PB6 pin"
newline
bitfld.long 0x0 1. "I2C1_PA1_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O." "0: PA1 pin operated in standard mode,1: FM+ mode is enabled on PA1 pin"
bitfld.long 0x0 0. "I2C1_PA0_FMP,I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O." "0: PA0 pin operated in standard mode,1: FM+ mode is enabled on PA0 pin"
line.long 0x4 "IO_DTR,IO_DTR register"
bitfld.long 0x4 31. "PB15_DT,PB15_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 30. "PB14_DT,PB14_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 29. "PB13_DT,PB13_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 28. "PB12_DT,PB12_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 27. "PB11_DT,PB11_DT:Interrupt Detection Type for port B I/Os." "0,1"
bitfld.long 0x4 26. "PB10_DT,PB10_DT:Interrupt Detection Type for port B I/Os." "0,1"
newline
bitfld.long 0x4 25. "PB9_DT,PB9_DT:Interrupt Detection Type for port B I/Os." "0,1"
bitfld.long 0x4 24. "PB8_DT,PB8_DT:Interrupt Detection Type for port B I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 27. "PB11_DT,PB11_DT:Interrupt Detection Type for port B I/Os." "0,1"
bitfld.long 0x4 26. "PB10_DT,PB10_DT:Interrupt Detection Type for port B I/Os." "0,1"
newline
bitfld.long 0x4 25. "PB9_DT,PB9_DT:Interrupt Detection Type for port B I/Os." "0,1"
bitfld.long 0x4 24. "PB8_DT,PB8_DT:Interrupt Detection Type for port B I/Os." "0,1"
newline
endif
bitfld.long 0x4 23. "PB7_DT,PB7_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 22. "PB6_DT,PB6_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 21. "PB5_DT,PB5_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 20. "PB4_DT,PB4_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 19. "PB3_DT,PB3_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 18. "PB2_DT,PB2_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 17. "PB1_DT,PB1_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 16. "PB0_DT,PB0_DT: Interrupt Detection Type for port B I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 11. "PA11_DT,PA11_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 10. "PA10_DT,PA10_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 9. "PA9_DT,PA9_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 8. "PA8_DT,PA8_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x4 7. "PA7_DT,PA7_DT:Interrupt Detection Type for port A I/Os." "0,1"
bitfld.long 0x4 6. "PA6_DT,PA6_DT:Interrupt Detection Type for port A I/Os." "0,1"
newline
bitfld.long 0x4 5. "PA5_DT,PA5_DT:Interrupt Detection Type for port A I/Os." "0,1"
bitfld.long 0x4 4. "PA4_DT,PA4_DT:Interrupt Detection Type for port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x4 7. "PA7_DT,PA7_DT:Interrupt Detection Type for port A I/Os." "0,1"
bitfld.long 0x4 6. "PA6_DT,PA6_DT:Interrupt Detection Type for port A I/Os." "0,1"
newline
bitfld.long 0x4 5. "PA5_DT,PA5_DT:Interrupt Detection Type for port A I/Os." "0,1"
bitfld.long 0x4 4. "PA4_DT,PA4_DT:Interrupt Detection Type for port A I/Os." "0,1"
newline
endif
bitfld.long 0x4 3. "PA3_DT,PA3_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 2. "PA2_DT,PA2_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
newline
bitfld.long 0x4 1. "PA1_DT,PA1_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
bitfld.long 0x4 0. "PA0_DT,PA0_DT: Interrupt Detection Type for port A I/Os." "0: edge detection,1: level detection"
line.long 0x8 "IO_IBER,IO_IBER register"
bitfld.long 0x8 31. "PB15_IBE,PB15_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 30. "PB14_IBE,PB14_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 29. "PB13_IBE,PB13_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 28. "PB12_IBE,PB12_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 27. "PB11_IBE,PB11_IBE: Interrupt edge selection for port B I/Os." "0,1"
bitfld.long 0x8 26. "PB10_IBE,PB10_IBE: Interrupt edge selection for port B I/Os." "0,1"
newline
bitfld.long 0x8 25. "PB9_IBE,PB9_IBE: Interrupt edge selection for port B I/Os." "0,1"
bitfld.long 0x8 24. "PB8_IBE,PB8_IBE: Interrupt edge selection for port B I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 27. "PB11_IBE,PB11_IBE: Interrupt edge selection for port B I/Os." "0,1"
bitfld.long 0x8 26. "PB10_IBE,PB10_IBE: Interrupt edge selection for port B I/Os." "0,1"
newline
bitfld.long 0x8 25. "PB9_IBE,PB9_IBE: Interrupt edge selection for port B I/Os." "0,1"
bitfld.long 0x8 24. "PB8_IBE,PB8_IBE: Interrupt edge selection for port B I/Os." "0,1"
newline
endif
bitfld.long 0x8 23. "PB7_IBE,PB7_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 22. "PB6_IBE,PB6_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 21. "PB5_IBE,PB5_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 20. "PB4_IBE,PB4_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 19. "PB3_IBE,PB3_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 18. "PB2_IBE,PB2_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 17. "PB1_IBE,PB1_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 16. "PB0_IBE,PB0_IBE: Interrupt edge selection for port B I/Os." "0: single edge detection,1: both edges detection"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 15. "PA15_IBE,PA15_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 14. "PA14_IBE,PA14_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
bitfld.long 0x8 13. "PA13_IBE,PA13_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 12. "PA12_IBE,PA12_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 15. "PA15_IBE,PA15_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 14. "PA14_IBE,PA14_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
bitfld.long 0x8 13. "PA13_IBE,PA13_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 12. "PA12_IBE,PA12_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
endif
bitfld.long 0x8 11. "PA11_IBE,PA11_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 10. "PA10_IBE,PA10_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 9. "PA9_IBE,PA9_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 8. "PA8_IBE,PA8_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x8 7. "PA7_IBE,PA7_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 6. "PA6_IBE,PA6_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
bitfld.long 0x8 5. "PA5_IBE,PA5_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 4. "PA4_IBE,PA4_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x8 7. "PA7_IBE,PA7_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 6. "PA6_IBE,PA6_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
bitfld.long 0x8 5. "PA5_IBE,PA5_IBE: Interrupt edge selection for Port A I/Os." "0,1"
bitfld.long 0x8 4. "PA4_IBE,PA4_IBE: Interrupt edge selection for Port A I/Os." "0,1"
newline
endif
bitfld.long 0x8 3. "PA3_IBE,PA3_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 2. "PA2_IBE,PA2_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
newline
bitfld.long 0x8 1. "PA1_IBE,PA1_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
bitfld.long 0x8 0. "PA0_IBE,PA0_IBE: Interrupt edge selection for Port A I/Os." "0: single edge detection,1: both edges detection"
line.long 0xC "IO_IEVR,IO_IEVR register"
bitfld.long 0xC 31. "PB15_IEV,PB15_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 30. "PB14_IEV,PB14_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 29. "PB13_IEV,PB13_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 28. "PB12_IEV,PB12_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0xC 27. "PB11_IEV,PB11_IEV : Interrupt polarity event for Port B I/Os." "0,1"
bitfld.long 0xC 26. "PB10_IEV,PB10_IEV : Interrupt polarity event for Port B I/Os." "0,1"
newline
bitfld.long 0xC 25. "PB9_IEV,PB9_IEV : Interrupt polarity event for Port B I/Os." "0,1"
bitfld.long 0xC 24. "PB8_IEV,PB8_IEV : Interrupt polarity event for Port B I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0xC 27. "PB11_IEV,PB11_IEV : Interrupt polarity event for Port B I/Os." "0,1"
bitfld.long 0xC 26. "PB10_IEV,PB10_IEV : Interrupt polarity event for Port B I/Os." "0,1"
newline
bitfld.long 0xC 25. "PB9_IEV,PB9_IEV : Interrupt polarity event for Port B I/Os." "0,1"
bitfld.long 0xC 24. "PB8_IEV,PB8_IEV : Interrupt polarity event for Port B I/Os." "0,1"
newline
endif
bitfld.long 0xC 23. "PB7_IEV,PB7_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 22. "PB6_IEV,PB6_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 21. "PB5_IEV,PB5_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 20. "PB4_IEV,PB4_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 19. "PB3_IEV,PB3_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 18. "PB2_IEV,PB2_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 17. "PB1_IEV,PB1_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 16. "PB0_IEV,PB0_IEV : Interrupt polarity event for Port B I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0xC 15. "PA15_IEV,PA15_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 14. "PA14_IEV,PA14_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
bitfld.long 0xC 13. "PA13_IEV,PA13_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 12. "PA12_IEV,PA12_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0xC 15. "PA15_IEV,PA15_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 14. "PA14_IEV,PA14_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
bitfld.long 0xC 13. "PA13_IEV,PA13_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 12. "PA12_IEV,PA12_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
endif
bitfld.long 0xC 11. "PA11_IEV,PA11_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 10. "PA10_IEV,PA10_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 9. "PA9_IEV,PA9_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 8. "PA8_IEV,PA8_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0xC 7. "PA7_IEV,PA7_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 6. "PA6_IEV,PA6_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
bitfld.long 0xC 5. "PA5_IEV,PA5_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 4. "PA4_IEV,PA4_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0xC 7. "PA7_IEV,PA7_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 6. "PA6_IEV,PA6_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
bitfld.long 0xC 5. "PA5_IEV,PA5_IEV : Interrupt polarity event for Port A I/Os." "0,1"
bitfld.long 0xC 4. "PA4_IEV,PA4_IEV : Interrupt polarity event for Port A I/Os." "0,1"
newline
endif
bitfld.long 0xC 3. "PA3_IEV,PA3_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 2. "PA2_IEV,PA2_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
newline
bitfld.long 0xC 1. "PA1_IEV,PA1_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
bitfld.long 0xC 0. "PA0_IEV,PA0_IEV : Interrupt polarity event for Port A I/Os." "0: falling edge / low level,1: rising edge / high level"
line.long 0x10 "IO_IER,IO_IER register"
bitfld.long 0x10 31. "PB15_IE,PB15_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 30. "PB14_IE,PB14_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 29. "PB13_IE,PB13_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 28. "PB12_IE,PB12_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x10 27. "PB11_IE,PB11_IE: Interrupt enable for port B I/Os." "0,1"
bitfld.long 0x10 26. "PB10_IE,PB10_IE: Interrupt enable for port B I/Os." "0,1"
newline
bitfld.long 0x10 25. "PB9_IE,PB9_IE: Interrupt enable for port B I/Os." "0,1"
bitfld.long 0x10 24. "PB8_IE,PB8_IE: Interrupt enable for port B I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x10 27. "PB11_IE,PB11_IE: Interrupt enable for port B I/Os." "0,1"
bitfld.long 0x10 26. "PB10_IE,PB10_IE: Interrupt enable for port B I/Os." "0,1"
newline
bitfld.long 0x10 25. "PB9_IE,PB9_IE: Interrupt enable for port B I/Os." "0,1"
bitfld.long 0x10 24. "PB8_IE,PB8_IE: Interrupt enable for port B I/Os." "0,1"
newline
endif
bitfld.long 0x10 23. "PB7_IE,PB7_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 22. "PB6_IE,PB6_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 21. "PB5_IE,PB5_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 20. "PB4_IE,PB4_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 19. "PB3_IE,PB3_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 18. "PB2_IE,PB2_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 17. "PB1_IE,PB1_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 16. "PB0_IE,PB0_IE: Interrupt enable for port B I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x10 15. "PA15_IE,PA15_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 14. "PA14_IE,PA14_IE: Interrupt enable for port A I/Os." "0,1"
newline
bitfld.long 0x10 13. "PA13_IE,PA13_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 12. "PA12_IE,PA12_IE: Interrupt enable for port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x10 15. "PA15_IE,PA15_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 14. "PA14_IE,PA14_IE: Interrupt enable for port A I/Os." "0,1"
newline
bitfld.long 0x10 13. "PA13_IE,PA13_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 12. "PA12_IE,PA12_IE: Interrupt enable for port A I/Os." "0,1"
newline
endif
bitfld.long 0x10 11. "PA11_IE,PA11_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 10. "PA10_IE,PA10_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 9. "PA9_IE,PA9_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 8. "PA8_IE,PA8_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x10 7. "PA7_IE,PA7_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 6. "PA6_IE,PA6_IE: Interrupt enable for port A I/Os." "0,1"
newline
bitfld.long 0x10 5. "PA5_IE,PA5_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 4. "PA4_IE,PA4_IE: Interrupt enable for port A I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x10 7. "PA7_IE,PA7_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 6. "PA6_IE,PA6_IE: Interrupt enable for port A I/Os." "0,1"
newline
bitfld.long 0x10 5. "PA5_IE,PA5_IE: Interrupt enable for port A I/Os." "0,1"
bitfld.long 0x10 4. "PA4_IE,PA4_IE: Interrupt enable for port A I/Os." "0,1"
newline
endif
bitfld.long 0x10 3. "PA3_IE,PA3_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 2. "PA2_IE,PA2_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
newline
bitfld.long 0x10 1. "PA1_IE,PA1_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
bitfld.long 0x10 0. "PA0_IE,PA0_IE: Interrupt enable for port A I/Os." "0: interrupt is disabled,1: interrupt is enabled"
line.long 0x14 "IO_ISCR,IO_ISCR register"
bitfld.long 0x14 31. "PB15_ISC,PB15_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 30. "PB14_ISC,PB14_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 29. "PB13_ISC,PB13_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 28. "PB12_ISC,PB12_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x14 27. "PB11_ISC,PB11_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
bitfld.long 0x14 26. "PB10_ISC,PB10_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
newline
bitfld.long 0x14 25. "PB9_ISC,PB9_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
bitfld.long 0x14 24. "PB8_ISC,PB8_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x14 27. "PB11_ISC,PB11_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
bitfld.long 0x14 26. "PB10_ISC,PB10_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
newline
bitfld.long 0x14 25. "PB9_ISC,PB9_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
bitfld.long 0x14 24. "PB8_ISC,PB8_ISC: Interrupt status (before mask) for port B I/Os.." "0,1"
newline
endif
bitfld.long 0x14 23. "PB7_ISC,PB7_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 22. "PB6_ISC,PB6_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 21. "PB5_ISC,PB5_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 20. "PB4_ISC,PB4_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 19. "PB3_ISC,PB3_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 18. "PB2_ISC,PB2_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 17. "PB1_ISC,PB1_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 16. "PB0_ISC,PB0_ISC: Interrupt status (before mask) for port B I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x14 15. "PA15_ISC,PA15_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
bitfld.long 0x14 14. "PA14_ISC,PA14_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
newline
bitfld.long 0x14 13. "PA13_ISC,PA13_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
bitfld.long 0x14 12. "PA12_ISC,PA12_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x14 15. "PA15_ISC,PA15_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
bitfld.long 0x14 14. "PA14_ISC,PA14_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
newline
bitfld.long 0x14 13. "PA13_ISC,PA13_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
bitfld.long 0x14 12. "PA12_ISC,PA12_ISC: Interrupt status (before mask) for port a I/Os." "0,1"
newline
endif
bitfld.long 0x14 11. "PA11_ISC,PA11_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 10. "PA10_ISC,PA10_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 9. "PA9_ISC,PA9_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 8. "PA8_ISC,PA8_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
sif (cpuis("STM32WB06*"))
bitfld.long 0x14 7. "PA7_ISC,PA7_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
bitfld.long 0x14 6. "PA6_ISC,PA6_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
newline
bitfld.long 0x14 5. "PA5_ISC,PA5_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
bitfld.long 0x14 4. "PA4_ISC,PA4_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
newline
endif
sif (cpuis("STM32WB07*"))
bitfld.long 0x14 7. "PA7_ISC,PA7_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
bitfld.long 0x14 6. "PA6_ISC,PA6_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
newline
bitfld.long 0x14 5. "PA5_ISC,PA5_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
bitfld.long 0x14 4. "PA4_ISC,PA4_ISC: Interrupt status (before mask) for port a I/Os.." "0,1"
newline
endif
bitfld.long 0x14 3. "PA3_ISC,PA3_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 2. "PA2_ISC,PA2_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
newline
bitfld.long 0x14 1. "PA1_ISC,PA1_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
bitfld.long 0x14 0. "PA0_ISC,PA0_ISC: Interrupt status (before mask) for port a I/Os." "0: no pending interrupt,1: event occurred on corresponding I/O / interrupt.."
line.long 0x18 "PWRC_IER,PWRC_IER register"
bitfld.long 0x18 2. "WKUP_IE,WKUP_IE: Power Controller Wakeup event interrupt enable." "0: Interrupt on wakeup event seen by the PWRC is..,1: Interrupt on wakeup event seen by the PWRC is.."
bitfld.long 0x18 1. "PVD_IE,PVD_IE: Programmable Voltage Detector interrupt enable." "0: PVD interrupt is disabled,1: PVD interrupt is enabled"
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0x18 0. "BORH_IE,BORH_IE: BORH interrupt enable." "0: BORH interrupt is disabled,1: BORH interrupt is enabled"
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x18 0. "BORH_IE,BORH_IE: BORH interrupt enable." "0: BORH interrupt is disabled,1: BORH interrupt is enabled"
endif
line.long 0x1C "PWRC_ISCR,PWRC_ISCR register"
bitfld.long 0x1C 2. "WKUP_ISC,WKUP_ISC: Indicates the Power Controller receives a Wakeup event." "0: no pending interrupt,1: Wakeup event on PWRC occurred / interrupt occurred"
bitfld.long 0x1C 1. "PVD_ISC,PVD_ISC: Programmable Voltage Detector status." "0: no pending interrupt,1: voltage went under programmed threshold /.."
newline
sif (cpuis("STM32WB05*"))
bitfld.long 0x1C 0. "BORH_ISC,BORH_ISC: BORH interrupt status." "0: no pending interrupt,1: voltage went under BORH threshold / interrupt.."
endif
sif (cpuis("STM32WB09*"))
bitfld.long 0x1C 0. "BORH_ISC,BORH_ISC: BORH interrupt status." "0: no pending interrupt,1: voltage went under BORH threshold / interrupt.."
endif
group.long 0x2C++0xF
line.long 0x0 "BLERXTX_DTR,BLERXTX_DTR register"
bitfld.long 0x0 1. "RX_DT,RX_DT: detection type on RX_SEQUENCE signal:" "0: detection on edge,1: detection on level"
bitfld.long 0x0 0. "TX_DT,TX_DT: detection type on TX_SEQUENCE signal:" "0: detection on edge,1: detection on level"
line.long 0x4 "BLERXTX_IBER,BLERXTX_IBER register"
bitfld.long 0x4 1. "RX_IBE,RX_IBE: interrupt edge register on RX_SEQUENCE signal:" "0: detection on single edge,1: detection on both edges"
bitfld.long 0x4 0. "TX_IBE,TX_IBE: interrupt edge register on TX_SEQUENCE signal:" "0: detection on single edge,1: detection on both edges"
line.long 0x8 "BLERXTX_IEVR,BLERXTX_IEVR register"
bitfld.long 0x8 1. "RX_IEV,RX_IEV: interrupt polarity event on RX_SEQUENCE signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
bitfld.long 0x8 0. "TX_IEV,TX_IEV: interrupt polarity event on TX_SEQUENCE signal:" "0: detection on falling edge / low level,1: detection on rising edge / high level"
line.long 0xC "BLERXTX_IER,BLERXTX_IER register"
bitfld.long 0xC 1. "RX_IE,RX_IE: interrupt enable on RX_SEQUENCE signal:" "0: RX_SEQUENCE interrupt is disabled,1: RX_SEQUENCE interrupt is enabled"
bitfld.long 0xC 0. "TX_IE,TX_IE: interrupt enable on TX_SEQUENCE signal:" "0: TX_SEQUENCE interrupt is disabled,1: TX_SEQUENCE interrupt is enabled"
rgroup.byte 0x3C++0x0
line.byte 0x0 "BLERXTX_ISCR,BLERXTX_ISCR register"
sif (cpuis("STM32WB05*"))
bitfld.byte 0x0 3. "RX_ISEDGE,RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal:" "0: falling edge on RX_SEQUENCE detected,1: rising edge on RX_SEQUENCE detected"
bitfld.byte 0x0 2. "TX_ISEDGE,TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal:" "0: falling edge on TX_SEQUENCE detected,1: rising edge on TX_SEQUENCE detected"
newline
endif
sif (cpuis("STM32WB09*"))
bitfld.byte 0x0 3. "RX_ISEDGE,RX_ISEDGE: interrupt edge status on RX_SEQUENCE signal:" "0: falling edge on RX_SEQUENCE detected,1: rising edge on RX_SEQUENCE detected"
bitfld.byte 0x0 2. "TX_ISEDGE,TX_ISEDGE: interrupt edge status on TX_SEQUENCE signal:" "0: falling edge on TX_SEQUENCE detected,1: rising edge on TX_SEQUENCE detected"
newline
endif
bitfld.byte 0x0 1. "RX_ISC,RX_ISC: interrupt status on RX_SEQUENCE signal (can be a rising or a falling edge" "0: no activity on RX_SEQUENCE detected,1: activity on RX_SEQUENCE occurred"
bitfld.byte 0x0 0. "TX_ISC,TX_ISC:interrupt status on TX_SEQUENCE signal (can be a rising or a falling edge" "0: no activity on TX_SEQUENCE detected,1: activity on TX_SEQUENCE occurred"
tree.end
tree "TIM (Timers)"
base ad:0x0
sif (cpuis("STM32WB05*")||cpuis("STM32WB09*"))
tree "TIM2"
base ad:0x40002000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIF_REMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
newline
bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 5.--6. "CMS,CMS[1:0]: Center-aligned mode selection" "0: Edge-aligned mode,1: Center-aligned mode 1,?,?"
newline
bitfld.long 0x0 4. "DIR,DIR: Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
newline
bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
newline
bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 7. "TI1S,TI1S: TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1"
bitfld.long 0x4 4.--6. "MMS,MMS: Master Mode Selection." "0: Reset - the UG bit from the GPT_EGR register is..,1: Enable - the Counter Enable signal cnt_en is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REF signal is used as trigger..,5: Compare - OC2REF signal is used as trigger..,6: Compare - OC3REF signal is used as trigger..,7: Compare - OC4REF signal is used as trigger.."
newline
bitfld.long 0x4 3. "CCDS,CCDS: Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
line.long 0x8 "SMCR,SMCR register"
bitfld.long 0x8 20.--21. "TS_4_3,Extended trigger selection. Not used. Not available in IUM" "0,1,2,3"
bitfld.long 0x8 16. "SMS_3,SMS[3]: Slave mode selection - bit 3" "0,1"
newline
bitfld.long 0x8 15. "ETP,ETP: External trigger polarity" "0: ETR is non-inverted,1: ETR is inverted"
bitfld.long 0x8 14. "ECE,ECE: External clock enable" "0: External clock mode 2 disabled,1: Setting the ECE bit has the same effect as.."
newline
bitfld.long 0x8 12.--13. "ETPS,ETPS[1:0]: External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,?,?"
hexmask.long.byte 0x8 8.--11. 1. "ETF,ETF[3:0]: External trigger filter"
newline
bitfld.long 0x8 7. "MSM,MSM: Master/Slave mode" "0: No action,1: The effect of an event on the trigger input"
bitfld.long 0x8 4.--6. "TS,TS[2:0]: Trigger selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 3. "OCCS,OCCS: OCREF clear selection" "0: OCREF_CLR_INT is connected to the OCREF_CLR input,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x8 0.--2. "SMS_2_0,SMS: Slave mode selection" "0: Slave mode disabled,1: Encoder mode 1,?,?,?,?,?,?"
line.long 0xC "DIER,DIER register"
bitfld.long 0xC 14. "TDE,TDE: Trigger DMA request Enable." "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
bitfld.long 0xC 12. "CC4DE,CC4DE: Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
newline
bitfld.long 0xC 11. "CC3DE,CC3DE: Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
bitfld.long 0xC 10. "CC2DE,CC2DE: Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
newline
bitfld.long 0xC 9. "CC1DE,CC1DE: Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.long 0xC 8. "UDE,UDE: Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
newline
bitfld.long 0xC 6. "TIE,TIE: Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
bitfld.long 0xC 4. "CC4IE,CC4IE: Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
newline
bitfld.long 0xC 3. "CC3IE,CC3IE: Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
bitfld.long 0xC 2. "CC2IE,CC2IE: Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
newline
bitfld.long 0xC 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0xC 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x10 "SR,SR register"
bitfld.long 0x10 12. "CC4OF,CC4OF: Capture/Compare 4 overcapture flag" "0,1"
bitfld.long 0x10 11. "CC3OF,CC3OF: Capture/Compare 3 overcapture flag" "0,1"
newline
bitfld.long 0x10 10. "CC2OF,CC2OF: Capture/Compare 2 overcapture flag" "0,1"
bitfld.long 0x10 9. "CC1OF,CC1OF: Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.long 0x10 6. "TIF,TIF: Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
bitfld.long 0x10 4. "CC4IF,CC4IF: Capture/Compare 4 interrupt flag" "0,1"
newline
bitfld.long 0x10 3. "CC3IF,CC3IF: Capture/Compare 3 interrupt flag" "0,1"
bitfld.long 0x10 2. "CC2IF,CC2IF: Capture/Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x10 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x10 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 6. "TG,TG: Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register"
bitfld.long 0x0 4. "CC4G,CC4G: Capture/Compare 4 generation" "0,1"
newline
bitfld.long 0x0 3. "CC3G,CC3G: Capture/Compare 3 generation" "0,1"
bitfld.long 0x0 2. "CC2G,CC2G: Capture/Compare 2 generation" "0,1"
newline
bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 24. "OC2M_3,OC2M[3]: Output Compare 2 mode (bit 3)" "0,1"
bitfld.long 0x0 16. "OC1M_3,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
newline
bitfld.long 0x0 15. "OC2CE,OC2CE: Output Compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M_2_0,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC2PE,OC2PE: Output Compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,OC2FE: Output Compare 2 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC2S,CC2S[1:0]: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable" "0: OC1Ref is not affected by the ETRF Input,1: OC1Ref is cleared as soon as a High level is.."
newline
bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M: Output Compare 1 mode" "0: Frozen,1: These bits can not be modified as long as LOCK..,2: In PWM mode,?,?,?,?,?"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
newline
bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x7
line.long 0x0 "CCMR1_in"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F: Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC[1:0]: Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,CC2S: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
line.long 0x4 "CCMR2,CCMR2 register"
bitfld.long 0x4 24. "OC4M_3,OC4M[3]: Output Compare 4 mode (bit 3)" "0,1"
bitfld.long 0x4 16. "OC3M_3,OC3M[3]: Output Compare 3 mode (bit 3)" "0,1"
newline
bitfld.long 0x4 15. "OC4CE,OC4CE: Output Compare 4 clear enable" "0,1"
bitfld.long 0x4 12.--14. "OC4M_2_0,OC4M[2:0]: Output Compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "OC4PE,OC4PE: Output Compare 4 preload enable" "0,1"
bitfld.long 0x4 10. "OC4FE,OC4FE: Output Compare 4 fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
bitfld.long 0x4 7. "OC3CE,OC3CE: Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x4 4.--6. "OC3M_2_0,OC3M: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "OC3PE,OC3PE: Output compare 3 preload enable" "0,1"
newline
bitfld.long 0x4 2. "OC3FE,OC3FE: Output compare 3 fast enable" "0,1"
bitfld.long 0x4 0.--1. "CC3S,CC3S: Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
group.long 0x1C++0x27
line.long 0x0 "CCMR2_in"
hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F: Input capture 4 filter"
bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC: Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F: Input capture 3 filter"
newline
bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC: Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CC3S,CC3S: Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
line.long 0x4 "CCER,CCER register"
bitfld.long 0x4 15. "CC4NP,CC4NP: Capture/Compare 4 Complementary output Polarity." "0,1"
bitfld.long 0x4 13. "CC4P,CC4P: Capture/Compare 4 output polarity" "0,1"
newline
bitfld.long 0x4 12. "CC4E,CC4E: Capture/Compare 4 output enable" "0,1"
bitfld.long 0x4 11. "CC3NP,CC3NP: Capture/Compare 3 Complementary output Polarity." "0,1"
newline
bitfld.long 0x4 9. "CC3P,CC3P: Capture/Compare 3 output polarity" "0,1"
bitfld.long 0x4 8. "CC3E,CC3E: Capture/Compare 3 output enable" "0,1"
newline
bitfld.long 0x4 7. "CC2NP,CC2NP: Capture/Compare 2 Complementary output Polarity." "0,1"
bitfld.long 0x4 5. "CC2P,CC2P: Capture/Compare 2 output polarity" "0,1"
newline
bitfld.long 0x4 4. "CC2E,CC2E: Capture/Compare 2 output enable" "0,1"
bitfld.long 0x4 3. "CC1NP,CC1NP: Capture/Compare 1 Complementary output Polarity." "0: OC1N active high.,1: OC1N active low."
newline
bitfld.long 0x4 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x4 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x8 "CNT,CNT register"
rbitfld.long 0x8 31. "UIF_CPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0xC "PSC,PSC register"
hexmask.long.word 0xC 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0x10 "ARR,ARR register"
hexmask.long.word 0x10 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x14 "RCR,RCR register"
hexmask.long.byte 0x14 0.--7. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x18 "CCR1,CCR1 register"
hexmask.long.word 0x18 0.--15. 1. "CCR1,CCR1[15:0]: Capture/Compare 1 value"
line.long 0x1C "CCR2,CCR2 register"
hexmask.long.word 0x1C 0.--15. 1. "CCR2,CCR2[15:0]: Capture/Compare 2 value"
line.long 0x20 "CCR3,CCR3 register"
hexmask.long.word 0x20 0.--15. 1. "CCR3,CCR3[15:0]: Capture/Compare 3 value"
line.long 0x24 "CCR4,CCR4 register"
hexmask.long.word 0x24 0.--15. 1. "CCR4,CCR4[15:0]: Capture/Compare 4 value"
group.long 0x48++0x7
line.long 0x0 "DCR,DCR register"
hexmask.long.byte 0x0 8.--12. 1. "DBL,DBL[4:0]: DMA burst length"
hexmask.long.byte 0x0 0.--4. 1. "DBA,DBA[4:0]: DMA base address"
line.long 0x4 "DMAR,DMAR register"
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMAB[15:0]: DMA register for burst accesses"
group.long 0x68++0x3
line.long 0x0 "TISEL,TISEL register"
hexmask.long.byte 0x0 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
newline
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] inputt"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
tree.end
endif
sif (cpuis("STM32WB05*")||cpuis("STM32WB09*"))
tree "TIM16"
base ad:0x40005000
group.long 0x0++0x7
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIF_REMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
newline
bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
newline
bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
newline
bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 9. "OIS1N,OIS1N: Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
bitfld.long 0x4 8. "OIS1,OIS1: Output Idle state 1 (OC1 output)" "0: OC1=0,1: OC1=1"
newline
bitfld.long 0x4 3. "CCDS,CCDS: Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
bitfld.long 0x4 2. "CCUS,CCUS: Capture/compare control update selection" "0: When capture/compare control bits are preloaded,1: When capture/compare control bits are preloaded"
newline
bitfld.long 0x4 0. "CCPC,CCPC: Capture/compare preloaded control" "0: CCxE,1: CCxE"
group.long 0xC++0x7
line.long 0x0 "DIER,DIER register"
bitfld.long 0x0 15. "BDE,BDE: Break DMA request Enable." "0: Break DMA request disabled,1: Break DMA request enabled"
bitfld.long 0x0 13. "CCUDE,CCUDE: CC-Update DMA request Enable." "0: CC-Update DMA request disabled,1: CC-Update DMA request enabled"
newline
bitfld.long 0x0 9. "CC1DE,CC1DE: Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.long 0x0 8. "UDE,UDE: Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
newline
bitfld.long 0x0 7. "BIE,BIE: Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
bitfld.long 0x0 5. "COMIE,COMIE: COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
newline
bitfld.long 0x0 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0x0 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x4 "SR,SR register"
bitfld.long 0x4 9. "CC1OF,CC1OF: Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x4 7. "BIF,BIF: Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
newline
bitfld.long 0x4 5. "COMIF,COMIF: COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
bitfld.long 0x4 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.long 0x4 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 7. "BG,BG: Break generation" "0: No action,1: A break event is generated"
bitfld.long 0x0 5. "COMG,COMG: Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set"
newline
bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 16. "OC1M_3,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable." "0: OC1REF is not affected by the ocref_clr_int signal,1: OC1REF is cleared as soon as a high level is.."
newline
bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M[2:0]: Output Compare 1 mode (bits 2 to 0)" "0: Frozen,1: These bits can not be modified as long as LOCK..,2: In PWM mode 1 or 2,?,?,?,?,?"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
newline
bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x3
line.long 0x0 "CCMR1_in"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
newline
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x20++0x17
line.long 0x0 "CCER,CCER register"
bitfld.long 0x0 3. "CC1NP,CC1NP: Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
bitfld.long 0x0 2. "CC1NE,CC1NE: Capture/Compare 1 complementary output enable" "0: Off,1: On"
newline
bitfld.long 0x0 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x0 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x4 "CNT,CNT register"
rbitfld.long 0x4 31. "UIF_CPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0x8 "PSC,PSC register"
hexmask.long.word 0x8 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0xC "ARR,ARR register"
hexmask.long.word 0xC 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x10 "RCR,RCR register"
hexmask.long.byte 0x10 0.--7. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x14 "CCR1,CCR1 register"
hexmask.long.word 0x14 0.--15. 1. "CCR,CCR1[15:0]: Capture/Compare 1 value"
group.long 0x44++0xB
line.long 0x0 "BDTR,BDTR register"
bitfld.long 0x0 28. "BKBID,BKBID: Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
bitfld.long 0x0 26. "BKDSRM,BKDSRM: Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
newline
bitfld.long 0x0 15. "MOE,MOE: Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
bitfld.long 0x0 14. "AOE,AOE: Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
newline
bitfld.long 0x0 13. "BKP,BKP: Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
bitfld.long 0x0 12. "BKE,BKE: Break enable" "0: Break inputs (BRK) disabled,?"
newline
bitfld.long 0x0 11. "OSSR,OSSR: Off-state selection for Run mode" "0: When inactive,1: When inactive"
bitfld.long 0x0 10. "OSSI,OSSI: Off-state selection for Idle mode" "0: When inactive,1: When inactive"
newline
bitfld.long 0x0 8.--9. "LOCK,LOCK[1:0]: Lock configuration" "0: LOCK OFF,1: DTG bits in TIMx_BDTR register,2: LOCK Level 1 + CC Polarity bits,3: LOCK Level 2 + CC Control bits"
hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG[7:0]: Dead-time generator setup"
line.long 0x4 "DCR,DCR register"
hexmask.long.byte 0x4 8.--12. 1. "DBL,DBL[4:0]: DMA burst length"
hexmask.long.byte 0x4 0.--4. 1. "DBA,DBA[4:0]: DMA base address"
line.long 0x8 "DMAR,DMAR register"
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMAB[15:0]: DMA register for burst accesses"
group.long 0x60++0x3
line.long 0x0 "AF1,AF1 register"
bitfld.long 0x0 12.--13. "AF1_13_12,AF1[13:12]" "0,1,2,3"
bitfld.long 0x0 11. "BKCMP2P,BKCMP2P: BRK COMP2 input polarity." "0: COMP2 input is active low,1: COMP2 input is active high"
newline
bitfld.long 0x0 10. "BKCMP1P,BKCMP1P: BRK COMP1 input polarity." "0: COMP1 input is active low,1: COMP1 input is active high"
bitfld.long 0x0 9. "BKINP,BKINP: BRK BKIN input polarity." "0: BKIN input is active low,1: BKIN input is active high"
newline
hexmask.long.byte 0x0 3.--8. 1. "AF1_8_3,AF1[13:12]"
bitfld.long 0x0 2. "BKCMP2E,BKCMP1E: BRK COMP1 enable." "0: COMP1 input disabled,1: COMP1 input enabled"
newline
bitfld.long 0x0 1. "BKCMP1E,BKCMP1E: BRK COMP1 enable." "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x0 0. "BKINE,BKINE: BRK BKIN enable." "0: BKIN input disabled,1: BKIN input enabled"
group.long 0x68++0x3
line.long 0x0 "TISEL,TISEL register"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
tree.end
endif
sif (cpuis("STM32WB05*")||cpuis("STM32WB09*"))
tree "TIM17"
base ad:0x40006000
group.long 0x0++0x7
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIF_REMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
newline
bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
newline
bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
newline
bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 9. "OIS1N,OIS1N: Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
bitfld.long 0x4 8. "OIS1,OIS1: Output Idle state 1 (OC1 output)" "0: OC1=0,1: OC1=1"
newline
bitfld.long 0x4 3. "CCDS,CCDS: Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
bitfld.long 0x4 2. "CCUS,CCUS: Capture/compare control update selection" "0: When capture/compare control bits are preloaded,1: When capture/compare control bits are preloaded"
newline
bitfld.long 0x4 0. "CCPC,CCPC: Capture/compare preloaded control" "0: CCxE,1: CCxE"
group.long 0xC++0x7
line.long 0x0 "DIER,DIER register"
bitfld.long 0x0 15. "BDE,BDE: Break DMA request Enable." "0: Break DMA request disabled,1: Break DMA request enabled"
bitfld.long 0x0 13. "CCUDE,CCUDE: CC-Update DMA request Enable." "0: CC-Update DMA request disabled,1: CC-Update DMA request enabled"
newline
bitfld.long 0x0 9. "CC1DE,CC1DE: Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.long 0x0 8. "UDE,UDE: Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
newline
bitfld.long 0x0 7. "BIE,BIE: Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
bitfld.long 0x0 5. "COMIE,COMIE: COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
newline
bitfld.long 0x0 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0x0 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x4 "SR,SR register"
bitfld.long 0x4 9. "CC1OF,CC1OF: Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x4 7. "BIF,BIF: Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
newline
bitfld.long 0x4 5. "COMIF,COMIF: COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
bitfld.long 0x4 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.long 0x4 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 7. "BG,BG: Break generation" "0: No action,1: A break event is generated"
bitfld.long 0x0 5. "COMG,COMG: Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set"
newline
bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 16. "OC1M_3,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable." "0: OC1REF is not affected by the ocref_clr_int signal,1: OC1REF is cleared as soon as a high level is.."
newline
bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M[2:0]: Output Compare 1 mode (bits 2 to 0)" "0: Frozen,1: These bits can not be modified as long as LOCK..,2: In PWM mode 1 or 2,?,?,?,?,?"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
newline
bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x3
line.long 0x0 "CCMR1_in"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
newline
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x20++0x17
line.long 0x0 "CCER,CCER register"
bitfld.long 0x0 3. "CC1NP,CC1NP: Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
bitfld.long 0x0 2. "CC1NE,CC1NE: Capture/Compare 1 complementary output enable" "0: Off,1: On"
newline
bitfld.long 0x0 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x0 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x4 "CNT,CNT register"
rbitfld.long 0x4 31. "UIF_CPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x4 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0x8 "PSC,PSC register"
hexmask.long.word 0x8 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0xC "ARR,ARR register"
hexmask.long.word 0xC 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x10 "RCR,RCR register"
hexmask.long.byte 0x10 0.--7. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x14 "CCR1,CCR1 register"
hexmask.long.word 0x14 0.--15. 1. "CCR,CCR1[15:0]: Capture/Compare 1 value"
group.long 0x44++0xF
line.long 0x0 "BDTR,BDTR register"
bitfld.long 0x0 28. "BKBID,BKBID: Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
bitfld.long 0x0 26. "BKDSRM,BKDSRM: Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
newline
bitfld.long 0x0 15. "MOE,MOE: Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
bitfld.long 0x0 14. "AOE,AOE: Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
newline
bitfld.long 0x0 13. "BKP,BKP: Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
bitfld.long 0x0 12. "BKE,BKE: Break enable" "0: Break inputs (BRK) disabled,?"
newline
bitfld.long 0x0 11. "OSSR,OSSR: Off-state selection for Run mode" "0: When inactive,1: When inactive"
bitfld.long 0x0 10. "OSSI,OSSI: Off-state selection for Idle mode" "0: When inactive,1: When inactive"
newline
bitfld.long 0x0 8.--9. "LOCK,LOCK[1:0]: Lock configuration" "0: LOCK OFF,1: DTG bits in TIMx_BDTR register,2: LOCK Level 1 + CC Polarity bits,3: LOCK Level 2 + CC Control bits"
hexmask.long.byte 0x0 0.--7. 1. "DTG,DTG[7:0]: Dead-time generator setup"
line.long 0x4 "DCR,DCR register"
hexmask.long.byte 0x4 8.--12. 1. "DBL,DBL[4:0]: DMA burst length"
hexmask.long.byte 0x4 0.--4. 1. "DBA,DBA[4:0]: DMA base address"
line.long 0x8 "DMAR,DMAR register"
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMAB[15:0]: DMA register for burst accesses"
line.long 0xC "OR1,OR1 register"
bitfld.long 0xC 0.--1. "TI1_RMP,TI1_RMP[1:0]: Timer 17 input 1 connection" "0: TIM17 TI1 is connected to GPIO,1: TIM17 TI1 is connected to LCO,?,?"
group.long 0x60++0x3
line.long 0x0 "AF1,AF1 register"
bitfld.long 0x0 12.--13. "AF1_13_12,AF1[13:12]" "0,1,2,3"
bitfld.long 0x0 11. "BKCMP2P,BKCMP2P: BRK COMP2 input polarity." "0: COMP2 input is active low,1: COMP2 input is active high"
newline
bitfld.long 0x0 10. "BKCMP1P,BKCMP1P: BRK COMP1 input polarity." "0: COMP1 input is active low,1: COMP1 input is active high"
bitfld.long 0x0 9. "BKINP,BKINP: BRK BKIN input polarity." "0: BKIN input is active low,1: BKIN input is active high"
newline
hexmask.long.byte 0x0 3.--8. 1. "AF1_8_3,AF1[13:12]"
bitfld.long 0x0 2. "BKCMP2E,BKCMP1E: BRK COMP1 enable." "0: COMP1 input disabled,1: COMP1 input enabled"
newline
bitfld.long 0x0 1. "BKCMP1E,BKCMP1E: BRK COMP1 enable." "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x0 0. "BKINE,BKINE: BRK BKIN enable." "0: BKIN input disabled,1: BKIN input enabled"
tree.end
endif
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*"))
tree "TIM1"
base ad:0x40002000
group.long 0x0++0x13
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 11. "UIFREMAP,UIFREMAP: UIF status bit remapping" "0: No remapping,1: Remapping enabled"
bitfld.long 0x0 8.--9. "CKD,CKD[1:0]: Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,?,?"
newline
bitfld.long 0x0 7. "ARPE,ARPE: Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.long 0x0 5.--6. "CMS,CMS[1:0]: Center-aligned mode selection" "0: Edge-aligned mode,1: Center-aligned mode 1,?,?"
newline
bitfld.long 0x0 4. "DIR,DIR: Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.long 0x0 3. "OPM,OPM: One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event"
newline
bitfld.long 0x0 2. "URS,URS: Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.long 0x0 1. "UDIS,UDIS: Update disable" "0: UEV enabled,1: UEV disabled"
newline
bitfld.long 0x0 0. "CEN,CEN: Counter enable" "0: Counter disabled,1: Counter enabled"
line.long 0x4 "CR2,CR2 register"
bitfld.long 0x4 18. "OIS6,Output idle state 6 (OC6 output). Refer to OIS1 bit." "0,1"
bitfld.long 0x4 16. "OIS5,Output idle state 5 (OC5 output). Refer to OIS1 bit." "0,1"
newline
bitfld.long 0x4 14. "OIS4,Output idle state 4 (OC4 output)." "0,1"
bitfld.long 0x4 13. "OIS3N,Output idle state 3 (OC3N output). Refer to OIS1N bit." "0,1"
newline
bitfld.long 0x4 12. "OIS3,Output idle state 3 (OC3 output). Refer to OIS1 bit." "0,1"
bitfld.long 0x4 11. "OIS2N,Output idle state 2 (OC2N output). Refer to OIS1N bit." "0,1"
newline
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output). Refer to OIS1 bit." "0,1"
bitfld.long 0x4 9. "OIS1N,Output idle state 1 (OC1N output)." "0,1"
newline
bitfld.long 0x4 8. "OIS1,Output idle state 1 (OC1 output)." "0,1"
bitfld.long 0x4 7. "TI1S,TI1S: TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1"
newline
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection." "0,1"
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control." "0,1"
line.long 0x8 "SMCR,SMCR register"
bitfld.long 0x8 16. "SMS_3,SMS[3]: Slave mode selection - bit 3" "0,1"
bitfld.long 0x8 15. "ETP,ETP: External trigger polarity" "0: ETR is non-inverted,1: ETR is inverted"
newline
bitfld.long 0x8 14. "ECE,ECE: External clock enable" "0: External clock mode 2 disabled,1: Setting the ECE bit has the same effect as.."
bitfld.long 0x8 12.--13. "ETPS,ETPS[1:0]: External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,?,?"
newline
hexmask.long.byte 0x8 8.--11. 1. "ETF,ETF[3:0]: External trigger filter"
bitfld.long 0x8 4.--6. "TS,TS[2:0]: Trigger selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 3. "OCCS,OCCS: OCREF clear selection" "0: OCREF_CLR_INT is connected to the OCREF_CLR input,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x8 0.--2. "SMS_2_0,SMS: Slave mode selection" "0: Slave mode disabled,1: Encoder mode 1,?,?,?,?,?,?"
line.long 0xC "DIER,DIER register"
bitfld.long 0xC 7. "BIE,Break interrupt enable." "0,1"
bitfld.long 0xC 6. "TIE,TIE: Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
newline
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
bitfld.long 0xC 4. "CC4IE,CC4IE: Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
newline
bitfld.long 0xC 3. "CC3IE,CC3IE: Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
bitfld.long 0xC 2. "CC2IE,CC2IE: Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
newline
bitfld.long 0xC 1. "CC1IE,CC1IE: Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.long 0xC 0. "UIE,UIE: Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
line.long 0x10 "SR,SR register"
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag." "0,1"
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag." "0,1"
newline
bitfld.long 0x10 12. "CC4OF,CC4OF: Capture/Compare 4 overcapture flag" "0,1"
bitfld.long 0x10 11. "CC3OF,CC3OF: Capture/Compare 3 overcapture flag" "0,1"
newline
bitfld.long 0x10 10. "CC2OF,CC2OF: Capture/Compare 2 overcapture flag" "0,1"
bitfld.long 0x10 9. "CC1OF,CC1OF: Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag." "0,1"
bitfld.long 0x10 7. "BIF,Break interrupt flag." "0,1"
newline
bitfld.long 0x10 6. "TIF,TIF: Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
bitfld.long 0x10 5. "COMIF,COM interrupt flag." "0,1"
newline
bitfld.long 0x10 4. "CC4IF,CC4IF: Capture/Compare 4 interrupt flag" "0,1"
bitfld.long 0x10 3. "CC3IF,CC3IF: Capture/Compare 3 interrupt flag" "0,1"
newline
bitfld.long 0x10 2. "CC2IF,CC2IF: Capture/Compare 2 interrupt flag" "0,1"
bitfld.long 0x10 1. "CC1IF,CC1IF: Capture/Compare 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.long 0x10 0. "UIF,UIF: Update interrupt flag" "0: No update occurred,1: Update interrupt pending"
wgroup.long 0x14++0x3
line.long 0x0 "EGR,EGR register"
bitfld.long 0x0 8. "B2G,Break 2 generation." "0,1"
bitfld.long 0x0 7. "BG,Break generation." "0,1"
newline
bitfld.long 0x0 6. "TG,TG: Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register"
bitfld.long 0x0 5. "COMG,Capture/compare control update generation." "0,1"
newline
bitfld.long 0x0 4. "CC4G,CC4G: Capture/Compare 4 generation" "0,1"
bitfld.long 0x0 3. "CC3G,CC3G: Capture/Compare 3 generation" "0,1"
newline
bitfld.long 0x0 2. "CC2G,CC2G: Capture/Compare 2 generation" "0,1"
bitfld.long 0x0 1. "CC1G,CC1G: Capture/Compare 1 generation" "0: No action,1: "
newline
bitfld.long 0x0 0. "UG,UG: Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "CCMR1,CCMR1 register"
bitfld.long 0x0 24. "OC2M_3,OC2M[3]: Output Compare 2 mode (bit 3)" "0,1"
bitfld.long 0x0 16. "OC1M,OC1M[3]: Output Compare 1 mode (bit 3)" "0,1"
newline
bitfld.long 0x0 15. "OC2CE,OC2CE: Output Compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M_2_0,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC2PE,OC2PE: Output Compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,OC2FE: Output Compare 2 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC2S,CC2S[1:0]: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
bitfld.long 0x0 7. "OC1CE,OC1CE: Output Compare 1 Clear Enable" "0: OC1Ref is not affected by the ETRF Input,1: OC1Ref is cleared as soon as a High level is.."
newline
bitfld.long 0x0 4.--6. "OC1M_2_0,OC1M: Output Compare 1 mode" "0: Frozen,1: These bits can not be modified as long as LOCK..,2: In PWM mode,?,?,?,?,?"
bitfld.long 0x0 3. "OC1PE,OC1PE: Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled,1: These bits can not be modified as long as LOCK.."
newline
bitfld.long 0x0 2. "OC1FE,OC1FE: Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
group.long 0x18++0x7
line.long 0x0 "CCMR1_in"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,IC2F: Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,IC2PSC[1:0]: Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,CC2S: Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,IC1PSC: Input capture 1 prescaler" "0: no prescaler,1: capture is done once every 2 events,?,?"
bitfld.long 0x0 0.--1. "CC1S,CC1S: Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input,?,?"
line.long 0x4 "CCMR2,CCMR2 register"
bitfld.long 0x4 24. "OC4M_3,OC4M[3]: Output Compare 4 mode (bit 3)" "0,1"
bitfld.long 0x4 16. "OC3M_3,OC3M[3]: Output Compare 3 mode (bit 3)" "0,1"
newline
bitfld.long 0x4 15. "OC4CE,OC4CE: Output Compare 4 clear enable" "0,1"
bitfld.long 0x4 12.--14. "OC4M_2_0,OC4M[2:0]: Output Compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 11. "OC4PE,OC4PE: Output Compare 4 preload enable" "0,1"
bitfld.long 0x4 10. "OC4FE,OC4FE: Output Compare 4 fast enable" "0,1"
newline
bitfld.long 0x4 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
bitfld.long 0x4 7. "OC3CE,OC3CE: Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x4 4.--6. "OC3M_2_0,OC3M: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "OC3PE,OC3PE: Output compare 3 preload enable" "0,1"
newline
bitfld.long 0x4 2. "OC3FE,OC3FE: Output compare 3 fast enable" "0,1"
bitfld.long 0x4 0.--1. "CC3S,CC3S: Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
group.long 0x1C++0x2B
line.long 0x0 "CCMR2_in"
hexmask.long.byte 0x0 12.--15. 1. "IC4F,IC4F: Input capture 4 filter"
bitfld.long 0x0 10.--11. "IC4PSC,IC4PSC: Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC4S,CC4S: Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input,?,?"
hexmask.long.byte 0x0 4.--7. 1. "IC3F,IC3F: Input capture 3 filter"
newline
bitfld.long 0x0 2.--3. "IC3PSC,IC3PSC: Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x0 0.--1. "CC3S,CC3S: Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input,?,?"
line.long 0x4 "CCER,CCER register"
bitfld.long 0x4 21. "CC6P,Capture/compare 6 output polarity. Refer to CC1P description." "0,1"
bitfld.long 0x4 20. "CC6E,Capture/compare 6 output enable. Refer to CC1E description." "0,1"
newline
bitfld.long 0x4 17. "CC5P,Capture/compare 5 output polarity. Refer to CC1P description." "0,1"
bitfld.long 0x4 16. "CC5E,Capture/compare 5 output enable. Refer to CC1E description." "0,1"
newline
bitfld.long 0x4 15. "CC4NP,CC4NP: Capture/Compare 4 Complementary output Polarity." "0,1"
bitfld.long 0x4 14. "CC4NE,Capture/compare 4 complementary output enable. Refer to CC1NE description." "0,1"
newline
bitfld.long 0x4 13. "CC4P,CC4P: Capture/Compare 4 output polarity" "0,1"
bitfld.long 0x4 12. "CC4E,CC4E: Capture/Compare 4 output enable" "0,1"
newline
bitfld.long 0x4 11. "CC3NP,CC3NP: Capture/Compare 3 Complementary output Polarity." "0,1"
bitfld.long 0x4 10. "CC3NE,Capture/compare 3 complementary output enable. Refer to CC1NE description." "0,1"
newline
bitfld.long 0x4 9. "CC3P,CC3P: Capture/Compare 3 output polarity" "0,1"
bitfld.long 0x4 8. "CC3E,CC3E: Capture/Compare 3 output enable" "0,1"
newline
bitfld.long 0x4 7. "CC2NP,CC2NP: Capture/Compare 2 Complementary output Polarity." "0,1"
bitfld.long 0x4 6. "CC2NE,Capture/compare 2 complementary output enable. Refer to CC1NE description." "0,1"
newline
bitfld.long 0x4 5. "CC2P,CC2P: Capture/Compare 2 output polarity" "0,1"
bitfld.long 0x4 4. "CC2E,CC2E: Capture/Compare 2 output enable" "0,1"
newline
bitfld.long 0x4 3. "CC1NP,CC1NP: Capture/Compare 1 Complementary output Polarity." "0: OC1N active high.,1: OC1N active low."
bitfld.long 0x4 2. "CC1NE" "0,1"
newline
bitfld.long 0x4 1. "CC1P,CC1P: Capture/Compare 1 output polarity" "0: Non-inverted/rising edge,1: Inverted/falling edge"
bitfld.long 0x4 0. "CC1E,CC1E: Capture/Compare 1 output enable" "0: Capture disabled,1: Capture enabled"
line.long 0x8 "CNT,CNT register"
rbitfld.long 0x8 31. "UIFCPY,UIFCPY: UIF Copy" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,CNT[15:0]: Counter value"
line.long 0xC "PSC,PSC register"
hexmask.long.word 0xC 0.--15. 1. "PSC,PSC[15:0]: Prescaler value"
line.long 0x10 "ARR,ARR register"
hexmask.long.word 0x10 0.--15. 1. "ARR,ARR[15:0]: Prescaler value"
line.long 0x14 "RCR,RCR register"
hexmask.long.word 0x14 0.--15. 1. "REP,REP[7:0]: Repetition counter value"
line.long 0x18 "CCR1,CCR1 register"
hexmask.long.word 0x18 0.--15. 1. "CCR1,CCR1[15:0]: Capture/Compare 1 value"
line.long 0x1C "CCR2,CCR2 register"
hexmask.long.word 0x1C 0.--15. 1. "CCR2,CCR2[15:0]: Capture/Compare 2 value"
line.long 0x20 "CCR3,CCR3 register"
hexmask.long.word 0x20 0.--15. 1. "CCR3,CCR3[15:0]: Capture/Compare 3 value"
line.long 0x24 "CCR4,CCR4 register"
hexmask.long.word 0x24 0.--15. 1. "CCR4,CCR4[15:0]: Capture/Compare 4 value"
line.long 0x28 "BDTR,BDTR register"
bitfld.long 0x28 25. "BK2P,Break 2 polarity." "0,1"
bitfld.long 0x28 24. "BK2E,Break 2 enable." "0,1"
newline
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter."
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter."
newline
bitfld.long 0x28 15. "MOE,Main output enable." "0,1"
bitfld.long 0x28 14. "AOE,Automatic output enable." "0,1"
newline
bitfld.long 0x28 13. "BKP,Break polarity." "0,1"
bitfld.long 0x28 12. "BKE,Break enable." "0,1"
newline
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode." "0,1"
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode." "0,1"
newline
bitfld.long 0x28 8.--9. "LOCK,Lock configuration." "0,1,2,3"
hexmask.long.byte 0x28 0.--7. 1. "DTG,Deadtime generator setup."
group.long 0x54++0x3
line.long 0x0 "CCMR3,CCMR3 register"
bitfld.long 0x0 24. "OC6M_3,Output compare 6 mode - bit 3." "0,1"
bitfld.long 0x0 16. "OC5M_3,Output compare 5 mode - bit 3." "0,1"
newline
bitfld.long 0x0 15. "OC6CE,Output compare 6 clear enable." "0,1"
bitfld.long 0x0 12.--14. "OC6M_2_0,Output compare 6 mode." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC6PE,Output compare 6 preload enable." "0,1"
bitfld.long 0x0 10. "OC6FE,Output compare 6 fast enable." "0,1"
newline
bitfld.long 0x0 7. "OC5CE,Output compare 5 clear enable." "0,1"
bitfld.long 0x0 4.--6. "OC5M_2_0,Output compare 5 mode." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3. "OC5PE,Output compare 5 preload enable." "0,1"
bitfld.long 0x0 2. "OC5FE,Output compare 5 fast enable" "0,1"
group.long 0x54++0x13
line.long 0x0 "CCMR3_in"
hexmask.long.byte 0x0 12.--15. 1. "IC6F,IC2F: Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC6PSC,IC6PSC[1:0]: Input capture 2 prescaler" "0,1,2,3"
newline
hexmask.long.byte 0x0 4.--7. 1. "IC5F,Bits 7:4 IC1F[3:0]: Input capture 1 filter"
bitfld.long 0x0 2.--3. "IC5PSC,IC5PSC: Input capture 1 prescaler" "0,1,2,3"
line.long 0x4 "CCR5,CCR5 register"
bitfld.long 0x4 31. "GC5C3,Group channel 5 and channel 3 distortion on channel 3 output:" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
bitfld.long 0x4 30. "GC5C2,Group channel 5 and channel 2 distortion on channel 2 output:" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
newline
bitfld.long 0x4 29. "GC5C1,Group channel 5 and channel 1 distortion on channel 1 output:" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
hexmask.long.word 0x4 0.--15. 1. "CCR5,Capture/compare 5 value"
line.long 0x8 "CCR6,CCR6 register"
hexmask.long.word 0x8 0.--15. 1. "CCR6,Capture/compare 6 value"
line.long 0xC "AF1,AF1 register"
bitfld.long 0xC 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
bitfld.long 0xC 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
newline
bitfld.long 0xC 9. "BKINP,BRK BKIN input polarity" "0,1"
bitfld.long 0xC 2. "BKCMP2E,BRK COMP2 enable" "0,1"
newline
bitfld.long 0xC 1. "BKCMP1E,BRK COMP1 enable" "0,1"
bitfld.long 0xC 0. "BKINE,BRK BKIN input enable" "0,1"
line.long 0x10 "AF2,AF2 register"
bitfld.long 0x10 11. "BK2CMP2P,BRK2 COMP2 input polarity." "0,1"
bitfld.long 0x10 10. "BK2CMP1P,BRK2 COMP1 input polarity." "0,1"
newline
bitfld.long 0x10 9. "BK2INP,BRK2 BKIN2 input polarity" "0,1"
bitfld.long 0x10 2. "BK2CMP2E,BRK2 COMP2 enable." "0,1"
newline
bitfld.long 0x10 1. "BK2CMP1E,BRK2 COMP1 enable." "0,1"
bitfld.long 0x10 0. "BK2INE,BRK2 BKIN input enable." "0,1"
tree.end
endif
tree.end
sif (cpuis("STM32WB09*"))
tree "TRNG (True Random Number Generator)"
base ad:0x48600000
group.long 0x0++0x3
line.long 0x0 "TRNG_CR,TRNG_CR register"
hexmask.long.word 0x0 8.--23. 1. "CLKDIV,Sampling Clock Enable Divider."
newline
bitfld.long 0x0 7. "RST_HEALTH_FLAGS,Reset Health error flags when writing a '1' without resetting the whole TRNG." "0: no reset,1: reset health flag"
newline
bitfld.long 0x0 6. "CLR_REVCLK_FLAG,Reset reveal clock error flags when writing a '1' without resetting the whole TRNG." "0: no reset,1: reset revclk flag"
newline
bitfld.long 0x0 0. "DISABLE,Disable" "0: The RNG core is enabled,1: The RNG core is disabled"
rgroup.long 0x4++0x7
line.long 0x0 "TRNG_SR,TRNG_SR register"
bitfld.long 0x0 25. "OSCS_ADAPT_ERROR,Logical OR of adaptive health test errors of individual oscillators composing the noise source." "0,1"
newline
bitfld.long 0x0 24. "OSCS_REPET_ERROR,Logical OR of repetition health test errors of individual oscillators composing the noise source." "0,1"
newline
bitfld.long 0x0 23. "OSCS_HEALTH_DONE,First run of source health tests of individual oscillators composing the noise source are completed.Reserved" "0,1"
newline
bitfld.long 0x0 22. "ADAPT_ERROR,Noise source Adaptive 1024 health test error" "0,1"
newline
bitfld.long 0x0 21. "REPET_ERROR,Noise source Repetition health test error" "0,1"
newline
bitfld.long 0x0 20. "SRC_HEALTH_DONE,First run of noise source health test is completed" "0,1"
newline
bitfld.long 0x0 5. "FIFO_FULL,Indicates whether random data FIFO is full." "0: FIFO is not full.,1: The internal data FIFO is full and four 32-bit.."
newline
bitfld.long 0x0 4. "VAL_READY,TRNG Value ready" "0: No value is ready in FIFO.,1: A 32-bit value is available in the internal FIFO"
newline
bitfld.long 0x0 3. "ENTROPY_ERR,The error refers to a fault in the bit sequence detected by the Entropy Monitor. Failed test is given by REPET_ERROR and ADAPT_ERROR OSCS_REPET_ERROR and OSCS_ADAPT_ERROR status flags." "0: No fault detected,1: Embedded heath monitor detects an error in bit.."
newline
bitfld.long 0x0 2. "REVEAL_CLK_ERR,The internal clock for the RNG core is not revealed." "0: Internal clock for RNG clock is present.,1: Internal RNG clock is not present."
newline
bitfld.long 0x0 1. "ALL_OSCS_DOWN,All oscillators of the random source noise have been powered down. This can cause the rising of OEC3 flag." "0: At least one oscillator is ON,1: All oscillators are down"
newline
bitfld.long 0x0 0. "TRNG_DISABLED,TRNG is disabled." "0: Normal operation.,1: RNG is disabled."
line.long 0x4 "TRNG_VAL,TRNG_VAL register"
hexmask.long 0x4 0.--31. 1. "RND_VAL,RND_VAL is a 32-bit Random Value. This is the output of the internal four-word FIFO."
group.long 0x30++0x7
line.long 0x0 "TRNG_OSCS_CR,TRNG_OSCS_CR register"
bitfld.long 0x0 31. "SYNC_OSCS,When set selection of resynchronized output of oscillators." "0,1"
newline
bitfld.long 0x0 7.--9. "PWRD3,Power down of individual oscillators in triple-oscillator block number 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4.--6. "PWRD2,Power down of individual oscillators in triple-oscillator block number 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1.--3. "PWRD1,Power down of individual oscillators in triple-oscillator block number 1" "0,1,2,3,4,5,6,7"
line.long 0x4 "TRNG_POSTP_CR,TRNG_POSTP_CR register"
hexmask.long.word 0x4 16.--31. 1. "NB_RND_REINIT,Number of 128-bit random words generated before AES automatically resets. This number is in the range of 1 to 65535 words. Value 0x0000 means that AES is never reinitialized."
newline
hexmask.long.byte 0x4 8.--11. 1. "NB_LOOP_AES,NB_LOOP_AES is the number of 128-bit words got from the noise source that have to be processed by AES for generating a single 128-bit random word."
newline
bitfld.long 0x4 0. "AES_RESET,Reset AES post processing." "0: No effect,1: Reset AES core"
rgroup.long 0x38++0x3
line.long 0x0 "TRNG_POSTP_SR,TRNG_POSTP_SR register"
bitfld.long 0x0 6. "AES_DOUT_ERROR,Health test error on AES-CMAC output generation" "0,1"
newline
bitfld.long 0x0 5. "AES_K12_ERROR,Health test error on AES-CMAC sub-keys generation" "0,1"
newline
bitfld.long 0x0 4. "AES_HEALTH_DONE,AES-CMAC health test is completed" "0,1"
newline
bitfld.long 0x0 3. "AES_BUSY,AES core is busy generating a random value." "0: AES core is idle,1: AES core is busy."
newline
bitfld.long 0x0 2. "AES_KEY_LD,AES random key has been generated and loaded in AES key register." "0: AES core is waiting for 128 random bits from the..,1: AES key register has been loaded with a random.."
newline
bitfld.long 0x0 1. "AES_INIT,AES Post processing has been fully initialized (key and state) and is ready for generating 128-bit random words." "0: AES core is not initialized (no key or state..,1: AES core is fully initialized."
group.long 0x40++0xF
line.long 0x0 "TRNG_DEFKEY0,TRNG_DEFKEY0 register"
hexmask.long 0x0 0.--31. 1. "RNG_DEFKEY0,Bits 31 to 0 of AES 128-bit Default Key."
line.long 0x4 "TRNG_DEFKEY1,TRNG_DEFKEY1 register"
hexmask.long 0x4 0.--31. 1. "RNG_DEFKEY1,Bits 63 to 31 of AES 128-bit Default Key."
line.long 0x8 "TRNG_DEFKEY2,TRNG_DEFKEY2 register"
hexmask.long 0x8 0.--31. 1. "RNG_DEFKEY2,Bits 95 to 64 of AES 128-bit Default Key."
line.long 0xC "TRNG_DEFKEY3,TRNG_DEFKEY3 register"
hexmask.long 0xC 0.--31. 1. "RNG_DEFKEY3,Bits 127 to 96 of AES 128-bit Default Key."
group.long 0x60++0x3
line.long 0x0 "TRNG_HEALTH_CR,TRNG_HEALTH_CR register"
bitfld.long 0x0 28.--29. "ITER_ADAP,Number of iterations minus 1 of Adaptive test during initialization phase. Default value is set to 0 i.e. 1 iteration." "0,1,2,3"
newline
hexmask.long.word 0x0 16.--25. 1. "ADAP_CUTOFF,Cutoff value of Adaptive Test."
newline
hexmask.long.byte 0x0 0.--7. 1. "REPET_CUTOFF,Cutoff value of Repetition Test."
group.long 0x68++0xB
line.long 0x0 "TRNG_HEALTH_OSC1_CR,TRNG_HEALTH_OSC1_CR register"
hexmask.long.word 0x0 16.--25. 1. "ADAP_CUTOFF_OSC1,Cutoff value of Adaptive Test."
newline
hexmask.long.byte 0x0 0.--7. 1. "REPET_CUTOFF_OSC1,Cutoff value of Repetition Test."
line.long 0x4 "TRNG_HEALTH_OSC2_CR,TRNG_HEALTH_OSC2_CR register"
hexmask.long.word 0x4 16.--25. 1. "ADAP_CUTOFF_OSC2,Cutoff value of Adaptive Test."
newline
hexmask.long.byte 0x4 0.--7. 1. "REPET_CUTOFF_OSC2,Cutoff value of Repetition Test."
line.long 0x8 "TRNG_HEALTH_OSC3_CR,TRNG_HEALTH_OSC3_CR register"
hexmask.long.word 0x8 16.--25. 1. "ADAP_CUTOFF_OSC3,Cutoff value of Adaptive Test."
newline
hexmask.long.byte 0x8 0.--7. 1. "REPET_CUTOFF_OSC3,Cutoff value of Repetition Test."
rgroup.long 0x74++0xB
line.long 0x0 "TRNG_HEALTH_OSC1_SR,TRNG_HEALTH_OSC1_SR register"
bitfld.long 0x0 5. "TO3_ADAPT_ERROR,Adaptive error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x0 4. "TO3_REPET_ERROR,Repetition error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x0 3. "TO2_ADAPT_ERROR,Adaptive error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x0 2. "TO2_REPET_ERROR,Repetition error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x0 1. "TO1_ADAPT_ERROR,Adaptive error flag of first oscillator of first triple-oscillator cell." "0,1"
newline
bitfld.long 0x0 0. "TO1_REPET_ERROR,Repetition error flag of first oscillator of first triple-oscillator cell." "0,1"
line.long 0x4 "TRNG_HEALTH_OSC2_SR,TRNG_HEALTH_OSC2_SR register"
bitfld.long 0x4 5. "TO3_ADAPT_ERROR,Adaptive error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x4 4. "TO3_REPET_ERROR,Repetition error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x4 3. "TO2_ADAPT_ERROR,Adaptive error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x4 2. "TO2_REPET_ERROR,Repetition error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x4 1. "TO1_ADAPT_ERROR,Adaptive error flag of first oscillator of first triple-oscillator cell." "0,1"
newline
bitfld.long 0x4 0. "TO1_REPET_ERROR,Repetition error flag of first oscillator of first triple-oscillator cell." "0,1"
line.long 0x8 "TRNG_HEALTH_OSC3_SR,TRNG_HEALTH_OSC3_SR register"
bitfld.long 0x8 5. "TO3_ADAPT_ERROR,Adaptive error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x8 4. "TO3_REPET_ERROR,Repetition error flag of first oscillator of third triple-oscillator cell." "0,1"
newline
bitfld.long 0x8 3. "TO2_ADAPT_ERROR,Adaptive error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x8 2. "TO2_REPET_ERROR,Repetition error flag of first oscillator of second triple-oscillator cell." "0,1"
newline
bitfld.long 0x8 1. "TO1_ADAPT_ERROR,Adaptive error flag of first oscillator of first triple-oscillator cell." "0,1"
newline
bitfld.long 0x8 0. "TO1_REPET_ERROR,Repetition error flag of third oscillator of first triple-oscillator cell." "0,1"
group.long 0x80++0x3
line.long 0x0 "TRNG_IRQ_CR,TRNG_IRQ_CR register"
bitfld.long 0x0 8. "EN_ERROR_IRQ,Enable the interrupt when an error is reported by the health tests." "0,1"
newline
bitfld.long 0x0 0. "EN_FF_FULL_IRQ,Enable the interrupt when the output fifo is full of new random." "0,1"
rgroup.long 0x84++0x3
line.long 0x0 "TRNG_IRQ_SR,TRNG_IRQ_SR register"
bitfld.long 0x0 8. "ERROR_IRQ,Set to 1 when an error is reported by the health tests. Flag is cleared by writing a 1." "0,1"
newline
bitfld.long 0x0 0. "FF_FULL_IRQ,Set to 1 when the output fifo is full of new random. Flag is cleared by writing a 1." "0,1"
tree.end
endif
tree "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
base ad:0x41004000
sif (cpuis("STM32WB05*"))
group.long 0x0++0x17
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 31. "RXFFIE,RXFFIE :RXFIFO Full interrupt enable" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFEIE :TXFIFO empty interrupt enable" "0,1"
newline
bitfld.long 0x0 29. "FIFOEN,FIFOEN :FIFO mode enable" "0,1"
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
bitfld.long 0x0 27. "EOBIE,EOBIE: End of Block interrupt enable" "0: Interrupt is inhibited,1: A USART interrupt is generated when the EOBF.."
bitfld.long 0x0 26. "RTOIE,RTOIE: Receiver timeout interrupt enable" "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT[4:0]: Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT[4:0]: Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,OVER8: Oversampling mode" "0,1"
bitfld.long 0x0 14. "CMIE,CMIE: Character match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MME,MME: Mute mode enable" "0,1"
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,WAKE: Receiver wakeup method" "0,1"
bitfld.long 0x0 10. "PCE,PCE: Parity control enable" "0,1"
newline
bitfld.long 0x0 9. "PS,PS: Parity selection" "0,1"
bitfld.long 0x0 8. "PEIE,PEIE: PE interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "TXEIE_TXFNFIE,TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,TCIE: Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RXNEIE_RXFNEIE,RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLEIE: IDLE interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TE,TE: Transmitter enable" "0,1"
bitfld.long 0x0 2. "RE,RE: Receiver enable" "0,1"
newline
bitfld.long 0x0 0. "UE,UE: USART enable" "0,1"
line.long 0x4 "CR2,CR2 register"
hexmask.long.byte 0x4 24.--31. 1. "ADD,ADD[7:0]: Address of the USART node"
bitfld.long 0x4 23. "RTOEN,RTOEN: Receiver timeout enable" "0,1"
newline
bitfld.long 0x4 21.--22. "ABRMOD,ABRMOD[1:0]: Auto baud rate mode" "?,1: Frame = Start10xxxxxx,?,?"
bitfld.long 0x4 20. "ABREN,ABREN: Auto baud rate enable" "0,1"
newline
bitfld.long 0x4 19. "MSBFIRST,MSBFIRST: Most significant bit first" "0,1"
bitfld.long 0x4 18. "DATAINV,DATAINV: Binary data inversion" "0: H,1: L"
newline
bitfld.long 0x4 17. "TXINV,TXINV: TX pin active level inversion" "0,1"
bitfld.long 0x4 16. "RXINV,RXINV: RX pin active level inversion" "0,1"
newline
bitfld.long 0x4 15. "SWAP,SWAP: Swap TX/RX pins" "0,1"
bitfld.long 0x4 14. "LINEN,LINEN: LIN mode enable" "0,1"
newline
bitfld.long 0x4 12.--13. "STOP,STOP[1:0]: STOP bits" "0,1,2,3"
bitfld.long 0x4 11. "CLKEN,CLKEN: Clock enable" "0,1"
newline
bitfld.long 0x4 10. "CPOL,CPOL: Clock polarity" "0,1"
bitfld.long 0x4 9. "CPHA,CPHA: Clock phase" "0,1"
newline
bitfld.long 0x4 8. "LBCL,LBCL: Last bit clock pulse" "0,1"
bitfld.long 0x4 6. "LBDIE,LBDIE: LIN break detection interrupt enable" "0,1"
newline
bitfld.long 0x4 5. "LBDL,LBDL: LIN break detection length" "0,1"
bitfld.long 0x4 4. "ADDM7,ADDM7:7-bit Address Detection/4-bit Address Detection" "0,1"
newline
bitfld.long 0x4 3. "DIS_NSS,DIS_NSS" "0,1"
bitfld.long 0x4 0. "SLVEN,SLVEN: Synchronous Slave mode enable" "0,1"
line.long 0x8 "CR3,CR3 register"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFTCFG: TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 28. "RXFTIE,RXFTIE: RXFIFO threshold interrupt enable" "0,1"
newline
bitfld.long 0x8 25.--27. "RXFTCFG,RXFTCFG: Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 24. "TCBGTIE,TCBGTIE: Transmission Complete before guard time interrupt enable" "0,1"
newline
bitfld.long 0x8 23. "TXFTIE,TXFTIE: TXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x8 17.--19. "SCARCNT,SCARCNT[2:0]: Smartcard auto-retry count" "?,?,?,?,?,?,?,7: number of automatic retransmission attempts"
newline
bitfld.long 0x8 15. "DEP,DEP: Driver enable polarity selection" "0,1"
bitfld.long 0x8 14. "DEM,DEM: Driver enable mode" "0,1"
newline
bitfld.long 0x8 13. "DDRE,DDRE: DMA Disable on Reception Error" "0,1"
bitfld.long 0x8 12. "OVRDIS,OVRDIS: Overrun Disable" "0,1"
newline
bitfld.long 0x8 11. "ONEBIT,ONEBIT: One sample bit method enable" "0,1"
bitfld.long 0x8 10. "CTSIE,CTSIE: CTS interrupt enable" "0,1"
newline
bitfld.long 0x8 9. "CTSE,CTSE: CTS enable" "0,1"
bitfld.long 0x8 8. "RTSE,RTSE: RTS enable" "0,1"
newline
bitfld.long 0x8 7. "DMAT,DMAT: DMA enable transmitter" "0,1"
bitfld.long 0x8 6. "DMAR,DMAR: DMA enable receiver" "0,1"
newline
bitfld.long 0x8 5. "SCEN,SCEN: Smartcard mode enable" "0,1"
bitfld.long 0x8 4. "NACK,NACK: Smartcard NACK enable" "0,1"
newline
bitfld.long 0x8 3. "HDSEL,HDSEL: Half-duplex selection" "0,1"
bitfld.long 0x8 2. "IRLP,IRLP: IrDA low-power" "0,1"
newline
bitfld.long 0x8 1. "IREN,IREN: IrDA mode enable" "0,1"
bitfld.long 0x8 0. "EIE,EIE: Error interrupt enable" "0,1"
line.long 0xC "BRR,BRR register"
hexmask.long.word 0xC 0.--15. 1. "BRR,BRR[15:4]"
line.long 0x10 "GTPR,GTPR register"
hexmask.long.byte 0x10 8.--15. 1. "GT,GT[7:0]: Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,PSC[7:0]: Prescaler value"
line.long 0x14 "RTOR,RTOR register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,BLEN[7:0]: Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,RTO[23:0]: Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "RQR,RQR register"
bitfld.long 0x0 4. "TXFRQ,TXFRQ: Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,RXFRQ: Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,MMRQ: Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,SBKRQ: Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,ABRRQ: Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "ISR,ISR register"
bitfld.long 0x0 27. "TXFT,TXFT: TXFIFO threshold flag" "0,1"
bitfld.long 0x0 26. "RXFT,RXFT: RXFIFO threshold flag" "0,1"
newline
bitfld.long 0x0 25. "TCBGT,TCBGT: Transmission complete before guard time flagl" "0,1"
bitfld.long 0x0 24. "RXFF,RXFF: RXFIFO Full" "0,1"
newline
bitfld.long 0x0 23. "TXFE,TXFE: TXFIFO Empty" "0,1"
bitfld.long 0x0 22. "REACK,REACK: Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,TEACK: Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 19. "RWU,RWU: Receiver wakeup from Mute mode" "0,1"
newline
bitfld.long 0x0 18. "SBKF,SBKF: Send break flag" "0,1"
bitfld.long 0x0 17. "CMF,CMF: Character match flag" "0,1"
newline
bitfld.long 0x0 16. "BUSY,BUSY: Busy flag" "0,1"
bitfld.long 0x0 15. "ABRF,ABRF: Auto baud rate flag" "0,1"
newline
bitfld.long 0x0 14. "ABRE,ABRE: Auto baud rate error" "0,1"
bitfld.long 0x0 13. "UDR,UDR: SPI slave underrun error flag" "0,1"
newline
bitfld.long 0x0 12. "EOBF,EOBF: End of block flag" "0,1"
bitfld.long 0x0 11. "RTOF,RTOF: Receiver timeout" "0,1"
newline
bitfld.long 0x0 10. "CTS,CTS: CTS flag" "0,1"
bitfld.long 0x0 9. "CTSIF,CTSIF: CTS interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "LBDF,LBDF: LIN break detection flag" "0,1"
bitfld.long 0x0 7. "TXE_TXFNF,TXE/TXFNF: Transmit data register empty/TXFIFO not full" "0,1"
newline
bitfld.long 0x0 6. "TC,TC: Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE_RXFNE,RXNE/RXFNE:Read data register not empty/RXFIFO not empty" "0,1"
newline
bitfld.long 0x0 4. "IDLE,IDLE: Idle line detected" "0,1"
bitfld.long 0x0 3. "ORE,ORE: Overrun error" "0,1"
newline
bitfld.long 0x0 2. "NF,NF: START bit Noise detection flag" "0,1"
bitfld.long 0x0 1. "FE,FE: Framing error" "0,1"
newline
bitfld.long 0x0 0. "PE,PE: Parity error" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "ICR,ICR register"
bitfld.long 0x0 17. "CMCF,CMCF: Character match clear flag" "0,1"
bitfld.long 0x0 13. "UDRCF,UDRCF:SPI slave underrun clear flag" "0,1"
newline
bitfld.long 0x0 12. "EOBCF,EOBCF: End of block clear flag" "0,1"
bitfld.long 0x0 11. "RTOCF,RTOCF: Receiver timeout clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTSCF: CTS clear flag" "0,1"
bitfld.long 0x0 8. "LBDCF,LBDCF: LIN break detection clear flag" "0,1"
newline
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF: Transmission complete before Guard time clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,TCCF: Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 5. "TXFECF,TXFECF: TXFIFO empty clear flag" "0,1"
bitfld.long 0x0 4. "IDLECF,IDLECF: Idle line detected clear flag" "0,1"
newline
bitfld.long 0x0 3. "ORECF,ORECF: Overrun error clear flag" "0,1"
bitfld.long 0x0 2. "NECF,NECF: Noise detected clear flag" "0,1"
newline
bitfld.long 0x0 1. "FECF,FECF: Framing error clear flag" "0,1"
bitfld.long 0x0 0. "PECF,PECF: Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDR,RDR register"
hexmask.long.word 0x0 0.--8. 1. "RDR,RDR[8:0]: Receive data value"
group.long 0x28++0x7
line.long 0x0 "TDR,TDR register"
hexmask.long.word 0x0 0.--8. 1. "TDR,TDR[8:0]: Transmit data value"
line.long 0x4 "PRESC,PRESC register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER[3:0]: Clock prescaler"
endif
sif (cpuis("STM32WB06*"))
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
endif
sif (cpuis("STM32WB06*"))
group.long 0x0++0x17
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
line.long 0x4 "USART_CR2,USART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
newline
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
newline
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
newline
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
newline
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
newline
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
newline
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
newline
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
newline
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
line.long 0x8 "USART_CR3,USART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page2587,?,?,7: number of automatic retransmission attempts"
newline
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
newline
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
newline
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
newline
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
newline
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
line.long 0xC "USART_BRR,USART baud rate register"
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
line.long 0x14 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
newline
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
newline
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
endif
sif (cpuis("STM32WB07*"))
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF=1 in the.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
endif
sif (cpuis("STM32WB07*"))
group.long 0x0++0x3
line.long 0x0 "USART_CR1_ALTERNATE1,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
endif
sif (cpuis("STM32WB09*"))
group.long 0x0++0x3
line.long 0x0 "CR1,CR1 register"
bitfld.long 0x0 31. "RXFFIE,RXFFIE :RXFIFO Full interrupt enable" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFEIE :TXFIFO empty interrupt enable" "0,1"
newline
bitfld.long 0x0 29. "FIFOEN,FIFOEN :FIFO mode enable" "0,1"
bitfld.long 0x0 28. "M_1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
bitfld.long 0x0 27. "EOBIE,EOBIE: End of Block interrupt enable" "0: Interrupt is inhibited,1: A USART interrupt is generated when the EOBF.."
bitfld.long 0x0 26. "RTOIE,RTOIE: Receiver timeout interrupt enable" "0,1"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT[4:0]: Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT[4:0]: Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,OVER8: Oversampling mode" "0,1"
bitfld.long 0x0 14. "CMIE,CMIE: Character match interrupt enable" "0,1"
newline
bitfld.long 0x0 13. "MME,MME: Mute mode enable" "0,1"
bitfld.long 0x0 12. "M_0,M0: Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,WAKE: Receiver wakeup method" "0,1"
bitfld.long 0x0 10. "PCE,PCE: Parity control enable" "0,1"
newline
bitfld.long 0x0 9. "PS,PS: Parity selection" "0,1"
bitfld.long 0x0 8. "PEIE,PEIE: PE interrupt enable" "0,1"
newline
bitfld.long 0x0 7. "TXEIE_TXFNFIE,TXEIE/TXFNFIE: Transmit data regsiter empty/TXFIFO not full interrupt enable" "0,1"
bitfld.long 0x0 6. "TCIE,TCIE: Transmission complete interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "RXNEIE_RXFNEIE,RXNEIE/RXFNEIE: Receive data register not empty/RXFIFO not empty interrupt enable" "0,1"
bitfld.long 0x0 4. "IDLEIE,IDLEIE: IDLE interrupt enable" "0,1"
newline
bitfld.long 0x0 3. "TE,TE: Transmitter enable" "0,1"
bitfld.long 0x0 2. "RE,RE: Receiver enable" "0,1"
newline
bitfld.long 0x0 0. "UE,UE: USART enable" "0,1"
endif
sif (cpuis("STM32WB07*"))
group.long 0x4++0x3
line.long 0x0 "USART_CR2,USART control register 2"
hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
newline
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
newline
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
newline
bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted.."
bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted.."
newline
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
newline
bitfld.long 0x0 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x0 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
newline
bitfld.long 0x0 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x0 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
newline
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
newline
bitfld.long 0x0 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
endif
sif (cpuis("STM32WB09*"))
group.long 0x4++0x3
line.long 0x0 "CR2,CR2 register"
hexmask.long.byte 0x0 24.--31. 1. "ADD,ADD[7:0]: Address of the USART node"
bitfld.long 0x0 23. "RTOEN,RTOEN: Receiver timeout enable" "0,1"
newline
bitfld.long 0x0 21.--22. "ABRMOD,ABRMOD[1:0]: Auto baud rate mode" "?,1: Frame = Start10xxxxxx,?,?"
bitfld.long 0x0 20. "ABREN,ABREN: Auto baud rate enable" "0,1"
newline
bitfld.long 0x0 19. "MSBFIRST,MSBFIRST: Most significant bit first" "0,1"
bitfld.long 0x0 18. "DATAINV,DATAINV: Binary data inversion" "0: H,1: L"
newline
bitfld.long 0x0 17. "TXINV,TXINV: TX pin active level inversion" "0,1"
bitfld.long 0x0 16. "RXINV,RXINV: RX pin active level inversion" "0,1"
newline
bitfld.long 0x0 15. "SWAP,SWAP: Swap TX/RX pins" "0,1"
bitfld.long 0x0 14. "LINEN,LINEN: LIN mode enable" "0,1"
newline
bitfld.long 0x0 12.--13. "STOP,STOP[1:0]: STOP bits" "0,1,2,3"
bitfld.long 0x0 11. "CLKEN,CLKEN: Clock enable" "0,1"
newline
bitfld.long 0x0 10. "CPOL,CPOL: Clock polarity" "0,1"
bitfld.long 0x0 9. "CPHA,CPHA: Clock phase" "0,1"
newline
bitfld.long 0x0 8. "LBCL,LBCL: Last bit clock pulse" "0,1"
bitfld.long 0x0 6. "LBDIE,LBDIE: LIN break detection interrupt enable" "0,1"
newline
bitfld.long 0x0 5. "LBDL,LBDL: LIN break detection length" "0,1"
bitfld.long 0x0 4. "ADDM7,ADDM7:7-bit Address Detection/4-bit Address Detection" "0,1"
newline
bitfld.long 0x0 3. "DIS_NSS,DIS_NSS" "0,1"
bitfld.long 0x0 0. "SLVEN,SLVEN: Synchronous Slave mode enable" "0,1"
endif
sif (cpuis("STM32WB07*"))
group.long 0x8++0x3
line.long 0x0 "USART_CR3,USART control register 3"
bitfld.long 0x0 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x0 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
newline
bitfld.long 0x0 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x0 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x0 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x0 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x0 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved.,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
bitfld.long 0x0 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page2587,?,?,7: number of automatic retransmission attempts"
newline
bitfld.long 0x0 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
bitfld.long 0x0 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
newline
bitfld.long 0x0 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
bitfld.long 0x0 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
newline
bitfld.long 0x0 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
bitfld.long 0x0 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x0 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x0 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x0 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x0 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x0 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
bitfld.long 0x0 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
newline
bitfld.long 0x0 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
bitfld.long 0x0 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
newline
bitfld.long 0x0 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
bitfld.long 0x0 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
endif
sif (cpuis("STM32WB09*"))
group.long 0x8++0x3
line.long 0x0 "CR3,CR3 register"
bitfld.long 0x0 29.--31. "TXFTCFG,TXFTCFG: TXFIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 28. "RXFTIE,RXFTIE: RXFIFO threshold interrupt enable" "0,1"
newline
bitfld.long 0x0 25.--27. "RXFTCFG,RXFTCFG: Receive FIFO threshold configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24. "TCBGTIE,TCBGTIE: Transmission Complete before guard time interrupt enable" "0,1"
newline
bitfld.long 0x0 23. "TXFTIE,TXFTIE: TXFIFO threshold interrupt enable" "0,1"
bitfld.long 0x0 17.--19. "SCARCNT,SCARCNT[2:0]: Smartcard auto-retry count" "?,?,?,?,?,?,?,7: number of automatic retransmission attempts"
newline
bitfld.long 0x0 15. "DEP,DEP: Driver enable polarity selection" "0,1"
bitfld.long 0x0 14. "DEM,DEM: Driver enable mode" "0,1"
newline
bitfld.long 0x0 13. "DDRE,DDRE: DMA Disable on Reception Error" "0,1"
bitfld.long 0x0 12. "OVRDIS,OVRDIS: Overrun Disable" "0,1"
newline
bitfld.long 0x0 11. "ONEBIT,ONEBIT: One sample bit method enable" "0,1"
bitfld.long 0x0 10. "CTSIE,CTSIE: CTS interrupt enable" "0,1"
newline
bitfld.long 0x0 9. "CTSE,CTSE: CTS enable" "0,1"
bitfld.long 0x0 8. "RTSE,RTSE: RTS enable" "0,1"
newline
bitfld.long 0x0 7. "DMAT,DMAT: DMA enable transmitter" "0,1"
bitfld.long 0x0 6. "DMAR,DMAR: DMA enable receiver" "0,1"
newline
bitfld.long 0x0 5. "SCEN,SCEN: Smartcard mode enable" "0,1"
bitfld.long 0x0 4. "NACK,NACK: Smartcard NACK enable" "0,1"
newline
bitfld.long 0x0 3. "HDSEL,HDSEL: Half-duplex selection" "0,1"
bitfld.long 0x0 2. "IRLP,IRLP: IrDA low-power" "0,1"
newline
bitfld.long 0x0 1. "IREN,IREN: IrDA mode enable" "0,1"
bitfld.long 0x0 0. "EIE,EIE: Error interrupt enable" "0,1"
endif
sif (cpuis("STM32WB07*"))
group.long 0xC++0x3
line.long 0x0 "USART_BRR,USART baud rate register"
hexmask.long.word 0x0 0.--15. 1. "BRR,USART baud rate"
endif
sif (cpuis("STM32WB09*"))
group.long 0xC++0x3
line.long 0x0 "BRR,BRR register"
hexmask.long.word 0x0 0.--15. 1. "BRR,BRR[15:4]"
endif
sif (cpuis("STM32WB07*"))
group.long 0x10++0x3
line.long 0x0 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x0 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescaler value"
endif
sif (cpuis("STM32WB09*"))
group.long 0x10++0x3
line.long 0x0 "GTPR,GTPR register"
hexmask.long.byte 0x0 8.--15. 1. "GT,GT[7:0]: Guard time value"
hexmask.long.byte 0x0 0.--7. 1. "PSC,PSC[7:0]: Prescaler value"
endif
sif (cpuis("STM32WB07*"))
group.long 0x14++0x3
line.long 0x0 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x0 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x0 0.--23. 1. "RTO,Receiver timeout value"
endif
sif (cpuis("STM32WB09*"))
group.long 0x14++0x3
line.long 0x0 "RTOR,RTOR register"
hexmask.long.byte 0x0 24.--31. 1. "BLEN,BLEN[7:0]: Block Length"
hexmask.long.tbyte 0x0 0.--23. 1. "RTO,RTO[23:0]: Receiver timeout value"
endif
sif (cpuis("STM32WB07*"))
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
endif
sif (cpuis("STM32WB09*"))
wgroup.long 0x18++0x3
line.long 0x0 "RQR,RQR register"
bitfld.long 0x0 4. "TXFRQ,TXFRQ: Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,RXFRQ: Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,MMRQ: Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,SBKRQ: Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,ABRRQ: Auto baud rate request" "0,1"
endif
sif (cpuis("STM32WB06*"))
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
newline
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
newline
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
newline
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
newline
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
endif
sif (cpuis("STM32WB07*"))
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
newline
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
newline
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
endif
sif (cpuis("STM32WB07*"))
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE1,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
newline
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
newline
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
newline
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
newline
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
endif
sif (cpuis("STM32WB09*"))
rgroup.long 0x1C++0x3
line.long 0x0 "ISR,ISR register"
bitfld.long 0x0 27. "TXFT,TXFT: TXFIFO threshold flag" "0,1"
bitfld.long 0x0 26. "RXFT,RXFT: RXFIFO threshold flag" "0,1"
newline
bitfld.long 0x0 25. "TCBGT,TCBGT: Transmission complete before guard time flagl" "0,1"
bitfld.long 0x0 24. "RXFF,RXFF: RXFIFO Full" "0,1"
newline
bitfld.long 0x0 23. "TXFE,TXFE: TXFIFO Empty" "0,1"
bitfld.long 0x0 22. "REACK,REACK: Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,TEACK: Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 19. "RWU,RWU: Receiver wakeup from Mute mode" "0,1"
newline
bitfld.long 0x0 18. "SBKF,SBKF: Send break flag" "0,1"
bitfld.long 0x0 17. "CMF,CMF: Character match flag" "0,1"
newline
bitfld.long 0x0 16. "BUSY,BUSY: Busy flag" "0,1"
bitfld.long 0x0 15. "ABRF,ABRF: Auto baud rate flag" "0,1"
newline
bitfld.long 0x0 14. "ABRE,ABRE: Auto baud rate error" "0,1"
bitfld.long 0x0 13. "UDR,UDR: SPI slave underrun error flag" "0,1"
newline
bitfld.long 0x0 12. "EOBF,EOBF: End of block flag" "0,1"
bitfld.long 0x0 11. "RTOF,RTOF: Receiver timeout" "0,1"
newline
bitfld.long 0x0 10. "CTS,CTS: CTS flag" "0,1"
bitfld.long 0x0 9. "CTSIF,CTSIF: CTS interrupt flag" "0,1"
newline
bitfld.long 0x0 8. "LBDF,LBDF: LIN break detection flag" "0,1"
bitfld.long 0x0 7. "TXE_TXFNF,TXE/TXFNF: Transmit data register empty/TXFIFO not full" "0,1"
newline
bitfld.long 0x0 6. "TC,TC: Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE_RXFNE,RXNE/RXFNE:Read data register not empty/RXFIFO not empty" "0,1"
newline
bitfld.long 0x0 4. "IDLE,IDLE: Idle line detected" "0,1"
bitfld.long 0x0 3. "ORE,ORE: Overrun error" "0,1"
newline
bitfld.long 0x0 2. "NF,NF: START bit Noise detection flag" "0,1"
bitfld.long 0x0 1. "FE,FE: Framing error" "0,1"
newline
bitfld.long 0x0 0. "PE,PE: Parity error" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "ICR,ICR register"
bitfld.long 0x0 17. "CMCF,CMCF: Character match clear flag" "0,1"
bitfld.long 0x0 13. "UDRCF,UDRCF:SPI slave underrun clear flag" "0,1"
newline
bitfld.long 0x0 12. "EOBCF,EOBCF: End of block clear flag" "0,1"
bitfld.long 0x0 11. "RTOCF,RTOCF: Receiver timeout clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTSCF: CTS clear flag" "0,1"
bitfld.long 0x0 8. "LBDCF,LBDCF: LIN break detection clear flag" "0,1"
newline
bitfld.long 0x0 7. "TCBGTCF,TCBGTCF: Transmission complete before Guard time clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,TCCF: Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 5. "TXFECF,TXFECF: TXFIFO empty clear flag" "0,1"
bitfld.long 0x0 4. "IDLECF,IDLECF: Idle line detected clear flag" "0,1"
newline
bitfld.long 0x0 3. "ORECF,ORECF: Overrun error clear flag" "0,1"
bitfld.long 0x0 2. "NECF,NECF: Noise detected clear flag" "0,1"
newline
bitfld.long 0x0 1. "FECF,FECF: Framing error clear flag" "0,1"
bitfld.long 0x0 0. "PECF,PECF: Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "RDR,RDR register"
hexmask.long.word 0x0 0.--8. 1. "RDR,RDR[8:0]: Receive data value"
group.long 0x28++0x7
line.long 0x0 "TDR,TDR register"
hexmask.long.word 0x0 0.--8. 1. "TDR,TDR[8:0]: Transmit data value"
line.long 0x4 "PRESC,PRESC register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,PRESCALER[3:0]: Clock prescaler"
endif
tree.end
sif (cpuis("STM32WB06*")||cpuis("STM32WB07*")||cpuis("STM32WB09*"))
tree "WAKEUP"
base ad:0x60001800
group.long 0x8++0x3
line.long 0x0 "WAKEUP_OFFSET,WAKEUP_OFFSET register"
hexmask.long.byte 0x0 0.--7. 1. "WAKEUP_OFFSET,delay of anticipation of the Soc device to settle power and clock"
rgroup.long 0x10++0xF
line.long 0x0 "ABSOLUTE_TIME,ABSOLUTE_TIME register"
hexmask.long 0x0 0.--31. 1. "ABSOLUTE_TIME,absolute time"
line.long 0x4 "MINIMUM_PERIOD_LENGTH,MINIMUM_PERIOD_LENGTH register"
hexmask.long.word 0x4 4.--13. 1. "LENGTH,minimum period length computed by Time Interpolator"
line.long 0x8 "AVERAGE_PERIOD_LENGTH,AVERAGE_PERIOD_LENGTH register"
hexmask.long.byte 0x8 24.--31. 1. "AVERAGE_COUNT,Number of slow clock cycles."
hexmask.long.word 0x8 4.--13. 1. "LENGTH_INT,average period length computed by Time Interpolator."
hexmask.long.byte 0x8 0.--3. 1. "LENGTH_FRACT,additional information/precision on slow clock frequency."
line.long 0xC "MAXIMUM_PERIOD_LENGTH,MAXIMUM_PERIOD_LENGTH register"
hexmask.long.word 0xC 4.--13. 1. "LENGTH,maximum period length computed by Time Interpolator"
group.long 0x20++0x13
line.long 0x0 "STATISTICS_RESTART,STATISTICS_RESTART register"
bitfld.long 0x0 1. "CLR_AVR,Write '1' to clear the AVERAGE_PERIOD_LENGTH register value." "0,1"
bitfld.long 0x0 0. "CLR_MIN_MAX,Write '1' to clear the minimum and maximum registers." "0,1"
line.long 0x4 "BLUE_WAKEUP_TIME,BLUE_WAKEUP_TIME register"
hexmask.long 0x4 0.--31. 1. "WAKEUP_TIME,programmed wakeup time for the IP_BLE."
line.long 0x8 "BLUE_SLEEP_REQUEST_MODE,BLUE_SLEEP_REQUEST_MODE register"
bitfld.long 0x8 31. "FORCE_SLEEPING,IP_BLE sleeping control:" "0,1"
bitfld.long 0x8 30. "BLE_WAKEUP_EN,IP_BLE wakeup enable:" "0,1"
bitfld.long 0x8 29. "SLEEP_EN,IP_BLE sleeping mode enable:" "0,1"
line.long 0xC "CM0_WAKEUP_TIME,CM0_WAKEUP_TIME register"
hexmask.long 0xC 4.--31. 1. "WAKEUP_TIME,programmed wakeup time for CPU."
line.long 0x10 "CM0_SLEEP_REQUEST_MODE,CM0_SLEEP_REQUEST_MODE register"
bitfld.long 0x10 31. "FORCE_SLEEPING,CPU sleeping control:" "0,1"
bitfld.long 0x10 30. "CPU_WAKEUP_EN,CPU wakeup enable:" "0,1"
group.long 0x40++0xF
line.long 0x0 "WAKEUP_BLE_IRQ_ENABLE,WAKEUP_BLE_IRQ_ENABLE register"
bitfld.long 0x0 0. "WAKEUP_IT,IP_BLE wakeup interrupt enable:" "0,1"
line.long 0x4 "WAKEUP_BLE_IRQ_STATUS,WAKEUP_BLE_IRQ_STATUS register"
bitfld.long 0x4 0. "WAKEUP_IT,On read returns the IP_BLE wakeup interrupt status." "0,1"
line.long 0x8 "WAKEUP_CM0_IRQ_ENABLE,WAKEUP_CM0_IRQ_ENABLE register"
bitfld.long 0x8 0. "WAKEUP_IT,CPU wakeup interrupt enable:" "0,1"
line.long 0xC "WAKEUP_CM0_IRQ_STATUS,WAKEUP_CM0_IRQ_STATUS register"
bitfld.long 0xC 0. "WAKEUP_IT,On read returns the CPU wakeup interrupt status." "0,1"
tree.end
endif
sif (cpuis("STM32WB05*"))
tree "WAKEUP_REG"
base ad:0x60001800
group.long 0x8++0x3
line.long 0x0 "WAKEUP_OFFSET,WAKEUP_OFFSET register"
hexmask.long.byte 0x0 0.--7. 1. "WAKEUP_OFFSET,delay of anticipation of the Soc device to settle power and clock"
rgroup.long 0x10++0xF
line.long 0x0 "ABSOLUTE_TIME,ABSOLUTE_TIME register"
hexmask.long 0x0 0.--31. 1. "ABSOLUTE_TIME,absolute time"
line.long 0x4 "MINIMUM_PERIOD_LENGTH,MINIMUM_PERIOD_LENGTH register"
hexmask.long.word 0x4 4.--13. 1. "LENGTH,minimum period length computed by Time Interpolator"
line.long 0x8 "AVERAGE_PERIOD_LENGTH,AVERAGE_PERIOD_LENGTH register"
hexmask.long.byte 0x8 24.--31. 1. "AVERAGE_COUNT,Number of slow clock cycles."
hexmask.long.word 0x8 4.--13. 1. "LENGTH_INT,average period length computed by Time Interpolator."
hexmask.long.byte 0x8 0.--3. 1. "LENGTH_FRACT,additional information/precision on slow clock frequency."
line.long 0xC "MAXIMUM_PERIOD_LENGTH,MAXIMUM_PERIOD_LENGTH register"
hexmask.long.word 0xC 4.--13. 1. "LENGTH,maximum period length computed by Time Interpolator"
group.long 0x20++0x13
line.long 0x0 "STATISTICS_RESTART,STATISTICS_RESTART register"
bitfld.long 0x0 1. "CLR_AVR,Write '1' to clear the AVERAGE_PERIOD_LENGTH register value." "0,1"
bitfld.long 0x0 0. "CLR_MIN_MAX,Write '1' to clear the minimum and maximum registers." "0,1"
line.long 0x4 "BLUE_WAKEUP_TIME,BLUE_WAKEUP_TIME register"
hexmask.long 0x4 0.--31. 1. "WAKEUP_TIME,programmed wakeup time for the IP_BLE."
line.long 0x8 "BLUE_SLEEP_REQUEST_MODE,BLUE_SLEEP_REQUEST_MODE register"
bitfld.long 0x8 31. "FORCE_SLEEPING,IP_BLE sleeping control:" "0,1"
bitfld.long 0x8 30. "BLE_WAKEUP_EN,IP_BLE wakeup enable:" "0,1"
bitfld.long 0x8 29. "SLEEP_EN,IP_BLE sleeping mode enable:" "0,1"
line.long 0xC "CM0_WAKEUP_TIME,CM0_WAKEUP_TIME register"
hexmask.long 0xC 4.--31. 1. "WAKEUP_TIME,programmed wakeup time for CPU."
line.long 0x10 "CM0_SLEEP_REQUEST_MODE,CM0_SLEEP_REQUEST_MODE register"
bitfld.long 0x10 31. "FORCE_SLEEPING,CPU sleeping control:" "0,1"
bitfld.long 0x10 30. "CPU_WAKEUP_EN,CPU wakeup enable:" "0,1"
group.long 0x40++0xF
line.long 0x0 "WAKEUP_BLE_IRQ_ENABLE,WAKEUP_BLE_IRQ_ENABLE register"
bitfld.long 0x0 0. "WAKEUP_IT,IP_BLE wakeup interrupt enable:" "0,1"
line.long 0x4 "WAKEUP_BLE_IRQ_STATUS,WAKEUP_BLE_IRQ_STATUS register"
bitfld.long 0x4 0. "WAKEUP_IT,On read returns the IP_BLE wakeup interrupt status." "0,1"
line.long 0x8 "WAKEUP_CM0_IRQ_ENABLE,WAKEUP_CM0_IRQ_ENABLE register"
bitfld.long 0x8 0. "WAKEUP_IT,CPU wakeup interrupt enable:" "0,1"
line.long 0xC "WAKEUP_CM0_IRQ_STATUS,WAKEUP_CM0_IRQ_STATUS register"
bitfld.long 0xC 0. "WAKEUP_IT,On read returns the CPU wakeup interrupt status." "0,1"
tree.end
endif
newline
AUTOINDENT.OFF
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