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27a5f79fcc6b8e95bb98cc32aa40ed94c496dc70
Work/Src/Gen4_R-Car_Trace32/2_Trunk/perstm32u0.per
woody 6daf21a46d add
2026-06-16 12:20:14 +09:00

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; --------------------------------------------------------------------------------
; @Title: STM32U0 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-07-26 NEJ
; @Manufacturer: STM - ST Microelectronics N.V.
; @Doc: Generated (TRACE32, build: 171280.), based on:
; STM32U083.svd (Ver. 1.0), STM32U073.svd (Ver. 1.0),
; STM32U031.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: STM32U031C6, STM32U031C8, STM32U031F4, STM32U031F6,
; STM32U031F8, STM32U031G6, STM32U031G8, STM32U031K4,
; STM32U031K6, STM32U031K8, STM32U031R6, STM32U031R8,
; STM32U073C8, STM32U073CB, STM32U073CC, STM32U073H8,
; STM32U073HB, STM32U073HC, STM32U073K8, STM32U073KB,
; STM32U073KC, STM32U073M8, STM32U073MB, STM32U073MC,
; STM32U073R8, STM32U073RB, STM32U073RC, STM32U083CC,
; STM32U083HC, STM32U083KC, STM32U083MC, STM32U083RC
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perstm32u0.per 18171 2024-07-30 08:46:37Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC21=Cortex-M1"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
elif (CORENAME()=="CORTEXM0+")
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC60=Cortex-M0+"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
else
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
abitfld.long 0x00 24.--31. " IMPLEMENTER ,Implementer code that Arm has assigned" "0x41=Arm Limited"
bitfld.long 0x00 20.--23. " VARIANT ,Variant number to distinguish between different product variants or major revisions of the product" "r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15"
textline " "
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Indicates the architecture version" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,ARMv6-M,0xD,0xE,0xF"
textline " "
abitfld.long 0x00 4.--15. " PARTNO ,Indicates part number" "0xC20=Cortex-M0"
bitfld.long 0x00 0.--3. " REVISION ,Revision number to distinguish between different patches of the product" "p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15"
endif
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "ADC (Analog-to-Digital Converter)"
base ad:0x40012400
group.long 0x0++0x17
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
newline
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
newline
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
newline
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
newline
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
line.long 0x4 "ADC_IER,ADC interrupt enable register"
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
newline
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
newline
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
newline
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
newline
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
line.long 0x8 "ADC_CR,ADC control register"
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
newline
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
newline
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
line.long 0xC "ADC_CFGR1,ADC configuration register 1"
hexmask.long.byte 0xC 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
bitfld.long 0xC 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
newline
bitfld.long 0xC 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
bitfld.long 0xC 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
newline
bitfld.long 0xC 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
bitfld.long 0xC 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
newline
bitfld.long 0xC 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
bitfld.long 0xC 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
newline
bitfld.long 0xC 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
bitfld.long 0xC 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
newline
bitfld.long 0xC 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
bitfld.long 0xC 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
newline
bitfld.long 0xC 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
bitfld.long 0xC 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL),1: Backward scan (from CHSEL to CHSEL0)"
newline
bitfld.long 0xC 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
bitfld.long 0xC 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
line.long 0x10 "ADC_CFGR2,ADC configuration register 2"
bitfld.long 0x10 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),?"
bitfld.long 0x10 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
newline
bitfld.long 0x10 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
hexmask.long.byte 0x10 5.--8. 1. "OVSS,Oversampling shift"
newline
bitfld.long 0x10 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
bitfld.long 0x10 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
line.long 0x14 "ADC_SMPR,ADC sampling time register"
bitfld.long 0x14 27. "SMPSEL19,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 26. "SMPSEL18,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 25. "SMPSEL17,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 24. "SMPSEL16,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 23. "SMPSEL15,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 22. "SMPSEL14,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 21. "SMPSEL13,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 20. "SMPSEL12,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 19. "SMPSEL11,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 18. "SMPSEL10,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 17. "SMPSEL9,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 16. "SMPSEL8,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 15. "SMPSEL7,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 14. "SMPSEL6,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 13. "SMPSEL5,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 12. "SMPSEL4,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 11. "SMPSEL3,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 10. "SMPSEL2,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 9. "SMPSEL1,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
bitfld.long 0x14 8. "SMPSEL0,Channel-x sampling time selection (x1=119 to 0)" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
newline
bitfld.long 0x14 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
bitfld.long 0x14 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
group.long 0x20++0xB
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
line.long 0x8 "ADC_CHSELR,ADC channel selection register"
bitfld.long 0x8 19. "CHSEL19,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
newline
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
group.long 0x28++0x7
line.long 0x0 "ADC_CHSELR_ALTERNATE,ADC channel selection register"
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
newline
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
newline
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
newline
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
rgroup.long 0x40++0x3
line.long 0x0 "ADC_DR,ADC data register"
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
group.long 0xA0++0x7
line.long 0x0 "ADC_AWD2CR,ADC analog watchdog 2 configuration register"
bitfld.long 0x0 19. "AWD2CH19,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
newline
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
bitfld.long 0x4 19. "AWD3CH19,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
newline
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
group.long 0xB4++0x3
line.long 0x0 "ADC_CALFACT,ADC calibration factor"
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
group.long 0x308++0x3
line.long 0x0 "ADC_CCR,ADC common configuration register"
bitfld.long 0x0 24. "VBATEN,V<sub>BAT</sub> enable" "0: V<sub>BAT</sub> channel disabled,1: V<sub>BAT</sub> channel enabled"
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
newline
bitfld.long 0x0 22. "VREFEN,V<sub>REFINT</sub> enable" "0: V<sub>REFINT</sub> disabled,1: V<sub>REFINT</sub> enabled"
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
tree.end
sif (cpuis("STM32U083*"))
tree "AES (Advanced Encryption Standard Hardware Accelerator)"
base ad:0x40026000
group.long 0x0++0x3
line.long 0x0 "AES_CR,AES control register"
bitfld.long 0x0 31. "IPRST,AES peripheral software reset" "0,1"
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block"
newline
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128-bit,1: 256-bit"
bitfld.long 0x0 16. "CHMOD_1,CHMOD[2]" "0,1"
newline
bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Initialization phase,1: Header phase,2: Payload phase,3: Final phase"
bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable"
bitfld.long 0x0 5.--6. "CHMOD,CHMOD[1:0]: Chaining mode" "0: Electronic codebook (ECB),1: Cipher-block chaining (CBC),2: Counter mode (CTR),3: Galois counter mode (GCM) and Galois message.."
newline
bitfld.long 0x0 3.--4. "MODE,Operating mode" "0: Encryption,1: Key derivation (or key preparation) for ECB/CBC..,2: Decryption,?"
bitfld.long 0x0 1.--2. "DATATYPE,Data type" "0: No swapping (32-bit data).,1: Half-word swapping (16-bit data),2: Byte swapping (8-bit data),3: Bit-level swapping"
newline
bitfld.long 0x0 0. "EN,Enable" "0: Disable,1: Enable"
rgroup.long 0x4++0x3
line.long 0x0 "AES_SR,AES status register"
bitfld.long 0x0 7. "KEYVALID,Key valid flag" "0: Key not valid,1: Key valid"
bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy"
newline
bitfld.long 0x0 2. "WRERRF,Write error flag" "0: No error,1: Unexpected write to AES_DINR register occurred.."
bitfld.long 0x0 1. "RDERRF,Read error flag" "0: No error,1: Unexpected read to AES_DOUTR register occurred.."
wgroup.long 0x8++0x3
line.long 0x0 "AES_DINR,AES data input register"
hexmask.long 0x0 0.--31. 1. "DIN,Data input"
rgroup.long 0xC++0x3
line.long 0x0 "AES_DOUTR,AES data output register"
hexmask.long 0x0 0.--31. 1. "DOUT,Data output"
wgroup.long 0x10++0xF
line.long 0x0 "AES_KEYR0,AES key register 0"
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]"
line.long 0x4 "AES_KEYR1,AES key register 1"
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]"
line.long 0x8 "AES_KEYR2,AES key register 2"
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]"
line.long 0xC "AES_KEYR3,AES key register 3"
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]"
group.long 0x20++0xF
line.long 0x0 "AES_IVR0,AES initialization vector register 0"
hexmask.long 0x0 0.--31. 1. "IVI,Initialization vector input bits [31:0]"
line.long 0x4 "AES_IVR1,AES initialization vector register 1"
hexmask.long 0x4 0.--31. 1. "IVI,Initialization vector input bits [63:32]"
line.long 0x8 "AES_IVR2,AES initialization vector register 2"
hexmask.long 0x8 0.--31. 1. "IVI,Initialization vector input bits [95:64]"
line.long 0xC "AES_IVR3,AES initialization vector register 3"
hexmask.long 0xC 0.--31. 1. "IVI,Initialization vector input bits [127:96]"
wgroup.long 0x30++0xF
line.long 0x0 "AES_KEYR4,AES key register 4"
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [159:128]"
line.long 0x4 "AES_KEYR5,AES key register 5"
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [191:160]"
line.long 0x8 "AES_KEYR6,AES key register 6"
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [223:192]"
line.long 0xC "AES_KEYR7,AES key register 7"
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [255:224]"
group.long 0x40++0x1F
line.long 0x0 "AES_SUSPR0,AES suspend registers"
hexmask.long 0x0 0.--31. 1. "SUSP,Suspend data"
line.long 0x4 "AES_SUSPR1,AES suspend registers"
hexmask.long 0x4 0.--31. 1. "SUSP,Suspend data"
line.long 0x8 "AES_SUSPR2,AES suspend registers"
hexmask.long 0x8 0.--31. 1. "SUSP,Suspend data"
line.long 0xC "AES_SUSPR3,AES suspend registers"
hexmask.long 0xC 0.--31. 1. "SUSP,Suspend data"
line.long 0x10 "AES_SUSPR4,AES suspend registers"
hexmask.long 0x10 0.--31. 1. "SUSP,Suspend data"
line.long 0x14 "AES_SUSPR5,AES suspend registers"
hexmask.long 0x14 0.--31. 1. "SUSP,Suspend data"
line.long 0x18 "AES_SUSPR6,AES suspend registers"
hexmask.long 0x18 0.--31. 1. "SUSP,Suspend data"
line.long 0x1C "AES_SUSPR7,AES suspend registers"
hexmask.long 0x1C 0.--31. 1. "SUSP,Suspend data"
group.long 0x300++0x3
line.long 0x0 "AES_IER,AES interrupt enable register"
bitfld.long 0x0 2. "KEIE,Key error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
bitfld.long 0x0 1. "RWEIE,Read or write error interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
newline
bitfld.long 0x0 0. "CCFIE,Computation complete flag interrupt enable" "0: Disabled (masked),1: Enabled (not masked)"
rgroup.long 0x304++0x3
line.long 0x0 "AES_ISR,AES interrupt status register"
bitfld.long 0x0 2. "KEIF,Key error interrupt flag" "0: No key error detected,1: Key information failed to load into key registers"
bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag" "0: No read or write error detected,1: Read or write error detected"
newline
bitfld.long 0x0 0. "CCF,Computation complete flag" "0: Not completed,1: Completed"
wgroup.long 0x308++0x3
line.long 0x0 "AES_ICR,AES interrupt clear register"
bitfld.long 0x0 2. "KEIF,Key error interrupt flag clear" "0,1"
bitfld.long 0x0 1. "RWEIF,Read or write error interrupt flag clear" "0,1"
newline
bitfld.long 0x0 0. "CCF,Computation complete flag clear" "0,1"
tree.end
endif
tree "COMP (Comparator)"
base ad:0x40010200
group.long 0x0++0x7
line.long 0x0 "COMP1_CSR,Comparator 1 control and status register"
bitfld.long 0x0 31. "LOCK,COMP_CSR register lock" "0: Not locked,1: Locked"
rbitfld.long 0x0 30. "VALUE,Comparator 1 output status" "0,1"
newline
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 1 blanking source selector"
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 1 power mode selector" "0: High speed/high power,1: Medium speed/medium power,2: Medium speed/medium power,3: Low speed/low power"
newline
bitfld.long 0x0 16.--17. "HYST,Comparator 1 hysteresis selector" "0: No hysteresis,1: Low hysteresis,2: Medium hysteresis,3: High hysteresis"
bitfld.long 0x0 15. "POLARITY,Comparator 1 polarity selector" "0: Non-inverted,1: Inverted"
newline
bitfld.long 0x0 14. "WINOUT,Comparator 1 output selector" "0: COMP_VALUE,1: COMP_VALUE XOR COMP_VALUE (required for window.."
bitfld.long 0x0 11. "WINMODE,Comparator 1 noninverting input selector for window mode" "0: Signal selected with INPSEL[2:0] bitfield of..,1: COMP_INP signal of the comparator 2 (required.."
newline
bitfld.long 0x0 8.--10. "INPSEL,Comparator 1 signal selector for noninverting input" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 1 signal selector for inverting input INM"
newline
bitfld.long 0x0 0. "EN,Comparator 1 enable bit" "0: Disable,1: Enable"
line.long 0x4 "COMP2_CSR,Comparator 2 control and status register"
bitfld.long 0x4 31. "LOCK,COMP_CSR register lock" "0: Not locked,1: Locked"
rbitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
newline
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source selector"
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode selector" "0: High speed/high power,1: Medium speed/medium power,2: Medium speed/medium power,3: Low speed/low power"
newline
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis selector" "0: No hysteresis,1: Low hysteresis,2: Medium hysteresis,3: High hysteresis"
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
newline
bitfld.long 0x4 14. "WINOUT,Comparator 2 output selector" "0: COMP_VALUE,1: COMP_VALUE XOR COMP_VALUE (required for window.."
bitfld.long 0x4 11. "WINMODE,Comparator 2 noninverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP_INP signal of the comparator 1 (required.."
newline
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for noninverting input" "0,1,2,3"
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for inverting input INM"
newline
bitfld.long 0x4 0. "EN,Comparator 2 enable bit" "0: Disable,1: Enable"
tree.end
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
base ad:0x40023000
group.long 0x0++0xB
line.long 0x0 "CRC_DR,CRC data register"
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
line.long 0x4 "CRC_IDR,CRC independent data register"
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register bits"
line.long 0x8 "CRC_CR,CRC control register"
bitfld.long 0x8 10. "RTYPE_OUT,Reverse type output" "0: Bit level output,1: Byte or half-word level output"
bitfld.long 0x8 9. "RTYPE_IN,Reverse type input" "0: Bit level input,1: Byte or half-word level input"
newline
bitfld.long 0x8 7.--8. "REV_OUT,Reverse output data" "0: Bit order not affected (RTYPE_OUT1=10 or 1),1: Bit-reversed output format (RTYPE_OUT1=10) or..,2: Bit order not affected (RTYPE_OUT1=10) or byte..,3: Bit order not affected (RTYPE_OUT1=10 or 1)"
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected (RTYPE_IN1=10 or 1),1: Bit reversal done by byte (RTYPE_IN1=10) or..,2: Bit reversal done by half-word (RTYPE_IN1=10) or..,3: Bit reversal done by word (RTYPE_IN1=10) or bit.."
newline
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
group.long 0x10++0x7
line.long 0x0 "CRC_INIT,CRC initial value"
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC value"
line.long 0x4 "CRC_POL,CRC polynomial"
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
tree.end
sif (cpuis("STM32U073*")||cpuis("STM32U083*"))
tree "CRS (Clock Recovery System)"
base ad:0x40006C00
group.long 0x0++0x7
line.long 0x0 "CRS_CR,CRS control register"
hexmask.long.byte 0x0 8.--14. 1. "TRIM,HSI48 oscillator smooth trimming"
bitfld.long 0x0 7. "SWSYNC,Generate software SYNC event" "0: No action,1: A software SYNC event is generated."
newline
bitfld.long 0x0 6. "AUTOTRIMEN,Automatic trimming enable" "0: Automatic trimming disabled TRIM bits can be..,1: Automatic trimming enabled TRIM bits are.."
bitfld.long 0x0 5. "CEN,Frequency error counter enable" "0: Frequency error counter disabled,1: Frequency error counter enabled"
newline
bitfld.long 0x0 3. "ESYNCIE,Expected SYNC interrupt enable" "0: Expected SYNC (ESYNCF) interrupt disabled,1: Expected SYNC (ESYNCF) interrupt enabled"
bitfld.long 0x0 2. "ERRIE,Synchronization or trimming error interrupt enable" "0: Synchronization or trimming error (ERRF)..,1: Synchronization or trimming error (ERRF).."
newline
bitfld.long 0x0 1. "SYNCWARNIE,SYNC warning interrupt enable" "0: SYNC warning (SYNCWARNF) interrupt disabled,1: SYNC warning (SYNCWARNF) interrupt enabled"
bitfld.long 0x0 0. "SYNCOKIE,SYNC event OK interrupt enable" "0: SYNC event OK (SYNCOKF) interrupt disabled,1: SYNC event OK (SYNCOKF) interrupt enabled"
line.long 0x4 "CRS_CFGR,CRS configuration register"
bitfld.long 0x4 31. "SYNCPOL,SYNC polarity selection" "0: SYNC active on rising edge (default),1: SYNC active on falling edge"
bitfld.long 0x4 28.--29. "SYNCSRC,SYNC signal source selection" "0: crs_sync_in_1 selected as SYNC signal source,1: crs_sync_in_2 selected as SYNC signal source,2: crs_sync_in_3 selected as SYNC signal source,3: crs_sync_in_4 selected as SYNC signal source"
newline
bitfld.long 0x4 24.--26. "SYNCDIV,SYNC divider" "0: SYNC not divided (default),1: SYNC divided by 2,2: SYNC divided by 4,3: SYNC divided by 8,4: SYNC divided by 16,5: SYNC divided by 32,6: SYNC divided by 64,7: SYNC divided by 128"
hexmask.long.byte 0x4 16.--23. 1. "FELIM,Frequency error limit"
newline
hexmask.long.word 0x4 0.--15. 1. "RELOAD,Counter reload value"
rgroup.long 0x8++0x3
line.long 0x0 "CRS_ISR,CRS interrupt and status register"
hexmask.long.word 0x0 16.--31. 1. "FECAP,Frequency error capture"
bitfld.long 0x0 15. "FEDIR,Frequency error direction" "0: Up-counting direction the actual frequency is..,1: Down-counting direction the actual frequency is.."
newline
bitfld.long 0x0 10. "TRIMOVF,Trimming overflow or underflow" "0: No trimming error signaled,1: Trimming error signaled"
bitfld.long 0x0 9. "SYNCMISS,SYNC missed" "0: No SYNC missed error signaled,1: SYNC missed error signaled"
newline
bitfld.long 0x0 8. "SYNCERR,SYNC error" "0: No SYNC error signaled,1: SYNC error signaled"
bitfld.long 0x0 3. "ESYNCF,Expected SYNC flag" "0: No expected SYNC signaled,1: Expected SYNC signaled"
newline
bitfld.long 0x0 2. "ERRF,Error flag" "0: No synchronization or trimming error signaled,1: Synchronization or trimming error signaled"
bitfld.long 0x0 1. "SYNCWARNF,SYNC warning flag" "0: No SYNC warning signaled,1: SYNC warning signaled"
newline
bitfld.long 0x0 0. "SYNCOKF,SYNC event OK flag" "0: No SYNC event OK signaled,1: SYNC event OK signaled"
group.long 0xC++0x3
line.long 0x0 "CRS_ICR,CRS interrupt flag clear register"
bitfld.long 0x0 3. "ESYNCC,Expected SYNC clear flag" "0,1"
bitfld.long 0x0 2. "ERRC,Error clear flag" "0,1"
newline
bitfld.long 0x0 1. "SYNCWARNC,SYNC warning clear flag" "0,1"
bitfld.long 0x0 0. "SYNCOKC,SYNC event OK clear flag" "0,1"
tree.end
endif
tree "DAC (Digital-to-Analog Converter)"
base ad:0x40007400
group.long 0x0++0x3
line.long 0x0 "DAC_CR,DAC control register"
bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0: DAC channel1 in Normal operating mode,1: DAC channel1 in calibration mode"
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0: DAC channel1 DMA Underrun Interrupt disabled,1: DAC channel1 DMA Underrun Interrupt enabled"
newline
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0: DAC channel1 DMA mode disabled,1: DAC channel1 DMA mode enabled"
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
newline
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection"
newline
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0: DAC channel1 trigger disabled and data written..,1: DAC channel1 trigger enabled and data from the.."
bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0: DAC channel1 disabled,1: DAC channel1 enabled"
wgroup.long 0x4++0x3
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0: No trigger,1: Trigger"
group.long 0x8++0xB
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data holding register"
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data"
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data holding register"
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data"
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data holding register"
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data"
rgroup.long 0x2C++0x3
line.long 0x0 "DAC_DOR1,DAC channel1 data output register"
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output"
group.long 0x34++0xF
line.long 0x0 "DAC_SR,DAC status register"
rbitfld.long 0x0 15. "BWST1,DAC channel1 busy writing sample time flag" "0: There is no write operation of DAC_SHSR1..,1: There is a write operation of DAC_SHSR1 ongoing:.."
rbitfld.long 0x0 14. "CAL_FLAG1,DAC channel1 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
newline
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
line.long 0x4 "DAC_CCR,DAC calibration control register"
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC channel1 offset trimming value"
line.long 0x8 "DAC_MCR,DAC mode control register"
bitfld.long 0x8 0.--2. "MODE1,DAC channel1 mode" "0: DAC channel1 is connected to external pin with..,1: DAC channel1 is connected to external pin and to..,2: DAC channel1 is connected to external pin with..,3: DAC channel1 is connected to on chip peripherals..,4: DAC channel1 is connected to external pin with..,5: DAC channel1 is connected to external pin and to..,6: DAC channel1 is connected to external pin and to..,7: DAC channel1 is connected to on chip peripherals.."
line.long 0xC "DAC_SHSR1,DAC channel1 sample and hold sample time register"
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC channel1 sample time (only valid in Sample and hold mode)"
group.long 0x48++0x7
line.long 0x0 "DAC_SHHR,DAC sample and hold time register"
hexmask.long.word 0x0 0.--9. 1. "THOLD1,DAC channel1 hold time (only valid in Sample and hold mode)"
line.long 0x4 "DAC_SHRR,DAC sample and hold refresh time register"
hexmask.long.byte 0x4 0.--7. 1. "TREFRESH1,DAC channel1 refresh time (only valid in Sample and hold mode)"
tree.end
tree "DBGMCU (MCU Debug Component)"
base ad:0x40015800
rgroup.long 0x0++0x3
line.long 0x0 "DBGMCU_IDCODE,DBGMCU device ID code register"
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifier"
newline
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
group.long 0x4++0xB
line.long 0x0 "DBGMCU_CR,DBGMCU configuration register"
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
newline
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
line.long 0x4 "DBGMCU_APB1FZR,DBGMCU APB1 freeze register"
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,LPTIM1 stop in debug" "0: normal operation. LPTIM1 continues to operate..,1: stop in debug. LPTIM1 is frozen while CPU is in.."
newline
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,LPTIM2 stop in debug" "0: normal operation. LPTIM2 continues to operate..,1: stop in debug. LPTIM2 is frozen while CPU is in.."
newline
bitfld.long 0x4 22. "DBG_I2C1_STOP,I2C1 SMBUS timeout stop in debug" "0: normal operation. I2C1 SMBUS timeout continues..,1: stop in debug. I2C1 SMBUS timeout is frozen.."
newline
bitfld.long 0x4 21. "DBG_I2C3_STOP,I2C3 SMBUS timeout stop in debug" "0: normal operation. I2C3 SMBUS timeout continues..,1: stop in debug. I2C3 SMBUS timeout is frozen.."
newline
bitfld.long 0x4 12. "DBG_IWDG_STOP,IWDG stop in debug" "0: normal operation. IWDG continues to operate..,1: stop in debug. IWDG is frozen while CPU is in.."
newline
bitfld.long 0x4 11. "DBG_WWDG_STOP,WWDG stop in debug" "0: normal operation. WWDG continues to operate..,1: stop in debug. WWDG is frozen while CPU is in.."
newline
bitfld.long 0x4 10. "DBG_RTC_STOP,RTC stop in debug" "0: normal operation. RTC counter continues to..,1: stop in debug. RTC counter is frozen while CPU.."
newline
bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 stop in debug" "0: normal operation. TIM7 continues to operate..,1: stop in debug. TIM7 is frozen while CPU is in.."
newline
bitfld.long 0x4 4. "DBG_TIM6_STOP,TIM6 stop in debug" "0: normal operation. TIM6 continues to operate..,1: stop in debug. TIM6 is frozen while CPU is in.."
newline
bitfld.long 0x4 2. "DBG_TIM4_STOP,TIM4 stop in debug" "0: normal operation. TIM4 continues to operate..,1: stop in debug. TIM34 is frozen while CPU is in.."
newline
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 stop in debug" "0: normal operation. TIM3 continues to operate..,1: stop in debug. TIM3 is frozen while CPU is in.."
newline
bitfld.long 0x4 0. "DBG_TIM2_STOP,TIM2 stop in debug" "0: normal operation. TIM2 continues to operate..,1: stop in debug. TIM2 is frozen while CPU is in.."
line.long 0x8 "DBGMCU_APB2FZR,DBG APB2 freeze register"
sif (cpuis("STM32U073*"))
bitfld.long 0x8 18. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0: normal operation. LPTIM3 continues to operate..,1: stop in debug. LPTIM3 is frozen while CPU is in.."
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x8 18. "DBG_LPTIM3_STOP,LPTIM3 stop in debug" "0: normal operation. LPTIM3 continues to operate..,1: stop in debug. LPTIM3 is frozen while CPU is in.."
newline
endif
bitfld.long 0x8 17. "DBG_TIM16_STOP,TIM16 stop in debug" "0: normal operation. TIM16 continues to operate..,1: stop in debug. TIM16 is frozen while CPU is in.."
newline
bitfld.long 0x8 16. "DBG_TIM15_STOP,TIM15 stop in debug" "0: normal operation. TIM15 continues to operate..,1: stop in debug. TIM15 is frozen while CPU is in.."
newline
bitfld.long 0x8 15. "DBG_TIM14_STOP,TIM14 stop in debug" "0: normal operation. TIM14 continues to operate..,1: stop in debug. TIM14 is frozen while CPU is in.."
newline
bitfld.long 0x8 11. "DBG_TIM1_STOP,TIM1 stop in debug" "0: normal operation. TIM1 continues to operate..,1: stop in debug. TIM1 is frozen while CPU is in.."
rgroup.long 0xFC++0x3
line.long 0x0 "DBGMCU_SR,DBGMCU status register"
bitfld.long 0x0 17. "AP0_ENABLED,Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)" "0: AP0 locked,1: AP0 enabled"
newline
bitfld.long 0x0 16. "AP1_ENABLED,Identifies whether access port AP0 is open (can be accessed via the debug port) or locked (debug access to the AP is blocked)" "0: AP1 locked,1: AP1 enabled"
newline
bitfld.long 0x0 1. "AP0_PRESENT,Identifies whether access port AP0 is present in device" "?,1: AP0 present"
newline
bitfld.long 0x0 0. "AP1_PRESENT,Identifies whether access port AP1 is present in device" "?,1: AP1 present"
group.long 0x100++0x3
line.long 0x0 "DBGMCU_DBG_AUTH_HOST,DBGMCU debug authentication mailbox host register"
hexmask.long 0x0 0.--31. 1. "MESSAGE,Debug host to device mailbox message."
rgroup.long 0x104++0x3
line.long 0x0 "DBGMCU_DBG_AUTH_DEVICE,DBGMCU debug authentication mailbox device register"
hexmask.long 0x0 0.--31. 1. "MESSAGE,Device to debug host mailbox message."
rgroup.long 0xFD0++0x3
line.long 0x0 "DBGMCU_PIDR4,DBGMCU CoreSight peripheral identity register 4"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,register file size"
newline
hexmask.long.byte 0x0 0.--3. 1. "JEP106CON,JEP106 continuation code"
rgroup.long 0xFE0++0x1F
line.long 0x0 "DBGMCU_PIDR0,DBGMCU CoreSight peripheral identity register 0"
hexmask.long.byte 0x0 0.--7. 1. "PARTNUM,part number bits [7:0]"
line.long 0x4 "DBGMCU_PIDR1,DBGMCU CoreSight peripheral identity register 1"
hexmask.long.byte 0x4 4.--7. 1. "JEP106ID,JEP106 identity code bits [3:0]"
newline
hexmask.long.byte 0x4 0.--3. 1. "PARTNUM,part number bits [11:8]"
line.long 0x8 "DBGMCU_PIDR2,DBGMCU CoreSight peripheral identity register 2"
hexmask.long.byte 0x8 4.--7. 1. "REVISION,component revision number"
newline
bitfld.long 0x8 3. "JEDEC,JEDEC assigned value" "?,1: designer identification specified by JEDEC"
newline
bitfld.long 0x8 0.--2. "JEP106ID,JEP106 identity code bits [6:4]" "?,?,2: STMicroelectronics JEDEC code,?,?,?,?,?"
line.long 0xC "DBGMCU_PIDR3,DBGMCU CoreSight peripheral identity register 3"
hexmask.long.byte 0xC 4.--7. 1. "REVAND,metal fix version"
newline
hexmask.long.byte 0xC 0.--3. 1. "CMOD,customer modified"
line.long 0x10 "DBGMCU_CIDR0,DBGMCU CoreSight component identity register 0"
hexmask.long.byte 0x10 0.--7. 1. "PREAMBLE,component identification bits [7:0]"
line.long 0x14 "DBGMCU_CIDR1,DBGMCU CoreSight component identity register 1"
hexmask.long.byte 0x14 4.--7. 1. "CLASS,component identification bits [15:12] - component class"
newline
hexmask.long.byte 0x14 0.--3. 1. "PREAMBLE,component identification bits [11:8]"
line.long 0x18 "DBGMCU_CIDR2,DBGMCU CoreSight component identity register 2"
hexmask.long.byte 0x18 0.--7. 1. "PREAMBLE,component identification bits [23:16]"
line.long 0x1C "DBGMCU_CIDR3,DBGMCU CoreSight component identity register 3"
hexmask.long.byte 0x1C 0.--7. 1. "PREAMBLE,component identification bits [31:24]"
tree.end
tree "DMA (Direct Memory Access)"
base ad:0x0
tree "DMA1"
base ad:0x40020000
rgroup.long 0x0++0x3
line.long 0x0 "DMA_ISR,DMA interrupt status register"
bitfld.long 0x0 27. "TEIF7,Transfer error (TE) flag for channel 7" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 26. "HTIF7,Half transfer (HT) flag for channel 7" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 25. "TCIF7,Transfer complete (TC) flag for channel 7" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 24. "GIF7,Global interrupt flag for channel 7" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 23. "TEIF6,Transfer error (TE) flag for channel 6" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 22. "HTIF6,Half transfer (HT) flag for channel 6" "0: No HT event,1: An HT event occurred."
newline
bitfld.long 0x0 21. "TCIF6,Transfer complete (TC) flag for channel 6" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 20. "GIF6,Global interrupt flag for channel 6" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
newline
bitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
newline
bitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
newline
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
newline
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
newline
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
wgroup.long 0x4++0x3
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
bitfld.long 0x0 27. "CTEIF7,Transfer error flag clear for channel 7" "0,1"
bitfld.long 0x0 26. "CHTIF7,Half transfer flag clear for channel 7" "0,1"
bitfld.long 0x0 25. "CTCIF7,Transfer complete flag clear for channel 7" "0,1"
newline
bitfld.long 0x0 24. "CGIF7,Global interrupt flag clear for channel 7" "0,1"
bitfld.long 0x0 23. "CTEIF6,Transfer error flag clear for channel 6" "0,1"
bitfld.long 0x0 22. "CHTIF6,Half transfer flag clear for channel 6" "0,1"
newline
bitfld.long 0x0 21. "CTCIF6,Transfer complete flag clear for channel 6" "0,1"
bitfld.long 0x0 20. "CGIF6,Global interrupt flag clear for channel 6" "0,1"
bitfld.long 0x0 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
newline
bitfld.long 0x0 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
bitfld.long 0x0 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
bitfld.long 0x0 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
newline
bitfld.long 0x0 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
bitfld.long 0x0 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
bitfld.long 0x0 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
newline
bitfld.long 0x0 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
newline
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
newline
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
newline
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
newline
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
group.long 0x8++0xF
line.long 0x0 "DMA_CCR1,DMA channel 1 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR1,DMA channel 1 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR1,DMA channel 1 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR1,DMA channel 1 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x1C++0xF
line.long 0x0 "DMA_CCR2,DMA channel 2 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR2,DMA channel 2 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR2,DMA channel 2 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR2,DMA channel 2 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x30++0xF
line.long 0x0 "DMA_CCR3,DMA channel 3 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR3,DMA channel 3 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR3,DMA channel 3 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR3,DMA channel 3 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x44++0xF
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x58++0xF
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x6C++0xF
line.long 0x0 "DMA_CCR6,DMA channel 6 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR6,DMA channel 6 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR6,DMA channel 6 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR6,DMA channel 6 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x80++0xF
line.long 0x0 "DMA_CCR7,DMA channel 7 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR7,DMA channel 7 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR7,DMA channel 7 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR7,DMA channel 7 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
tree.end
tree "DMA2"
base ad:0x40020400
rgroup.long 0x0++0x3
line.long 0x0 "DMA_ISR,DMA interrupt status register"
bitfld.long 0x0 27. "TEIF7,Transfer error (TE) flag for channel 7" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 26. "HTIF7,Half transfer (HT) flag for channel 7" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 25. "TCIF7,Transfer complete (TC) flag for channel 7" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 24. "GIF7,Global interrupt flag for channel 7" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 23. "TEIF6,Transfer error (TE) flag for channel 6" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 22. "HTIF6,Half transfer (HT) flag for channel 6" "0: No HT event,1: An HT event occurred."
newline
bitfld.long 0x0 21. "TCIF6,Transfer complete (TC) flag for channel 6" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 20. "GIF6,Global interrupt flag for channel 6" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 19. "TEIF5,Transfer error (TE) flag for channel 5" "0: No TE event,1: A TE event occurred."
newline
bitfld.long 0x0 18. "HTIF5,Half transfer (HT) flag for channel 5" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 17. "TCIF5,Transfer complete (TC) flag for channel 5" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
newline
bitfld.long 0x0 15. "TEIF4,Transfer error (TE) flag for channel 4" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 14. "HTIF4,Half transfer (HT) flag for channel 4" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 13. "TCIF4,Transfer complete (TC) flag for channel 4" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 11. "TEIF3,Transfer error (TE) flag for channel 3" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 10. "HTIF3,Half transfer (HT) flag for channel 3" "0: No HT event,1: An HT event occurred."
newline
bitfld.long 0x0 9. "TCIF3,Transfer complete (TC) flag for channel 3" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 8. "GIF3,Global interrupt flag for channel 3" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
bitfld.long 0x0 7. "TEIF2,Transfer error (TE) flag for channel 2" "0: No TE event,1: A TE event occurred."
newline
bitfld.long 0x0 6. "HTIF2,Half transfer (HT) flag for channel 2" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 5. "TCIF2,Transfer complete (TC) flag for channel 2" "0: No TC event,1: A TC event occurred."
bitfld.long 0x0 4. "GIF2,Global interrupt flag for channel 2" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
newline
bitfld.long 0x0 3. "TEIF1,Transfer error (TE) flag for channel 1" "0: No TE event,1: A TE event occurred."
bitfld.long 0x0 2. "HTIF1,Half transfer (HT) flag for channel 1" "0: No HT event,1: An HT event occurred."
bitfld.long 0x0 1. "TCIF1,Transfer complete (TC) flag for channel 1" "0: No TC event,1: A TC event occurred."
newline
bitfld.long 0x0 0. "GIF1,Global interrupt flag for channel 1" "0: No TE HT or TC event,1: A TE HT or TC event occurred."
wgroup.long 0x4++0x3
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
bitfld.long 0x0 27. "CTEIF7,Transfer error flag clear for channel 7" "0,1"
bitfld.long 0x0 26. "CHTIF7,Half transfer flag clear for channel 7" "0,1"
bitfld.long 0x0 25. "CTCIF7,Transfer complete flag clear for channel 7" "0,1"
newline
bitfld.long 0x0 24. "CGIF7,Global interrupt flag clear for channel 7" "0,1"
bitfld.long 0x0 23. "CTEIF6,Transfer error flag clear for channel 6" "0,1"
bitfld.long 0x0 22. "CHTIF6,Half transfer flag clear for channel 6" "0,1"
newline
bitfld.long 0x0 21. "CTCIF6,Transfer complete flag clear for channel 6" "0,1"
bitfld.long 0x0 20. "CGIF6,Global interrupt flag clear for channel 6" "0,1"
bitfld.long 0x0 19. "CTEIF5,Transfer error flag clear for channel 5" "0,1"
newline
bitfld.long 0x0 18. "CHTIF5,Half transfer flag clear for channel 5" "0,1"
bitfld.long 0x0 17. "CTCIF5,Transfer complete flag clear for channel 5" "0,1"
bitfld.long 0x0 16. "CGIF5,Global interrupt flag clear for channel 5" "0,1"
newline
bitfld.long 0x0 15. "CTEIF4,Transfer error flag clear for channel 4" "0,1"
bitfld.long 0x0 14. "CHTIF4,Half transfer flag clear for channel 4" "0,1"
bitfld.long 0x0 13. "CTCIF4,Transfer complete flag clear for channel 4" "0,1"
newline
bitfld.long 0x0 12. "CGIF4,Global interrupt flag clear for channel 4" "0,1"
bitfld.long 0x0 11. "CTEIF3,Transfer error flag clear for channel 3" "0,1"
bitfld.long 0x0 10. "CHTIF3,Half transfer flag clear for channel 3" "0,1"
newline
bitfld.long 0x0 9. "CTCIF3,Transfer complete flag clear for channel 3" "0,1"
bitfld.long 0x0 8. "CGIF3,Global interrupt flag clear for channel 3" "0,1"
bitfld.long 0x0 7. "CTEIF2,Transfer error flag clear for channel 2" "0,1"
newline
bitfld.long 0x0 6. "CHTIF2,Half transfer flag clear for channel 2" "0,1"
bitfld.long 0x0 5. "CTCIF2,Transfer complete flag clear for channel 2" "0,1"
bitfld.long 0x0 4. "CGIF2,Global interrupt flag clear for channel 2" "0,1"
newline
bitfld.long 0x0 3. "CTEIF1,Transfer error flag clear for channel 1" "0,1"
bitfld.long 0x0 2. "CHTIF1,Half transfer flag clear for channel 1" "0,1"
bitfld.long 0x0 1. "CTCIF1,Transfer complete flag clear for channel 1" "0,1"
newline
bitfld.long 0x0 0. "CGIF1,Global interrupt flag clear for channel 1" "0,1"
group.long 0x8++0xF
line.long 0x0 "DMA_CCR1,DMA channel 1 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR1,DMA channel 1 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR1,DMA channel 1 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR1,DMA channel 1 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x1C++0xF
line.long 0x0 "DMA_CCR2,DMA channel 2 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR2,DMA channel 2 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR2,DMA channel 2 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR2,DMA channel 2 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x30++0xF
line.long 0x0 "DMA_CCR3,DMA channel 3 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR3,DMA channel 3 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR3,DMA channel 3 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR3,DMA channel 3 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x44++0xF
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR4,DMA channel 4 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR4,DMA channel 4 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR4,DMA channel 4 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x58++0xF
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR5,DMA channel 5 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR5,DMA channel 5 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR5,DMA channel 5 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x6C++0xF
line.long 0x0 "DMA_CCR6,DMA channel 6 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR6,DMA channel 6 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR6,DMA channel 6 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR6,DMA channel 6 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
group.long 0x80++0xF
line.long 0x0 "DMA_CCR7,DMA channel 7 configuration register"
bitfld.long 0x0 14. "MEM2MEM,Memory-to-memory mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 12.--13. "PL,Priority level" "0: Low,1: Medium,2: High,3: Very high"
bitfld.long 0x0 10.--11. "MSIZE,Memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
newline
bitfld.long 0x0 8.--9. "PSIZE,Peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
bitfld.long 0x0 7. "MINC,Memory increment mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 6. "PINC,Peripheral increment mode" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 5. "CIRC,Circular mode" "0: Disabled,1: Enabled"
bitfld.long 0x0 4. "DIR,Data transfer direction" "0: Read from peripheral,1: Read from memory"
bitfld.long 0x0 3. "TEIE,Transfer error interrupt enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 2. "HTIE,Half transfer interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 1. "TCIE,Transfer complete interrupt enable" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "EN,Channel enable" "0: Disabled,1: Enabled"
line.long 0x4 "DMA_CNDTR7,DMA channel 7 number of data to transfer register"
hexmask.long.word 0x4 0.--15. 1. "NDT,Number of data to transfer"
line.long 0x8 "DMA_CPAR7,DMA channel 7 peripheral address register"
hexmask.long 0x8 0.--31. 1. "PA,Peripheral address"
line.long 0xC "DMA_CMAR7,DMA channel 7 memory address register"
hexmask.long 0xC 0.--31. 1. "MA,Peripheral address"
tree.end
tree.end
tree "DMAMUX (DMA Multiplexer)"
base ad:0x40020800
group.long 0x0++0x2F
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel 0 configuration register"
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x0 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x0 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x0 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel 1 configuration register"
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x4 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x4 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x4 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel 2 configuration register"
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x8 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x8 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x8 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel 3 configuration register"
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0xC 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0xC 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0xC 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel 4 configuration register"
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x10 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x10 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x10 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel 5 configuration register"
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x14 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x14 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x14 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel 6 configuration register"
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x18 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x18 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x18 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x1C "DMAMUX_C7CR,DMAMUX request line multiplexer channel 7 configuration register"
hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x1C 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x1C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x1C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x1C 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x20 "DMAMUX_C8CR,DMAMUX request line multiplexer channel 8 configuration register"
hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x20 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x20 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x20 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x20 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x24 "DMAMUX_C9CR,DMAMUX request line multiplexer channel 9 configuration register"
hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x24 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x24 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x24 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x24 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x28 "DMAMUX_C10CR,DMAMUX request line multiplexer channel 10 configuration register"
hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x28 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x28 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x28 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x28 0.--6. 1. "DMAREQ_ID,DMA request identification"
line.long 0x2C "DMAMUX_C11CR,DMAMUX request line multiplexer channel 11 configuration register"
hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization identification"
hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
newline
bitfld.long 0x2C 17.--18. "SPOL,Synchronization polarity" "0: No event (no synchronization no detection).,1: Rising edge,2: Falling edge,3: Rising and falling edges"
bitfld.long 0x2C 16. "SE,Synchronization enable" "0: Synchronization disabled,1: Synchronization enabled"
newline
bitfld.long 0x2C 9. "EGE,Event generation enable" "0: Event generation disabled,1: Event generation enabled"
bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
newline
hexmask.long.byte 0x2C 0.--6. 1. "DMAREQ_ID,DMA request identification"
rgroup.long 0x80++0x3
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
bitfld.long 0x0 11. "SOF11,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 10. "SOF10,Synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 9. "SOF9,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 8. "SOF8,Synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 7. "SOF7,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
wgroup.long 0x84++0x3
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
bitfld.long 0x0 11. "CSOF11,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 10. "CSOF10,Clear synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 9. "CSOF9,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 8. "CSOF8,Clear synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 7. "CSOF7,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
newline
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
group.long 0x100++0xF
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel 0 configuration register"
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
newline
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
newline
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel 1 configuration register"
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
newline
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
newline
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel 2 configuration register"
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
newline
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
newline
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel 3 configuration register"
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: No event i.e. no trigger detection nor generation.,1: Rising edge,2: Falling edge,3: Rising and falling edges"
newline
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: Interrupt on a trigger overrun event occurrence..,1: Interrupt on a trigger overrun event occurrence.."
newline
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
rgroup.long 0x140++0x3
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
newline
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
wgroup.long 0x144++0x3
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
newline
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
tree.end
tree "EXTI (Extended Interrupt/Event Controller)"
base ad:0x40021800
group.long 0x0++0x13
line.long 0x0 "EXTI_RTSR1,EXTI rising trigger selection register"
bitfld.long 0x0 21. "RT21,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 19. "RT19,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
line.long 0x4 "EXTI_FTSR1,EXTI falling trigger selection register 1"
bitfld.long 0x4 21. "FT21,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 20. "FT20,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 19. "FT19,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line x (x1=1211to10)" "0: Disable,1: Enable"
line.long 0x8 "EXTI_SWIER1,EXTI software interrupt event register 1"
bitfld.long 0x8 21. "SWI21,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 20. "SWI20,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 19. "SWI19,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 18. "SWI18,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 17. "SWI17,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 16. "SWI16,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
newline
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line x (x1=1211to10)" "0: No effect,1: Rising edge event generated on the corresponding.."
line.long 0xC "EXTI_RPR1,EXTI rising edge pending register 1"
bitfld.long 0xC 21. "RPIF21,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 20. "RPIF20,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 19. "RPIF19,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 18. "RPIF18,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 17. "RPIF17,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 16. "RPIF16,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 15. "RPIF15,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 14. "RPIF14,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 13. "RPIF13,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 12. "RPIF12,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 11. "RPIF11,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 10. "RPIF10,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 9. "RPIF9,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 8. "RPIF8,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 7. "RPIF7,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 6. "RPIF6,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 5. "RPIF5,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 4. "RPIF4,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 3. "RPIF3,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 2. "RPIF2,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
newline
bitfld.long 0xC 1. "RPIF1,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
bitfld.long 0xC 0. "RPIF0,Rising edge event pending for configurable line x (x1=1211to10)" "0: No rising edge trigger request occurred,1: Rising edge trigger request occurred"
line.long 0x10 "EXTI_FPR1,EXTI falling edge pending register 1"
bitfld.long 0x10 21. "FPIF21,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 20. "FPIF20,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 19. "FPIF19,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 18. "FPIF18,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 17. "FPIF17,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 16. "FPIF16,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 15. "FPIF15,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 14. "FPIF14,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 13. "FPIF13,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 12. "FPIF12,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 11. "FPIF11,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 10. "FPIF10,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 9. "FPIF9,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 8. "FPIF8,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 7. "FPIF7,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 6. "FPIF6,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 5. "FPIF5,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 4. "FPIF4,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 3. "FPIF3,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 2. "FPIF2,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
newline
bitfld.long 0x10 1. "FPIF1,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
bitfld.long 0x10 0. "FPIF0,Falling edge event pending for configurable line x (x1=1211to10)" "0: No falling edge trigger request occurred,1: Falling edge trigger request occurred"
group.long 0x60++0xF
line.long 0x0 "EXTI_EXTICR1,EXTI external interrupt selection register 1"
hexmask.long.byte 0x0 24.--31. 1. "EXTI3,EXTI3 GPIO port selection"
hexmask.long.byte 0x0 16.--23. 1. "EXTI2,EXTI2 GPIO port selection"
newline
hexmask.long.byte 0x0 8.--15. 1. "EXTI1,EXTI1 GPIO port selection"
hexmask.long.byte 0x0 0.--7. 1. "EXTI0,EXTI0 GPIO port selection"
line.long 0x4 "EXTI_EXTICR2,EXTI external interrupt selection register 2"
hexmask.long.byte 0x4 24.--31. 1. "EXTI7,EXTI7 GPIO port selection"
hexmask.long.byte 0x4 16.--23. 1. "EXTI6,EXTI6 GPIO port selection"
newline
hexmask.long.byte 0x4 8.--15. 1. "EXTI5,EXTI5 GPIO port selection"
hexmask.long.byte 0x4 0.--7. 1. "EXTI4,EXTI4 GPIO port selection"
line.long 0x8 "EXTI_EXTICR3,EXTI external interrupt selection register 3"
hexmask.long.byte 0x8 24.--31. 1. "EXTI11,EXTI11 GPIO port selection"
hexmask.long.byte 0x8 16.--23. 1. "EXTI10,EXTI10 GPIO port selection"
newline
hexmask.long.byte 0x8 8.--15. 1. "EXTI9,EXTI9 GPIO port selection"
hexmask.long.byte 0x8 0.--7. 1. "EXTI8,EXTI8 GPIO port selection"
line.long 0xC "EXTI_EXTICR4,EXTI external interrupt selection register 4"
hexmask.long.byte 0xC 24.--31. 1. "EXTI15,EXTI15 GPIO port selection"
hexmask.long.byte 0xC 16.--23. 1. "EXTI14,EXTI14 GPIO port selection"
newline
hexmask.long.byte 0xC 8.--15. 1. "EXTI13,EXTI13 GPIO port selection"
hexmask.long.byte 0xC 0.--7. 1. "EXTI12,EXTI12 GPIO port selection"
group.long 0x80++0x7
line.long 0x0 "EXTI_IMR1,EXTI CPU wake-up with interrupt mask register"
bitfld.long 0x0 31. "IM31,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 30. "IM30,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 29. "IM29,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 28. "IM28,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 27. "IM27,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 26. "IM26,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 25. "IM25,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 24. "IM24,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 23. "IM23,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 22. "IM22,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 21. "IM21,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 20. "IM20,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 19. "IM19,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 18. "IM18,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 17. "IM17,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 16. "IM16,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 15. "IM15,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 14. "IM14,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 13. "IM13,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 12. "IM12,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 11. "IM11,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 10. "IM10,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 9. "IM9,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 8. "IM8,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 7. "IM7,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 6. "IM6,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 5. "IM5,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 4. "IM4,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 3. "IM3,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 2. "IM2,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
newline
bitfld.long 0x0 1. "IM1,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
bitfld.long 0x0 0. "IM0,CPU wake-up with interrupt mask on line x (x1=131 to 0)" "0: wake-up with interrupt masked,1: wake-up with interrupt unasked"
line.long 0x4 "EXTI_EMR1,EXTI CPU wake-up with event mask register"
bitfld.long 0x4 31. "EM31,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 30. "EM30,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 29. "EM29,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 28. "EM28,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 27. "EM27,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 26. "EM26,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 25. "EM25,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 24. "EM24,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 23. "EM23,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 22. "EM22,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 21. "EM21,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 20. "EM20,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 19. "EM19,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 18. "EM18,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 17. "EM17,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 16. "EM16,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 15. "EM15,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 14. "EM14,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 13. "EM13,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 12. "EM12,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 11. "EM11,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 10. "EM10,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 9. "EM9,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 8. "EM8,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 7. "EM7,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 6. "EM6,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 5. "EM5,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 4. "EM4,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 3. "EM3,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 2. "EM2,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 1. "EM1,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 0. "EM0,CPU wake-up with event generation mask on line x (x1=1311to10)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
group.long 0x90++0x7
line.long 0x0 "EXTI_IMR2,EXTI CPU wake-up with interrupt mask register"
bitfld.long 0x0 5. "IM37,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
bitfld.long 0x0 4. "IM36,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
newline
bitfld.long 0x0 3. "IM35,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
bitfld.long 0x0 2. "IM34,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
newline
bitfld.long 0x0 1. "IM33,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
bitfld.long 0x0 0. "IM32,CPU wake-up with interrupt mask on line x (x1=1371to132)" "0: wake-up with interrupt request from Line x is..,1: wake-up with interrupt request from Line x is.."
line.long 0x4 "EXTI_EMR2,EXTI CPU wake-up with event mask register"
bitfld.long 0x4 5. "EM37,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 4. "EM36,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 3. "EM35,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 2. "EM34,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
newline
bitfld.long 0x4 1. "EM33,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
bitfld.long 0x4 0. "EM32,CPU wake-up with event generation mask on line x (x1=1371to132)" "0: wake-up with event generation masked,1: wake-up with event generation unmasked"
tree.end
tree "FLASH (Embedded Flash Memory)"
base ad:0x40022000
group.long 0x0++0x3
line.long 0x0 "FLASH_ACR,FLASH access control register"
bitfld.long 0x0 18. "DBG_SWEN,Debug access software enable" "0: Debugger disabled,1: Debugger enabled"
newline
bitfld.long 0x0 16. "EMPTY,Main flash memory area empty" "0: Main flash memory area programmed,1: Main flash memory area empty"
newline
bitfld.long 0x0 11. "ICRST,CPU Instruction cache reset" "0: CPU Instruction cache is not reset,1: CPU Instruction cache is reset"
newline
bitfld.long 0x0 9. "ICEN,CPU Instruction cache enable" "0: CPU Instruction cache is disabled,1: CPU Instruction cache is enabled"
newline
bitfld.long 0x0 8. "PRFTEN,CPU Prefetch enable" "0: CPU Prefetch disabled,1: CPU Prefetch enabled"
newline
bitfld.long 0x0 0.--2. "LATENCY,Flash memory access latency" "0: Zero wait states,1: One wait state,?,?,?,?,?,?"
wgroup.long 0x8++0x7
line.long 0x0 "FLASH_KEYR,FLASH key register"
hexmask.long 0x0 0.--31. 1. "KEY,FLASH key"
line.long 0x4 "FLASH_OPTKEYR,FLASH option key register"
hexmask.long 0x4 0.--31. 1. "OPTKEY,Option byte key"
group.long 0x10++0xB
line.long 0x0 "FLASH_SR,FLASH status register"
rbitfld.long 0x0 18. "CFGBSY,Programming or erase configuration busy." "0,1"
newline
rbitfld.long 0x0 16. "BSY1,Busy" "0,1"
newline
bitfld.long 0x0 15. "OPTVERR,Option and Engineering bits loading validity error" "0,1"
newline
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
newline
bitfld.long 0x0 9. "FASTERR,Fast programming error" "0,1"
newline
bitfld.long 0x0 8. "MISSERR,Fast programming data miss error" "0,1"
newline
bitfld.long 0x0 7. "PGSERR,Programming sequence error" "0,1"
newline
bitfld.long 0x0 6. "SIZERR,Size error" "0,1"
newline
bitfld.long 0x0 5. "PGAERR,Programming alignment error" "0,1"
newline
bitfld.long 0x0 4. "WRPERR,Write protection error" "0,1"
newline
bitfld.long 0x0 3. "PROGERR,Programming error" "0,1"
newline
bitfld.long 0x0 1. "OPERR,Operation error" "0,1"
newline
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
line.long 0x4 "FLASH_CR,FLASH control register"
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
newline
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
newline
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection enable" "0: Disable (securable area accessible),1: Enable (securable area not accessible)"
newline
bitfld.long 0x4 27. "OBL_LAUNCH,Option byte load launch" "0,1"
newline
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 24. "EOPIE,End-of-operation interrupt enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 18. "FSTPG,Fast programming enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 17. "OPTSTRT,Start of modification of option bytes" "0,1"
newline
bitfld.long 0x4 16. "STRT,Start erase operation" "0,1"
newline
hexmask.long.byte 0x4 3.--9. 1. "PNB,Page number selection"
newline
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
newline
bitfld.long 0x4 1. "PER,Page erase enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 0. "PG,Flash memory programming enable" "0: Disable,1: Enable"
line.long 0x8 "FLASH_ECCR,FLASH ECC register"
bitfld.long 0x8 31. "ECCD,ECC detection" "0,1"
newline
bitfld.long 0x8 30. "ECCC,ECC correction" "0,1"
newline
bitfld.long 0x8 24. "ECCCIE,ECC correction interrupt enable" "0: ECCC interrupt disabled,1: ECCC interrupt enabled"
newline
rbitfld.long 0x8 20. "SYSF_ECC,System Flash memory ECC fail" "0,1"
newline
hexmask.long.word 0x8 0.--13. 1. "ADDR_ECC,ECC fail double-word address offset"
group.long 0x20++0x3
line.long 0x0 "FLASH_OPTR,FLASH option register"
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable bit" "0: Internal resets are propagated as simple pulse..,1: Internal resets drives NRST pin low until it is.."
newline
bitfld.long 0x0 27.--28. "NRST_MODE,NRST pin configuration" "?,1: Reset input only: a low level on the NRST pin..,2: Standard GPIO: only internal RESET is possible,3: Bidirectional reset: the NRST pin is configured.."
newline
bitfld.long 0x0 26. "NBOOT0,NBOOT0 option bit" "0: NBOOT01=10,1: NBOOT01=11"
newline
bitfld.long 0x0 25. "NBOOT1,Boot configuration" "0,1"
newline
bitfld.long 0x0 24. "NBOOT_SEL,BOOT0 signal source selection" "0: BOOT0 pin (legacy mode),1: NBOOT0 option bit"
newline
bitfld.long 0x0 23. "BKPSRAM_HW_ERASE_DISABLE,Backup SRAM erase prevention" "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "RAM_PARITY_CHECK,SRAM parity check control enable/disable" "0: Enable,1: Disable"
newline
bitfld.long 0x0 21. "BDRST,Backup domain reset" "0: Enable,1: Disable"
newline
bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0: Hardware window watchdog,1: Software window watchdog"
newline
bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in Standby mode" "0: Independent watchdog counter is frozen in..,1: Independent watchdog counter is running in.."
newline
bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in Stop mode" "0: Independent watchdog counter is frozen in Stop..,1: Independent watchdog counter is running in Stop.."
newline
bitfld.long 0x0 16. "IWDG_SW,Independent watchdog selection" "0: Hardware independent watchdog,1: Software independent watchdog"
newline
bitfld.long 0x0 15. "NRST_SHDW,Reset generated when entering Shutdown mode" "0: Reset generated when entering the Shutdown mode,1: No reset generated when entering the Shutdown mode"
newline
bitfld.long 0x0 14. "NRST_STDBY,Reset generated when entering Standby mode" "0: Reset generated when entering the Standby mode,1: No reset generate when entering the Standby mode"
newline
bitfld.long 0x0 13. "NRST_STOP,Reset generated when entering Stop mode" "0: Reset generated when entering the Stop mode,1: No reset generated when entering the Stop mode"
newline
bitfld.long 0x0 8.--10. "BORR_LEV,BOR reset level" "0: BOR rising level 1 with threshold around 2.1 V,1: BOR rising level 2 with threshold around 2.3 V,2: BOR rising level 3 with threshold around 2.6 V,3: BOR rising level 4 with threshold around 2.9 V,?,?,?,?"
newline
hexmask.long.byte 0x0 0.--7. 1. "RDP,Read protection level"
group.long 0x2C++0x7
line.long 0x0 "FLASH_WRP1AR,FLASH WRP area A address register"
hexmask.long.byte 0x0 16.--22. 1. "WRP1A_END,WRP area A end offset"
newline
hexmask.long.byte 0x0 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
line.long 0x4 "FLASH_WRP1BR,FLASH WRP area B address register"
hexmask.long.byte 0x4 16.--22. 1. "WRP1B_END,WRP area B end offset"
newline
hexmask.long.byte 0x4 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
group.long 0x80++0x3
line.long 0x0 "FLASH_SECR,FLASH security register"
hexmask.long.byte 0x0 24.--31. 1. "HDP1EN,Hide protection area enable"
newline
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user area" "0: Boot based on the pad/option bit configuration,1: Boot forced from main flash memory"
newline
hexmask.long.byte 0x0 0.--6. 1. "HDP1_PEND,Last page of the first hide protection area"
tree.end
tree "GPIO (General Purpose Inputs/Outputs)"
base ad:0x0
tree "GPIOA"
base ad:0x50000000
group.long 0x0++0xF
line.long 0x0 "GPIOA_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOA_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOA_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOA_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOA_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOA_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOA_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOA_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOA_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOA_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOA_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree "GPIOB"
base ad:0x50000400
group.long 0x0++0xF
line.long 0x0 "GPIOB_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOB_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOB_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOB_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOB_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOB_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOB_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOB_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOB_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOB_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOB_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree "GPIOC"
base ad:0x50000800
group.long 0x0++0xF
line.long 0x0 "GPIOC_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOC_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOC_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOC_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOC_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOC_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOC_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOC_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOC_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOC_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOC_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree "GPIOD"
base ad:0x50000C00
group.long 0x0++0xF
line.long 0x0 "GPIOD_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOD_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOD_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOD_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOD_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOD_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOD_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOD_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOD_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOD_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOD_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree "GPIOE"
base ad:0x50001000
group.long 0x0++0xF
line.long 0x0 "GPIOE_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOE_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOE_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOE_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOE_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOE_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOE_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOE_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOE_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOE_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOE_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree "GPIOF"
base ad:0x50001400
group.long 0x0++0xF
line.long 0x0 "GPIOF_MODER,GPIO port mode register"
bitfld.long 0x0 30.--31. "MODE15,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 28.--29. "MODE14,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 26.--27. "MODE13,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 24.--25. "MODE12,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 22.--23. "MODE11,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 20.--21. "MODE10,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 18.--19. "MODE9,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 16.--17. "MODE8,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 14.--15. "MODE7,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 12.--13. "MODE6,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 10.--11. "MODE5,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 8.--9. "MODE4,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 6.--7. "MODE3,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 4.--5. "MODE2,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
newline
bitfld.long 0x0 2.--3. "MODE1,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
bitfld.long 0x0 0.--1. "MODE0,Port x configuration I/O pin y" "0: Input mode,1: General purpose output mode,2: Alternate function mode,3: Analog mode (reset state)"
line.long 0x4 "GPIOF_OTYPER,GPIO port output type register"
bitfld.long 0x4 15. "OT15,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 14. "OT14,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 13. "OT13,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 12. "OT12,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 11. "OT11,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 10. "OT10,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 9. "OT9,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 8. "OT8,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 7. "OT7,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 6. "OT6,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 5. "OT5,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 4. "OT4,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 3. "OT3,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 2. "OT2,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
newline
bitfld.long 0x4 1. "OT1,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
bitfld.long 0x4 0. "OT0,Port x configuration I/O pin y" "0: Output push-pull (reset state),1: Output open-drain"
line.long 0x8 "GPIOF_OSPEEDR,GPIO port output speed register"
bitfld.long 0x8 30.--31. "OSPEED15,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 28.--29. "OSPEED14,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 26.--27. "OSPEED13,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 24.--25. "OSPEED12,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 22.--23. "OSPEED11,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 20.--21. "OSPEED10,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 18.--19. "OSPEED9,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 16.--17. "OSPEED8,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 14.--15. "OSPEED7,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 12.--13. "OSPEED6,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 10.--11. "OSPEED5,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 8.--9. "OSPEED4,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 6.--7. "OSPEED3,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 4.--5. "OSPEED2,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
newline
bitfld.long 0x8 2.--3. "OSPEED1,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
bitfld.long 0x8 0.--1. "OSPEED0,Port x configuration I/O pin y" "0: Low speed,1: Medium speed,2: High speed,3: Very high speed"
line.long 0xC "GPIOF_PUPDR,GPIO port pull-up/pull-down register"
bitfld.long 0xC 30.--31. "PUPD15,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 28.--29. "PUPD14,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 26.--27. "PUPD13,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 24.--25. "PUPD12,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 22.--23. "PUPD11,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 20.--21. "PUPD10,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 18.--19. "PUPD9,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 16.--17. "PUPD8,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 14.--15. "PUPD7,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 12.--13. "PUPD6,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 10.--11. "PUPD5,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 8.--9. "PUPD4,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 6.--7. "PUPD3,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 4.--5. "PUPD2,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
newline
bitfld.long 0xC 2.--3. "PUPD1,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
bitfld.long 0xC 0.--1. "PUPD0,Port x configuration I/O pin y" "0: No pull-up pull-down,1: Pull-up,2: Pull-down,?"
rgroup.long 0x10++0x3
line.long 0x0 "GPIOF_IDR,GPIO port input data register"
bitfld.long 0x0 15. "ID15,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 14. "ID14,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "ID13,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 12. "ID12,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "ID11,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 10. "ID10,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "ID9,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 8. "ID8,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "ID7,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 6. "ID6,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "ID5,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 4. "ID4,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "ID3,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 2. "ID2,Port x input data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "ID1,Port x input data I/O pin y" "0,1"
bitfld.long 0x0 0. "ID0,Port x input data I/O pin y" "0,1"
group.long 0x14++0x3
line.long 0x0 "GPIOF_ODR,GPIO port output data register"
bitfld.long 0x0 15. "OD15,Port output data I/O pin y" "0,1"
bitfld.long 0x0 14. "OD14,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 13. "OD13,Port output data I/O pin y" "0,1"
bitfld.long 0x0 12. "OD12,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 11. "OD11,Port output data I/O pin y" "0,1"
bitfld.long 0x0 10. "OD10,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 9. "OD9,Port output data I/O pin y" "0,1"
bitfld.long 0x0 8. "OD8,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 7. "OD7,Port output data I/O pin y" "0,1"
bitfld.long 0x0 6. "OD6,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 5. "OD5,Port output data I/O pin y" "0,1"
bitfld.long 0x0 4. "OD4,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 3. "OD3,Port output data I/O pin y" "0,1"
bitfld.long 0x0 2. "OD2,Port output data I/O pin y" "0,1"
newline
bitfld.long 0x0 1. "OD1,Port output data I/O pin y" "0,1"
bitfld.long 0x0 0. "OD0,Port output data I/O pin y" "0,1"
wgroup.long 0x18++0x3
line.long 0x0 "GPIOF_BSRR,GPIO port bit set/reset register"
bitfld.long 0x0 31. "BR15,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 30. "BR14,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 29. "BR13,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 28. "BR12,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 27. "BR11,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 26. "BR10,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 25. "BR9,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 24. "BR8,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 23. "BR7,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 22. "BR6,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 21. "BR5,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 20. "BR4,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 19. "BR3,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 18. "BR2,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 17. "BR1,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
bitfld.long 0x0 16. "BR0,Port x reset I/O pin y" "0: No action on the corresponding ODx bit,1: Resets the corresponding ODx bit"
newline
bitfld.long 0x0 15. "BS15,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 14. "BS14,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BS13,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 12. "BS12,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BS11,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 10. "BS10,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BS9,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 8. "BS8,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BS7,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 6. "BS6,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BS5,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 4. "BS4,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BS3,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 2. "BS2,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BS1,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
bitfld.long 0x0 0. "BS0,Port x set I/O pin y" "0: No action on the corresponding ODx bit,1: Sets the corresponding ODx bit"
group.long 0x1C++0xB
line.long 0x0 "GPIOF_LCKR,GPIO port configuration lock register"
bitfld.long 0x0 16. "LCKK,Lock key" "0: Port configuration lock key not active,1: Port configuration lock key active. The.."
bitfld.long 0x0 15. "LCK15,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 14. "LCK14,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 13. "LCK13,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 12. "LCK12,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 11. "LCK11,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 10. "LCK10,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 9. "LCK9,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 8. "LCK8,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 7. "LCK7,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 6. "LCK6,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 5. "LCK5,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 4. "LCK4,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 3. "LCK3,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 2. "LCK2,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
bitfld.long 0x0 1. "LCK1,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
newline
bitfld.long 0x0 0. "LCK0,Port x lock I/O pin y" "0: Port configuration not locked,1: Port configuration locked"
line.long 0x4 "GPIOF_AFRL,GPIO alternate function low register"
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x I/O pin y"
line.long 0x8 "GPIOF_AFRH,GPIO alternate function high register"
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x I/O pin y"
newline
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x I/O pin y"
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x I/O pin y"
wgroup.long 0x28++0x3
line.long 0x0 "GPIOF_BRR,GPIO port bit reset register"
bitfld.long 0x0 15. "BR15,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 14. "BR14,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 13. "BR13,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 12. "BR12,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 11. "BR11,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 10. "BR10,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 9. "BR9,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 8. "BR8,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 7. "BR7,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 6. "BR6,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 5. "BR5,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 4. "BR4,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 3. "BR3,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 2. "BR2,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
newline
bitfld.long 0x0 1. "BR1,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
bitfld.long 0x0 0. "BR0,Port x reset IO pin y" "0: No action on the corresponding ODx bit,1: Reset the corresponding ODx bit"
tree.end
tree.end
tree "I2C (Inter-Integrated Circuit Interface)"
base ad:0x0
tree "I2C1"
base ad:0x40005400
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C control register 1"
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware cleared by..,1: STOPF flag remains cleared by hardware. This.."
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware cleared by software..,1: ADDR flag remains cleared by hardware. This mode.."
newline
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
newline
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disable.,1: Wake-up from Stop mode enable."
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
newline
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C control register 2"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
newline
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
newline
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
newline
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master only sends the first seven bits of.."
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
newline
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
line.long 0xC "I2C_OAR2,I2C own address 2 register"
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMINGR,I2C timing register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
newline
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
newline
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
newline
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
newline
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
newline
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
newline
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
newline
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PECR,I2C PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
tree.end
tree "I2C2"
base ad:0x40005800
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C control register 1"
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware cleared by..,1: STOPF flag remains cleared by hardware. This.."
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware cleared by software..,1: ADDR flag remains cleared by hardware. This mode.."
newline
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
newline
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disable.,1: Wake-up from Stop mode enable."
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
newline
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C control register 2"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
newline
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
newline
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
newline
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master only sends the first seven bits of.."
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
newline
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
line.long 0xC "I2C_OAR2,I2C own address 2 register"
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMINGR,I2C timing register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
newline
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
newline
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
newline
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
newline
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
newline
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
newline
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
newline
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PECR,I2C PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
tree.end
tree "I2C3"
base ad:0x40008800
group.long 0x0++0x1B
line.long 0x0 "I2C_CR1,I2C control register 1"
bitfld.long 0x0 31. "STOPFACLR,STOP detection flag (STOPF) automatic clear" "0: STOPF flag is set by hardware cleared by..,1: STOPF flag remains cleared by hardware. This.."
bitfld.long 0x0 30. "ADDRACLR,Address match flag (ADDR) automatic clear" "0: ADDR flag is set by hardware cleared by software..,1: ADDR flag remains cleared by hardware. This mode.."
newline
bitfld.long 0x0 24. "FMP,Fast-mode Plus 20 mA drive enable" "0: 20 mA I/O drive disabled,1: 20 mA I/O drive enabled"
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
newline
bitfld.long 0x0 18. "WUPEN,Wake-up from Stop mode enable" "0: Wake-up from Stop mode disable.,1: Wake-up from Stop mode enable."
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
newline
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
newline
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
newline
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
newline
bitfld.long 0x0 6. "TCIE,Transfer complete interrupt enable" "0: Transfer complete interrupt disabled,1: Transfer complete interrupt enabled"
bitfld.long 0x0 5. "STOPIE,Stop detection interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
newline
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
newline
bitfld.long 0x0 2. "RXIE,RX interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
bitfld.long 0x0 1. "TXIE,TX interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
newline
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
line.long 0x4 "I2C_CR2,I2C control register 2"
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
newline
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
newline
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation,1: Stop generation after current byte transfer"
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation,1: Restart/Start generation:"
newline
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10-bit slave..,1: The master only sends the first seven bits of.."
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
newline
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer,1: Master requests a read transfer"
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
line.long 0x8 "I2C_OAR1,I2C own address 1 register"
bitfld.long 0x8 15. "OA1EN,Own address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
bitfld.long 0x8 10. "OA1MODE,Own address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
newline
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
line.long 0xC "I2C_OAR2,I2C own address 2 register"
bitfld.long 0xC 15. "OA2EN,Own address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
bitfld.long 0xC 8.--10. "OA2MSK,Own address 2 masks" "0: No mask,1: OA2[1] is masked and dont care. Only OA2[7:2]..,2: OA2[2:1] are masked and dont care. Only OA2[7:3]..,3: OA2[3:1] are masked and dont care. Only OA2[7:4]..,4: OA2[4:1] are masked and dont care. Only OA2[7:5]..,5: OA2[5:1] are masked and dont care. Only OA2[7:6]..,6: OA2[6:1] are masked and dont care. Only OA2[7]..,7: OA2[7:1] are masked and dont care. No comparison.."
newline
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
line.long 0x10 "I2C_TIMINGR,I2C timing register"
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
newline
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master mode)"
newline
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master mode)"
line.long 0x14 "I2C_TIMEOUTR,I2C timeout register"
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
newline
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
newline
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
line.long 0x18 "I2C_ISR,I2C interrupt and status register"
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (slave mode)"
rbitfld.long 0x18 16. "DIR,Transfer direction (slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
newline
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave mode)" "0,1"
newline
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
newline
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
rbitfld.long 0x18 6. "TC,Transfer Complete (master mode)" "0,1"
newline
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
rbitfld.long 0x18 4. "NACKF,Not Acknowledge received flag" "0,1"
newline
rbitfld.long 0x18 3. "ADDR,Address matched (slave mode)" "0,1"
rbitfld.long 0x18 2. "RXNE,Receive data register not empty (receivers)" "0,1"
newline
bitfld.long 0x18 1. "TXIS,Transmit interrupt status (transmitters)" "0,1"
bitfld.long 0x18 0. "TXE,Transmit data register empty (transmitters)" "0,1"
wgroup.long 0x1C++0x3
line.long 0x0 "I2C_ICR,I2C interrupt clear register"
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag clear" "0,1"
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag clear" "0,1"
newline
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
bitfld.long 0x0 5. "STOPCF,STOP detection flag clear" "0,1"
newline
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
bitfld.long 0x0 3. "ADDRCF,Address matched flag clear" "0,1"
rgroup.long 0x20++0x7
line.long 0x0 "I2C_PECR,I2C PEC register"
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking register"
line.long 0x4 "I2C_RXDR,I2C receive data register"
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
group.long 0x28++0x3
line.long 0x0 "I2C_TXDR,I2C transmit data register"
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
tree.end
tree.end
tree "IWDG (Independent Watchdog)"
base ad:0x40003000
wgroup.long 0x0++0x3
line.long 0x0 "IWDG_KR,IWDG key register"
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read 0x0000)"
group.long 0x4++0x7
line.long 0x0 "IWDG_PR,IWDG prescaler register"
hexmask.long.byte 0x0 0.--3. 1. "PR,Prescaler divider"
line.long 0x4 "IWDG_RLR,IWDG reload register"
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload value"
rgroup.long 0xC++0x3
line.long 0x0 "IWDG_SR,IWDG status register"
bitfld.long 0x0 14. "EWIF,Watchdog early interrupt flag" "0,1"
bitfld.long 0x0 8. "ONF,Watchdog enable status bit" "0: The IWDG is not activated,1: The IWDG is activated and needs to be refreshed.."
bitfld.long 0x0 3. "EWU,Watchdog interrupt comparator value update" "0,1"
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
newline
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
group.long 0x10++0x7
line.long 0x0 "IWDG_WINR,IWDG window register"
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window value"
line.long 0x4 "IWDG_EWCR,IWDG early wake-up interrupt register"
bitfld.long 0x4 15. "EWIE,Watchdog early interrupt enable" "0: The early interrupt interface is disabled.,1: The early interrupt interface is enabled."
bitfld.long 0x4 14. "EWIC,Watchdog early interrupt acknowledge" "0,1"
hexmask.long.word 0x4 0.--11. 1. "EWIT,Watchdog counter window value"
tree.end
sif (cpuis("STM32U073*")||cpuis("STM32U083*"))
tree "LCDC (LCD Controller)"
base ad:0x40002400
group.long 0x0++0xB
line.long 0x0 "LCD_CR,LCD control register"
bitfld.long 0x0 8. "BUFEN,Voltage output buffer enable" "0: Output buffer disabled,1: Output buffer enabled"
bitfld.long 0x0 7. "MUX_SEG,Mux segment enable" "0: SEG pin multiplexing disabled,1: SEG[31:28] multiplexed with SEG[43:40]"
newline
bitfld.long 0x0 5.--6. "BIAS,Bias selector" "0: Bias 1/4,1: Bias 1/2,2: Bias 1/3,?"
bitfld.long 0x0 2.--4. "DUTY,Duty selection" "0: Static duty,1: 1/2 duty,2: 1/3 duty,3: 1/4 duty,4: 1/8 duty,?,?,?"
newline
bitfld.long 0x0 1. "VSEL,Voltage source selection" "0: Internal source (voltage stepup converter),1: External source (VLCD pin)"
bitfld.long 0x0 0. "LCDEN,LCD controller enable" "0: LCD controller disabled,1: LCD controller enabled"
line.long 0x4 "LCD_FCR,LCD frame control register"
hexmask.long.byte 0x4 22.--25. 1. "PS,PS 16-bit prescaler"
hexmask.long.byte 0x4 18.--21. 1. "DIV,DIV clock divider"
newline
bitfld.long 0x4 16.--17. "BLINK,Blink mode selection" "0: Blink disabled,1: Blink enabled on SEG[0] COM[0] (1 pixel),2: Blink enabled on SEG[0] all COMs (up to 8 pixels..,3: Blink enabled on all SEGs and all COMs (all.."
bitfld.long 0x4 13.--15. "BLINKF,Blink frequency selection" "0: f<sub>LCD</sub>/8,1: f<sub>LCD</sub>/16,2: f<sub>LCD</sub>/32,3: f<sub>LCD</sub>/64,4: f<sub>LCD</sub>/128,5: f<sub>LCD</sub>/256,6: f<sub>LCD</sub>/512,7: f<sub>LCD</sub>/1024"
newline
bitfld.long 0x4 10.--12. "CC,Contrast control" "0: V<sub>LCD0</sub>,1: V<sub>LCD1</sub>,2: V<sub>LCD2</sub>,3: V<sub>LCD3</sub>,4: V<sub>LCD4</sub>,5: V<sub>LCD5</sub>,6: V<sub>LCD6</sub>,7: V<sub>LCD7</sub>"
bitfld.long 0x4 7.--9. "DEAD,Dead time duration" "0: No dead time,1: 1 phase period dead time,2: 2 phase period dead time,?,?,?,?,7: 7 phase period dead time"
newline
bitfld.long 0x4 4.--6. "PON,Pulse ON duration" "0: 0 1s,1: 244 1s,2: 488 1s,3: 782 1s,4: 976 1s,5: 1.22 ms,6: 1.46 ms,7: 1.71 ms"
bitfld.long 0x4 3. "UDDIE,Update display done interrupt enable" "0: LCD update display done interrupt disabled,1: LCD update display done interrupt enabled"
newline
bitfld.long 0x4 1. "SOFIE,Start of frame interrupt enable" "0: LCD start-of-frame interrupt disabled,1: LCD start-of-frame interrupt enabled"
bitfld.long 0x4 0. "HD,High drive enable" "0: Permanent high drive disabled,1: Permanent high drive enabled. When HD = 1.."
line.long 0x8 "LCD_SR,LCD status register"
rbitfld.long 0x8 5. "FCRSF,LCD frame control register synchronization flag" "0: LCD frame control register not yet synchronized,1: LCD frame control register synchronized"
rbitfld.long 0x8 4. "RDY,Ready flag" "0: Not ready,1: Stepup converter enabled and ready to provide.."
newline
rbitfld.long 0x8 3. "UDD,Update display done" "0: No event,1: Update display request done. A UDD interrupt is.."
bitfld.long 0x8 2. "UDR,Update display request" "0: No effect,1: Update display request"
newline
rbitfld.long 0x8 1. "SOF,Start-of-frame flag" "0: No event,1: Start-of-frame event occurred. An LCD SOF.."
rbitfld.long 0x8 0. "ENS,LCD enabled status" "0: LCD controller disabled,1: LCD controller enabled"
wgroup.long 0xC++0x3
line.long 0x0 "LCD_CLR,LCD clear register"
bitfld.long 0x0 3. "UDDC,Update display done clear" "0: No effect,1: Clear UDD flag."
bitfld.long 0x0 1. "SOFC,Start-of-frame flag clear" "0: No effect,1: Clear SOF flag."
group.long 0x14++0x3F
line.long 0x0 "LCD_RAM0,LCD display memory"
hexmask.long 0x0 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x4 "LCD_RAM1,LCD display memory"
hexmask.long.tbyte 0x4 0.--19. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x8 "LCD_RAM2,LCD display memory"
hexmask.long 0x8 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0xC "LCD_RAM3,LCD display memory"
hexmask.long.tbyte 0xC 0.--19. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x10 "LCD_RAM4,LCD display memory"
hexmask.long 0x10 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x14 "LCD_RAM5,LCD display memory"
hexmask.long.tbyte 0x14 0.--19. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x18 "LCD_RAM6,LCD display memory"
hexmask.long 0x18 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x1C "LCD_RAM7,LCD display memory"
hexmask.long.tbyte 0x1C 0.--19. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x20 "LCD_RAM8,LCD display memory"
hexmask.long 0x20 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x24 "LCD_RAM9,LCD display memory"
hexmask.long.word 0x24 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x28 "LCD_RAM10,LCD display memory"
hexmask.long 0x28 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x2C "LCD_RAM11,LCD display memory"
hexmask.long.word 0x2C 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x30 "LCD_RAM12,LCD display memory"
hexmask.long 0x30 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x34 "LCD_RAM13,LCD display memory"
hexmask.long.word 0x34 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x38 "LCD_RAM14,LCD display memory"
hexmask.long 0x38 0.--31. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
line.long 0x3C "LCD_RAM15,LCD display memory"
hexmask.long.word 0x3C 0.--15. 1. "SEGMENT_DATA,Each bit corresponds to one pixel of the LCD display."
tree.end
endif
tree "LPTIM (Low-power Timer)"
base ad:0x0
tree "LPTIM1"
base ad:0x40007C00
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM1_ISR_OUTPUT,LPTIM1 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 21. "CMP4OK,Compare register 4 update OK" "0,1"
newline
bitfld.long 0x0 20. "CMP3OK,Compare register 3 update OK" "0,1"
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
newline
bitfld.long 0x0 11. "CC4IF,Compare 4 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 10. "CC3IF,Compare 3 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
newline
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
newline
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
newline
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
newline
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM1_ISR_INPUT,LPTIM1 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 15. "CC4OF,Capture 4 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 14. "CC3OF,Capture 3 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 11. "CC4IF,Capture 4 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 10. "CC3IF,Capture 3 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
newline
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
newline
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM1_ICR_OUTPUT,LPTIM1 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 21. "CMP4OKCF,Compare register 4 update OK clear flag" "0,1"
newline
bitfld.long 0x0 20. "CMP3OKCF,Compare register 3 update OK clear flag" "0,1"
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
newline
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
newline
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
newline
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
newline
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
newline
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM1_ICR_INPUT,LPTIM1 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 15. "CC4OCF,Capture/compare 4 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 14. "CC3OCF,Capture/compare 3 over-capture clear flag" "0,1"
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
newline
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
newline
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
newline
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
newline
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
group.long 0x8++0x3
line.long 0x0 "LPTIM1_DIER_OUTPUT,LPTIM1 interrupt enable register [alternate]"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
bitfld.long 0x0 21. "CMP4OKIE,Compare register 4 update OK interrupt enable" "0: CMPOK register 4 interrupt disabled,1: CMPOK register 4 interrupt enabled"
newline
bitfld.long 0x0 20. "CMP3OKIE,Compare register 3 update OK interrupt enable" "0: CMPOK register 3 interrupt disabled,1: CMPOK register 3 interrupt enabled"
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
newline
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
newline
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
newline
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
newline
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
newline
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
group.long 0x8++0x13
line.long 0x0 "LPTIM1_DIER_INPUT,LPTIM1 interrupt enable register [alternate]"
bitfld.long 0x0 27. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled. Writing '0' to the..,1: CC4 DMA request enabled"
bitfld.long 0x0 26. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled. Writing '0' to the..,1: CC3 DMA request enabled"
newline
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
newline
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
bitfld.long 0x0 15. "CC4OIE,Capture/compare 4 over-capture interrupt enable" "0: CC4 over-capture interrupt disabled,1: CC4 over-capture interrupt enabled"
newline
bitfld.long 0x0 14. "CC3OIE,Capture/compare 3 over-capture interrupt enable" "0: CC3 over-capture interrupt disabled,1: CC3 over-capture interrupt enabled"
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
newline
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
newline
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
newline
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
newline
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
newline
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
line.long 0x4 "LPTIM1_CFGR,LPTIM configuration register"
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
newline
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode"
newline
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
newline
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: LPTIM1_ext_trig0,1: LPTIM1_ext_trig1,2: LPTIM1_ext_trig2,3: LPTIM input and trigger mapping for details,4: LPTIM1_ext_trig4,5: LPTIM1_ext_trig5,6: LPTIM1_ext_trig6,7: LPTIM1_ext_trig7"
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
newline
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
newline
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
line.long 0x8 "LPTIM1_CR,LPTIM control register"
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
newline
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
newline
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled"
line.long 0xC "LPTIM1_CCR1,LPTIM compare register 1"
hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value"
line.long 0x10 "LPTIM1_ARR,LPTIM autoreload register"
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
rgroup.long 0x1C++0x3
line.long 0x0 "LPTIM1_CNT,LPTIM counter register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.long 0x24++0x1B
line.long 0x0 "LPTIM1_CFGR2,LPTIM configuration register 2"
bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: LPTIM1_ic2_mux0,1: LPTIM1_ic2_mux1,2: LPTIM1_ic2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: LPTIM1_ic1_mux0,1: LPTIM1_ic1_mux1,2: LPTIM1_ic1_mux2,3: LPTIM input and trigger mapping"
newline
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: LPTIM1_in2_mux0,1: LPTIM1_in2_mux1,2: LPTIM1_in2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: LPTIM1_in1_mux0,1: LPTIM1_in1_mux1,2: LPTIM1_in1_mux2,3: LPTIM input and trigger mapping"
line.long 0x4 "LPTIM1_RCR,LPTIM repetition register"
hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value"
line.long 0x8 "LPTIM1_CCMR1,LPTIM capture/compare mode register 1"
bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0,1,2,3"
bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0,1"
newline
bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode"
bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0,1,2,3"
newline
bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0,1"
bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode"
line.long 0xC "LPTIM1_CCMR2,LPTIM capture/compare mode register 2"
bitfld.long 0xC 28.--29. "IC4F,Input capture 4 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0xC 24.--25. "IC4PSC,Input capture 4 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0xC 18.--19. "CC4P,Capture/compare 4 output polarity." "0: rising edge circuit is sensitive to IC4 rising..,1: falling edge circuit is sensitive to IC4 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC4.."
bitfld.long 0xC 17. "CC4E,Capture/compare 4 output enable." "0: Capture disabled. Writing '0' to the CC4E bit..,1: Capture enabled."
newline
bitfld.long 0xC 16. "CC4SEL,Capture/compare 4 selection" "0: CC4 channel is configured in output PWM mode,1: CC4 channel is configured in input capture mode"
bitfld.long 0xC 12.--13. "IC3F,Input capture 3 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0xC 8.--9. "IC3PSC,Input capture 3 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0xC 2.--3. "CC3P,Capture/compare 3 output polarity." "0: rising edge circuit is sensitive to IC3 rising..,1: falling edge circuit is sensitive to IC3 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC3.."
newline
bitfld.long 0xC 1. "CC3E,Capture/compare 3 output enable." "0: Capture disabled. Writing '0' to the CC3E bit..,1: Capture enabled."
bitfld.long 0xC 0. "CC3SEL,Capture/compare 3 selection" "0: CC3 channel is configured in output PWM mode,1: CC3 channel is configured in input capture mode"
line.long 0x10 "LPTIM1_CCR2,LPTIM compare register 2"
hexmask.long.word 0x10 0.--15. 1. "CCR2,Capture/compare 2 value"
line.long 0x14 "LPTIM1_CCR3,LPTIM compare register 3"
hexmask.long.word 0x14 0.--15. 1. "CCR3,Capture/compare 3 value"
line.long 0x18 "LPTIM1_CCR4,LPTIM compare register 4"
hexmask.long.word 0x18 0.--15. 1. "CCR4,Capture/compare 4 value"
tree.end
sif (cpuis("STM32U073*"))
tree "LPTIM3"
base ad:0x40009000
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 21. "CMP4OK,Compare register 4 update OK" "0,1"
newline
bitfld.long 0x0 20. "CMP3OK,Compare register 3 update OK" "0,1"
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
newline
bitfld.long 0x0 11. "CC4IF,Compare 4 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 10. "CC3IF,Compare 3 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
newline
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
newline
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
newline
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
newline
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 15. "CC4OF,Capture 4 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 14. "CC3OF,Capture 3 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 11. "CC4IF,Capture 4 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 10. "CC3IF,Capture 3 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
newline
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
newline
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 21. "CMP4OKCF,Compare register 4 update OK clear flag" "0,1"
newline
bitfld.long 0x0 20. "CMP3OKCF,Compare register 3 update OK clear flag" "0,1"
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
newline
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
newline
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
newline
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
newline
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
newline
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 15. "CC4OCF,Capture/compare 4 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 14. "CC3OCF,Capture/compare 3 over-capture clear flag" "0,1"
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
newline
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
newline
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
newline
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
newline
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
group.long 0x8++0x3
line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
bitfld.long 0x0 21. "CMP4OKIE,Compare register 4 update OK interrupt enable" "0: CMPOK register 4 interrupt disabled,1: CMPOK register 4 interrupt enabled"
newline
bitfld.long 0x0 20. "CMP3OKIE,Compare register 3 update OK interrupt enable" "0: CMPOK register 3 interrupt disabled,1: CMPOK register 3 interrupt enabled"
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
newline
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
newline
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
newline
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
newline
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
newline
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
group.long 0x8++0x13
line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]"
bitfld.long 0x0 27. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled. Writing '0' to the..,1: CC4 DMA request enabled"
bitfld.long 0x0 26. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled. Writing '0' to the..,1: CC3 DMA request enabled"
newline
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
newline
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
bitfld.long 0x0 15. "CC4OIE,Capture/compare 4 over-capture interrupt enable" "0: CC4 over-capture interrupt disabled,1: CC4 over-capture interrupt enabled"
newline
bitfld.long 0x0 14. "CC3OIE,Capture/compare 3 over-capture interrupt enable" "0: CC3 over-capture interrupt disabled,1: CC3 over-capture interrupt enabled"
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
newline
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
newline
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
newline
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
newline
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
newline
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
line.long 0x4 "LPTIM3_CFGR,LPTIM configuration register"
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
newline
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode"
newline
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
newline
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: LPTIM3_ext_trig0,1: LPTIM3_ext_trig1,2: LPTIM3_ext_trig2,3: LPTIM input and trigger mapping for details,4: LPTIM3_ext_trig4,5: LPTIM3_ext_trig5,6: LPTIM3_ext_trig6,7: LPTIM3_ext_trig7"
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
newline
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
newline
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
line.long 0x8 "LPTIM3_CR,LPTIM control register"
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
newline
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
newline
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled"
line.long 0xC "LPTIM3_CCR1,LPTIM compare register 1"
hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value"
line.long 0x10 "LPTIM3_ARR,LPTIM autoreload register"
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
rgroup.long 0x1C++0x3
line.long 0x0 "LPTIM3_CNT,LPTIM counter register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.long 0x24++0x1B
line.long 0x0 "LPTIM3_CFGR2,LPTIM configuration register 2"
bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: LPTIM3_ic2_mux0,1: LPTIM3_ic2_mux1,2: LPTIM3_ic2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: LPTIM3_ic1_mux0,1: LPTIM3_ic1_mux1,2: LPTIM3_ic1_mux2,3: LPTIM input and trigger mapping"
newline
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: LPTIM3_in2_mux0,1: LPTIM3_in2_mux1,2: LPTIM3_in2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: LPTIM3_in1_mux0,1: LPTIM3_in1_mux1,2: LPTIM3_in1_mux2,3: LPTIM input and trigger mapping"
line.long 0x4 "LPTIM3_RCR,LPTIM repetition register"
hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value"
line.long 0x8 "LPTIM3_CCMR1,LPTIM capture/compare mode register 1"
bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0,1,2,3"
bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0,1"
newline
bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode"
bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0,1,2,3"
newline
bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0,1"
bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode"
line.long 0xC "LPTIM3_CCMR2,LPTIM capture/compare mode register 2"
bitfld.long 0xC 28.--29. "IC4F,Input capture 4 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0xC 24.--25. "IC4PSC,Input capture 4 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0xC 18.--19. "CC4P,Capture/compare 4 output polarity." "0: rising edge circuit is sensitive to IC4 rising..,1: falling edge circuit is sensitive to IC4 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC4.."
bitfld.long 0xC 17. "CC4E,Capture/compare 4 output enable." "0: Capture disabled. Writing '0' to the CC4E bit..,1: Capture enabled."
newline
bitfld.long 0xC 16. "CC4SEL,Capture/compare 4 selection" "0: CC4 channel is configured in output PWM mode,1: CC4 channel is configured in input capture mode"
bitfld.long 0xC 12.--13. "IC3F,Input capture 3 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0xC 8.--9. "IC3PSC,Input capture 3 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0xC 2.--3. "CC3P,Capture/compare 3 output polarity." "0: rising edge circuit is sensitive to IC3 rising..,1: falling edge circuit is sensitive to IC3 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC3.."
newline
bitfld.long 0xC 1. "CC3E,Capture/compare 3 output enable." "0: Capture disabled. Writing '0' to the CC3E bit..,1: Capture enabled."
bitfld.long 0xC 0. "CC3SEL,Capture/compare 3 selection" "0: CC3 channel is configured in output PWM mode,1: CC3 channel is configured in input capture mode"
line.long 0x10 "LPTIM3_CCR2,LPTIM compare register 2"
hexmask.long.word 0x10 0.--15. 1. "CCR2,Capture/compare 2 value"
line.long 0x14 "LPTIM3_CCR3,LPTIM compare register 3"
hexmask.long.word 0x14 0.--15. 1. "CCR3,Capture/compare 3 value"
line.long 0x18 "LPTIM3_CCR4,LPTIM compare register 4"
hexmask.long.word 0x18 0.--15. 1. "CCR4,Capture/compare 4 value"
tree.end
endif
sif (cpuis("STM32U083*"))
tree "LPTIM3"
base ad:0x40009000
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM3_ISR_OUTPUT,LPTIM3 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 21. "CMP4OK,Compare register 4 update OK" "0,1"
newline
bitfld.long 0x0 20. "CMP3OK,Compare register 3 update OK" "0,1"
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
newline
bitfld.long 0x0 11. "CC4IF,Compare 4 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 10. "CC3IF,Compare 3 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
newline
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
newline
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
newline
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
newline
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM3_ISR_INPUT,LPTIM3 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 15. "CC4OF,Capture 4 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 14. "CC3OF,Capture 3 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 11. "CC4IF,Capture 4 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 10. "CC3IF,Capture 3 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
newline
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
newline
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM3_ICR_OUTPUT,LPTIM3 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 21. "CMP4OKCF,Compare register 4 update OK clear flag" "0,1"
newline
bitfld.long 0x0 20. "CMP3OKCF,Compare register 3 update OK clear flag" "0,1"
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
newline
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
newline
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
newline
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
newline
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
newline
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM3_ICR_INPUT,LPTIM3 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 15. "CC4OCF,Capture/compare 4 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 14. "CC3OCF,Capture/compare 3 over-capture clear flag" "0,1"
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
newline
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
newline
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
newline
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
newline
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
group.long 0x8++0x3
line.long 0x0 "LPTIM3_DIER_OUTPUT,LPTIM3 interrupt enable register [alternate]"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
bitfld.long 0x0 21. "CMP4OKIE,Compare register 4 update OK interrupt enable" "0: CMPOK register 4 interrupt disabled,1: CMPOK register 4 interrupt enabled"
newline
bitfld.long 0x0 20. "CMP3OKIE,Compare register 3 update OK interrupt enable" "0: CMPOK register 3 interrupt disabled,1: CMPOK register 3 interrupt enabled"
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
newline
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
newline
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
newline
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
newline
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
newline
bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
group.long 0x8++0x13
line.long 0x0 "LPTIM3_DIER_INPUT,LPTIM3 interrupt enable register [alternate]"
bitfld.long 0x0 27. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled. Writing '0' to the..,1: CC4 DMA request enabled"
bitfld.long 0x0 26. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled. Writing '0' to the..,1: CC3 DMA request enabled"
newline
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
newline
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
bitfld.long 0x0 15. "CC4OIE,Capture/compare 4 over-capture interrupt enable" "0: CC4 over-capture interrupt disabled,1: CC4 over-capture interrupt enabled"
newline
bitfld.long 0x0 14. "CC3OIE,Capture/compare 3 over-capture interrupt enable" "0: CC3 over-capture interrupt disabled,1: CC3 over-capture interrupt enabled"
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
newline
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
newline
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
newline
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
newline
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
newline
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
line.long 0x4 "LPTIM3_CFGR,LPTIM configuration register"
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
newline
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode"
newline
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
newline
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: LPTIM3_ext_trig0,1: LPTIM3_ext_trig1,2: LPTIM3_ext_trig2,3: LPTIM input and trigger mapping for details,4: LPTIM3_ext_trig4,5: LPTIM3_ext_trig5,6: LPTIM3_ext_trig6,7: LPTIM3_ext_trig7"
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
newline
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
newline
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
line.long 0x8 "LPTIM3_CR,LPTIM control register"
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
newline
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
newline
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled"
line.long 0xC "LPTIM3_CCR1,LPTIM compare register 1"
hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value"
line.long 0x10 "LPTIM3_ARR,LPTIM autoreload register"
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
rgroup.long 0x1C++0x3
line.long 0x0 "LPTIM3_CNT,LPTIM counter register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.long 0x24++0x1B
line.long 0x0 "LPTIM3_CFGR2,LPTIM configuration register 2"
bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: LPTIM3_ic2_mux0,1: LPTIM3_ic2_mux1,2: LPTIM3_ic2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: LPTIM3_ic1_mux0,1: LPTIM3_ic1_mux1,2: LPTIM3_ic1_mux2,3: LPTIM input and trigger mapping"
newline
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: LPTIM3_in2_mux0,1: LPTIM3_in2_mux1,2: LPTIM3_in2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: LPTIM3_in1_mux0,1: LPTIM3_in1_mux1,2: LPTIM3_in1_mux2,3: LPTIM input and trigger mapping"
line.long 0x4 "LPTIM3_RCR,LPTIM repetition register"
hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value"
line.long 0x8 "LPTIM3_CCMR1,LPTIM capture/compare mode register 1"
bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0,1,2,3"
bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0,1"
newline
bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode"
bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0,1,2,3"
newline
bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0,1"
bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode"
line.long 0xC "LPTIM3_CCMR2,LPTIM capture/compare mode register 2"
bitfld.long 0xC 28.--29. "IC4F,Input capture 4 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0xC 24.--25. "IC4PSC,Input capture 4 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0xC 18.--19. "CC4P,Capture/compare 4 output polarity." "0: rising edge circuit is sensitive to IC4 rising..,1: falling edge circuit is sensitive to IC4 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC4.."
bitfld.long 0xC 17. "CC4E,Capture/compare 4 output enable." "0: Capture disabled. Writing '0' to the CC4E bit..,1: Capture enabled."
newline
bitfld.long 0xC 16. "CC4SEL,Capture/compare 4 selection" "0: CC4 channel is configured in output PWM mode,1: CC4 channel is configured in input capture mode"
bitfld.long 0xC 12.--13. "IC3F,Input capture 3 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0xC 8.--9. "IC3PSC,Input capture 3 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0xC 2.--3. "CC3P,Capture/compare 3 output polarity." "0: rising edge circuit is sensitive to IC3 rising..,1: falling edge circuit is sensitive to IC3 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC3.."
newline
bitfld.long 0xC 1. "CC3E,Capture/compare 3 output enable." "0: Capture disabled. Writing '0' to the CC3E bit..,1: Capture enabled."
bitfld.long 0xC 0. "CC3SEL,Capture/compare 3 selection" "0: CC3 channel is configured in output PWM mode,1: CC3 channel is configured in input capture mode"
line.long 0x10 "LPTIM3_CCR2,LPTIM compare register 2"
hexmask.long.word 0x10 0.--15. 1. "CCR2,Capture/compare 2 value"
line.long 0x14 "LPTIM3_CCR3,LPTIM compare register 3"
hexmask.long.word 0x14 0.--15. 1. "CCR3,Capture/compare 3 value"
line.long 0x18 "LPTIM3_CCR4,LPTIM compare register 4"
hexmask.long.word 0x18 0.--15. 1. "CCR4,Capture/compare 4 value"
tree.end
endif
tree "LPTIM2"
base ad:0x40009400
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM2_ISR_OUTPUT,LPTIM2 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 21. "CMP4OK,Compare register 4 update OK" "0,1"
newline
bitfld.long 0x0 20. "CMP3OK,Compare register 3 update OK" "0,1"
bitfld.long 0x0 19. "CMP2OK,Compare register 2 update OK" "0,1"
newline
bitfld.long 0x0 11. "CC4IF,Compare 4 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 10. "CC3IF,Compare 3 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
newline
bitfld.long 0x0 9. "CC2IF,Compare 2 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
newline
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
newline
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
newline
bitfld.long 0x0 3. "CMP1OK,Compare register 1 update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,Compare 1 interrupt flag" "0: No match,1: The content of the counter LPTIM_CNT register.."
rgroup.long 0x0++0x3
line.long 0x0 "LPTIM2_ISR_INPUT,LPTIM2 interrupt and status register [alternate]"
bitfld.long 0x0 24. "DIEROK,Interrupt enable register update OK" "0,1"
bitfld.long 0x0 15. "CC4OF,Capture 4 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 14. "CC3OF,Capture 3 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 13. "CC2OF,Capture 2 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
newline
bitfld.long 0x0 12. "CC1OF,Capture 1 over-capture flag" "0: No over-capture has been detected.,1: The counter value has been captured in.."
bitfld.long 0x0 11. "CC4IF,Capture 4 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 10. "CC3IF,Capture 3 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
bitfld.long 0x0 9. "CC2IF,Capture 2 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
newline
bitfld.long 0x0 8. "REPOK,Repetition register update OK" "0,1"
bitfld.long 0x0 7. "UE,LPTIM update event occurred" "0,1"
newline
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
newline
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
newline
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
bitfld.long 0x0 0. "CC1IF,capture 1 interrupt flag" "0: No input capture occurred,1: The counter value has been captured in the.."
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM2_ICR_OUTPUT,LPTIM2 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 21. "CMP4OKCF,Compare register 4 update OK clear flag" "0,1"
newline
bitfld.long 0x0 20. "CMP3OKCF,Compare register 3 update OK clear flag" "0,1"
bitfld.long 0x0 19. "CMP2OKCF,Compare register 2 update OK clear flag" "0,1"
newline
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
newline
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
newline
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
newline
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
newline
bitfld.long 0x0 3. "CMP1OKCF,Compare register 1 update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
newline
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
wgroup.long 0x4++0x3
line.long 0x0 "LPTIM2_ICR_INPUT,LPTIM2 interrupt clear register [alternate]"
bitfld.long 0x0 24. "DIEROKCF,Interrupt enable register update OK clear flag" "0,1"
bitfld.long 0x0 15. "CC4OCF,Capture/compare 4 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 14. "CC3OCF,Capture/compare 3 over-capture clear flag" "0,1"
bitfld.long 0x0 13. "CC2OCF,Capture/compare 2 over-capture clear flag" "0,1"
newline
bitfld.long 0x0 12. "CC1OCF,Capture/compare 1 over-capture clear flag" "0,1"
bitfld.long 0x0 11. "CC4CF,Capture/compare 4 clear flag" "0,1"
newline
bitfld.long 0x0 10. "CC3CF,Capture/compare 3 clear flag" "0,1"
bitfld.long 0x0 9. "CC2CF,Capture/compare 2 clear flag" "0,1"
newline
bitfld.long 0x0 8. "REPOKCF,Repetition register update OK clear flag" "0,1"
bitfld.long 0x0 7. "UECF,Update event clear flag" "0,1"
newline
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
newline
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
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bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
bitfld.long 0x0 0. "CC1CF,Capture/compare 1 clear flag" "0,1"
group.long 0x8++0x3
line.long 0x0 "LPTIM2_DIER_OUTPUT,LPTIM2 interrupt enable register [alternate]"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
bitfld.long 0x0 21. "CMP4OKIE,Compare register 4 update OK interrupt enable" "0: CMPOK register 4 interrupt disabled,1: CMPOK register 4 interrupt enabled"
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bitfld.long 0x0 20. "CMP3OKIE,Compare register 3 update OK interrupt enable" "0: CMPOK register 3 interrupt disabled,1: CMPOK register 3 interrupt enabled"
bitfld.long 0x0 19. "CMP2OKIE,Compare register 2 update OK interrupt enable" "0: CMPOK register 2 interrupt disabled,1: CMPOK register 2 interrupt enabled"
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bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
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bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
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bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
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bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
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bitfld.long 0x0 3. "CMP1OKIE,Compare register 1 update OK interrupt enable" "0: CMPOK register 1 interrupt disabled,1: CMPOK register 1 interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
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bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
group.long 0x8++0x13
line.long 0x0 "LPTIM2_DIER_INPUT,LPTIM2 interrupt enable register [alternate]"
bitfld.long 0x0 27. "CC4DE,Capture/compare 4 DMA request enable" "0: CC4 DMA request disabled. Writing '0' to the..,1: CC4 DMA request enabled"
bitfld.long 0x0 26. "CC3DE,Capture/compare 3 DMA request enable" "0: CC3 DMA request disabled. Writing '0' to the..,1: CC3 DMA request enabled"
newline
bitfld.long 0x0 25. "CC2DE,Capture/compare 2 DMA request enable" "0: CC2 DMA request disabled. Writing '0' to the..,1: CC2 DMA request enabled"
bitfld.long 0x0 23. "UEDE,Update event DMA request enable" "0: UE DMA request disabled. Writing '0' to the UEDE..,1: UE DMA request enabled"
newline
bitfld.long 0x0 16. "CC1DE,Capture/compare 1 DMA request enable" "0: CC1 DMA request disabled. Writing '0' to the..,1: CC1 DMA request enabled"
bitfld.long 0x0 15. "CC4OIE,Capture/compare 4 over-capture interrupt enable" "0: CC4 over-capture interrupt disabled,1: CC4 over-capture interrupt enabled"
newline
bitfld.long 0x0 14. "CC3OIE,Capture/compare 3 over-capture interrupt enable" "0: CC3 over-capture interrupt disabled,1: CC3 over-capture interrupt enabled"
bitfld.long 0x0 13. "CC2OIE,Capture/compare 2 over-capture interrupt enable" "0: CC2 over-capture interrupt disabled,1: CC2 over-capture interrupt enabled"
newline
bitfld.long 0x0 12. "CC1OIE,Capture/compare 1 over-capture interrupt enable" "0: CC1 over-capture interrupt disabled,1: CC1 over-capture interrupt enabled"
bitfld.long 0x0 11. "CC4IE,Capture/compare 4 interrupt enable" "0: Capture/compare 4 interrupt disabled,1: Capture/compare 4 interrupt enabled"
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bitfld.long 0x0 10. "CC3IE,Capture/compare 3 interrupt enable" "0: Capture/compare 3 interrupt disabled,1: Capture/compare 3 interrupt enabled"
bitfld.long 0x0 9. "CC2IE,Capture/compare 2 interrupt enable" "0: Capture/compare 2 interrupt disabled,1: Capture/compare 2 interrupt enabled"
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bitfld.long 0x0 8. "REPOKIE,Repetition register update OK interrupt Enable" "0: Repetition register update OK interrupt disabled,1: Repetition register update OK interrupt enabled"
bitfld.long 0x0 7. "UEIE,Update event interrupt enable" "0: Update event interrupt disabled,1: Update event interrupt enabled"
newline
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
newline
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
newline
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
bitfld.long 0x0 0. "CC1IE,Capture/compare 1 interrupt enable" "0: Capture/compare 1 interrupt disabled,1: Capture/compare 1 interrupt enabled"
line.long 0x4 "LPTIM2_CFGR,LPTIM configuration register"
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
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bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode,1: Activate the Set-once mode"
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bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
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bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: LPTIM2_ext_trig0,1: LPTIM2_ext_trig1,2: LPTIM2_ext_trig2,3: LPTIM input and trigger mapping for details,4: LPTIM2_ext_trig4,5: LPTIM2_ext_trig5,6: LPTIM2_ext_trig6,7: LPTIM2_ext_trig7"
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
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bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
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bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
line.long 0x8 "LPTIM2_CR,LPTIM control register"
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
newline
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
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bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled. Writing '0' to the ENABLE bit..,1: LPTIM is enabled"
line.long 0xC "LPTIM2_CCR1,LPTIM compare register 1"
hexmask.long.word 0xC 0.--15. 1. "CCR1,Capture/compare 1 value"
line.long 0x10 "LPTIM2_ARR,LPTIM autoreload register"
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
rgroup.long 0x1C++0x3
line.long 0x0 "LPTIM2_CNT,LPTIM counter register"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.long 0x24++0x1B
line.long 0x0 "LPTIM2_CFGR2,LPTIM configuration register 2"
bitfld.long 0x0 20.--21. "IC2SEL,LPTIM input capture 2 selection" "0: LPTIM2_ic2_mux0,1: LPTIM2_ic2_mux1,2: LPTIM2_ic2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 16.--17. "IC1SEL,LPTIM input capture 1 selection" "0: LPTIM2_ic1_mux0,1: LPTIM2_ic1_mux1,2: LPTIM2_ic1_mux2,3: LPTIM input and trigger mapping"
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bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: LPTIM2_in2_mux0,1: LPTIM2_in2_mux1,2: LPTIM2_in2_mux2,3: LPTIM input and trigger mapping"
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: LPTIM2_in1_mux0,1: LPTIM2_in1_mux1,2: LPTIM2_in1_mux2,3: LPTIM input and trigger mapping"
line.long 0x4 "LPTIM2_RCR,LPTIM repetition register"
hexmask.long.byte 0x4 0.--7. 1. "REP,Repetition register value"
line.long 0x8 "LPTIM2_CCMR1,LPTIM capture/compare mode register 1"
bitfld.long 0x8 28.--29. "IC2F,Input capture 2 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0x8 24.--25. "IC2PSC,Input capture 2 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x8 18.--19. "CC2P,Capture/compare 2 output polarity." "0,1,2,3"
bitfld.long 0x8 17. "CC2E,Capture/compare 2 output enable." "0,1"
newline
bitfld.long 0x8 16. "CC2SEL,Capture/compare 2 selection" "0: CC2 channel is configured in output PWM mode,1: CC2 channel is configured in input capture mode"
bitfld.long 0x8 12.--13. "IC1F,Input capture 1 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0x8 8.--9. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x8 2.--3. "CC1P,Capture/compare 1 output polarity." "0,1,2,3"
newline
bitfld.long 0x8 1. "CC1E,Capture/compare 1 output enable." "0,1"
bitfld.long 0x8 0. "CC1SEL,Capture/compare 1 selection" "0: CC1 channel is configured in output PWM mode,1: CC1 channel is configured in input capture mode"
line.long 0xC "LPTIM2_CCMR2,LPTIM capture/compare mode register 2"
bitfld.long 0xC 28.--29. "IC4F,Input capture 4 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
bitfld.long 0xC 24.--25. "IC4PSC,Input capture 4 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
newline
bitfld.long 0xC 18.--19. "CC4P,Capture/compare 4 output polarity." "0: rising edge circuit is sensitive to IC4 rising..,1: falling edge circuit is sensitive to IC4 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC4.."
bitfld.long 0xC 17. "CC4E,Capture/compare 4 output enable." "0: Capture disabled. Writing '0' to the CC4E bit..,1: Capture enabled."
newline
bitfld.long 0xC 16. "CC4SEL,Capture/compare 4 selection" "0: CC4 channel is configured in output PWM mode,1: CC4 channel is configured in input capture mode"
bitfld.long 0xC 12.--13. "IC3F,Input capture 3 filter" "0: any external input capture signal level change..,1: external input capture signal level change must..,2: external input capture signal level change must..,3: external input capture signal level change must.."
newline
bitfld.long 0xC 8.--9. "IC3PSC,Input capture 3 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0xC 2.--3. "CC3P,Capture/compare 3 output polarity." "0: rising edge circuit is sensitive to IC3 rising..,1: falling edge circuit is sensitive to IC3 falling..,2: reserved do not use this configuration.,3: both edges circuit is sensitive to both IC3.."
newline
bitfld.long 0xC 1. "CC3E,Capture/compare 3 output enable." "0: Capture disabled. Writing '0' to the CC3E bit..,1: Capture enabled."
bitfld.long 0xC 0. "CC3SEL,Capture/compare 3 selection" "0: CC3 channel is configured in output PWM mode,1: CC3 channel is configured in input capture mode"
line.long 0x10 "LPTIM2_CCR2,LPTIM compare register 2"
hexmask.long.word 0x10 0.--15. 1. "CCR2,Capture/compare 2 value"
line.long 0x14 "LPTIM2_CCR3,LPTIM compare register 3"
hexmask.long.word 0x14 0.--15. 1. "CCR3,Capture/compare 3 value"
line.long 0x18 "LPTIM2_CCR4,LPTIM compare register 4"
hexmask.long.word 0x18 0.--15. 1. "CCR4,Capture/compare 4 value"
tree.end
tree.end
tree "LPUART (Low-power Universal Asynchronous Receiver Transmitter)"
base ad:0x0
tree "LPUART1"
base ad:0x40008000
group.long 0x0++0x3
line.long 0x0 "LPUART_CR1,LPUART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
group.long 0x0++0xF
line.long 0x0 "LPUART_CR1_ALTERNATE,LPUART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
line.long 0x4 "LPUART_CR2,LPUART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
newline
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
newline
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
newline
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,1: Reserved.,2: 2 stop bits,?"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
line.long 0x8 "LPUART_CR3,LPUART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
newline
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.."
line.long 0xC "LPUART_BRR,LPUART baud rate register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)"
wgroup.long 0x18++0x3
line.long 0x0 "LPUART_RQR,LPUART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR,LPUART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full."
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty."
newline
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR_ALTERNATE,LPUART interrupt and status register"
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "LPUART_RDR,LPUART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
tree "LPUART2"
base ad:0x40008400
group.long 0x0++0x3
line.long 0x0 "LPUART_CR1,LPUART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
group.long 0x0++0xF
line.long 0x0 "LPUART_CR1_ALTERNATE,LPUART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
line.long 0x4 "LPUART_CR2,LPUART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
newline
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
newline
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
newline
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,1: Reserved.,2: 2 stop bits,?"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
line.long 0x8 "LPUART_CR3,LPUART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
newline
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.."
line.long 0xC "LPUART_BRR,LPUART baud rate register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)"
wgroup.long 0x18++0x3
line.long 0x0 "LPUART_RQR,LPUART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR,LPUART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full."
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty."
newline
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR_ALTERNATE,LPUART interrupt and status register"
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "LPUART_RDR,LPUART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
sif (cpuis("STM32U073*"))
tree "LPUART3"
base ad:0x40008C00
group.long 0x0++0x3
line.long 0x0 "LPUART_CR1,LPUART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
group.long 0x0++0xF
line.long 0x0 "LPUART_CR1_ALTERNATE,LPUART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
line.long 0x4 "LPUART_CR2,LPUART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
newline
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
newline
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
newline
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,1: Reserved.,2: 2 stop bits,?"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
line.long 0x8 "LPUART_CR3,LPUART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
newline
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.."
line.long 0xC "LPUART_BRR,LPUART baud rate register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)"
wgroup.long 0x18++0x3
line.long 0x0 "LPUART_RQR,LPUART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR,LPUART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full."
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty."
newline
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR_ALTERNATE,LPUART interrupt and status register"
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "LPUART_RDR,LPUART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
endif
sif (cpuis("STM32U083*"))
tree "LPUART3"
base ad:0x40008C00
group.long 0x0++0x3
line.long 0x0 "LPUART_CR1,LPUART control register 1"
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF=1 in.."
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE=1 in.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXFNF.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
group.long 0x0++0xF
line.long 0x0 "LPUART_CR1_ALTERNATE,LPUART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
newline
bitfld.long 0x0 12. "M0,Word length" "0,1"
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
newline
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
newline
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE=1.."
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever TXE =1.."
newline
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC=1.."
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE=1.."
newline
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE=1.."
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
newline
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
bitfld.long 0x0 1. "UESM,LPUART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
newline
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
line.long 0x4 "LPUART_CR2,LPUART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
newline
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
newline
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
newline
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,1: Reserved.,2: 2 stop bits,?"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
line.long 0x8 "LPUART_CR3,LPUART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
newline
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
newline
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
newline
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
newline
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE=1 or ORE=1 or.."
line.long 0xC "LPUART_BRR,LPUART baud rate register"
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate division (LPUARTDIV)"
wgroup.long 0x18++0x3
line.long 0x0 "LPUART_RQR,LPUART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR,LPUART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO is not Full.,1: RXFIFO is Full."
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO is not empty.,1: TXFIFO is empty."
newline
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "LPUART_ISR_ALTERNATE,LPUART interrupt and status register"
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
newline
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
newline
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
newline
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
newline
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
newline
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
newline
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "LPUART_RDR,LPUART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
endif
tree.end
tree "OPAMP (Operational Amplifiers)"
base ad:0x40007800
group.long 0x0++0xB
line.long 0x0 "OPAMP_CSR,OPAMP control/status register"
bitfld.long 0x0 31. "OPA_RANGE,Operational amplifier power supply range for stability" "0: Low range (VDDA < 2.4V),1: High range (VDDA > 2.4V)"
rbitfld.long 0x0 15. "CALOUT,Operational amplifier calibration output" "0,1"
newline
bitfld.long 0x0 14. "USERTRIM,allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values" "0: factory trim code used,1: user trim code used"
bitfld.long 0x0 13. "CALSEL,Calibration selection" "0: NMOS calibration (200mV applied on OPAMP inputs),1: PMOS calibration (VDDA-200mV applied on OPAMP.."
newline
bitfld.long 0x0 12. "CALON,Calibration mode enabled" "0: Normal mode,1: Calibration mode (all switches opened by HW)"
bitfld.long 0x0 10. "VP_SEL,Non inverted input selection" "0: GPIO connected to VINP,1: DAC connected to VINP"
newline
bitfld.long 0x0 8.--9. "VM_SEL,Inverting input selection" "0: GPIO connected to VINM (valid also in PGA mode..,?,?,?"
bitfld.long 0x0 4.--5. "PGA_GAIN,Operational amplifier Programmable amplifier gain value" "0: internal PGA Gain 2,1: internal PGA Gain 4,2: internal PGA Gain 8,3: internal PGA Gain 16"
newline
bitfld.long 0x0 2.--3. "OPAMODE,Operational amplifier PGA mode" "0: internal PGA disable,1: internal PGA disable,2: internal PGA enable gain programmed in PGA_GAIN,3: internal follower"
bitfld.long 0x0 1. "OPALPM,Operational amplifier Low Power Mode" "0: operational amplifier in normal mode,1: operational amplifier in low-power mode"
newline
bitfld.long 0x0 0. "OPAEN,Operational amplifier Enable" "0: operational amplifier disabled,1: operational amplifier enabled"
line.long 0x4 "OPAMP_OTR,OPAMP offset trimming register in normal mode"
hexmask.long.byte 0x4 8.--12. 1. "TRIMOFFSETP,Trim for PMOS differential pairs"
hexmask.long.byte 0x4 0.--4. 1. "TRIMOFFSETN,Trim for NMOS differential pairs"
line.long 0x8 "OPAMP_LPOTR,OPAMP offset trimming register in low-power mode"
hexmask.long.byte 0x8 8.--12. 1. "TRIMLPOFFSETP,Low-power mode trim for PMOS differential pairs"
hexmask.long.byte 0x8 0.--4. 1. "TRIMLPOFFSETN,Low-power mode trim for NMOS differential pairs"
tree.end
tree "PWR (Power Control)"
base ad:0x40007000
group.long 0x0++0xF
line.long 0x0 "PWR_CR1,Power control register 1"
bitfld.long 0x0 14. "LPR,Low-power run" "0,1"
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range selection" "0: Cannot be written (forbidden by hardware),1: Range 1,2: Range 2,3: Cannot be written (forbidden by hardware)"
newline
bitfld.long 0x0 8. "DBP,Disable backup domain write protection" "0: Access to RTC and Backup registers disabled,1: Access to RTC and Backup registers enabled"
bitfld.long 0x0 5. "FPD_LPSLP,Flash memory powered down during Low-power sleep mode." "0: Flash memory idle,1: Flash memory powered down"
newline
bitfld.long 0x0 4. "FPD_LPRUN,Flash memory powered down during Low-power run mode." "0: Flash memory idle,1: Flash memory powered down"
bitfld.long 0x0 3. "FPD_STOP,Flash memory powered down during Stop mode." "0: Flash memory idle,1: Flash memory powered down"
newline
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0: Stop 0 mode,1: Stop 1 mode,2: Stop 2 mode,3: Standby mode,?,?,?,?"
line.long 0x4 "PWR_CR2,Power control register 2"
bitfld.long 0x4 10. "USV,V<sub>DDUSB</sub> USB supply valid" "0: V<sub>DDUSB</sub> is not present. Logical and..,1: V<sub>DDUSB</sub> is valid."
bitfld.long 0x4 6. "PVME4,Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. 1.861V" "0: PVM4 (V<sub>DDA</sub> monitoring vs. 1.861V..,1: PVM4 (V<sub>DDA</sub> monitoring vs. 1.86 V.."
newline
bitfld.long 0x4 5. "PVME3,Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. 1.621V" "0: PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V..,1: PVM3 (V<sub>DDA</sub> monitoring vs. 1.621V.."
bitfld.long 0x4 4. "PVME1,Peripheral voltage monitoring 1 enable: V<sub>DDUSB</sub> vs. 1.21V" "0: PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V..,1: PVM1 (V<sub>DDUSB</sub> monitoring vs. 1.21V.."
newline
bitfld.long 0x4 1.--3. "PLS,Programmable voltage detector level selection." "0: V<sub>PVD0</sub> around 2.01V,1: V<sub>PVD1</sub> around 2.21V,2: V<sub>PVD2</sub> around 2.41V,3: V<sub>PVD3</sub> around 2.51V,4: V<sub>PVD4</sub> around 2.61V,5: V<sub>PVD5</sub> around 2.81V,6: V<sub>PVD6</sub> around 2.91V,7: External input analog voltage PVD_IN (compared.."
bitfld.long 0x4 0. "PVDE,Programmable voltage detector enable" "0: Programmable voltage detector disable.,1: Programmable voltage detector enable."
line.long 0x8 "PWR_CR3,Power control register 3"
bitfld.long 0x8 15. "EIWUL,Enable internal wake-up line" "0: Internal wake-up line disable.,1: Internal wake-up line enable."
bitfld.long 0x8 10. "APC,Apply pull-up and pull-down configuration" "0,1"
newline
bitfld.long 0x8 9. "ENULP,Enable ULP sampling" "0,1"
bitfld.long 0x8 8. "RRS,SRAM2 retention in Standby mode" "0: SRAM2 is powered off in Standby mode (SRAM2..,1: SRAM2 is powered by the low-power regulator in.."
newline
bitfld.long 0x8 6. "EWUP7,Enable Wake-up pin WKUP7." "0,1"
bitfld.long 0x8 4. "EWUP5,Enable Wake-up pin WKUP5" "0,1"
newline
bitfld.long 0x8 3. "EWUP4,Enable Wake-up pin WKUP4" "0,1"
bitfld.long 0x8 2. "EWUP3,Enable Wake-up pin WKUP3" "0,1"
newline
bitfld.long 0x8 1. "EWUP2,Enable Wake-up pin WKUP2" "0,1"
bitfld.long 0x8 0. "EWUP1,Enable Wake-up pin WKUP1" "0,1"
line.long 0xC "PWR_CR4,Power control register 4"
bitfld.long 0xC 9. "VBRS,V<sub>BAT</sub> battery charging resistor selection" "0: Charge V<sub>BAT</sub> through a 5 kOhms resistor,1: Charge V<sub>BAT</sub> through a 1.5 kOhms.."
bitfld.long 0xC 8. "VBE,V<sub>BAT</sub> battery charging enable" "0: V<sub>BAT</sub> battery charging disable,1: V<sub>BAT</sub> battery charging enable"
newline
bitfld.long 0xC 6. "WP7,Wake-up pin WKUP7 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 4. "WP5,Wake-up pin WKUP5 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 3. "WP4,Wake-up pin WKUP4 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 2. "WP3,Wake-up pin WKUP3 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
newline
bitfld.long 0xC 1. "WP2,Wake-up pin WKUP2 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
bitfld.long 0xC 0. "WP1,Wake-up pin WKUP1 polarity" "0: Detection on high level (rising edge),1: Detection on low level (falling edge)"
rgroup.long 0x10++0x7
line.long 0x0 "PWR_SR1,Power status register 1"
bitfld.long 0x0 15. "WUFI,Wake-up flag internal" "0,1"
bitfld.long 0x0 9.--11. "STOPF,Stop Flags" "0: The device did not enter any Stop mode.,?,?,?,4: The device entered in Stop 0 mode.,5: The device entered in Stop 1 mode.,6: The device entered in Stop 2 mode.,?"
newline
bitfld.long 0x0 8. "SBF,Standby flag" "0: The device did not enter the Standby mode,1: The device entered the Standby mode"
bitfld.long 0x0 6. "WUF7,Wake-up flag 7" "0,1"
newline
bitfld.long 0x0 4. "WUF5,Wake-up flag 5" "0,1"
bitfld.long 0x0 3. "WUF4,Wake-up flag 4" "0,1"
newline
bitfld.long 0x0 2. "WUF3,Wake-up flag 3" "0,1"
bitfld.long 0x0 1. "WUF2,Wake-up flag 2" "0,1"
newline
bitfld.long 0x0 0. "WUF1,Wake-up flag 1" "0,1"
line.long 0x4 "PWR_SR2,Power status register 2"
bitfld.long 0x4 15. "PVMO4,Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 2.21V" "0: V<sub>DDA</sub> voltage is above PVM4 threshold..,1: V<sub>DDA</sub> voltage is below PVM4 threshold.."
bitfld.long 0x4 14. "PVMO3,Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.621V" "0: V<sub>DDA</sub> voltage is above PVM3 threshold..,1: V<sub>DDA</sub> voltage is below PVM3 threshold.."
newline
bitfld.long 0x4 12. "PVMO1,Peripheral voltage monitoring output: V<sub>DDUSB</sub> vs. 1.2 V" "0: V<sub>DDUSB</sub> voltage is above PVM1..,1: V<sub>DDUSB</sub> voltage is below PVM1.."
bitfld.long 0x4 11. "PVDO,Programmable voltage detector output" "0: V<sub>DD</sub> is above the selected PVD threshold,1: V<sub>DD</sub> is below the selected PVD threshold"
newline
bitfld.long 0x4 10. "VOSF,Voltage scaling flag" "0: The regulator is ready in the selected voltage..,1: The regulator output voltage is changing to the.."
bitfld.long 0x4 9. "REGLPF,Low-power regulator flag" "0: The regulator is ready in main mode (MR),1: The regulator is in low-power mode (LPR)"
newline
bitfld.long 0x4 8. "REGLPS,Low-power regulator started" "0: The low-power regulator is not ready,1: The low-power regulator is ready"
bitfld.long 0x4 7. "FLASH_RDY,Flash ready flag" "0: Flash memory in power down,1: Flash memory ready to be accessed"
wgroup.long 0x18++0x3
line.long 0x0 "PWR_SCR,Power status clear register"
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
bitfld.long 0x0 6. "CWUF7,Clear wake-up flag 7" "0,1"
newline
bitfld.long 0x0 4. "CWUF5,Clear wake-up flag 5" "0,1"
bitfld.long 0x0 3. "CWUF4,Clear wake-up flag 4" "0,1"
newline
bitfld.long 0x0 2. "CWUF3,Clear wake-up flag 3" "0,1"
bitfld.long 0x0 1. "CWUF2,Clear wake-up flag 2" "0,1"
newline
bitfld.long 0x0 0. "CWUF1,Clear wake-up flag 1" "0,1"
group.long 0x20++0x2F
line.long 0x0 "PWR_PUCRA,Power Port A pull-up control register"
bitfld.long 0x0 15. "PU15,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 14. "PU14,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 13. "PU13,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 12. "PU12,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 11. "PU11,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 10. "PU10,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 9. "PU9,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 8. "PU8,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 7. "PU7,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 6. "PU6,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 5. "PU5,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 4. "PU4,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 3. "PU3,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 2. "PU2,Port A pull-up bit y (y1=115 to 0)" "0,1"
newline
bitfld.long 0x0 1. "PU1,Port A pull-up bit y (y1=115 to 0)" "0,1"
bitfld.long 0x0 0. "PU0,Port A pull-up bit y (y1=115 to 0)" "0,1"
line.long 0x4 "PWR_PDCRA,Power Port A pull-down control register"
bitfld.long 0x4 15. "PD15,Port A pull-down bit y" "0,1"
bitfld.long 0x4 14. "PD14,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 13. "PD13,Port A pull-down bit y" "0,1"
bitfld.long 0x4 12. "PD12,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 11. "PD11,Port A pull-down bit y" "0,1"
bitfld.long 0x4 10. "PD10,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 9. "PD9,Port A pull-down bit y" "0,1"
bitfld.long 0x4 8. "PD8,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 7. "PD7,Port A pull-down bit y" "0,1"
bitfld.long 0x4 6. "PD6,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 5. "PD5,Port A pull-down bit y" "0,1"
bitfld.long 0x4 4. "PD4,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 3. "PD3,Port A pull-down bit y" "0,1"
bitfld.long 0x4 2. "PD2,Port A pull-down bit y" "0,1"
newline
bitfld.long 0x4 1. "PD1,Port A pull-down bit y" "0,1"
bitfld.long 0x4 0. "PD0,Port A pull-down bit y" "0,1"
line.long 0x8 "PWR_PUCRB,Power Port B pull-up control register"
bitfld.long 0x8 15. "PU15,Port B pull-up bit y" "0,1"
bitfld.long 0x8 14. "PU14,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 13. "PU13,Port B pull-up bit y" "0,1"
bitfld.long 0x8 12. "PU12,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 11. "PU11,Port B pull-up bit y" "0,1"
bitfld.long 0x8 10. "PU10,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 9. "PU9,Port B pull-up bit y" "0,1"
bitfld.long 0x8 8. "PU8,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 7. "PU7,Port B pull-up bit y" "0,1"
bitfld.long 0x8 6. "PU6,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 5. "PU5,Port B pull-up bit y" "0,1"
bitfld.long 0x8 4. "PU4,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 3. "PU3,Port B pull-up bit y" "0,1"
bitfld.long 0x8 2. "PU2,Port B pull-up bit y" "0,1"
newline
bitfld.long 0x8 1. "PU1,Port B pull-up bit y" "0,1"
bitfld.long 0x8 0. "PU0,Port B pull-up bit y" "0,1"
line.long 0xC "PWR_PDCRB,Power Port B pull-down control register"
bitfld.long 0xC 15. "PD15,Port B pull-down bit y" "0,1"
bitfld.long 0xC 14. "PD14,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 13. "PD13,Port B pull-down bit y" "0,1"
bitfld.long 0xC 12. "PD12,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 11. "PD11,Port B pull-down bit y" "0,1"
bitfld.long 0xC 10. "PD10,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 9. "PD9,Port B pull-down bit y" "0,1"
bitfld.long 0xC 8. "PD8,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 7. "PD7,Port B pull-down bit y" "0,1"
bitfld.long 0xC 6. "PD6,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 5. "PD5,Port B pull-down bit y" "0,1"
bitfld.long 0xC 4. "PD4,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 3. "PD3,Port B pull-down bit y" "0,1"
bitfld.long 0xC 2. "PD2,Port B pull-down bit y" "0,1"
newline
bitfld.long 0xC 1. "PD1,Port B pull-down bit y" "0,1"
bitfld.long 0xC 0. "PD0,Port B pull-down bit y" "0,1"
line.long 0x10 "PWR_PUCRC,Power Port C pull-up control register"
bitfld.long 0x10 15. "PU15,Port C pull-up bit y" "0,1"
bitfld.long 0x10 14. "PU14,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 13. "PU13,Port C pull-up bit y" "0,1"
bitfld.long 0x10 12. "PU12,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 11. "PU11,Port C pull-up bit y" "0,1"
bitfld.long 0x10 10. "PU10,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 9. "PU9,Port C pull-up bit y" "0,1"
bitfld.long 0x10 8. "PU8,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 7. "PU7,Port C pull-up bit y" "0,1"
bitfld.long 0x10 6. "PU6,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 5. "PU5,Port C pull-up bit y" "0,1"
bitfld.long 0x10 4. "PU4,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 3. "PU3,Port C pull-up bit y" "0,1"
bitfld.long 0x10 2. "PU2,Port C pull-up bit y" "0,1"
newline
bitfld.long 0x10 1. "PU1,Port C pull-up bit y" "0,1"
bitfld.long 0x10 0. "PU0,Port C pull-up bit y" "0,1"
line.long 0x14 "PWR_PDCRC,Power Port C pull-down control register"
bitfld.long 0x14 15. "PD15,Port C pull-down bit y" "0,1"
bitfld.long 0x14 14. "PD14,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 13. "PD13,Port C pull-down bit y" "0,1"
bitfld.long 0x14 12. "PD12,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 11. "PD11,Port C pull-down bit y" "0,1"
bitfld.long 0x14 10. "PD10,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 9. "PD9,Port C pull-down bit y" "0,1"
bitfld.long 0x14 8. "PD8,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 7. "PD7,Port C pull-down bit y" "0,1"
bitfld.long 0x14 6. "PD6,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 5. "PD5,Port C pull-down bit y" "0,1"
bitfld.long 0x14 4. "PD4,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 3. "PD3,Port C pull-down bit y" "0,1"
bitfld.long 0x14 2. "PD2,Port C pull-down bit y" "0,1"
newline
bitfld.long 0x14 1. "PD1,Port C pull-down bit y" "0,1"
bitfld.long 0x14 0. "PD0,Port C pull-down bit y" "0,1"
line.long 0x18 "PWR_PUCRD,Power Port D pull-up control register"
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 9. "PU9,Port D pull-up bit y" "0,1"
bitfld.long 0x18 8. "PU8,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 6. "PU6,Port D pull-up bit y" "0,1"
bitfld.long 0x18 5. "PU5,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 4. "PU4,Port D pull-up bit y" "0,1"
bitfld.long 0x18 3. "PU3,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 2. "PU2,Port D pull-up bit y" "0,1"
bitfld.long 0x18 1. "PU1,Port D pull-up bit y" "0,1"
newline
bitfld.long 0x18 0. "PU0,Port D pull-up bit y" "0,1"
line.long 0x1C "PWR_PDCRD,Power Port D pull-down control register"
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 9. "PD9,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 8. "PD8,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 6. "PD6,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 5. "PD5,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 4. "PD4,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 3. "PD3,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 2. "PD2,Port D pull-down bit y" "0,1"
bitfld.long 0x1C 1. "PD1,Port D pull-down bit y" "0,1"
newline
bitfld.long 0x1C 0. "PD0,Port D pull-down bit y" "0,1"
line.long 0x20 "PWR_PUCRE,Power Port E pull-up control register"
bitfld.long 0x20 9. "PU9,Port E pull-up bit y" "0,1"
bitfld.long 0x20 8. "PU8,Port E pull-up bit y" "0,1"
newline
bitfld.long 0x20 7. "PU7,Port E pull-up bit y" "0,1"
bitfld.long 0x20 3. "PU3,Port E pull-up bit 3" "0,1"
line.long 0x24 "PWR_PDCRE,Power Port E pull-down control register"
bitfld.long 0x24 9. "PD9,Port E pull-down bit y" "0,1"
bitfld.long 0x24 8. "PD8,Port E pull-down bit y" "0,1"
newline
bitfld.long 0x24 7. "PD7,Port E pull-down bit y" "0,1"
bitfld.long 0x24 3. "PD3,Port E pull-down bit 3" "0,1"
line.long 0x28 "PWR_PUCRF,Power Port F pull-up control register"
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
bitfld.long 0x28 2. "PU2,Port F pull-up bit y" "0,1"
newline
bitfld.long 0x28 1. "PU1,Port F pull-up bit y" "0,1"
bitfld.long 0x28 0. "PU0,Port F pull-up bit y" "0,1"
line.long 0x2C "PWR_PDCRF,Power Port F pull-down control register"
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
bitfld.long 0x2C 2. "PD2,Port F pull-down bit y" "0,1"
newline
bitfld.long 0x2C 1. "PD1,Port F pull-down bit y" "0,1"
bitfld.long 0x2C 0. "PD0,Port F pull-down bit y" "0,1"
tree.end
tree "RCC (Reset and Clock Control)"
base ad:0x40021000
group.long 0x0++0xF
line.long 0x0 "RCC_CR,Clock control register"
rbitfld.long 0x0 25. "PLLRDY,PLL clock ready flag" "0: PLL unlocked,1: PLL locked"
bitfld.long 0x0 24. "PLLON,PLL enable" "0: PLL OFF,1: PLL ON"
newline
bitfld.long 0x0 19. "CSSON,Clock security system enable" "0: Clock security system OFF (clock detector OFF),1: Clock security system ON (Clock detector ON if.."
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator bypass" "0: HSE crystal oscillator not bypassed,1: HSE crystal oscillator bypassed with external.."
newline
rbitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0: HSE oscillator not ready,1: HSE oscillator ready"
bitfld.long 0x0 16. "HSEON,HSE clock enable" "0: HSE oscillator OFF,1: HSE oscillator ON"
newline
rbitfld.long 0x0 11. "HSIASFS,HSI16 automatic start from Stop" "0: HSI16 oscillator is not enabled by hardware when..,1: HSI16 oscillator is enabled by hardware when.."
rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0: HSI16 oscillator not ready,1: HSI16 oscillator ready"
newline
bitfld.long 0x0 9. "HSIKERON,HSI16 always enable for peripheral kernels." "0: No effect on HSI16 oscillator.,1: HSI16 oscillator is forced ON even in Stop mode."
bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0: HSI16 oscillator OFF,1: HSI16 oscillator ON"
newline
hexmask.long.byte 0x0 4.--7. 1. "MSIRANGE,MSI clock ranges"
bitfld.long 0x0 3. "MSIRGSEL,MSI clock range selection" "0: MSI Range is provided by MSISRANGE[3:0] in..,1: MSI Range is provided by MSIRANGE[3:0] in the.."
newline
bitfld.long 0x0 2. "MSIPLLEN,MSI clock PLL enable" "0: MSI PLL OFF,1: MSI PLL ON"
rbitfld.long 0x0 1. "MSIRDY,MSI clock ready flag" "0: MSI oscillator not ready,1: MSI oscillator ready"
newline
bitfld.long 0x0 0. "MSION,MSI clock enable" "0: MSI oscillator OFF,1: MSI oscillator ON"
line.long 0x4 "RCC_ICSCR,Internal clock sources calibration register"
hexmask.long.byte 0x4 24.--30. 1. "HSITRIM,HSI16 clock trimming"
hexmask.long.byte 0x4 16.--23. 1. "HSICAL,HSI16 clock calibration"
newline
hexmask.long.byte 0x4 8.--15. 1. "MSITRIM,MSI clock trimming"
hexmask.long.byte 0x4 0.--7. 1. "MSICAL,MSI clock calibration"
line.long 0x8 "RCC_CFGR,Clock configuration register"
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output prescaler"
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock output clock selector"
newline
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,Microcontroller clock output 2 prescaler"
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,Microcontroller clock output 2 clock selector"
newline
bitfld.long 0x8 15. "STOPWUCK,Wake-up from Stop and CSS backup clock selection" "0: MSI oscillator selected as wake-up from stop..,1: HSI16 oscillator selected as wake-up from stop.."
bitfld.long 0x8 12.--14. "PPRE,APB prescaler" "?,?,?,?,4: 2,5: 4,6: 8,7: 16"
newline
hexmask.long.byte 0x8 8.--11. 1. "HPRE,AHB prescaler"
rbitfld.long 0x8 3.--5. "SWS,System clock switch status" "0: MSI,1: HSI16,2: HSE,3: PLLRCLK,4: LSI,5: LSE,?,?"
newline
bitfld.long 0x8 0.--2. "SW,System clock switch" "0: MSI,1: HSI16,2: HSE,3: PLLRCLK,4: LSI,5: LSE,?,?"
line.long 0xC "RCC_PLLCFGR,PLL configuration register"
bitfld.long 0xC 29.--31. "PLLR,PLL VCO division factor R for PLLRCLK clock output" "?,1: 2,2: 3,3: 4,4: 5,5: 6,6: 7,7: 8"
bitfld.long 0xC 28. "PLLREN,PLLRCLK clock output enable" "0: Disable,1: Enable"
newline
bitfld.long 0xC 25.--27. "PLLQ,PLL VCO division factor Q for PLLQCLK clock output" "?,1: 2,2: 3,3: 4,4: 5,5: 6,6: 7,7: 8"
bitfld.long 0xC 24. "PLLQEN,PLLQCLK clock output enable" "0: Disable,1: Enable"
newline
hexmask.long.byte 0xC 17.--21. 1. "PLLP,PLL VCO division factor P for PLLPCLK clock output"
bitfld.long 0xC 16. "PLLPEN,PLLPCLK clock output enable" "0: Disable,1: Enable"
newline
hexmask.long.byte 0xC 8.--14. 1. "PLLN,PLL frequency multiplication factor N"
bitfld.long 0xC 4.--6. "PLLM,Division factor M of the PLL input clock divider" "0: 1,1: 2,2: 3,3: 4,4: 5,5: 6,6: 7,7: 8"
newline
bitfld.long 0xC 0.--1. "PLLSRC,PLL input clock source" "0: No clock,1: MSI,2: HSI16,3: HSE"
group.long 0x18++0x3
line.long 0x0 "RCC_CIER,Clock interrupt enable register"
bitfld.long 0x0 10. "HSI48RDYIE,HSI48 ready interrupt enable" "0: HSI48 ready interrupt disabled,1: HSI48 ready interrupt enabled"
bitfld.long 0x0 9. "LSECSSIE,LSE clock security system interrupt enable" "0: Clock security interrupt caused by LSE clock..,1: Clock security interrupt caused by LSE clock.."
newline
bitfld.long 0x0 5. "PLLRDYIE,PLL ready interrupt enable" "0: Disable,1: Enable"
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 3. "HSIRDYIE,HSI16 ready interrupt enable" "0: Disable,1: Enable"
bitfld.long 0x0 2. "MSIRDYIE,MSI ready interrupt enable" "0: MSI ready interrupt disabled,1: MSI ready interrupt enabled"
newline
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0: Disable,1: Enable"
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0: Disable,1: Enable"
rgroup.long 0x1C++0x3
line.long 0x0 "RCC_CIFR,Clock interrupt flag register"
bitfld.long 0x0 10. "HSI48RDYF,HSI48 ready interrupt flag" "0: No clock ready interrupt caused by the HSI48..,1: Clock ready interrupt caused by the HSI48.."
bitfld.long 0x0 9. "LSECSSF,LSE clock security system interrupt flag" "0: No clock security interrupt caused by LSE clock..,1: Clock security interrupt caused by LSE clock.."
newline
bitfld.long 0x0 8. "CSSF,HSE clock security system interrupt flag" "0: No clock security interrupt caused by HSE clock..,1: Clock security interrupt caused by HSE clock.."
bitfld.long 0x0 5. "PLLRDYF,PLL ready interrupt flag" "0: No clock ready interrupt caused by PLL lock,1: Clock ready interrupt caused by PLL lock"
newline
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0: No clock ready interrupt caused by the HSE..,1: Clock ready interrupt caused by the HSE oscillator"
bitfld.long 0x0 3. "HSIRDYF,HSI16 ready interrupt flag" "0: No clock ready interrupt caused by the HSI16..,1: Clock ready interrupt caused by the HSI16.."
newline
bitfld.long 0x0 2. "MSIRDYF,MSI ready interrupt flag" "0: No clock ready interrupt caused by the MSI..,1: Clock ready interrupt caused by the MSI oscillator"
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0: No clock ready interrupt caused by the LSE..,1: Clock ready interrupt caused by the LSE oscillator"
newline
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0: No clock ready interrupt caused by the LSI..,1: Clock ready interrupt caused by the LSI oscillator"
wgroup.long 0x20++0x3
line.long 0x0 "RCC_CICR,Clock interrupt clear register"
bitfld.long 0x0 10. "HSI48RDYC,HSI48 oscillator ready interrupt clear" "0: No effect,1: Clear the HSI48RDYC flag"
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt clear" "0: No effect,1: Clear LSECSSF flag"
newline
bitfld.long 0x0 8. "CSSC,Clock security system interrupt clear" "0: No effect,1: Clear CSSF flag"
bitfld.long 0x0 5. "PLLRDYC,PLL ready interrupt clear" "0: No effect,1: Clear PLLRDYF flag"
newline
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0: No effect,1: Clear HSERDYF flag"
bitfld.long 0x0 3. "HSIRDYC,HSI16 ready interrupt clear" "0: No effect,1: Clear HSIRDYF flag"
newline
bitfld.long 0x0 2. "MSIRDYC,MSI ready interrupt clear" "0: No effect,1: MSIRDYF cleared"
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0: No effect,1: Clear LSERDYF flag"
newline
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0: No effect,1: Clear LSIRDYF flag"
group.long 0x28++0x7
line.long 0x0 "RCC_AHBRSTR,AHB peripheral reset register"
bitfld.long 0x0 24. "TSCRST,Touch sensing controller reset" "0: No effect,1: Reset TSC"
bitfld.long 0x0 18. "RNGRST,Random number generator reset" "0: No effect,1: Reset RNG"
newline
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "AESRST,AES hardware accelerator reset" "0: No effect,1: Reset AES"
endif
bitfld.long 0x0 12. "CRCRST,CRC reset" "0: No effect,1: Reset CRC"
newline
bitfld.long 0x0 8. "FLASHRST,Flash memory interface reset" "0: No effect,1: Reset flash memory interface"
bitfld.long 0x0 1. "DMA2RST,DMA2 and DMAMUX reset" "0: No effect,1: Reset DMA2 and DMAMUX"
newline
bitfld.long 0x0 0. "DMA1RST,DMA1 and DMAMUX reset" "0: No effect,1: Reset DMA1 and DMAMUX"
line.long 0x4 "RCC_IOPRSTR,I/O port reset register"
bitfld.long 0x4 5. "GPIOFRST,I/O port F reset" "0: no effect,1: Reset I/O port F"
bitfld.long 0x4 4. "GPIOERST,I/O port E reset" "0: no effect,1: Reset I/O port E"
newline
bitfld.long 0x4 3. "GPIODRST,I/O port D reset" "0: no effect,1: Reset I/O port D"
bitfld.long 0x4 2. "GPIOCRST,I/O port C reset" "0: no effect,1: Reset I/O port C"
newline
bitfld.long 0x4 1. "GPIOBRST,I/O port B reset" "0: no effect,1: Reset I/O port B"
bitfld.long 0x4 0. "GPIOARST,I/O port A reset" "0: no effect,1: Reset I/O port A"
group.long 0x38++0x3
line.long 0x0 "RCC_APBRSTR1,APB peripheral reset register 1"
bitfld.long 0x0 31. "LPTIM1RST,Low Power Timer 1 reset" "0: No effect,1: Reset LPTIM1"
bitfld.long 0x0 30. "LPTIM2RST,Low Power Timer 2 reset" "0: No effect,1: Reset LPTIM2"
newline
bitfld.long 0x0 29. "DAC1RST,DAC1 interface reset" "0: No effect,1: Reset DAC1 interface"
bitfld.long 0x0 28. "PWRRST,Power interface reset" "0: No effect,1: Reset PWR"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 26. "LPTIM3RST,LPTIM3 reset" "0: No effect,1: Reset LPTIM3"
bitfld.long 0x0 25. "I2C4RST,I2C4 reset<sup>(1)</sup>" "0: No effect,1: Reset I2C4"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 26. "LPTIM3RST,LPTIM3 reset" "0: No effect,1: Reset LPTIM3"
bitfld.long 0x0 25. "I2C4RST,I2C4 reset<sup>(1)</sup>" "0: No effect,1: Reset I2C4"
newline
endif
bitfld.long 0x0 24. "OPAMPRST,OPAMP reset" "0: No effect,1: Reset the OPAMP"
bitfld.long 0x0 23. "I2C3RST,I2C3 reset" "0: No effect,1: Reset I2C3"
newline
bitfld.long 0x0 22. "I2C2RST,I2C2 reset" "0: No effect,1: Reset I2C2"
bitfld.long 0x0 21. "I2C1RST,I2C1 reset" "0: No effect,1: Reset I2C1"
newline
bitfld.long 0x0 20. "LPUART1RST,LPUART1 reset" "0: No effect,1: Reset LPUART1"
bitfld.long 0x0 19. "USART4RST,USART4 reset" "0: No effect,1: Reset USART4"
newline
bitfld.long 0x0 18. "USART3RST,USART3 reset" "0: No effect,1: Reset USART3"
bitfld.long 0x0 17. "USART2RST,USART2 reset" "0: No effect,1: Reset USART2"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 16. "CRSRST,CRS reset<sup>(1)</sup>" "0: No effect,1: Reset CRS"
bitfld.long 0x0 15. "SPI3RST,SPI3 reset<sup>(1)</sup>" "0: No effect,1: Reset SPI3"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "CRSRST,CRS reset<sup>(1)</sup>" "0: No effect,1: Reset CRS"
bitfld.long 0x0 15. "SPI3RST,SPI3 reset<sup>(1)</sup>" "0: No effect,1: Reset SPI3"
newline
endif
bitfld.long 0x0 14. "SPI2RST,SPI2 reset" "0: No effect,1: Reset SPI2"
bitfld.long 0x0 13. "USBRST,USB reset<sup>(1)</sup>" "0: No effect,1: Reset USB"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 12. "LPUART3RST,LPUART3 reset<sup>(1)</sup>" "0: No effect,1: Reset LPUART3"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 12. "LPUART3RST,LPUART3 reset<sup>(1)</sup>" "0: No effect,1: Reset LPUART3"
newline
endif
bitfld.long 0x0 9. "LCDRST,LCD reset<sup>(1)</sup>" "0: No effect,1: Reset LCD"
bitfld.long 0x0 7. "LPUART2RST,LPUART2 reset" "0: No effect,1: Reset LPUART2"
newline
bitfld.long 0x0 5. "TIM7RST,TIM7 timer reset" "0: No effect,1: Reset TIM7"
bitfld.long 0x0 4. "TIM6RST,TIM6 timer reset" "0: No effect,1: Reset TIM6"
newline
bitfld.long 0x0 1. "TIM3RST,TIM3 timer reset" "0: No effect,1: Reset TIM3"
bitfld.long 0x0 0. "TIM2RST,TIM2 timer reset" "0: No effect,1: Reset TIM2"
group.long 0x40++0x3
line.long 0x0 "RCC_APBRSTR2,APB peripheral reset register 2"
bitfld.long 0x0 20. "ADCRST,ADC reset" "0: No effect,1: Reset ADC"
bitfld.long 0x0 17. "TIM16RST,TIM16 timer reset" "0: No effect,1: Reset TIM16 timer"
newline
bitfld.long 0x0 16. "TIM15RST,TIM15 timer reset" "0: No effect,1: Reset TIM15 timer"
bitfld.long 0x0 14. "USART1RST,USART1 reset" "0: No effect,1: Reset USART1"
newline
bitfld.long 0x0 12. "SPI1RST,SPI1 reset" "0: No effect,1: Reset SPI1"
bitfld.long 0x0 11. "TIM1RST,TIM1 timer reset" "0: No effect,1: Reset TIM1 timer"
newline
bitfld.long 0x0 0. "SYSCFGRST,SYSCFG COMP and VREFBUF reset" "0: No effect,1: Reset SYSCFG + COMP + VREFBUF"
group.long 0x48++0xB
line.long 0x0 "RCC_AHBENR,AHB peripheral clock enable register"
bitfld.long 0x0 24. "TSCEN,Touch sensing controller clock enable" "0: TSC clock disable,1: TSC clock enable"
bitfld.long 0x0 18. "RNGEN,Random number generator clock enable" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "AESEN,AES hardware accelerator" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 12. "CRCEN,CRC clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 8. "FLASHEN,Flash memory interface clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 1. "DMA2EN,DMA2 and DMAMUX clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 0. "DMA1EN,DMA1 and DMAMUX clock enable" "0: Disable,1: Enable"
line.long 0x4 "RCC_IOPENR,I/O port clock enable register"
bitfld.long 0x4 5. "GPIOFEN,I/O port F clock enable" "0: Disable,1: Enable"
bitfld.long 0x4 4. "GPIOEEN,I/O port E clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
bitfld.long 0x4 3. "GPIODEN,I/O port D clock enable" "0: Disable,1: Enable"
bitfld.long 0x4 2. "GPIOCEN,I/O port C clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "GPIOBEN,I/O port B clock enable" "0: Disable,1: Enable"
bitfld.long 0x4 0. "GPIOAEN,I/O port A clock enable" "0: Disable,1: Enable"
line.long 0x8 "RCC_DBGCFGR,Debug configuration register"
bitfld.long 0x8 1. "DBGRST,Debug support reset" "0: No effect,1: Reset DBG"
bitfld.long 0x8 0. "DBGEN,Debug support clock enable" "0: Disable,1: Enable"
group.long 0x58++0x3
line.long 0x0 "RCC_APBENR1,APB peripheral clock enable register 1"
bitfld.long 0x0 31. "LPTIM1EN,LPTIM1 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 30. "LPTIM2EN,LPTIM2 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 29. "DAC1EN,DAC1 interface clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 28. "PWREN,Power interface clock enable" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 26. "LPTIM3EN,LPTIM3 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 25. "I2C4EN,I2C4EN clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 26. "LPTIM3EN,LPTIM3 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 25. "I2C4EN,I2C4EN clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 24. "OPAMPEN,OPAMP clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 23. "I2C3EN,I2C3 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "I2C2EN,I2C2 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 21. "I2C1EN,I2C1 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "LPUART1EN,LPUART1 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 19. "USART4EN,USART4 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "USART3EN,USART3 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 17. "USART2EN,USART2 clock enable" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 16. "CRSEN,CRS clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 15. "SPI3EN,SPI3 clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "CRSEN,CRS clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 15. "SPI3EN,SPI3 clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 14. "SPI2EN,SPI2 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 13. "USBEN,USB clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 12. "LPUART3EN,LPUART3 clock enable" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 12. "LPUART3EN,LPUART3 clock enable" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 11. "WWDGEN,WWDG clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 10. "RTCAPBEN,RTC APB clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "LCDEN,LCD clock enable<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 7. "LPUART2EN,LPUART2 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "TIM7EN,TIM7 timer clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 4. "TIM6EN,TIM6 timer clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "TIM3EN,TIM3 timer clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 0. "TIM2EN,TIM2 timer clock enable" "0: Disable,1: Enable"
group.long 0x60++0x3
line.long 0x0 "RCC_APBENR2,APB peripheral clock enable register 2"
bitfld.long 0x0 20. "ADCEN,ADC clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 17. "TIM16EN,TIM16 timer clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 16. "TIM15EN,TIM15 timer clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 14. "USART1EN,USART1 clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 12. "SPI1EN,SPI1 clock enable" "0: Disable,1: Enable"
bitfld.long 0x0 11. "TIM1EN,TIM1 timer clock enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 0. "SYSCFGEN,SYSCFG COMP and VREFBUF clock enable" "0: Disable,1: Enable"
group.long 0x68++0x7
line.long 0x0 "RCC_AHBSMENR,AHB peripheral clock enable in Sleep/Stop mode register"
bitfld.long 0x0 24. "TSCSMEN,TSC clock enable during Sleep and Stop mode" "0: Disable,1: Enable"
bitfld.long 0x0 18. "RNGSMEN,RNG clock enable during Sleep and Stop mode" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "AESSMEN,AES hardware accelerator clock enable during Sleep mode" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 12. "CRCSMEN,CRC clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "SRAMSMEN,SRAM clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 8. "FLASHSMEN,Flash memory interface clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "DMA2SMEN,DMA2 and DMAMUX clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 0. "DMA1SMEN,DMA1 and DMAMUX clock enable during Sleep mode" "0: Disable,1: Enable"
line.long 0x4 "RCC_IOPSMENR,I/O port in Sleep mode clock enable register"
bitfld.long 0x4 5. "GPIOFSMEN,I/O port F clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x4 4. "GPIOESMEN,I/O port E clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x4 3. "GPIODSMEN,I/O port D clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x4 2. "GPIOCSMEN,I/O port C clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x4 1. "GPIOBSMEN,I/O port B clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x4 0. "GPIOASMEN,I/O port A clock enable during Sleep mode" "0: Disable,1: Enable"
group.long 0x78++0x3
line.long 0x0 "RCC_APBSMENR1,APB peripheral clock enable in Sleep/Stop mode register 1"
bitfld.long 0x0 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
bitfld.long 0x0 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
bitfld.long 0x0 29. "DAC1SMEN,DAC1 interface clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
bitfld.long 0x0 28. "PWRSMEN,Power interface clock enable during Sleep mode" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 26. "LPTIM3SMEN,Low power timer 3 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 25. "I2C4SMEN,I2C4 clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 26. "LPTIM3SMEN,Low power timer 3 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 25. "I2C4SMEN,I2C4 clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 24. "OPAMPSMEN,OPAMP clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
bitfld.long 0x0 23. "I2C3SMEN,I2C3 clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "I2C2SMEN,I2C2 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 21. "I2C1SMEN,I2C1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
bitfld.long 0x0 20. "LPUART1SMEN,LPUART1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
bitfld.long 0x0 19. "USART4SMEN,USART4 clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "USART3SMEN,USART3 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 17. "USART2SMEN,USART2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 15. "SPI3SMEN,SPI3 clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 16. "CRSSMEN,CRS clock enable during Sleep and Stop modes<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 15. "SPI3SMEN,SPI3 clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 14. "SPI2SMEN,SPI2 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 13. "USBSMEN,USB clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 12. "LPUART3SMEN,LPUART3 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 12. "LPUART3SMEN,LPUART3 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
endif
bitfld.long 0x0 11. "WWDGSMEN,WWDG clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
bitfld.long 0x0 10. "RTCAPBSMEN,RTC APB clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 9. "LCDSMEN,LCD clock enable during Sleep mode<sup>(1)</sup>" "0: Disable,1: Enable"
bitfld.long 0x0 7. "LPUART2SMEN,LPUART2 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
bitfld.long 0x0 5. "TIM7SMEN,TIM7 timer clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 4. "TIM6SMEN,TIM6 timer clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 1. "TIM3SMEN,TIM3 timer clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 0. "TIM2SMEN,TIM2 timer clock enable during Sleep mode" "0: Disable,1: Enable"
group.long 0x80++0x3
line.long 0x0 "RCC_APBSMENR2,APB peripheral clock enable in Sleep/Stop mode register 2"
bitfld.long 0x0 20. "ADCSMEN,ADC clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 17. "TIM16SMEN,TIM16 timer clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 16. "TIM15SMEN,TIM15 timer clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 14. "USART1SMEN,USART1 clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
newline
bitfld.long 0x0 12. "SPI1SMEN,SPI1 clock enable during Sleep mode" "0: Disable,1: Enable"
bitfld.long 0x0 11. "TIM1SMEN,TIM1 timer clock enable during Sleep mode" "0: Disable,1: Enable"
newline
bitfld.long 0x0 0. "SYSCFGSMEN,SYSCFG COMP and VREFBUF clock enable during Sleep and Stop modes" "0: Disable,1: Enable"
group.long 0x88++0x3
line.long 0x0 "RCC_CCIPR,Peripherals independent clock configuration register"
bitfld.long 0x0 28.--29. "ADCSEL,ADCs clock source selection" "0: System clock,1: PLLPCLK,2: HSI16,?"
bitfld.long 0x0 26.--27. "CLK48SEL,481MHz clock source selection" "0: No clock,1: MSI,2: PLLQCLK,3: HSI48<sup>(1)</sup>"
newline
bitfld.long 0x0 25. "TIM15SEL,TIM15 clock source selection" "0: TIMPCLK,1: PLLQCLK"
bitfld.long 0x0 24. "TIM1SEL,TIM1 clock source selection" "0: TIMPCLK,1: PLLQCLK"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 22.--23. "LPTIM3SEL,LPTIM3 clock source selection" "0: PCLK,1: LSI,2: HSI16,3: LSE"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 22.--23. "LPTIM3SEL,LPTIM3 clock source selection" "0: PCLK,1: LSI,2: HSI16,3: LSE"
newline
endif
bitfld.long 0x0 20.--21. "LPTIM2SEL,LPTIM2 clock source selection" "0: PCLK,1: LSI,2: HSI16,3: LSE"
bitfld.long 0x0 18.--19. "LPTIM1SEL,LPTIM1 clock source selection" "0: PCLK,1: LSI,2: HSI16,3: LSE"
newline
bitfld.long 0x0 16.--17. "I2C3SEL,I2C3 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,?"
bitfld.long 0x0 12.--13. "I2C1SEL,I2C1 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,?"
newline
bitfld.long 0x0 10.--11. "LPUART1SEL,LPUART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
bitfld.long 0x0 8.--9. "LPUART2SEL,LPUART2 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
newline
sif (cpuis("STM32U073*"))
bitfld.long 0x0 6.--7. "LPUART3SEL,LPUART3 clock source selection<sup>(1)</sup>" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x0 6.--7. "LPUART3SEL,LPUART3 clock source selection<sup>(1)</sup>" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
newline
endif
bitfld.long 0x0 2.--3. "USART2SEL,USART2 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
bitfld.long 0x0 0.--1. "USART1SEL,USART1 clock source selection" "0: PCLK,1: SYSCLK,2: HSI16,3: LSE"
group.long 0x90++0xB
line.long 0x0 "RCC_BDCR,RTC domain control register"
bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output selection" "0: LSI,1: LSE"
bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO) enable" "0: Disable,1: Enable"
newline
bitfld.long 0x0 16. "BDRST,RTC domain software reset" "0: No effect,1: Reset"
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0: Disable,1: Enable"
newline
rbitfld.long 0x0 11. "LSESYSRDY,LSE clock ready for system usage" "0: LSE clock not ready for system,1: LSE clock ready for system"
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0: No clock,1: LSE,2: LSI,3: HSE divided by 32"
newline
bitfld.long 0x0 7. "LSESYSEN,LSE clock enable for system usage" "0: Disabled,1: Enabled LSE distributed to peripherals including.."
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure Detection" "0: No failure detected,1: Failure detected"
newline
bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0: Disable,1: Enable"
bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive capability" "0: low driving capability,1: medium-low driving capability,2: medium-high driving capability,3: high driving capability"
newline
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0: Not bypassed,1: Bypassed"
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0: Not ready,1: Ready"
newline
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0: Disable,1: Enable"
line.long 0x4 "RCC_CSR,Control/status register"
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0: No illegal mode reset occurred,1: Illegal mode reset occurred"
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0: No window watchdog reset occurred,1: Window watchdog reset occurred"
newline
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset flag" "0: No independent watchdog reset occurred,1: Independent watchdog reset occurred"
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0: No software reset occurred,1: Software reset occurred"
newline
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0: No BOR or POR occurred,1: BOR or POR occurred"
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0: No reset from NRST pin occurred,1: Reset from NRST pin occurred"
newline
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset flag" "0: No reset from Option byte loading occurred,1: Reset from Option byte loading occurred"
bitfld.long 0x4 23. "RMVF,Remove reset flags" "0: No effect,1: Clear reset flags"
newline
hexmask.long.byte 0x4 8.--11. 1. "MSISRANGE,MSI range after Standby mode"
bitfld.long 0x4 2. "LSIPREDIV,Internal low-speed oscillator pre-divided by 128" "0: LSI RC oscillator is not divided,1: LSI RC oscillator is divided by 128"
newline
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0: Not ready,1: Ready"
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0: Disable,1: Enable"
line.long 0x8 "RCC_CRRCR,RCC clock recovery RC register"
hexmask.long.word 0x8 7.--15. 1. "HSI48CAL,HSI48 clock calibration"
rbitfld.long 0x8 1. "HSI48RDY,HSI48 clock ready flag<sup>(1)</sup>" "0,1"
newline
bitfld.long 0x8 0. "HSI48ON,HSI48 RC oscillator enable<sup>(1)</sup>" "0: Disable,1: Enable"
tree.end
tree "RNG (Random Number Generator)"
base ad:0x40025000
group.long 0x0++0x7
line.long 0x0 "RNG_CR,RNG control register"
bitfld.long 0x0 31. "CONFIGLOCK,RNG Config lock" "0: Writes to the RNG_HTCR and RNG_CR configuration..,1: Writes to the RNG_HTCR and RNG_CR configuration.."
bitfld.long 0x0 30. "CONDRST,Conditioning soft reset" "0,1"
newline
hexmask.long.byte 0x0 20.--25. 1. "RNG_CONFIG1,RNG configuration 1"
hexmask.long.byte 0x0 16.--19. 1. "CLKDIV,Clock divider factor"
newline
bitfld.long 0x0 13.--15. "RNG_CONFIG2,RNG configuration 2" "?,?,?,?,?,?,?,?"
bitfld.long 0x0 12. "NISTC,NIST custom" "0: Hardware default values for NIST compliant RNG.,1: Custom values for NIST compliant RNG. See.."
newline
hexmask.long.byte 0x0 8.--11. 1. "RNG_CONFIG3,RNG configuration 3"
bitfld.long 0x0 7. "ARDIS,Auto reset disable" "0: When a noise source error occurs RNG performs an..,1: When a noise source error occurs the application.."
newline
bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection enabled,1: Clock error detection is disabled"
bitfld.long 0x0 3. "IE,Interrupt enable" "0: RNG interrupt is disabled,1: RNG interrupt is enabled. An interrupt is.."
newline
bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled."
line.long 0x4 "RNG_SR,RNG status register"
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence is detected. See.."
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (f<sub>RNGCLK</sub>>..,1: The RNG clock before the internal divider is.."
newline
rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequences.."
rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (f<sub>RNGCLK</sub>>..,1: The RNG clock is too slow (f<sub>RNGCLK</sub><.."
newline
rbitfld.long 0x4 0. "DRDY,Data ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data."
rgroup.long 0x8++0x3
line.long 0x0 "RNG_DR,RNG data register"
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
group.long 0x10++0x3
line.long 0x0 "RNG_HTCR,RNG health test control register"
hexmask.long 0x0 0.--31. 1. "HTCFG,health test configuration"
tree.end
tree "RTC (Real-Time Clock)"
base ad:0x40002800
group.long 0x0++0x7
line.long 0x0 "RTC_TR,RTC time register"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
line.long 0x4 "RTC_DR,RTC date register"
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
newline
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
rgroup.long 0x8++0x3
line.long 0x0 "RTC_SSR,RTC subsecond register"
hexmask.long 0x0 0.--31. 1. "SS,Synchronous binary counter"
group.long 0xC++0xF
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
bitfld.long 0x0 10.--12. "BCDU,BCD update (BIN = 10 or 11)" "0: 1s calendar increment is generated each time..,1: 1s calendar increment is generated each time..,2: 1s calendar increment is generated each time..,3: 1s calendar increment is generated each time..,4: 1s calendar increment is generated each time..,5: 1s calendar increment is generated each time..,6: 1s calendar increment is generated each time..,7: 1s calendar increment is generated each time.."
newline
bitfld.long 0x0 8.--9. "BIN,Binary mode" "0: Free running BCD calendar mode (Binary mode..,1: Free running Binary mode (BCD mode disabled),2: Free running BCD calendar and Binary modes,3: Free running BCD calendar and Binary modes"
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
newline
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
newline
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
newline
rbitfld.long 0x0 2. "WUTWF,Wake-up timer write flag" "0: Wake-up timer configuration update not allowed..,1: Wake-up timer configuration update allowed"
line.long 0x4 "RTC_PRER,RTC prescaler register"
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
line.long 0x8 "RTC_WUTR,RTC wake-up timer register"
hexmask.long.word 0x8 16.--31. 1. "WUTOCLR,Wake-up auto-reload output clear value"
hexmask.long.word 0x8 0.--15. 1. "WUT,Wake-up auto-reload value bits"
line.long 0xC "RTC_CR,RTC control register"
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0,1"
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
newline
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
bitfld.long 0xC 28. "ALRBFCLR,Alarm B flag automatic clear" "0: Alarm B event generates a trigger event and..,1: Alarm B event generates a trigger event. ALRBF.."
newline
bitfld.long 0xC 27. "ALRAFCLR,Alarm A flag automatic clear" "0: Alarm A event generates a trigger event and..,1: Alarm A event generates a trigger event. ALRAF.."
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
newline
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
newline
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wake-up output enabled"
newline
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 5121Hz,1: Calibration output is 11Hz"
newline
bitfld.long 0xC 18. "BKP,Backup" "0,1"
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
newline
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
newline
bitfld.long 0xC 14. "WUTIE,Wake-up timer interrupt enable" "0: Wake-up timer interrupt disabled,1: Wake-up timer interrupt enabled"
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
newline
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
newline
bitfld.long 0xC 10. "WUTE,Wake-up timer enable" "0: Wake-up timer disabled,1: Wake-up timer enabled"
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
newline
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
bitfld.long 0xC 7. "SSRUIE,SSR underflow interrupt enable" "0: SSR underflow interrupt disabled,1: SSR underflow interrupt enabled"
newline
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
newline
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 601Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
newline
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wake-up clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
wgroup.long 0x24++0x3
line.long 0x0 "RTC_WPR,RTC write protection register"
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
group.long 0x28++0x3
line.long 0x0 "RTC_CALR,RTC calibration register"
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.51ppm." "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
newline
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
bitfld.long 0x0 12. "LPCAL,RTC low-power mode" "0: Calibration window is 2<sup>20</sup> RTCCLK..,1: Calibration window is 2<sup>20</sup> ck_apre.."
newline
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
wgroup.long 0x2C++0x3
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
rgroup.long 0x30++0xB
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
line.long 0x8 "RTC_TSSSR,RTC timestamp subsecond register"
hexmask.long 0x8 0.--31. 1. "SS,Subsecond value/synchronous binary counter values"
group.long 0x40++0xF
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day dont care in alarm A comparison"
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is dont.."
newline
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
newline
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours dont care in alarm A comparison"
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
newline
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
newline
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes dont care in alarm A comparison"
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds dont care in alarm A comparison"
newline
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
line.long 0x4 "RTC_ALRMASSR,RTC alarm A subsecond register"
bitfld.long 0x4 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.."
hexmask.long.byte 0x4 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit"
newline
hexmask.long.word 0x4 0.--14. 1. "SS,Subseconds value"
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day dont care in alarm B comparison"
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is dont.."
newline
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
newline
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours dont care in alarm B comparison"
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
newline
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
newline
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes dont care in alarm B comparison"
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds dont care in alarm B comparison"
newline
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
line.long 0xC "RTC_ALRMBSSR,RTC alarm B subsecond register"
bitfld.long 0xC 31. "SSCLR,Clear synchronous counter on alarm (Binary mode only)" "0: The synchronous binary counter (SS[31:0] in..,1: The synchronous binary counter (SS[31:0] in.."
hexmask.long.byte 0xC 24.--29. 1. "MASKSS,Mask the most-significant bits starting at this bit"
newline
hexmask.long.word 0xC 0.--14. 1. "SS,Subseconds value"
rgroup.long 0x50++0x7
line.long 0x0 "RTC_SR,RTC status register"
bitfld.long 0x0 6. "SSRUF,SSR underflow flag" "0,1"
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
newline
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
newline
bitfld.long 0x0 2. "WUTF,Wake-up timer flag" "0,1"
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
newline
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
bitfld.long 0x4 6. "SSRUMF,SSR underflow masked flag" "0,1"
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
newline
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
newline
bitfld.long 0x4 2. "WUTMF,Wake-up timer masked flag" "0,1"
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
newline
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
wgroup.long 0x5C++0x3
line.long 0x0 "RTC_SCR,RTC status clear register"
bitfld.long 0x0 6. "CSSRUF,Clear SSR underflow flag" "0,1"
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
newline
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
newline
bitfld.long 0x0 2. "CWUTF,Clear wake-up timer flag" "0,1"
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
newline
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
group.long 0x70++0x7
line.long 0x0 "RTC_ALRABINR,RTC alarm A binary mode register"
hexmask.long 0x0 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode"
line.long 0x4 "RTC_ALRBBINR,RTC alarm B binary mode register"
hexmask.long 0x4 0.--31. 1. "SS,Synchronous counter alarm value in Binary mode"
tree.end
tree "SPI (Serial Peripheral Interface)"
base ad:0x0
sif (cpuis("STM32U073*"))
tree "SPI3"
base ad:0x40003C00
group.word 0x0++0x1
line.word 0x0 "SPI_CR1,SPI control register 1"
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
newline
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
newline
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
newline
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
group.word 0x4++0x1
line.word 0x0 "SPI_CR2,SPI control register 2"
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
newline
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
newline
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
group.word 0x8++0x1
line.word 0x0 "SPI_SR,SPI status register"
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
newline
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI not busy,1: SPI is busy in communication or Tx buffer is not.."
newline
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
newline
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
group.word 0xC++0x1
line.word 0x0 "SPI_DR,SPI data register"
hexmask.word 0x0 0.--15. 1. "DR,Data register"
group.word 0x10++0x1
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.word 0x14++0x1
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
rgroup.word 0x18++0x1
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
tree.end
endif
sif (cpuis("STM32U083*"))
tree "SPI3"
base ad:0x40003C00
group.word 0x0++0x1
line.word 0x0 "SPI_CR1,SPI control register 1"
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
newline
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
newline
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
newline
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
group.word 0x4++0x1
line.word 0x0 "SPI_CR2,SPI control register 2"
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
newline
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
newline
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
group.word 0x8++0x1
line.word 0x0 "SPI_SR,SPI status register"
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
newline
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI not busy,1: SPI is busy in communication or Tx buffer is not.."
newline
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
newline
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
group.word 0xC++0x1
line.word 0x0 "SPI_DR,SPI data register"
hexmask.word 0x0 0.--15. 1. "DR,Data register"
group.word 0x10++0x1
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.word 0x14++0x1
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
rgroup.word 0x18++0x1
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
tree.end
endif
tree "SPI1"
base ad:0x40013000
group.word 0x0++0x1
line.word 0x0 "SPI_CR1,SPI control register 1"
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
newline
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
newline
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
newline
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
group.word 0x4++0x1
line.word 0x0 "SPI_CR2,SPI control register 2"
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
newline
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
newline
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
group.word 0x8++0x1
line.word 0x0 "SPI_SR,SPI status register"
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
newline
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI not busy,1: SPI is busy in communication or Tx buffer is not.."
newline
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
newline
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
group.word 0xC++0x1
line.word 0x0 "SPI_DR,SPI data register"
hexmask.word 0x0 0.--15. 1. "DR,Data register"
group.word 0x10++0x1
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.word 0x14++0x1
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
rgroup.word 0x18++0x1
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
tree.end
tree "SPI2"
base ad:0x40003800
group.word 0x0++0x1
line.word 0x0 "SPI_CR1,SPI control register 1"
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
newline
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
newline
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
newline
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
newline
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
newline
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: f<sub>PCLK</sub>/2,1: f<sub>PCLK</sub>/4,2: f<sub>PCLK</sub>/8,3: f<sub>PCLK</sub>/16,4: f<sub>PCLK</sub>/32,5: f<sub>PCLK</sub>/64,6: f<sub>PCLK</sub>/128,7: f<sub>PCLK</sub>/256"
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
newline
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
group.word 0x4++0x1
line.word 0x0 "SPI_CR2,SPI control register 2"
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
newline
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
newline
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
newline
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
newline
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
newline
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
group.word 0x8++0x1
line.word 0x0 "SPI_SR,SPI status register"
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
newline
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI not busy,1: SPI is busy in communication or Tx buffer is not.."
newline
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
newline
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
newline
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
group.word 0xC++0x1
line.word 0x0 "SPI_DR,SPI data register"
hexmask.word 0x0 0.--15. 1. "DR,Data register"
group.word 0x10++0x1
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
rgroup.word 0x14++0x1
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
rgroup.word 0x18++0x1
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
tree.end
tree.end
tree "SYSCFG (System Configuration Controller)"
base ad:0x40010000
group.long 0x0++0x3
line.long 0x0 "SYSCFG_CFGR1,SYSCFG configuration register 1"
bitfld.long 0x0 24. "I2C3_FMP,Fast Mode Plus (FM+) enable for I2C3" "0: Disable,1: Enable"
bitfld.long 0x0 23. "I2C_PA10_FMP,Fast Mode Plus (FM+) enable for PA10" "0: Disable,1: Enable"
newline
bitfld.long 0x0 22. "I2C_PA9_FMP,Fast Mode Plus (FM+) enable for PA9" "0: Disable,1: Enable"
bitfld.long 0x0 19. "I2C_PB9_FMP,Fast Mode Plus (FM+) enable for PB9" "0: Disable,1: Enable"
newline
bitfld.long 0x0 18. "I2C_PB8_FMP,Fast Mode Plus (FM+) enable for PB8" "0: Disable,1: Enable"
bitfld.long 0x0 17. "I2C_PB7_FMP,Fast Mode Plus (FM+) enable for PB7" "0: Disable,1: Enable"
newline
bitfld.long 0x0 16. "I2C_PB6_FMP,Fast Mode Plus (FM+) enable for PB6" "0: Disable,1: Enable"
bitfld.long 0x0 8. "BOOSTEN,I/O analog switch voltage booster enable" "0: V<sub>DD</sub>,1: Dedicated voltage booster (supplied by.."
newline
bitfld.long 0x0 6.--7. "IR_MOD,IR Modulation Envelope signal selection" "0: TIM16,1: USART1,2: USART2,?"
bitfld.long 0x0 5. "IR_POL,IR output polarity selection" "0: Output of IRTIM (IR_OUT) is not inverted,1: Output of IRTIM (IR_OUT) is inverted"
newline
bitfld.long 0x0 4. "PA12_RMP,PA12 pin remapping" "0: No remap (PA12),1: Remap (PA10)"
bitfld.long 0x0 3. "PA11_RMP,PA11 pin remapping" "0: No remap (PA11),1: Remap (PA9)"
newline
bitfld.long 0x0 0.--1. "MEM_MODE,Memory mapping selection bits" "?,1: System flash memory mapped at 0x000010000,?,3: Embedded SRAM mapped at 0x000010000"
group.long 0x18++0x7
line.long 0x0 "SYSCFG_CFGR2,SYSCFG configuration register 2"
bitfld.long 0x0 8. "SPF,SRAM1 parity error flag" "0: No SRAM1 parity error detected,1: SRAM1 parity error detected"
bitfld.long 0x0 7. "BKPF,Backup SRAM2 parity error flag" "0: No SRAM2 parity error detected,1: SRAM2 parity error detected"
newline
bitfld.long 0x0 4. "BKPL,Backup SRAM2 parity lock" "0: SRAM2 parity error disconnected from TIM1/15/16..,1: SRAM2 parity error connected to TIM1/15/16 Break.."
bitfld.long 0x0 3. "ECCL,ECC error lock bit" "0: ECC error disconnected from TIM1/15/16 Break input,1: ECC error connected to TIM1/15/16 Break input"
newline
bitfld.long 0x0 2. "PVDL,PVD lock enable bit" "0: PVD interrupt disconnected from TIM1/15/16 Break..,1: PVD interrupt connected to TIM1/15/16 Break.."
bitfld.long 0x0 1. "SPL,SRAM1 parity lock bit" "0: SRAM1 parity error disconnected from TIM1/15/16..,1: SRAM1 parity error connected to TIM1/15/16 Break.."
newline
bitfld.long 0x0 0. "CCL,Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP bit enable bit" "0: Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP..,1: Cortex<Superscript>1<Default 1 Font>-M0+ LOCKUP.."
line.long 0x4 "SYSCFG_SCSR,SYSCFG SRAM2 control and status register"
rbitfld.long 0x4 1. "SRAM2BSY,SRAM2 busy by erase operation" "0: No SRAM2 erase operation is ongoing,1: SRAM2 erase operation is ongoing"
bitfld.long 0x4 0. "SRAM2ER,SRAM2 erase" "0,1"
wgroup.long 0x20++0x3
line.long 0x0 "SYSCFG_SKR,SYSCFG SRAM2 key register"
hexmask.long.byte 0x0 0.--7. 1. "KEY,SRAM2 write protection key for software erase"
group.long 0x24++0x3
line.long 0x0 "SYSCFG_TSCCR,SYSCFG TSC comparator register"
bitfld.long 0x0 5. "TSC_IOCTRL,I/O control in comparator mode" "0: I/O configured through the corresponding control..,1: I/O configured as analog when TSC AF is activated"
bitfld.long 0x0 4. "G7_IO1,Comparator mode for group 7 on I/O 1" "0: Disabled,1: Enable connection of PA9 to COMP1"
newline
bitfld.long 0x0 3. "G6_IO1,Comparator mode for group 6 on I/O 1" "0: Disabled,1: Enable connection of PD10 to COMP1"
bitfld.long 0x0 2. "G4_IO3,Comparator mode for group 4 on I/O 3" "0: Disabled,1: Enable connection of PC6 to COMP2"
newline
bitfld.long 0x0 1. "G2_IO3,Comparator mode for group 2 on I/O 3" "0: Disabled,1: Enable connection of PB6 to COMP2"
bitfld.long 0x0 0. "G2_IO1,Comparator mode for group 2 on I/O 1" "0: Disabled,1: Enable connection of PB4 to COMP2"
rgroup.long 0x80++0x7F
line.long 0x0 "SYSCFG_ITLINE0,SYSCFG interrupt line 0 status register"
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending flag" "0,1"
line.long 0x4 "SYSCFG_ITLINE1,SYSCFG interrupt line 1 status register"
bitfld.long 0x4 3. "PVMOUT4,DAC supply monitoring interrupt request pending (EXTI line 21)" "0,1"
bitfld.long 0x4 2. "PVMOUT3,ADC supply monitoring interrupt request pending (EXTI line 20)" "0,1"
newline
bitfld.long 0x4 1. "PVMOUT1,V<sub>DDUSB</sub> supply monitoring interrupt request pending (EXTI line 19)" "0,1"
bitfld.long 0x4 0. "PVDOUT,PVD supply monitoring interrupt request pending (EXTI line 16)." "0,1"
line.long 0x8 "SYSCFG_ITLINE2,SYSCFG interrupt line 2 status register"
bitfld.long 0x8 1. "RTC,RTC interrupt request pending (EXTI line 19)" "0,1"
bitfld.long 0x8 0. "TAMP,Tamper interrupt request pending (EXTI line 21)" "0,1"
line.long 0xC "SYSCFG_ITLINE3,SYSCFG interrupt line 3 status register"
bitfld.long 0xC 1. "FLASH_ECC,Flash interface ECC interrupt request pending" "0,1"
bitfld.long 0xC 0. "FLASH_ITF,Flash interface interrupt request pending" "0,1"
line.long 0x10 "SYSCFG_ITLINE4,SYSCFG interrupt line 4 status register"
sif (cpuis("STM32U073*"))
bitfld.long 0x10 1. "CRS,CRS interrupt request pending" "0,1"
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x10 1. "CRS,CRS interrupt request pending" "0,1"
newline
endif
bitfld.long 0x10 0. "RCC,Reset and clock control interrupt request pending" "0,1"
line.long 0x14 "SYSCFG_ITLINE5,SYSCFG interrupt line 5 status register"
bitfld.long 0x14 1. "EXTI1,EXTI line 1 interrupt request pending" "0,1"
bitfld.long 0x14 0. "EXTI0,EXTI line 0 interrupt request pending" "0,1"
line.long 0x18 "SYSCFG_ITLINE6,SYSCFG interrupt line 6 status register"
bitfld.long 0x18 1. "EXTI3,EXTI line 3 interrupt request pending" "0,1"
bitfld.long 0x18 0. "EXTI2,EXTI line 2 interrupt request pending" "0,1"
line.long 0x1C "SYSCFG_ITLINE7,SYSCFG interrupt line 7 status register"
bitfld.long 0x1C 11. "EXTI15,EXTI line 15 interrupt request pending" "0,1"
bitfld.long 0x1C 10. "EXTI14,EXTI line 14 interrupt request pending" "0,1"
newline
bitfld.long 0x1C 9. "EXTI13,EXTI line 13 interrupt request pending" "0,1"
bitfld.long 0x1C 8. "EXTI12,EXTI line 12 interrupt request pending" "0,1"
newline
bitfld.long 0x1C 7. "EXTI11,EXTI line 11 interrupt request pending" "0,1"
bitfld.long 0x1C 6. "EXTI10,EXTI line 10 interrupt request pending" "0,1"
newline
bitfld.long 0x1C 5. "EXTI9,EXTI line 9 interrupt request pending" "0,1"
bitfld.long 0x1C 4. "EXTI8,EXTI line 8 interrupt request pending" "0,1"
newline
bitfld.long 0x1C 3. "EXTI7,EXTI line 7 interrupt request pending" "0,1"
bitfld.long 0x1C 2. "EXTI6,EXTI line 6 interrupt request pending" "0,1"
newline
bitfld.long 0x1C 1. "EXTI5,EXTI line 5 interrupt request pending" "0,1"
bitfld.long 0x1C 0. "EXTI4,EXTI line 4 interrupt request pending" "0,1"
line.long 0x20 "SYSCFG_ITLINE8,SYSCFG interrupt line 8 status register"
bitfld.long 0x20 0. "USB,USB interrupt request pending" "0,1"
line.long 0x24 "SYSCFG_ITLINE9,SYSCFG interrupt line 9 status register"
bitfld.long 0x24 0. "DMA1_CH1,DMA1 channel 1 interrupt request pending" "0,1"
line.long 0x28 "SYSCFG_ITLINE10,SYSCFG interrupt line 10 status register"
bitfld.long 0x28 1. "DMA1_CH3,DMA1 channel 3 interrupt request pending" "0,1"
bitfld.long 0x28 0. "DMA1_CH2,DMA1 channel 2 interrupt request pending" "0,1"
line.long 0x2C "SYSCFG_ITLINE11,SYSCFG interrupt line 11 status register"
bitfld.long 0x2C 9. "DMA2_CH5,DMA2 channel 5 interrupt request pending" "0,1"
bitfld.long 0x2C 8. "DMA2_CH4,DMA2 channel 4 interrupt request pending" "0,1"
newline
bitfld.long 0x2C 7. "DMA2_CH3,DMA2 channel 3 interrupt request pending" "0,1"
bitfld.long 0x2C 6. "DMA2_CH2,DMA2 channel 2 interrupt request pending" "0,1"
newline
bitfld.long 0x2C 5. "DMA2_CH1,DMA2 channel 1 interrupt request pending" "0,1"
bitfld.long 0x2C 4. "DMA1_CH7,DMA1 channel 7 interrupt request pending" "0,1"
newline
bitfld.long 0x2C 3. "DMA1_CH6,DMA1 channel 6 interrupt request pending" "0,1"
bitfld.long 0x2C 2. "DMA1_CH5,DMA1 channel 5 interrupt request pending" "0,1"
newline
bitfld.long 0x2C 1. "DMA1_CH4,DMA1 channel 4 interrupt request pending" "0,1"
bitfld.long 0x2C 0. "DMAMUX,DMAMUX interrupt request pending" "0,1"
line.long 0x30 "SYSCFG_ITLINE12,SYSCFG interrupt line 12 status register"
sif (cpuis("STM32U073*"))
bitfld.long 0x30 2. "COMP2,Comparator 2 interrupt request pending (EXTI line 18)" "0,1"
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x30 2. "COMP2,Comparator 2 interrupt request pending (EXTI line 18)" "0,1"
newline
endif
bitfld.long 0x30 1. "COMP1,Comparator 1 interrupt request pending (EXTI line 17)" "0,1"
bitfld.long 0x30 0. "ADC,ADC interrupt request pending" "0,1"
line.long 0x34 "SYSCFG_ITLINE13,SYSCFG interrupt line 13 status register"
bitfld.long 0x34 3. "TIM1_BRK,Timer 1 break interrupt request pending" "0,1"
bitfld.long 0x34 2. "TIM1_UPD,Timer 1 update interrupt request pending" "0,1"
newline
bitfld.long 0x34 1. "TIM1_TRG,Timer 1 trigger interrupt request pending" "0,1"
bitfld.long 0x34 0. "TIM1_CCU,Timer 1 commutation interrupt request pending" "0,1"
line.long 0x38 "SYSCFG_ITLINE14,SYSCFG interrupt line 14 status register"
bitfld.long 0x38 3. "TIM1_CC4,Timer 1 capture compare 4 interrupt request pending" "0,1"
bitfld.long 0x38 2. "TIM1_CC3,Timer 1 capture compare 3 interrupt request pending" "0,1"
newline
bitfld.long 0x38 1. "TIM1_CC2,Timer 1 capture compare 2 interrupt request pending" "0,1"
bitfld.long 0x38 0. "TIM1_CC1,Timer 1 capture compare 1 interrupt request pending" "0,1"
line.long 0x3C "SYSCFG_ITLINE15,SYSCFG interrupt line 15 status register"
bitfld.long 0x3C 0. "TIM2,Timer 2 interrupt request pending" "0,1"
line.long 0x40 "SYSCFG_ITLINE16,SYSCFG interrupt line 16 status register"
bitfld.long 0x40 0. "TIM3,Timer 3 interrupt request pending" "0,1"
line.long 0x44 "SYSCFG_ITLINE17,SYSCFG interrupt line 17 status register"
bitfld.long 0x44 2. "LPTIM1,Low-power timer 1 interrupt request pending (EXTI line 29)" "0,1"
bitfld.long 0x44 1. "DAC,DAC underrun interrupt request pending" "0,1"
newline
bitfld.long 0x44 0. "TIM6,Timer 6 interrupt request pending" "0,1"
line.long 0x48 "SYSCFG_ITLINE18,SYSCFG interrupt line 18 status register"
bitfld.long 0x48 1. "LPTIM2,Low-power timer 2 interrupt request pending (EXTI line 30)" "0,1"
bitfld.long 0x48 0. "TIM7,Timer 7 interrupt request pending" "0,1"
line.long 0x4C "SYSCFG_ITLINE19,SYSCFG interrupt line 19 status register"
sif (cpuis("STM32U073*"))
bitfld.long 0x4C 1. "LPTIM3,Low-power timer 3 interrupt request pending" "0,1"
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x4C 1. "LPTIM3,Low-power timer 3 interrupt request pending" "0,1"
newline
endif
bitfld.long 0x4C 0. "TIM15,Timer 15 interrupt request pending" "0,1"
line.long 0x50 "SYSCFG_ITLINE20,SYSCFG interrupt line 20 status register"
bitfld.long 0x50 0. "TIM16,Timer 16 interrupt request pending" "0,1"
line.long 0x54 "SYSCFG_ITLINE21,SYSCFG interrupt line 21 status register"
bitfld.long 0x54 1. "TSC_EOA,TSC end of acquisition interrupt request pending" "0,1"
bitfld.long 0x54 0. "TSC_MCE,TSC max count error interrupt request pending" "0,1"
line.long 0x58 "SYSCFG_ITLINE22,SYSCFG interrupt line 22 status register"
bitfld.long 0x58 0. "LCD,LCD interrupt request pending" "0,1"
line.long 0x5C "SYSCFG_ITLINE23,SYSCFG interrupt line 23 status register"
bitfld.long 0x5C 0. "I2C1,I2C1 interrupt request pending (EXTI line 33)" "0,1"
line.long 0x60 "SYSCFG_ITLINE24,SYSCFG interrupt line 24 status register"
bitfld.long 0x60 2. "I2C3,I2C3 interrupt request pending (EXTI line 23)" "0,1"
sif (cpuis("STM32U073*"))
bitfld.long 0x60 1. "I2C4,I2C4 interrupt request pending" "0,1"
newline
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x60 1. "I2C4,I2C4 interrupt request pending" "0,1"
endif
bitfld.long 0x60 0. "I2C2,I2C2 interrupt request pending" "0,1"
line.long 0x64 "SYSCFG_ITLINE25,SYSCFG interrupt line 25 status register"
bitfld.long 0x64 0. "SPI1,SPI1 interrupt request pending" "0,1"
line.long 0x68 "SYSCFG_ITLINE26,SYSCFG interrupt line 26 status register"
sif (cpuis("STM32U073*"))
bitfld.long 0x68 1. "SPI3,SPI3 interrupt request pending" "0,1"
endif
sif (cpuis("STM32U083*"))
bitfld.long 0x68 1. "SPI3,SPI3 interrupt request pending" "0,1"
newline
endif
bitfld.long 0x68 0. "SPI2,SPI2 interrupt request pending" "0,1"
line.long 0x6C "SYSCFG_ITLINE27,SYSCFG interrupt line 27 status register"
bitfld.long 0x6C 0. "USART1,USART1 interrupt request pending combined with EXTI line 25" "0,1"
line.long 0x70 "SYSCFG_ITLINE28,SYSCFG interrupt line 28 status register"
bitfld.long 0x70 1. "LPUART2,LPUART2 interrupt request pending (EXTI line 31)" "0,1"
bitfld.long 0x70 0. "USART2,USART2 interrupt request pending (EXTI line 35)" "0,1"
line.long 0x74 "SYSCFG_ITLINE29,SYSCFG interrupt line 29 status register"
bitfld.long 0x74 1. "LPUART1,LPUART1 interrupt request pending (EXTI line 30)" "0,1"
bitfld.long 0x74 0. "USART3,USART3 interrupt request pending" "0,1"
line.long 0x78 "SYSCFG_ITLINE30,SYSCFG interrupt line 30 status register"
bitfld.long 0x78 1. "LPUART3,LPUART3 interrupt request pending (EXTI line 32)" "0,1"
bitfld.long 0x78 0. "USART4,USART4 interrupt request pending" "0,1"
line.long 0x7C "SYSCFG_ITLINE31,SYSCFG interrupt line 31 status register"
sif (cpuis("STM32U083*"))
bitfld.long 0x7C 1. "AES,AES interrupt request pending" "0,1"
endif
bitfld.long 0x7C 0. "RNG,RNG interrupt request pending" "0,1"
tree.end
tree "TAMP (Tamper and Backup Registers)"
base ad:0x4000B000
group.long 0x0++0xF
line.long 0x0 "TAMP_CR1,TAMP control register 1"
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled."
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled."
newline
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled."
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled."
newline
bitfld.long 0x0 4. "TAMP5E,Tamper detection on TAMP_IN5 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN5 is disabled.,1: Tamper detection on TAMP_IN5 is enabled."
bitfld.long 0x0 3. "TAMP4E,Tamper detection on TAMP_IN4 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN4 is disabled.,1: Tamper detection on TAMP_IN4 is enabled."
newline
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable<sup>(1)</sup>" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
newline
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
line.long 0x4 "TAMP_CR2,TAMP control register 2"
bitfld.long 0x4 28. "TAMP5TRG,Active level for tamper 5 input (active mode disabled)" "0: If TAMPFLT different from 00 tamper 5 input..,1: If TAMPFLT different from 00 tamper 5 input.."
bitfld.long 0x4 27. "TAMP4TRG,Active level for tamper 4 input (active mode disabled)" "0: If TAMPFLT different from 00 tamper 4 input..,1: If TAMPFLT different from 00 tamper 4 input.."
newline
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input" "0: If TAMPFLT different from 00 tamper 3 input..,1: If TAMPFLT different from 00 tamper 3 input.."
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input" "0: If TAMPFLT different from 00 tamper 2 input..,1: If TAMPFLT different from 00 tamper 2 input.."
newline
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input" "0: If TAMPFLT different from 00 tamper 1 input..,1: If TAMPFLT different from 00 tamper 1 input.."
bitfld.long 0x4 23. "BKERASE,Backup registers and device secrets<sup>(1)</sup> erase" "0,1"
newline
bitfld.long 0x4 22. "BKBLOCK,Backup registers and device secrets<sup>(1)</sup> access blocked" "0: backup registers and device..,1: backup registers and device.."
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
newline
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
newline
bitfld.long 0x4 4. "TAMP5POM,Tamper 5 potential mode" "0: Tamper 5 event detection is in confirmed..,1: Tamper 5 event detection is in potential.."
bitfld.long 0x4 3. "TAMP4POM,Tamper 4 potential mode" "0: Tamper 4 event detection is in confirmed..,1: Tamper 4 event detection is in potential.."
newline
bitfld.long 0x4 2. "TAMP3POM,Tamper 3 potential mode" "0: Tamper 3 event detection is in confirmed..,1: Tamper 3 event detection is in potential.."
bitfld.long 0x4 1. "TAMP2POM,Tamper 2 potential mode" "0: Tamper 2 event detection is in confirmed..,1: Tamper 2 event detection is in potential.."
newline
bitfld.long 0x4 0. "TAMP1POM,Tamper 1 potential mode" "0: Tamper 1 event detection is in confirmed mode.,1: Tamper 1 event detection is in potential mode."
line.long 0x8 "TAMP_CR3,TAMP control register 3"
bitfld.long 0x8 5. "ITAMP6POM,Internal tamper 6 potential mode" "0: Internal tamper 6 event detection is in..,1: Internal tamper 6 event detection is in.."
bitfld.long 0x8 4. "ITAMP5POM,Internal tamper 5 potential mode" "0: Internal tamper 5 event detection is in..,1: Internal tamper 5 event detection is in.."
newline
bitfld.long 0x8 3. "ITAMP4POM,Internal tamper 4 potential mode" "0: Internal tamper 4 event detection is in..,1: Internal tamper 4 event detection is in.."
bitfld.long 0x8 2. "ITAMP3POM,Internal tamper 3 potential mode" "0: Internal tamper 3 event detection is in..,1: Internal tamper 3 event detection is in.."
line.long 0xC "TAMP_FLTCR,TAMP filter control register"
bitfld.long 0xC 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
bitfld.long 0xC 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
newline
bitfld.long 0xC 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
bitfld.long 0xC 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (11Hz when RTCCLK = 327681Hz),1: RTCCLK / 16384 (21Hz when RTCCLK = 327681Hz),2: RTCCLK / 8192 (41Hz when RTCCLK = 327681Hz),3: RTCCLK / 4096 (81Hz when RTCCLK = 327681Hz),4: RTCCLK / 2048 (161Hz when RTCCLK = 327681Hz),5: RTCCLK / 1024 (321Hz when RTCCLK = 327681Hz),6: RTCCLK / 512 (641Hz when RTCCLK = 327681Hz),7: RTCCLK / 256 (1281Hz when RTCCLK = 327681Hz)"
group.long 0x2C++0x3
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
newline
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
newline
bitfld.long 0x0 4. "TAMP5IE,Tamper 5 interrupt enable" "0: Tamper 5 interrupt disabled.,1: Tamper 5 interrupt enabled."
bitfld.long 0x0 3. "TAMP4IE,Tamper 4 interrupt enable" "0: Tamper 4 interrupt disabled.,1: Tamper 4 interrupt enabled."
newline
bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
newline
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
rgroup.long 0x30++0x7
line.long 0x0 "TAMP_SR,TAMP status register"
bitfld.long 0x0 21. "ITAMP6F,Internal tamper 6 flag" "0,1"
bitfld.long 0x0 20. "ITAMP5F,Internal tamper 5 flag" "0,1"
newline
bitfld.long 0x0 19. "ITAMP4F,Internal tamper 4 flag" "0,1"
bitfld.long 0x0 18. "ITAMP3F,Internal tamper 3 flag" "0,1"
newline
bitfld.long 0x0 4. "TAMP5F,TAMP5 detection flag" "0,1"
bitfld.long 0x0 3. "TAMP4F,TAMP4 detection flag" "0,1"
newline
bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1"
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
newline
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
bitfld.long 0x4 21. "ITAMP6MF,Internal tamper 6 interrupt masked flag" "0,1"
bitfld.long 0x4 20. "ITAMP5MF,Internal tamper 5 interrupt masked flag" "0,1"
newline
bitfld.long 0x4 19. "ITAMP4MF,Internal tamper 4 interrupt masked flag" "0,1"
bitfld.long 0x4 18. "ITAMP3MF,Internal tamper 3 interrupt masked flag" "0,1"
newline
bitfld.long 0x4 4. "TAMP5MF,TAMP5 interrupt masked flag" "0,1"
bitfld.long 0x4 3. "TAMP4MF,TAMP4 interrupt masked flag" "0,1"
newline
bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
newline
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
wgroup.long 0x3C++0x3
line.long 0x0 "TAMP_SCR,TAMP status clear register"
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
newline
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
newline
bitfld.long 0x0 4. "CTAMP5F,Clear TAMP5 detection flag" "0,1"
bitfld.long 0x0 3. "CTAMP4F,Clear TAMP4 detection flag" "0,1"
newline
bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
newline
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
group.long 0x100++0x23
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x14 "TAMP_BKP5R,TAMP backup 5 register"
hexmask.long 0x14 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x18 "TAMP_BKP6R,TAMP backup 6 register"
hexmask.long 0x18 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x1C "TAMP_BKP7R,TAMP backup 7 register"
hexmask.long 0x1C 0.--31. 1. "BKP,The application can write or read data to and from these registers."
line.long 0x20 "TAMP_BKP8R,TAMP backup 8 register"
hexmask.long 0x20 0.--31. 1. "BKP,The application can write or read data to and from these registers."
tree.end
tree "TIM (Timers)"
base ad:0x0
tree "TIM1 (Advanced-control Timer)"
base ad:0x40012C00
group.word 0x0++0x1
line.word 0x0 "TIM1_CR1,TIM1 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: t<sub>DTS</sub>=t<sub>CK_INT</sub>,1: t<sub>DTS</sub>=2*t<sub>CK_INT</sub>,2: t<sub>DTS</sub>=4*t<sub>CK_INT</sub>,3: Reserved do not program this value"
newline
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
newline
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
newline
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
newline
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.long 0x4++0x7
line.long 0x0 "TIM1_CR2,TIM1 control register 2"
hexmask.long.byte 0x0 20.--23. 1. "MMS2,Master mode selection 2"
bitfld.long 0x0 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
newline
bitfld.long 0x0 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
bitfld.long 0x0 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
newline
bitfld.long 0x0 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
bitfld.long 0x0 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
newline
bitfld.long 0x0 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
bitfld.long 0x0 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
newline
bitfld.long 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
bitfld.long 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
newline
bitfld.long 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
bitfld.long 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
newline
bitfld.long 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
bitfld.long 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
newline
bitfld.long 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
line.long 0x4 "TIM1_SMCR,TIM1 slave mode control register"
bitfld.long 0x4 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
bitfld.long 0x4 16. "SMS_1,SMS[3]" "0,1"
newline
bitfld.long 0x4 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
bitfld.long 0x4 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
newline
bitfld.long 0x4 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
hexmask.long.byte 0x4 8.--11. 1. "ETF,External trigger filter"
newline
bitfld.long 0x4 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
bitfld.long 0x4 4.--6. "TS,TS[0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
newline
bitfld.long 0x4 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x4 0.--2. "SMS,SMS[0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
group.word 0xC++0x1
line.word 0x0 "TIM1_DIER,TIM1 DMA/interrupt enable register"
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
newline
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
newline
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
newline
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
newline
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
newline
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
newline
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
newline
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
group.long 0x10++0x3
line.long 0x0 "TIM1_SR,TIM1 status register"
bitfld.long 0x0 17. "CC6IF,Compare 6 interrupt flag" "0,1"
bitfld.long 0x0 16. "CC5IF,Compare 5 interrupt flag" "0,1"
newline
bitfld.long 0x0 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
bitfld.long 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
newline
bitfld.long 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
bitfld.long 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
newline
bitfld.long 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
bitfld.long 0x0 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
newline
bitfld.long 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
bitfld.long 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
newline
bitfld.long 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
bitfld.long 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
newline
bitfld.long 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
bitfld.long 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
newline
bitfld.long 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
bitfld.long 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
wgroup.word 0x14++0x1
line.word 0x0 "TIM1_EGR,TIM1 event generation register"
bitfld.word 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
newline
bitfld.word 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
bitfld.word 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
newline
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
newline
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "TIM1_CCMR1_INPUT,TIM1 capture/compare mode register 1"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
group.long 0x18++0x7
line.long 0x0 "TIM1_CCMR1_OUTPUT,TIM1 capture/compare mode register 1"
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
newline
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
line.long 0x4 "TIM1_CCMR2_INPUT,TIM1 capture/compare mode register 2"
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
newline
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x4 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
group.long 0x1C++0xB
line.long 0x0 "TIM1_CCMR2_OUTPUT,TIM1 capture/compare mode register 1"
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
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bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
line.long 0x4 "TIM1_CCER,TIM1 capture/compare enable register"
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
newline
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
newline
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
newline
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
newline
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
newline
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
newline
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
newline
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
newline
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
newline
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
line.long 0x8 "TIM1_CNT,TIM1 counter"
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
group.word 0x28++0x1
line.word 0x0 "TIM1_PSC,TIM1 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.word 0x2C++0x1
line.word 0x0 "TIM1_ARR,TIM1 auto-reload register"
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
group.word 0x30++0x1
line.word 0x0 "TIM1_RCR,TIM1 repetition counter register"
hexmask.word 0x0 0.--15. 1. "REP,Repetition counter value"
group.word 0x34++0x1
line.word 0x0 "TIM1_CCR1,TIM1 capture/compare register 1"
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
group.word 0x38++0x1
line.word 0x0 "TIM1_CCR2,TIM1 capture/compare register 2"
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
group.word 0x3C++0x1
line.word 0x0 "TIM1_CCR3,TIM1 capture/compare register 3"
hexmask.word 0x0 0.--15. 1. "CCR3,Capture/Compare value"
group.word 0x40++0x1
line.word 0x0 "TIM1_CCR4,TIM1 capture/compare register 4"
hexmask.word 0x0 0.--15. 1. "CCR4,Capture/Compare value"
group.long 0x44++0x3
line.long 0x0 "TIM1_BDTR,TIM1 break and dead-time register"
bitfld.long 0x0 29. "BK2BID,Break2 bidirectional" "0,1"
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
newline
bitfld.long 0x0 27. "BK2DSRM,Break2 Disarm" "0,1"
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
newline
bitfld.long 0x0 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
bitfld.long 0x0 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
newline
hexmask.long.byte 0x0 20.--23. 1. "BK2F,Break 2 filter"
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
newline
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
newline
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
bitfld.long 0x0 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
newline
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
newline
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
group.word 0x48++0x1
line.word 0x0 "TIM1_DCR,TIM1 DMA control register"
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
group.long 0x4C++0xF
line.long 0x0 "TIM1_DMAR,TIM1 DMA address for full transfer"
hexmask.long 0x0 0.--31. 1. "DMAB,DMA register for burst accesses"
line.long 0x4 "TIM1_OR1,TIM1 option register 1"
bitfld.long 0x4 0.--1. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input,?,?"
line.long 0x8 "TIM1_CCMR3,TIM1 capture/compare mode register 3"
bitfld.long 0x8 24. "OC6M_1,OC6M[3]" "0,1"
bitfld.long 0x8 16. "OC5M_1,OC5M[3]" "0,1"
newline
bitfld.long 0x8 15. "OC6CE,Output compare 6 clear enable" "0,1"
bitfld.long 0x8 12.--14. "OC6M,OC6M[0]: Output compare 6 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11. "OC6PE,Output compare 6 preload enable" "0,1"
bitfld.long 0x8 10. "OC6FE,Output compare 6 fast enable" "0,1"
newline
bitfld.long 0x8 7. "OC5CE,Output compare 5 clear enable" "0,1"
bitfld.long 0x8 4.--6. "OC5M,OC5M[0]: Output compare 5 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 3. "OC5PE,Output compare 5 preload enable" "0,1"
bitfld.long 0x8 2. "OC5FE,Output compare 5 fast enable" "0,1"
line.long 0xC "TIM1_CCR5,TIM1 capture/compare register 5"
bitfld.long 0xC 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
bitfld.long 0xC 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
newline
bitfld.long 0xC 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
hexmask.long.word 0xC 0.--15. 1. "CCR5,Capture/Compare 5 value"
group.word 0x5C++0x1
line.word 0x0 "TIM1_CCR6,TIM1 capture/compare register 6"
hexmask.word 0x0 0.--15. 1. "CCR6,Capture/Compare 6 value"
group.long 0x60++0xB
line.long 0x0 "TIM1_AF1,TIM1 alternate function option register 1"
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
newline
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
newline
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
newline
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
line.long 0x4 "TIM1_AF2,TIM1 Alternate function register 2"
bitfld.long 0x4 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
bitfld.long 0x4 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
newline
bitfld.long 0x4 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
bitfld.long 0x4 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
newline
bitfld.long 0x4 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x4 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
line.long 0x8 "TIM1_TISEL,TIM1 timer input selection register"
hexmask.long.byte 0x8 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
hexmask.long.byte 0x8 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
newline
hexmask.long.byte 0x8 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
hexmask.long.byte 0x8 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
tree.end
tree "TIM2 (General-purpose Timer)"
base ad:0x40000000
group.word 0x0++0x1
line.word 0x0 "TIM2_CR1,TIM2 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: B_0x0,1: B_0x1,2: B_0x2,?"
newline
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode.,1: Center-aligned mode 1.,2: Center-aligned mode 2.,3: Center-aligned mode 3."
newline
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
newline
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
newline
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM2_CR2,TIM2 control register 2"
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
newline
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
group.long 0x8++0x3
line.long 0x0 "TIM2_SMCR,TIM2 slave mode control register"
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
newline
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled."
newline
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
newline
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
newline
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
group.word 0xC++0x1
line.word 0x0 "TIM2_DIER,TIM2 DMA/Interrupt enable register"
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
newline
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
newline
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
newline
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
newline
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
newline
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
group.word 0x10++0x1
line.word 0x0 "TIM2_SR,TIM2 status register"
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
newline
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
newline
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
newline
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending."
wgroup.word 0x14++0x1
line.word 0x0 "TIM2_EGR,TIM2 event generation register"
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register."
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
newline
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
newline
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
group.long 0x18++0x3
line.long 0x0 "TIM2_CCMR1,TIM2 capture/compare mode register 1"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
group.long 0x18++0x7
line.long 0x0 "TIM2_CCMR1_ALTERNATE1,TIM2 capture/compare mode register 1"
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
newline
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
newline
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
line.long 0x4 "TIM2_CCMR2,TIM2 capture/compare mode register 2"
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
newline
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
group.long 0x1C++0x3
line.long 0x0 "TIM2_CCMR2_ALTERNATE1,TIM2 capture/compare mode register 2"
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
newline
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
group.word 0x20++0x1
line.word 0x0 "TIM2_CCER,TIM2 capture/compare enable register"
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
newline
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
newline
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
newline
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
newline
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
newline
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
group.long 0x24++0x3
line.long 0x0 "TIM2_CNT,TIM2 counter"
hexmask.long 0x0 0.--31. 1. "CNT,Least significant part of counter value"
group.long 0x24++0x3
line.long 0x0 "TIM2_CNT_ALTERNATE1,TIM2 counter"
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
group.word 0x28++0x1
line.word 0x0 "TIM2_PSC,TIM2 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.long 0x2C++0x3
line.long 0x0 "TIM2_ARR,TIM2 auto-reload register"
hexmask.long 0x0 0.--31. 1. "ARR,Low Auto-reload value"
group.long 0x34++0xF
line.long 0x0 "TIM2_CCR1,TIM2 capture/compare register 1"
hexmask.long 0x0 0.--31. 1. "CCR1,Low Capture/Compare 1 value"
line.long 0x4 "TIM2_CCR2,TIM2 capture/compare register 2"
hexmask.long 0x4 0.--31. 1. "CCR2,Low Capture/Compare 2 value"
line.long 0x8 "TIM2_CCR3,TIM2 capture/compare register 3"
hexmask.long 0x8 0.--31. 1. "CCR3,Low Capture/Compare value"
line.long 0xC "TIM2_CCR4,TIM2 capture/compare register 4"
hexmask.long 0xC 0.--31. 1. "CCR4,Low Capture/Compare value"
group.word 0x48++0x1
line.word 0x0 "TIM2_DCR,TIM2 DMA control register"
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
group.word 0x4C++0x1
line.word 0x0 "TIM2_DMAR,TIM2 DMA address for full transfer"
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
group.long 0x50++0x3
line.long 0x0 "TIM2_OR1,TIM2 option register 1"
bitfld.long 0x0 0.--1. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input,?,?"
group.long 0x60++0x3
line.long 0x0 "TIM2_AF1,TIM2 alternate function option register 1"
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
group.long 0x68++0x3
line.long 0x0 "TIM2_TISEL,TIM2 timer input selection register"
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
newline
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
tree.end
tree "TIM3 (General-purpose Timer)"
base ad:0x40000400
group.word 0x0++0x1
line.word 0x0 "TIM3_CR1,TIM3 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: B_0x0,1: B_0x1,2: B_0x2,?"
newline
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.word 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode.,1: Center-aligned mode 1.,2: Center-aligned mode 2.,3: Center-aligned mode 3."
newline
bitfld.word 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
newline
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
newline
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM3_CR2,TIM3 control register 2"
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
newline
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
group.long 0x8++0x3
line.long 0x0 "TIM3_SMCR,TIM3 slave mode control register"
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
newline
bitfld.long 0x0 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
bitfld.long 0x0 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled."
newline
bitfld.long 0x0 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
hexmask.long.byte 0x0 8.--11. 1. "ETF,External trigger filter"
newline
bitfld.long 0x0 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
newline
bitfld.long 0x0 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
group.word 0xC++0x1
line.word 0x0 "TIM3_DIER,TIM3 DMA/Interrupt enable register"
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
bitfld.word 0x0 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
newline
bitfld.word 0x0 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
bitfld.word 0x0 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
newline
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
newline
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
bitfld.word 0x0 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
newline
bitfld.word 0x0 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
newline
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
group.word 0x10++0x1
line.word 0x0 "TIM3_SR,TIM3 status register"
bitfld.word 0x0 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
bitfld.word 0x0 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
newline
bitfld.word 0x0 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
bitfld.word 0x0 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
newline
bitfld.word 0x0 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
newline
bitfld.word 0x0 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending."
wgroup.word 0x14++0x1
line.word 0x0 "TIM3_EGR,TIM3 event generation register"
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register."
bitfld.word 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
newline
bitfld.word 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
bitfld.word 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
newline
bitfld.word 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
group.long 0x18++0x3
line.long 0x0 "TIM3_CCMR1,TIM3 capture/compare mode register 1"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
group.long 0x18++0x7
line.long 0x0 "TIM3_CCMR1_ALTERNATE1,TIM3 capture/compare mode register 1"
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output compare 2 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload enable" "0,1"
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
newline
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
newline
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
line.long 0x4 "TIM3_CCMR2,TIM3 capture/compare mode register 2"
hexmask.long.byte 0x4 12.--15. 1. "IC4F,Input capture 4 filter"
bitfld.long 0x4 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
hexmask.long.byte 0x4 4.--7. 1. "IC3F,Input capture 3 filter"
newline
bitfld.long 0x4 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
group.long 0x1C++0x3
line.long 0x0 "TIM3_CCMR2_ALTERNATE1,TIM3 capture/compare mode register 2"
bitfld.long 0x0 24. "OC4M_1,OC4M[3]" "0,1"
bitfld.long 0x0 16. "OC3M_1,OC3M[3]" "0,1"
newline
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear enable" "0,1"
bitfld.long 0x0 12.--14. "OC4M,OC4M[2:0]: Output compare 4 mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload enable" "0,1"
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast enable" "0,1"
newline
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear enable" "0,1"
newline
bitfld.long 0x0 4.--6. "OC3M,OC3M[2:0]: Output compare 3 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload enable" "0,1"
newline
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast enable" "0,1"
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
group.word 0x20++0x1
line.word 0x0 "TIM3_CCER,TIM3 capture/compare enable register"
bitfld.word 0x0 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
bitfld.word 0x0 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
newline
bitfld.word 0x0 12. "CC4E,Capture/Compare 4 output enable." "0,1"
bitfld.word 0x0 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
newline
bitfld.word 0x0 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
bitfld.word 0x0 8. "CC3E,Capture/Compare 3 output enable." "0,1"
newline
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
newline
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable." "0,1"
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
newline
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
group.long 0x24++0x3
line.long 0x0 "TIM3_CNT,TIM3 counter"
hexmask.long 0x0 0.--31. 1. "CNT,Least significant part of counter value"
group.long 0x24++0x3
line.long 0x0 "TIM3_CNT_ALTERNATE1,TIM3 counter"
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long 0x0 0.--30. 1. "CNT,Least significant part of counter value"
group.word 0x28++0x1
line.word 0x0 "TIM3_PSC,TIM3 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.long 0x2C++0x3
line.long 0x0 "TIM3_ARR,TIM3 auto-reload register"
hexmask.long 0x0 0.--31. 1. "ARR,Low Auto-reload value"
group.long 0x34++0xF
line.long 0x0 "TIM3_CCR1,TIM3 capture/compare register 1"
hexmask.long 0x0 0.--31. 1. "CCR1,Low Capture/Compare 1 value"
line.long 0x4 "TIM3_CCR2,TIM3 capture/compare register 2"
hexmask.long 0x4 0.--31. 1. "CCR2,Low Capture/Compare 2 value"
line.long 0x8 "TIM3_CCR3,TIM3 capture/compare register 3"
hexmask.long 0x8 0.--31. 1. "CCR3,Low Capture/Compare value"
line.long 0xC "TIM3_CCR4,TIM3 capture/compare register 4"
hexmask.long 0xC 0.--31. 1. "CCR4,Low Capture/Compare value"
group.word 0x48++0x1
line.word 0x0 "TIM3_DCR,TIM3 DMA control register"
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
group.word 0x4C++0x1
line.word 0x0 "TIM3_DMAR,TIM3 DMA address for full transfer"
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
group.long 0x50++0x3
line.long 0x0 "TIM3_OR1,TIM3 option register 1"
bitfld.long 0x0 0.--1. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input,?,?"
group.long 0x60++0x3
line.long 0x0 "TIM3_AF1,TIM3 alternate function option register 1"
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
group.long 0x68++0x3
line.long 0x0 "TIM3_TISEL,TIM3 timer input selection register"
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
newline
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
tree.end
tree "TIM6 (Basic Timer)"
base ad:0x40001000
group.word 0x0++0x1
line.word 0x0 "TIM6_CR1,TIM6 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
newline
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
newline
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM6_CR2,TIM6 control register 2"
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
group.word 0xC++0x1
line.word 0x0 "TIM6_DIER,TIM6 DMA/Interrupt enable register"
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
group.word 0x10++0x1
line.word 0x0 "TIM6_SR,TIM6 status register"
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
wgroup.word 0x14++0x1
line.word 0x0 "TIM6_EGR,TIM6 event generation register"
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
group.long 0x24++0x3
line.long 0x0 "TIM6_CNT,TIM6 counter"
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.word 0x28++0x1
line.word 0x0 "TIM6_PSC,TIM6 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.word 0x2C++0x1
line.word 0x0 "TIM6_ARR,TIM6 auto-reload register"
hexmask.word 0x0 0.--15. 1. "ARR,Prescaler value"
tree.end
tree "TIM7 (Basic Timer)"
base ad:0x40001400
group.word 0x0++0x1
line.word 0x0 "TIM7_CR1,TIM7 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
newline
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
newline
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM7_CR2,TIM7 control register 2"
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
group.word 0xC++0x1
line.word 0x0 "TIM7_DIER,TIM7 DMA/Interrupt enable register"
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
group.word 0x10++0x1
line.word 0x0 "TIM7_SR,TIM7 status register"
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
wgroup.word 0x14++0x1
line.word 0x0 "TIM7_EGR,TIM7 event generation register"
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
group.long 0x24++0x3
line.long 0x0 "TIM7_CNT,TIM7 counter"
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.word 0x28++0x1
line.word 0x0 "TIM7_PSC,TIM7 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.word 0x2C++0x1
line.word 0x0 "TIM7_ARR,TIM7 auto-reload register"
hexmask.word 0x0 0.--15. 1. "ARR,Prescaler value"
tree.end
tree "TIM15 (General-purpose Timer)"
base ad:0x40014000
group.word 0x0++0x1
line.word 0x0 "TIM15_CR1,TIM15 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: B_0x0,1: B_0x1,2: B_0x2,?"
newline
bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.word 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
newline
bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
newline
bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM15_CR2,TIM15 control register 2"
bitfld.word 0x0 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
newline
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
bitfld.word 0x0 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
newline
bitfld.word 0x0 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
newline
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
group.long 0x8++0x3
line.long 0x0 "TIM15_SMCR,TIM15 slave mode control register"
bitfld.long 0x0 20.--21. "TS_1,TS[4:3]" "0,1,2,3"
bitfld.long 0x0 16. "SMS_1,SMS[3]" "0,1"
newline
bitfld.long 0x0 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
bitfld.long 0x0 4.--6. "TS,TS[2:0]: Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
newline
bitfld.long 0x0 0.--2. "SMS,SMS[2:0]: Slave mode selection" "0: Slave mode disabled - if CEN = 1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
group.word 0xC++0x1
line.word 0x0 "TIM15_DIER,TIM15 DMA/interrupt enable register"
bitfld.word 0x0 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
bitfld.word 0x0 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
newline
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
newline
bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
bitfld.word 0x0 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
newline
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
bitfld.word 0x0 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
newline
bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
group.word 0x10++0x1
line.word 0x0 "TIM15_SR,TIM15 status register"
bitfld.word 0x0 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
newline
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
bitfld.word 0x0 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
newline
bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
bitfld.word 0x0 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
newline
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending."
group.word 0x14++0x1
line.word 0x0 "TIM15_EGR,TIM15 event generation register"
bitfld.word 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated."
bitfld.word 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register."
newline
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
bitfld.word 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
newline
bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
bitfld.word 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "TIM15_CCMR1,TIM15 capture/compare mode register 1"
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
newline
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
group.long 0x18++0x3
line.long 0x0 "TIM15_CCMR1_ALTERNATE1,TIM15 capture/compare mode register 1"
bitfld.long 0x0 24. "OC2M_1,OC2M[3]" "0,1"
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
newline
bitfld.long 0x0 12.--14. "OC2M,OC2M[2:0]: Output Compare 2 mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
newline
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
newline
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
newline
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
group.word 0x20++0x1
line.word 0x0 "TIM15_CCER,TIM15 capture/compare enable register"
bitfld.word 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
bitfld.word 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
newline
bitfld.word 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
newline
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active.,1: On - OC1N signal is output on the corresponding.."
bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
newline
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
group.long 0x24++0x3
line.long 0x0 "TIM15_CNT,TIM15 counter"
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.word 0x28++0x1
line.word 0x0 "TIM15_PSC,TIM15 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.word 0x2C++0x1
line.word 0x0 "TIM15_ARR,TIM15 auto-reload register"
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
group.word 0x30++0x1
line.word 0x0 "TIM15_RCR,TIM15 repetition counter register"
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
group.word 0x34++0x1
line.word 0x0 "TIM15_CCR1,TIM15 capture/compare register 1"
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
group.word 0x38++0x1
line.word 0x0 "TIM15_CCR2,TIM15 capture/compare register 2"
hexmask.word 0x0 0.--15. 1. "CCR2,Capture/Compare 2 value"
group.long 0x44++0x3
line.long 0x0 "TIM15_BDTR,TIM15 break and dead-time register"
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
newline
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
newline
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
newline
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
newline
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
newline
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
group.word 0x48++0x1
line.word 0x0 "TIM15_DCR,TIM15 DMA control register"
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
group.word 0x4C++0x1
line.word 0x0 "TIM15_DMAR,TIM15 DMA address for full transfer"
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
group.long 0x60++0x3
line.long 0x0 "TIM15_AF1,TIM15 alternate register 1"
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
group.long 0x68++0x3
line.long 0x0 "TIM15_TISEL,TIM15 input selection register"
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
tree.end
tree "TIM16 (General-purpose Timer)"
base ad:0x40014400
group.word 0x0++0x1
line.word 0x0 "TIM16_CR1,TIM16 control register 1"
bitfld.word 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping.,1: Remapping enabled."
bitfld.word 0x0 8.--9. "CKD,Clock division" "0: B_0x0,1: B_0x1,2: B_0x2,?"
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bitfld.word 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
bitfld.word 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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bitfld.word 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
bitfld.word 0x0 1. "UDIS,Update disable" "0: UEV enabled.,1: UEV disabled."
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bitfld.word 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
group.word 0x4++0x1
line.word 0x0 "TIM16_CR2,TIM16 control register 2"
bitfld.word 0x0 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
bitfld.word 0x0 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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bitfld.word 0x0 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
bitfld.word 0x0 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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bitfld.word 0x0 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
group.word 0xC++0x1
line.word 0x0 "TIM16_DIER,TIM16 DMA/interrupt enable register"
bitfld.word 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
bitfld.word 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.word 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
bitfld.word 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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bitfld.word 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
bitfld.word 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
group.word 0x10++0x1
line.word 0x0 "TIM16_SR,TIM16 status register"
bitfld.word 0x0 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
bitfld.word 0x0 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.word 0x0 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
bitfld.word 0x0 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.word 0x0 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending."
wgroup.word 0x14++0x1
line.word 0x0 "TIM16_EGR,TIM16 event generation register"
bitfld.word 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated."
bitfld.word 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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bitfld.word 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
bitfld.word 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
group.long 0x18++0x3
line.long 0x0 "TIM16_CCMR1,TIM16 capture/compare mode register 1"
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
group.long 0x18++0x3
line.long 0x0 "TIM16_CCMR1_ALTERNATE1,TIM16 capture/compare mode register 1"
bitfld.long 0x0 16. "OC1M_1,OC1M[3]" "0,1"
bitfld.long 0x0 4.--6. "OC1M,OC1M[2:0]: Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match.,2: Set channel 1 to inactive level on match.,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
group.word 0x20++0x1
line.word 0x0 "TIM16_CCER,TIM16 capture/compare enable register"
bitfld.word 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
bitfld.word 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active.,1: On - OC1N signal is output on the corresponding.."
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bitfld.word 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: OC1 active high (output mode) / Edge sensitivity..,1: OC1 active low (output mode) / Edge sensitivity.."
bitfld.word 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
group.long 0x24++0x3
line.long 0x0 "TIM16_CNT,TIM16 counter"
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
group.word 0x28++0x1
line.word 0x0 "TIM16_PSC,TIM16 prescaler"
hexmask.word 0x0 0.--15. 1. "PSC,Prescaler value"
group.word 0x2C++0x1
line.word 0x0 "TIM16_ARR,TIM16 auto-reload register"
hexmask.word 0x0 0.--15. 1. "ARR,Auto-reload value"
group.word 0x30++0x1
line.word 0x0 "TIM16_RCR,TIM16 repetition counter register"
hexmask.word.byte 0x0 0.--7. 1. "REP,Repetition counter value"
group.word 0x34++0x1
line.word 0x0 "TIM16_CCR1,TIM16 capture/compare register 1"
hexmask.word 0x0 0.--15. 1. "CCR1,Capture/Compare 1 value"
group.long 0x44++0x3
line.long 0x0 "TIM16_BDTR,TIM16 break and dead-time register"
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
group.word 0x48++0x1
line.word 0x0 "TIM16_DCR,TIM16 DMA control register"
hexmask.word.byte 0x0 8.--12. 1. "DBL,DMA burst length"
hexmask.word.byte 0x0 0.--4. 1. "DBA,DMA base address"
group.word 0x4C++0x1
line.word 0x0 "TIM16_DMAR,TIM16 DMA address for full transfer"
hexmask.word 0x0 0.--15. 1. "DMAB,DMA register for burst accesses"
group.long 0x60++0x3
line.long 0x0 "TIM16_AF1,TIM16 alternate function register 1"
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
group.long 0x68++0x3
line.long 0x0 "TIM16_TISEL,TIM16 input selection register"
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
tree.end
tree.end
tree "TSC (Touch Sensing Controller)"
base ad:0x40024000
group.long 0x0++0xB
line.long 0x0 "TSC_CR,TSC control register"
hexmask.long.byte 0x0 28.--31. 1. "CTPH,Charge transfer pulse high"
hexmask.long.byte 0x0 24.--27. 1. "CTPL,Charge transfer pulse low"
newline
hexmask.long.byte 0x0 17.--23. 1. "SSD,Spread spectrum deviation"
bitfld.long 0x0 16. "SSE,Spread spectrum enable" "0: Spread spectrum disabled,1: Spread spectrum enabled"
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bitfld.long 0x0 15. "SSPSC,Spread spectrum prescaler" "0: f<sub>HCLK</sub>,1: f<sub>HCLK</sub> /2"
bitfld.long 0x0 12.--14. "PGPSC,Pulse generator prescaler" "0: f<sub>HCLK</sub>,1: f<sub>HCLK</sub> /2,2: f<sub>HCLK</sub> /4,3: f<sub>HCLK</sub> /8,4: Charge transfer acquisition sequence for details,5: f<sub>HCLK</sub> /32,6: f<sub>HCLK</sub> /64,7: f<sub>HCLK</sub> /128"
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bitfld.long 0x0 5.--7. "MCV,Max count value" "0: 255,1: 511,2: 1023,3: 2047,4: 4095,5: 8191,6: 16383,?"
bitfld.long 0x0 4. "IODEF,I/O Default mode" "0: I/Os are forced to output push-pull low,1: I/Os are in input floating"
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bitfld.long 0x0 3. "SYNCPOL,Synchronization pin polarity" "0: Falling edge only,1: Rising edge and high level"
bitfld.long 0x0 2. "AM,Acquisition mode" "0: Normal acquisition mode (acquisition starts as..,1: Synchronized acquisition mode (acquisition.."
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bitfld.long 0x0 1. "START,Start a new acquisition" "0: Acquisition not started,1: Start a new acquisition"
bitfld.long 0x0 0. "TSCE,Touch sensing controller enable" "0: Touch sensing controller disabled,1: Touch sensing controller enabled"
line.long 0x4 "TSC_IER,TSC interrupt enable register"
bitfld.long 0x4 1. "MCEIE,Max count error interrupt enable" "0: Max count error interrupt disabled,1: Max count error interrupt enabled"
bitfld.long 0x4 0. "EOAIE,End of acquisition interrupt enable" "0: End of acquisition interrupt disabled,1: End of acquisition interrupt enabled"
line.long 0x8 "TSC_ICR,TSC interrupt clear register"
bitfld.long 0x8 1. "MCEIC,Max count error interrupt clear" "0: No effect,1: Clears the corresponding MCEF of the TSC_ISR.."
bitfld.long 0x8 0. "EOAIC,End of acquisition interrupt clear" "0: No effect,1: Clears the corresponding EOAF of the TSC_ISR.."
rgroup.long 0xC++0x3
line.long 0x0 "TSC_ISR,TSC interrupt status register"
bitfld.long 0x0 1. "MCEF,Max count error flag" "0: No max count error (MCE) detected,1: Max count error (MCE) detected"
bitfld.long 0x0 0. "EOAF,End of acquisition flag" "0: Acquisition is ongoing or not started,1: Acquisition is complete"
group.long 0x10++0x3
line.long 0x0 "TSC_IOHCR,TSC I/O hysteresis control register"
bitfld.long 0x0 27. "G7_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 26. "G7_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 25. "G7_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 24. "G7_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 23. "G6_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 22. "G6_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 21. "G6_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 20. "G6_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 19. "G5_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 18. "G5_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 17. "G5_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 16. "G5_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 15. "G4_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 14. "G4_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 13. "G4_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 12. "G4_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 11. "G3_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 10. "G3_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 9. "G3_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 8. "G3_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 7. "G2_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 6. "G2_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 5. "G2_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 4. "G2_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 3. "G1_IO4,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 2. "G1_IO3,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
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bitfld.long 0x0 1. "G1_IO2,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
bitfld.long 0x0 0. "G1_IO1,Gx_IOy Schmitt trigger hysteresis mode" "0: Gx_IOy Schmitt trigger hysteresis disabled,1: Gx_IOy Schmitt trigger hysteresis enabled"
group.long 0x18++0x3
line.long 0x0 "TSC_IOASCR,TSC I/O analog switch control register"
bitfld.long 0x0 27. "G7_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 26. "G7_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 25. "G7_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 24. "G7_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 23. "G6_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 22. "G6_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 21. "G6_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 20. "G6_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 19. "G5_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 18. "G5_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 17. "G5_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 16. "G5_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 15. "G4_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 14. "G4_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 13. "G4_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 12. "G4_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 11. "G3_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 10. "G3_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 9. "G3_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 8. "G3_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 7. "G2_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 6. "G2_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 5. "G2_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 4. "G2_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
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bitfld.long 0x0 3. "G1_IO4,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 2. "G1_IO3,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
newline
bitfld.long 0x0 1. "G1_IO2,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
bitfld.long 0x0 0. "G1_IO1,Gx_IOy analog switch enable" "0: Gx_IOy analog switch disabled (opened),1: Gx_IOy analog switch enabled (closed)"
group.long 0x20++0x3
line.long 0x0 "TSC_IOSCR,TSC I/O sampling control register"
bitfld.long 0x0 27. "G7_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 26. "G7_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 25. "G7_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 24. "G7_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 23. "G6_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 22. "G6_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 21. "G6_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 20. "G6_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 19. "G5_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 18. "G5_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 17. "G5_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 16. "G5_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 15. "G4_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 14. "G4_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 13. "G4_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 12. "G4_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 11. "G3_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 10. "G3_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 9. "G3_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 8. "G3_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 7. "G2_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 6. "G2_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 5. "G2_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 4. "G2_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 3. "G1_IO4,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 2. "G1_IO3,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
newline
bitfld.long 0x0 1. "G1_IO2,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
bitfld.long 0x0 0. "G1_IO1,Gx_IOy sampling mode" "0: Gx_IOy unused,1: Gx_IOy used as sampling capacitor"
group.long 0x28++0x3
line.long 0x0 "TSC_IOCCR,TSC I/O channel control register"
bitfld.long 0x0 27. "G7_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 26. "G7_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 25. "G7_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 24. "G7_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 23. "G6_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 22. "G6_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 21. "G6_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 20. "G6_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 19. "G5_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 18. "G5_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 17. "G5_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 16. "G5_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 15. "G4_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 14. "G4_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 13. "G4_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 12. "G4_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 11. "G3_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 10. "G3_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 9. "G3_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 8. "G3_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 7. "G2_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 6. "G2_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 5. "G2_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 4. "G2_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 3. "G1_IO4,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 2. "G1_IO3,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
newline
bitfld.long 0x0 1. "G1_IO2,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
bitfld.long 0x0 0. "G1_IO1,Gx_IOy channel mode" "0: Gx_IOy unused,1: Gx_IOy used as channel"
group.long 0x30++0x3
line.long 0x0 "TSC_IOGCSR,TSC I/O group control status register"
rbitfld.long 0x0 22. "G7S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
rbitfld.long 0x0 21. "G6S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
newline
rbitfld.long 0x0 20. "G5S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
rbitfld.long 0x0 19. "G4S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
newline
rbitfld.long 0x0 18. "G3S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
rbitfld.long 0x0 17. "G2S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
newline
rbitfld.long 0x0 16. "G1S,Analog I/O group x status" "0: Acquisition on analog I/O group x is ongoing or..,1: Acquisition on analog I/O group x is complete"
bitfld.long 0x0 6. "G7E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
newline
bitfld.long 0x0 5. "G6E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
bitfld.long 0x0 4. "G5E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
newline
bitfld.long 0x0 3. "G4E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
bitfld.long 0x0 2. "G3E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
newline
bitfld.long 0x0 1. "G2E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
bitfld.long 0x0 0. "G1E,Analog I/O group x enable" "0: Acquisition on analog I/O group x disabled,1: Acquisition on analog I/O group x enabled"
rgroup.long 0x34++0x1B
line.long 0x0 "TSC_IOG1CR,TSC I/O group 1 counter register"
hexmask.long.word 0x0 0.--13. 1. "CNT,Counter value"
line.long 0x4 "TSC_IOG2CR,TSC I/O group 2 counter register"
hexmask.long.word 0x4 0.--13. 1. "CNT,Counter value"
line.long 0x8 "TSC_IOG3CR,TSC I/O group 3 counter register"
hexmask.long.word 0x8 0.--13. 1. "CNT,Counter value"
line.long 0xC "TSC_IOG4CR,TSC I/O group 4 counter register"
hexmask.long.word 0xC 0.--13. 1. "CNT,Counter value"
line.long 0x10 "TSC_IOG5CR,TSC I/O group 5 counter register"
hexmask.long.word 0x10 0.--13. 1. "CNT,Counter value"
line.long 0x14 "TSC_IOG6CR,TSC I/O group 6 counter register"
hexmask.long.word 0x14 0.--13. 1. "CNT,Counter value"
line.long 0x18 "TSC_IOG7CR,TSC I/O group 7 counter register"
hexmask.long.word 0x18 0.--13. 1. "CNT,Counter value"
tree.end
tree "USART (Universal Synchronous/Asynchronous Receiver Transmitter)"
base ad:0x0
tree "USART1"
base ad:0x40013800
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,None" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
newline
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
group.long 0x0++0x17
line.long 0x0 "USART_CR1_ALTERNATE,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
line.long 0x4 "USART_CR2,USART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
newline
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
newline
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
newline
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
newline
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
newline
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
newline
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
newline
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
newline
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
line.long 0x8 "USART_CR3,USART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page1826,?,?,7: number of automatic retransmission attempts"
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
newline
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
newline
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
line.long 0xC "USART_BRR,USART baud rate register"
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
line.long 0x14 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
newline
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
newline
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
newline
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
tree "USART2"
base ad:0x40004400
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,None" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
group.long 0x0++0x17
line.long 0x0 "USART_CR1_ALTERNATE,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
line.long 0x4 "USART_CR2,USART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
newline
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
newline
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
newline
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
newline
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
newline
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
newline
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
line.long 0x8 "USART_CR3,USART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page1826,?,?,7: number of automatic retransmission attempts"
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
newline
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
newline
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
newline
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
newline
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
newline
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
line.long 0xC "USART_BRR,USART baud rate register"
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
line.long 0x14 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
newline
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
newline
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
tree "USART3"
base ad:0x40004800
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,None" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
group.long 0x0++0x17
line.long 0x0 "USART_CR1_ALTERNATE,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
newline
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
newline
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
newline
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
newline
bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
newline
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
newline
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
newline
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
line.long 0x4 "USART_CR2,USART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
newline
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
newline
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
newline
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
newline
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
newline
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
newline
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
newline
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
newline
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
line.long 0x8 "USART_CR3,USART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
newline
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
newline
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page1826,?,?,7: number of automatic retransmission attempts"
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
newline
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
newline
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
newline
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
newline
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
newline
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
line.long 0xC "USART_BRR,USART baud rate register"
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
line.long 0x14 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
newline
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
tree "USART4"
base ad:0x40004C00
group.long 0x0++0x3
line.long 0x0 "USART_CR1,USART control register 1"
bitfld.long 0x0 31. "RXFFIE,None" "0,1"
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE=1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
group.long 0x0++0x17
line.long 0x0 "USART_CR1_ALTERNATE,USART control register 1"
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
newline
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in Active mode permanently,1: Receiver can switch between Mute mode and Active.."
bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wake-up method" "0: Idle line,1: Address mark"
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
newline
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE=1 in the.."
newline
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC=1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE=1 or.."
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE=1 in the.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power mode."
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
line.long 0x4 "USART_CR2,USART control register 2"
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted."
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: CK pin disabled,1: CK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on CK pin outside transmission..,1: Steady high value on CK pin outside transmission.."
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF=1 in the.."
newline
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
line.long 0x8 "USART_CR3,USART control register 3"
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
newline
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
bitfld.long 0x8 22. "WUFIE,Wake-up from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF=1 in the.."
newline
bitfld.long 0x8 21. "WUS1,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
bitfld.long 0x8 20. "WUS0,Wake-up from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,1: Reserved."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,?,?,?,4: USART implementation on page1826,?,?,7: number of automatic retransmission attempts"
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
newline
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
newline
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
newline
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF=1 in.."
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
newline
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
newline
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard mode disabled,1: Smartcard mode enabled"
newline
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half-duplex mode is not selected,1: Half-duplex mode is selected"
newline
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
newline
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE=1 or ORE=1 or NE=1.."
line.long 0xC "USART_BRR,USART baud rate register"
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
line.long 0x10 "USART_GTPR,USART guard time and prescaler register"
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
line.long 0x14 "USART_RTOR,USART receiver timeout register"
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
wgroup.long 0x18++0x3
line.long 0x0 "USART_RQR,USART request register"
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
newline
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
newline
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR,USART interrupt and status register"
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
newline
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0: RXFIFO not full.,1: RXFIFO Full."
newline
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0: TXFIFO not empty.,1: TXFIFO empty."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
rgroup.long 0x1C++0x3
line.long 0x0 "USART_ISR_ALTERNATE,USART interrupt and status register"
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
newline
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
bitfld.long 0x0 20. "WUF,Wake-up from low-power mode flag" "0,1"
newline
bitfld.long 0x0 19. "RWU,Receiver wake-up from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
bitfld.long 0x0 18. "SBKF,Send break flag" "0: No break character transmitted,1: Break character transmitted"
newline
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character match detected"
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
newline
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
newline
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
newline
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
bitfld.long 0x0 10. "CTS,CTS flag" "0: CTS line set,1: CTS line reset"
newline
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the CTS status line,1: A change occurred on the CTS status line"
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
newline
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register full"
bitfld.long 0x0 6. "TC,Transmission complete" "0,1"
newline
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
newline
bitfld.long 0x0 3. "ORE,Overrun error" "?,1: Overrun error is detected"
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
newline
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
wgroup.long 0x20++0x3
line.long 0x0 "USART_ICR,USART interrupt flag clear register"
bitfld.long 0x0 20. "WUCF,Wake-up from low-power mode clear flag" "0,1"
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
newline
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
newline
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
newline
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
newline
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
newline
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
newline
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
newline
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "USART_RDR,USART receive data register"
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
group.long 0x28++0x7
line.long 0x0 "USART_TDR,USART transmit data register"
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
line.long 0x4 "USART_PRESC,USART prescaler register"
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
tree.end
tree.end
sif (cpuis("STM32U073*")||cpuis("STM32U083*"))
tree "USB (Universal Serial Bus Full-Speed)"
base ad:0x40005C00
group.long 0x0++0x1F
line.long 0x0 "USB_CHEP0R,USB endpoint/channel 0 register"
bitfld.long 0x0 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x0 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x0 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x0 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x0 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x0 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x0 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x0 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x0 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x0 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x0 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x0 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x0 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x0 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x0 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x0 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "EA,endpoint/channel address"
line.long 0x4 "USB_CHEP1R,USB endpoint/channel 1 register"
bitfld.long 0x4 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x4 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x4 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x4 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x4 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x4 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x4 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x4 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x4 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x4 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x4 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x4 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x4 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x4 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x4 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x4 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "EA,endpoint/channel address"
line.long 0x8 "USB_CHEP2R,USB endpoint/channel 2 register"
bitfld.long 0x8 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x8 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x8 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x8 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x8 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x8 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x8 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x8 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x8 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x8 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x8 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x8 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x8 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x8 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x8 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x8 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x8 0.--3. 1. "EA,endpoint/channel address"
line.long 0xC "USB_CHEP3R,USB endpoint/channel 3 register"
bitfld.long 0xC 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0xC 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0xC 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0xC 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0xC 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0xC 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0xC 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0xC 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0xC 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0xC 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0xC 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0xC 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0xC 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0xC 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0xC 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0xC 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0xC 0.--3. 1. "EA,endpoint/channel address"
line.long 0x10 "USB_CHEP4R,USB endpoint/channel 4 register"
bitfld.long 0x10 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x10 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x10 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x10 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x10 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x10 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x10 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x10 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x10 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x10 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x10 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x10 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x10 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x10 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x10 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x10 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x10 0.--3. 1. "EA,endpoint/channel address"
line.long 0x14 "USB_CHEP5R,USB endpoint/channel 5 register"
bitfld.long 0x14 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x14 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x14 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x14 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x14 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x14 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x14 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x14 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x14 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x14 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x14 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x14 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x14 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x14 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x14 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x14 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x14 0.--3. 1. "EA,endpoint/channel address"
line.long 0x18 "USB_CHEP6R,USB endpoint/channel 6 register"
bitfld.long 0x18 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x18 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x18 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x18 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x18 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x18 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x18 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x18 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x18 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x18 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x18 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x18 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x18 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x18 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x18 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x18 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--3. 1. "EA,endpoint/channel address"
line.long 0x1C "USB_CHEP7R,USB endpoint/channel 7 register"
bitfld.long 0x1C 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
bitfld.long 0x1C 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
newline
bitfld.long 0x1C 26. "ERR_RX,Received error for an IN transaction" "0,1"
bitfld.long 0x1C 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
newline
bitfld.long 0x1C 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
bitfld.long 0x1C 23. "NAK,Host mode" "0,1"
newline
hexmask.long.byte 0x1C 16.--22. 1. "DEVADDR,Host mode"
bitfld.long 0x1C 15. "VTRX,USB valid transaction received" "0,1"
newline
bitfld.long 0x1C 14. "DTOGRX,Data Toggle for reception transfers" "?,1: 1DATA0"
bitfld.long 0x1C 12.--13. "STATRX,Status bits for reception transfers" "?,?,?,3: Double-buffered endpoints and usage in Device mode"
newline
rbitfld.long 0x1C 11. "SETUP,Setup transaction completed" "0,1"
bitfld.long 0x1C 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
newline
bitfld.long 0x1C 8. "EPKIND,endpoint/channel kind" "0,1"
bitfld.long 0x1C 7. "VTTX,Valid USB transaction transmitted" "0,1"
newline
bitfld.long 0x1C 6. "DTOGTX,Data toggle for transmission transfers" "?,1: 1DATA0"
bitfld.long 0x1C 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
newline
hexmask.long.byte 0x1C 0.--3. 1. "EA,endpoint/channel address"
group.long 0x40++0x7
line.long 0x0 "USB_CNTR,USB control register"
bitfld.long 0x0 31. "HOST,HOST mode" "0: USB Device function,1: USB host function (Reserved host function is not.."
bitfld.long 0x0 17. "DDISCM,Device disconnection mask" "0: Device disconnection interrupt disabled,1: Device disconnection interrupt enabled"
newline
bitfld.long 0x0 16. "THR512M,512 byte threshold interrupt mask" "0: 512 byte threshold interrupt disabled,1: 512 byte threshold interrupt enabled"
bitfld.long 0x0 15. "CTRM,Correct transfer interrupt mask" "0: Correct transfer (CTR) interrupt disabled.,1: CTR interrupt enabled an interrupt request is.."
newline
bitfld.long 0x0 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0: PMAOVR interrupt disabled.,1: PMAOVR interrupt enabled an interrupt request is.."
bitfld.long 0x0 13. "ERRM,Error interrupt mask" "0: ERR interrupt disabled.,1: ERR interrupt enabled an interrupt request is.."
newline
bitfld.long 0x0 12. "WKUPM,Wake-up interrupt mask" "0: WKUP interrupt disabled.,1: WKUP interrupt enabled an interrupt request is.."
bitfld.long 0x0 11. "SUSPM,Suspend mode interrupt mask" "0: Suspend mode request (SUSP) interrupt disabled.,1: SUSP interrupt enabled an interrupt request is.."
newline
bitfld.long 0x0 10. "RST_DCONM,USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask" "0: RESET interrupt disabled.,1: RESET interrupt enabled an interrupt request is.."
bitfld.long 0x0 9. "SOFM,Start of frame interrupt mask" "0: SOF interrupt disabled.,1: SOF interrupt enabled an interrupt request is.."
newline
bitfld.long 0x0 8. "ESOFM,Expected start of frame interrupt mask" "0: Expected start of frame (ESOF) interrupt disabled.,1: ESOF interrupt enabled an interrupt request is.."
bitfld.long 0x0 7. "L1REQM,LPM L1 state request interrupt mask" "0: LPM L1 state request (L1REQ) interrupt disabled.,1: L1REQ interrupt enabled an interrupt request is.."
newline
bitfld.long 0x0 5. "L1RES,L1 remote wake-up / resume driver" "0: No effect,1: send 50 micro s remote wake up signaling to host"
bitfld.long 0x0 4. "L2RES,L2 remote wake-up / resume driver" "0: No effect,1: Send L2 resume signaling to device"
newline
bitfld.long 0x0 3. "SUSPEN,Suspend state enable" "0: No effect,1: Enter L1/L2 suspend"
rbitfld.long 0x0 2. "SUSPRDY,Suspend state effective" "0: Normal operation,1: Suspend state"
newline
bitfld.long 0x0 1. "PDWN,Power down" "0: Exit power down,1: Enter power down mode"
bitfld.long 0x0 0. "USBRST,USB Reset" "0: No effect,1: USB core is under reset"
line.long 0x4 "USB_ISTR,USB interrupt status register"
rbitfld.long 0x4 30. "LS_DCON,Low speed device connected" "0,1"
rbitfld.long 0x4 29. "DCON_STAT,Device connection status" "0: No device connected,1: FS or LS device connected to the host"
newline
bitfld.long 0x4 17. "DDISC,Device connection" "0,1"
bitfld.long 0x4 16. "THR512,512 byte threshold interrupt" "0,1"
newline
rbitfld.long 0x4 15. "CTR,Completed transfer in host mode" "0,1"
bitfld.long 0x4 14. "PMAOVR,Packet memory area over / underrun" "0,1"
newline
bitfld.long 0x4 13. "ERR,Error" "0,1"
bitfld.long 0x4 12. "WKUP,Wake-up" "0,1"
newline
bitfld.long 0x4 11. "SUSP,Suspend mode request" "0,1"
bitfld.long 0x4 10. "RST_DCON,USB reset request (Device mode) or device connect/disconnect (Host mode)" "0,1"
newline
bitfld.long 0x4 9. "SOF,Start of frame" "0,1"
bitfld.long 0x4 8. "ESOF,Expected start of frame" "0,1"
newline
bitfld.long 0x4 7. "L1REQ,LPM L1 state request" "0,1"
rbitfld.long 0x4 4. "DIR,Direction of transaction" "0,1"
newline
hexmask.long.byte 0x4 0.--3. 1. "IDN,Device Endpoint / host channel identification number"
rgroup.long 0x48++0x3
line.long 0x0 "USB_FNR,USB frame number register"
bitfld.long 0x0 15. "RXDP,Receive data + line status" "0,1"
bitfld.long 0x0 14. "RXDM,Receive data - line status" "0,1"
newline
bitfld.long 0x0 13. "LCK,Locked" "0,1"
bitfld.long 0x0 11.--12. "LSOF,Lost SOF" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--10. 1. "FN,Frame number"
group.long 0x4C++0x3
line.long 0x0 "USB_DADDR,USB Device address"
bitfld.long 0x0 7. "EF,Enable function" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "ADD,Device address"
group.long 0x54++0x7
line.long 0x0 "USB_LPMCSR,LPM control and status register"
hexmask.long.byte 0x0 4.--7. 1. "BESL,BESL value"
rbitfld.long 0x0 3. "REMWAKE,bRemoteWake value" "0,1"
newline
bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: the valid LPM token is NYET.,1: the valid LPM token is ACK."
bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1"
line.long 0x4 "USB_BCDR,Battery charging detector"
bitfld.long 0x4 15. "DPPU_DPD,DP pull-up / DPDM pull-down" "0,1"
rbitfld.long 0x4 7. "PS2DET,DM pull-up detection status" "0: Normal port detected (connected to SDP ACA CDP..,1: PS2 port or proprietary charger detected."
newline
rbitfld.long 0x4 6. "SDET,Secondary detection (SD) status" "0: CDP detected.,1: DCP detected."
rbitfld.long 0x4 5. "PDET,Primary detection (PD) status" "0: no BCD support detected (connected to SDP or..,1: BCD support detected (connected to ACA CDP or.."
newline
rbitfld.long 0x4 4. "DCDET,Data contact detection (DCD) status" "0: data lines contact not detected.,1: data lines contact detected."
bitfld.long 0x4 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
newline
bitfld.long 0x4 2. "PDEN,Primary detection (PD) mode enable" "0,1"
bitfld.long 0x4 1. "DCDEN,Data contact detection (DCD) mode enable" "0,1"
newline
bitfld.long 0x4 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
tree.end
endif
tree "VREFBUF (Voltage Reference Buffer)"
base ad:0x40010030
group.long 0x0++0x7
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status register"
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to V<sub>REF_OUT1</sub>..,1: Voltage reference set to V<sub>REF_OUT2</sub>.."
newline
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: V<sub>REF+</sub> pin is internally connected to..,1: V<sub>REF+</sub> pin is high impedance."
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control register"
hexmask.long.byte 0x4 0.--5. 1. "TRIM,None"
tree.end
tree "WWDG (Window Watchdog)"
base ad:0x40002C00
group.long 0x0++0xB
line.long 0x0 "WWDG_CR,WWDG control register"
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
line.long 0x4 "WWDG_CFR,WWDG configuration register"
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK counter clock (PCLK div 4096) div 1,1: CK counter clock (PCLK div 4096) div 2,2: CK counter clock (PCLK div 4096) div 4,3: CK counter clock (PCLK div 4096) div 8,4: CK counter clock (PCLK div 4096) div 16,5: CK counter clock (PCLK div 4096) div 32,6: CK counter clock (PCLK div 4096) div 64,7: CK counter clock (PCLK div 4096) div 128"
bitfld.long 0x4 9. "EWI,Early wake-up interrupt enable" "0,1"
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
line.long 0x8 "WWDG_SR,WWDG status register"
bitfld.long 0x8 0. "EWIF,Early wake-up interrupt flag" "0,1"
tree.end
AUTOINDENT.OFF
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